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GAIN (V/V)
25°C
7
GAIN (dB)
1
Figure 2. AVMAX = 9.4 V/V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMH6505
SNOSAT4E – DECEMBER 2005 – REVISED APRIL 2013 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum output current (IOUT) is determined by device power dissipation limitations or value specified, whichever is lower.
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the Electrical
Tables under conditions of internal self-heating where TJ > TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Flat Band Attenuation (Relative To Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain
flatness specified (either ±0.2 dB or ±0.1 dB), relative to AVMAX gain. For example, for f < 30 MHz, here are the Flat Band Attenuation
ranges:
±0.2 dB: 19.7 dB down to -6.3 dB = 26 dB range
±0.1 dB: 19.7 dB down to 10.2 dB = 9.5 dB range
(5) Gain control frequency response schematic:
RF
1 k:
+0.2 VDC
+VIN ROUT
+ 50:
R1 PORT 2
LMH6505
50:
- RL
VG 50:
RG
100:
C1 +5V
RF IN 0.01 PF
RP1
RT 10 k:
PORT 1 1V DC
50:
-5V
(6) Slew rate is the average of the rising and falling slew rates.
Connection Diagram
1 8 +
VG V
2 7 -
VIN I
X1
RG 3 6 VOUT
-
4 + 5
GND V-
PHASE (°)
PHASE (°)
-3 -3
GAIN (dB)
GAIN (dB)
85°C
-4 -100 -4 -100
25°C
-5 -150 -5 -150
-40°C VG = 0.7V
-6 -200 -6 -200
VG = 0.9V VG = 2V
-7 -250 -7 -250
0 -100 -2 -80
2 VPP
VG = 0.8V
PHASE (°)
PHASE (°)
-3
GAIN (dB)
-120
GAIN (dB)
-1 -150 4 VPP
PHASE -4 -160
-2 -200
-5 -200
-3 AVMAX = 2V/V -250 PHASE 1 VPP
VG = 0.8V -6 -240
RF = 1 k: -300
-4 -7 -280
RG = 510: VG = 1V 2 VPP 4 VPP
-5 -350 -8 -320
PIN = 4 dBm VG = 2V 1 VPP
-6 -400 -9 -360
0 0
f (50 MHz/DIV)
f (50 MHz/DIV)
Gain/Phase normalized to low frequency value at each setting.
Figure 6. Figure 7.
PHASE (°)
GAIN (dB)
GAIN (dB)
PHASE
-3 -80 -6 -150
PHASE 2V 4 VPP
-4 -120 -8 -200
AVMAX = 100V/V
-5 -160 -10 -250
RF = 2.32 k:
2 VPP
-6 RG = 18: -200 -12 -300
PIN = -24 dBm,
-7 -240 -14 -350
0 0
f (10 MHz/DIV) f (20 MHz/DIV)
Gain/Phase normalized to low frequency value at each setting. Gain/Phase normalized to low frequency value at each setting.
Figure 8. Figure 9.
40°C 12
-10 -80
IS (mA)
25°C 10
-15 -120 25°C
85°C
-20 -160 8
-25 -200 6
VG (AC) = -13.7 dBm -40°C
-30 VIN = 0.2V (DC) -240 4
-35 VG = 0.98 AVERAGE -280 2
-40 -320
0
100k 1M 10M 100M 1G
3 3.5 4 4.5 5 5.5 6
FREQUENCY (Hz)
±SUPPLY VOTLAGE (V)
See Electrical Characteristics Note (5).
Figure 10. Figure 11.
18 RL = OPEN
16
85°C -0.5
14
12 85°C 25°C
IS (mA)
IB (PA)
10 25°C -0.6
8
6
-40°C -0.7
4
-40°C
2
0 -0.8
3 3.5 4 4.5 5 5.5 6 2 3 4 5 6
±SUPPLY VOTLAGE (V) ±SUPPLY VOLTAGE (V)
-10
10
-20
-30 8
AVMAX (V/V)
PSRR (dB)
-PSRR 85°C
-40 6
-50 25°C
4
-60 -40°C
+PSRR
2
-70
-80 0
100 1k 10k 100k 1M 10M 100M 2.5 3 3.5 4 4.5 5 5.5 6
FREQUENCY (Hz) ±SUPPLY VOLTAGE
See Electrical Characteristics Note (9)
Figure 14. Figure 15.
0
GAIN (dB)
-60 0.1
-80
-100 0.01
100k 1M 10M 100M 1G 0 0.5 1 1.5 2
VG (V)
FREQUENCY (Hz)
Figure 16. Figure 17.
GAIN (V/V)
25°C
7
GAIN (dB)
-2
IR G (mA)
dB -55°C
-30 6
0
5
125°C V/V
+2 -50 4
25°C
+4 3
-55°C
-70 2
+6
1
+8 -90 0
-1.5 -1 -0.5 0 0.5 1 1.5 -0.5 0 0.5 1 1.5 2
VIN (V) VG (V)
See Electrical Characteristics Note (7).
Figure 18. Figure 19.
Output Offset Voltage vs. VG (Typical Unit #1) Output Offset Voltage vs. VG (Typical Unit #2)
10 30
25°C
-40°C 25
5
85°C
VO_OFFSET (mV)
VO_OFFSET (mV)
20
0
25°C 15
-5
10
85°C
85°C
-10
5
-40°C
-15 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VG (V) VG (V)
20
14
15 12
-40°C 10
10 8
85°C
6
5 4
2
25°C
0 0
-55 -45 -35 -25 -15 -5 5 15 25 35 45 55
0 0.5 1 1.5 2 2.5
OFFSET VOLTAGE (mV)
VG (V)
Output Noise Density vs. Frequency Output Noise Density vs. Frequency
10000 100000
RSOURCE - 50: AVMAX = 100
RF = 2.4 k:
10000 RG = 22:
VG_MAX
1000 VG_MAX RSOURCE = 50:
eno (nV/ Hz)
VG_MID
VG_MID 1000
100 VG_MIN
100
VG_MIN
10 10
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24. Figure 25.
Output Noise Density vs. Frequency Input Referred Noise Density vs. Frequency
10000 1000 1000
AVMAX = 2
RG = 510:
RSOURCE = 50:
1000 VG_MAX 100 VOLTAGE 100
eno (nV/ Hz)
Hz)
Ini (pA/
VG_MID
100 10 10
VG_MIN
CURRENT
10 1 1
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 26. Figure 27.
+
-
3 -40°C 3 -40°C
2 25°C 2
85°C 85°C
1 1
0 0
0 20 40 60 80 100 120 0 20 40 60 80 100 120
IOUT (mA) IOUT (mA)
-80
HD (dBc)
HD (dBc)
-60
-70
THD
-70 -60
HD2
HD3 -50
-80
HD2, 20 MHz
-40
HD3, 20 MHz
-90 -30
-100 -20
100k 1M 10M 100M -10 -5 0 5 10 15 20
FREQUENCY (Hz) POUT (dBm)
Figure 30. Figure 31.
-70 20 MHz
THD (dBc)
THD (dBc)
THD (dBc)
-50
20 MHz -40
-40
20 MHz
-30
-30
-20 -20
-10 -10
0 0
-15 -10 -5 0 5 10 15 20
-5 0 5 10 15 20
GAIN (dB) GAIN (dB)
IG (nA)
DP (°)
0.2 0 880
DG
0.1 -0.05 860
0 -0.1 840
LS REF LS REF
4 VPP LARGE SIGNAL 4 VPP LARGE SIGNAL
VG = VG_MID
5 ns/DIV 5 ns/DIV
Figure 38. Figure 39.
GAIN 9
2 8
7
VG
GAIN (V/V)
1.5 6
VG (V)
5
1 4
3
0.5 2
1
VIN = 0.3V
0 0
t (10 ns/DIV)
Figure 40.
APPLICATION INFORMATION
GENERAL DESCRIPTION
The key features of the LMH6505 are:
• Low power
• Broad voltage controlled gain and attenuation range (from AVMAX down to complete cutoff)
• Bandwidth independent, resistor programmable gain range (RG)
• Broad signal and gain control bandwidths
• Frequency response may be adjusted with RF
• High impedance signal and gain control inputs
The LMH6505 combines a closed loop input buffer (“X1” Block in Figure 41), a voltage controlled variable gain
cell (“MULT” Block) and an output amplifier (“CFA” Block). The input buffer is a transconductance stage whose
gain is set by the gain setting resistor, RG. The output amplifier is a current feedback op amp and is configured
as a transimpedance stage whose gain is set by, and is equal to, the feedback resistor, RF. The maximum gain,
AVMAX, of the LMH6505 is defined by the ratio: K · RF/RG where “K” is the gain multiplier with a nominal value of
0.940. As the gain control input (VG) changes over its 0 to 2V range, the gain is adjusted over a range of about
80 dB relative to the maximum set gain.
INPUT 5V + -
SIGNAL 6.8 µF
GAIN
CONTROL VG +VCC 0.1 µF
MULT RF
RX VIN I-
50:
X1 1 k:
RG VO RO OUTPUT
RIN
50: - 50:
GND CFA -VCC
+
RG -
100: 0.1 µF 6.8 µF
+
-5V
As the IRG_MAX limit is approached with increasing the input voltage or with the lowering of RG, the device's
harmonic distortion will increase. Changes in RF will have a dramatic effect on the small signal bandwidth. The
output amplifier of the LMH6505 is a current feedback amplifier (CFA) and its bandwidth is determined by RF. As
with any CFA, doubling the feedback resistor will roughly cut the bandwidth of the device in half.
For more about CFAs, see the basic tutorial, OA-20, Current Feedback Myths Debunked, (literature number
SNOA376), or a more rigorous analysis, OA-13, Current Feedback Amplifier Loop Gain Analysis and
Performance Enhancements, (literature number SNOA366).
OTHER CONFIGURATIONS
1. Single Supply Operation
The LMH6505 can be configured for use in a single supply environment. Doing so requires the following:
(a) Bias pin 4 and RG to a “virtual half supply” somewhere close to the middle of V+ and V− range. The other
end of RG is tied to pin 3. The “virtual half supply” needs to be capable of sinking and sourcing the
expected current flow through RG.
(b) Ensure that VG can be adjusted from 0V to 2V above the “virtual half supply”.
(c) Bias the input (pin 2) to make sure that it stays within the range of 2V above V− to 2V below V+. See the
Input Voltage Range specification in the Electrical Characteristics table. This can be accomplished by
either DC biasing the input and AC coupling the input signal, or alternatively, by direct coupling if the
output of the driving stage is also biased to half supply.
Arranged this way, the LMH6505 will respond to the current flowing through RG. The gain control relationship
will be similar to the split supply arrangement with VG measured with reference to pin 4. Keep in mind that
the circuit described above will also center the output voltage to the “virtual half supply voltage.”
2. Arbitrarily Referenced Input Signal
Having a wide input voltage range on the input (pin 2) (±3V typical), the LMH6505 can be configured to
control the gain on signals which are not referenced to ground (e.g. Half Supply biased circuits). This node
will be called the “reference node”. In such cases, the other end of RG which is the side not tied to pin 3 can
be tied to this reference node so that RG will “look at” the difference between the signal and this reference
only. Keep in mind that the reference node needs to source and sink the current flowing through RG.
GAIN ACCURACY
Gain accuracy is defined as the actual gain compared against the theoretical gain at a certain VG, the results of
which are expressed in dB. (See Figure 42).
Theoretical gain is given by:
RF 1
A(V/V) = K x x
RG N - VG
VC
1+e
where
• K = 0.940 (nominal) N = 1.01V
• VC = 79 mV at room temperature (3)
For a VG range, the value specified in the tables represents the worst case accuracy over the entire range. The
"Typical" value would be the difference between the "Typical Gain" and the "Theoretical Gain." The "Max" value
would be the worst case difference between the actual gain and the "Theoretical Gain" for the entire population.
GAIN MATCHING
As Figure 42 shows, gain matching is the limit on gain variation at a certain VG, expressed in dB, and is specified
as "±Max" only. There is no "Typical." For a VG range, the value specified represents the worst case matching
over the entire range. The "Max" value would be the worst case difference between the actual gain and the
typical gain for the entire population.
THEORETICAL GAIN
GAIN (dB)
D
TYPICAL GAIN
C
PARAMETER:
VG (V)
GAIN PARTITIONING
If high levels of gain are needed, gain partitioning should be considered:
VG
VIN + 25: 1
2
LMH6624
6
RC LMH6505 VO
-
3
7
4
R2
RF
RG
R1
The maximum gain range for this circuit is given by the following equation:
R2 RF
MAXIMUM GAIN = 1+ · ·K
R1 RG
(4)
The LMH6624 is a low noise wideband voltage feedback amplifier. Setting R2 at 909Ω and R1 at 100Ω produces
a gain of 20 dB. Setting RF at 1000Ω as recommended and RG at 50Ω, produces a gain of about 26 dB in the
LMH6505. The total gain of this circuit is therefore approximately 46 dB. It is important to understand that when
partitioning to obtain high levels of gain, very small signal levels will drive the amplifiers to full scale output. For
example, with 46 dB of gain, a 20 mV signal at the input will drive the output of the LMH6624 to 200 mV and the
output of the LMH6505 to 4V. Accordingly, the designer must carefully consider the contributions of each stage
to the overall characteristics. Through gain partitioning the designer is provided with an opportunity to optimize
the frequency response, noise, distortion, settling time, and loading effects of each amplifier to achieve improved
overall performance.
GAIN STABILITY
The LMH6505 architecture allows complete attenuation of the output signal from full gain to complete cutoff. This
is achieved by having the gain control signal VG “throttle” the signal which gets through to the final stage and
which results in the output signal. As a consequence, the RG pin's (pin 3) average current (DC current) influences
the operating point of this “throttle” circuit and affects the LMH6505's gain slightly. Figure 44 below, shows this
effect as a function of the gain set by VG.
4.5
4
3.5
3
DELTA AV (dB)
4.5 mA SOURCING
2.5
2
1.5
1
4.5 mA SINKING
0.5
0
-0.5
-80 -60 -40 -20 0 20
AV (dB)
Figure 44. LMH6505 Gain Variation over RG DC Current Capability vs. Gain
This plot shows the expected gain variation for the maximum RG DC current capability (±4.5 mA). For example,
with gain (AV) set to −60 dB, if the RG pin DC current is increased to 4.5 mA sourcing, one would expect to see
the gain increase by about 3 dB (to −57 dB). Conversely, 4.5 mA DC sinking current through RG would increase
gain by 1.75 dB (to −58.25 dB). As you can see from Figure 44 above, the effect is most pronounced with
reduced gain and is limited to less than 3.75 dB variation maximum.
If the application is expected to experience RG DC current variation and the LMH6505 gain variation is beyond
acceptable limits, please refer to the LMH6502 (Differential Linear in dB variable gain amplifier) datasheet
instead at http://www.ti.com/lit/gpn/LMH6502.
VG
1
2
6
LMH6505 VO
25: 3
VIN 7
RG 4
RF
The input signal is applied through the RG resistor. The VIN pin should be grounded through a 25Ω resistor. The
maximum gain range of this configuration is given in the following equation:
RF
AVMAX = - ·K
RG
(5)
The inverting slew rate of the LMH6505 is much higher than that of the non-inverting slew rate. This ≈ 2X
performance improvement comes about because in the non-inverting configuration the slew rate of the overall
amplifier is limited by the input buffer. In the inverting circuit, the input buffer remains at a fixed voltage and does
not affect slew rate.
CO
ZO 1
2 ZO
6
RS LMH6505 OUTPUT
SIGNAL RI 3
INPUT
+- 7 RO
4 RT
RG RF
The resistors RS, RI, RO, and RT are equal to the characteristic impedance, ZO, of the transmission line or cable.
Use CO to match the output transmission line over a greater frequency range. It compensates for the increase of
the op amp’s output impedance with frequency.
RECOMMENDATIONS
Here are some recommendations to avoid problems and to get the best performance:
• Do not place a capacitor across RF. However, an appropriately chosen series RC combination can be used to
shape the frequency response.
• Keep traces connecting RF separated and as short as possible.
• Place a small resistor (20-50Ω) between the output and CL.
• Cut away the ground plane, if any, under RG.
• Keep decoupling capacitors as close as possible to the LMH6505.
• Connect pin 2 through a minimum resistance of 25Ω.
VG
1
2
VIN
6
LMH6505 VO
3
+5V 7 RF
4
R2
+5V
10 k: RG
R1 R3
10 k: 10 k:
R4
0.1 µF
10 k:
0.1 µF
-5V
-5V
DIGITAL
INPUT
RFB
Io1
VREF -
DAC0830 LMC8101
+ 2 1
Io2 VIN VO
6
LMH6505
3
7
4
RG
100: RF
1 k:
INCLUDES SCOPE
PROBE CAPACITANCE
C3 2 1
VIN
40 pF + OUTPUT
U4 6
20 MHz,
LMH6505
0.1 VPP
- 7 C1
R10 3 RF
4 1.0 µF
RG
500:
100: R1
C2 20:
680 pF
R5 R3
25: 300:
R8
+
500: U2
- LMH6714
U3
LMH6609 -
R6 R4
+ R9
300: 300:
4.22 k: -
U1
R7 LMH6714
300: 1N5712
SCHOTTKY +
-5V
R2
25:
Signal frequencies must not reach the gain control port of the LMH6505, or the output signal will be distorted
(modulated by itself). A fast settling AGC needs additional filtering beyond the integrator stage to block signal
frequencies. This is provided in Figure 49 by a simple R-C filter (R10 and C3); better distortion performance can
be achieved with a more complex filter. These filters should be scaled with the input signal frequency. Loops with
slower response time, which means longer integration time constants, may not need the R10 – C3 filter.
Checking the loop stability can be done by monitoring the VG voltage while applying a step change in input signal
amplitude. Changing the input signal amplitude can be easily done with an arbitrary waveform generator.
REVISION HISTORY
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Aug-2017
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Aug-2017
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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