F2114/2114L 1024 x 4 Static RAM MOS Memory Products Description Logic Symbol The F2114 is a 4096-bit static Random Acc Memory (RAM) organized as 1024 words of locking or refreshing required, It from a single +5 V supply and is directly a TTL compatible at ail inputs and outpute including the four bidirectional data I/O pine aA Fanta Parr—19 ate qe vos} sa Tho F21 14 is manufactured using Fairchld's n-channel sy 1 silicon gate leoplanar process. the innovative u wot pots polysilicon resistors in the static memory cell . Permits a high bit packing density and insures sane low-power characteristics. It is a\ uA Veg = Pi 18 CnD = Pin © 1026 x 4-817 ORGANIZATION = SINGLE +5 V SUPPLY ST © COMPLETELY STATIC—NO CLOCKS OR REFRESH Connection Diagram = TOTALLY TTL COMPATIBLE 1ePin DIP 1 COMMON DATA 1/0 PINS WITH S-STATE CAPABILITY w= IDENTICAL CYCLE AND ACCESS TIMES = Low PoweR (21141) Pin Names Ao-Ag. Inputs: cs (Active LOW) we Write Enable (Active LOW) DG,-DQ, Data Input/Output Voc +5 V Power Supply Gh Ground Absolute Maximum Ratings Respect -05vt0+7.0¥ Operating, Temperature (Ambient) O°C to +70°C ‘Storage Temperature (Ambient) —55°C to +150°C (Top View) 1 ee Order Package Outing Code Ceramic DIP | @D D Plastic oI | ay P ecification fe nol implied. Exposure imum rating conditions for extended periods of time may affect device reliability —_—_—_—_—— SE 38F2114/2114L Block Diagram —_ Ey aa eel FE] sw | wet ae ope] ee cota nex couvun eur us emeu t+ : BR Functional Description All inputs and bidirectional DQ pins are directly TTL ‘The F2114, organized as 1024 words by four bit ‘compatible with data always being read out in the controlled by the Chip Select (CS), Write Enable (WE) same polarity as it was written (i.e, not inverted). ‘and the ten address inputs. When CS goes HIGH the memory becomes deselected; the bidirectional Truth Table input/output pins becor a le AWE Input ia ignored. Th Wwe [oa Comment operations may occur. T a x High | Chip Deselected to be OR-tied directly to a data bus. When the memory ri Al selected (CS LOW), and the WE pin is in the HIGH the 4-bit word stored at the memory location t L L specified by the address inputs is gated through to t ry Data time. tf 1e HIGH dat the DQ pins after a delay equal to the acc the WE is forced LOW, then the DQ pins be impedance inputs so that an externally supp! word may be placed on them. SS 38SS F2114/2114L DC Electrical Requirements and Characteristics T, = 0 to 70°C, Voc = 5.0 V + 5%, Atvltages are ih Teopoat arsine, Nate ‘Symbol Characteristic Min Typ Max Unit Condition _ Vor [input HGH Vonage 20 Wee |v vu [apo LoW Vonage =08 08 |v Vou [ouput FIGH Vategs Za Veo” |v Jiour = = ma Yor output tow Varese o oa [Vout = 32 mA tos urn nore 65 ma |vour=ov ‘Average Vec Supply Caren To wa Wen = Bev, soo (eatualas SS nnaeY Griat ‘Average Voc Supply Current Room an career M18 camer Oma in Input Leakage Curent [ek [v= Oto 5 Sv tco—-|voteakage cure (v0 wo a [eae M ave Gm | pw Cepactance oo lor [TAS BC T= 10M Coa |v0 cepectance so for [fas BRC T= LOM AC Electrical Requirements And Characteristics Ta = 0°C to 70°C, Voc = 5.0 VV + 5%, Notes 1 and 3 raivaia |ezivacd ]patvaL Feneo’|esines’ (faite srmbot_|charactere win [Max |Win [wax [win —[wox—|unit_|note teva [Read or Write Gye Tine [p00 300 450 rr taco [Read Access Tine 70 36 Ins tco ‘ES LOW to Output Valid Delay 70 100 100 [ns tesx [C5 LOW to Output Active Delay |20 20 Bee [conse | meat ns toon _[Rupereataowtine [so ‘0 2 ns tore _[owteutButter Ten-or7Osiay oop fo lao fo [100 |no iw Tadeese fo Wie Setap Tine [0 G A = ‘twe ‘WE Pulse Width 120 150, 200 ns. twh | Wite Recovery Tine 3 o 0 a tos. Input Data Set-up Time 120 150 200 ns itu [input Data oid Tne 3 0 0 7 ‘tent Noe The F214 ample as tart octet 2. AC Characterii Test Conditions pereseSel F2114/2114L Read Mode Timing Diagram, Note 1 ADDRESS ‘oureur DATA, ineut Data DONT CARE INPUT CONDITION Notes 1. WE must romain HIGH during READ cycles 2 ing edge of either CS or 10.90 LOW) fo the eising ‘edge of either CS or WE (whichever is the frst 10 90 HIGH)