sec D ‘ime! 20 minutes Question 3 Use Verilog to describe the 2:1 muliplexer ss shown nthe followin firme,1. Use gate level modeing 2 marks) mole mux2_1 (SEL, A, B, OUD) input SEL, A,B: Bipnour; She KI): NOTE, SL): i AND( A): AND( 2, © Se) OR( our, 4,2) enimoale “ 2, Use continuous assignment statements (2 maths) A,B,OUD) assign Out= i (AZ~*) cendmodule 4. Use an "always" procedure block (2 marks) module mux2_1 (SEL, A, B, OUT) | input SEL, A, Bs j ‘output OUT: eg OUT always @¢ SLX) bein ifSEL) or = B~_Draw the block diagram of bit ripple cary adder and properly mention names of inputs outpu ‘wire that you would use in writing the veri code3 marks) rite veil code for 4 bit ripple carry adder using fll adders and ful adders should be using half ‘adder modules. ie total of 3 modules (7 marks) We 2) pg eh) a7 bet alo ae rel ee) d a), 8 mcile hol adder ( ma HD oepek Ty ids ous oy wh Tes om iopak >) ., aa OST a iy ‘ as. ae.Guedihe — full_adler 4 Com, courts @ . opt (z-0J sem Qusper Cony inp inpux fall_odde Rw a