GATE pe AI ELECTRONICS ENGINEERING Computer Organization mADE as aie PRIME} SY New Deh, NopGATE pe AI Contents S.No. TOPICS PAGE No. 1 Machine Instructions and Addressing Modes 4 2. ALU, data-path and Control Unit WW 3 Instruction Pipelining 15Computer Organization Chapter-1 : Machine Instructions and Addressing Modes * Basics of the computer design = Computer System + Layers of abstraction = Computer organization and architecture = Evolution of digital computers = Structure and function of a computer system = Components of computer structure = Bus structure + Data storage in the memory + Instruction cycle = Machine instructions + Instruction formats + Addressing modes + Instruction set = Types of machine instructions = Instruction stream (vs) Data stream Description Sheet Chapter-2 : ALU, data-path and Control Unit ALUstructure: = Introduction = ALU design System bus structure: = Data paths = Bus organization of data path = Independent of data path Control unit design: = Introduction = Multicycle data path and control = Control unit = Micro operations and control signals = Control unitimplementation Chapter-3 : Instruction Pipeline Performance Instruction processing Differences between ai paths Pipeline design and Issues: + Pipeline data path = Pipeline hazards + Pipeline performance analysis, = SpeedupMachine Instructions and Addressing Modes Multiple Cholce Questions Q.1_ The most relevant addressing mode to write position independent codes is (@) Directmode —(b) Indirectmode (¢) Relative mode (d) Indexed mode [GATE-1987] Common Data For 0.2 & 0.3 Consider the following assembly language program for a hypothetical processor. A, 8 and C are 8-bit registers. The meanings as various instructions are shown as comments. MOV B, #0; BeO MOV C, #8, CeB Z CMP C, #0; Compare Cwitho JZ X; Jump to Xitzerotiagis set SUB C, #1; CeC-1 RRC A, #1; Rotate right A through carry by one bit. wc OY: Jump to Y if carry flag is set MP Z; Jump to Z Yo Add B, #1; BeB+1 MP Z; Jump to Z x Q.2 Ifthe initial value of register Ais A, The value of register Bator the program execution will be (a) The number of 0’ bits in A, (b) The number of 1” bits in A, A, 8 [GATE 2003] Q.3° Which of the following instructions when inserted at location X will ensure that the value of register A after program execution is the same as its intial value wwwmadeeasyprime.com MCOqHIOM LZ0Z ALVD (@) RRC A, #1; Rotate right A through carry (0) NOP; No operation (¢) LAC A, #1; Left rotate A through carry (@) ADDA HAC A+ [GATE 2003] Which of the following addressing modes are suitable for program relocation at run time 1. Absolute addressing 2, Based addressing 3. Rolative addressing 4, Indirect addressing fa) 1and4 (b) 1and2 (c) 2and3. (a) 1,2anda [GATE 2004] a4 Common Data For Q.5 to 0.6 Solve the problems and choose the correct answers Consider the following program segment for a hypothetical CPU having three user registers R,, R, and Ry g Instruction Operation Instruction size 3 (words) MM Mov R,,5000; Rye M[S000] 2 Ny) MOV R,.(R,): Ry MILA] 1 Sand R,, Ry ROR, +B, 1 MOV 6000,R,; M[6000}—-R, 2 = fet Machine Halts 1 2 Q5 Consider that the memory is byte addressable x with word size 32 bits, and the program has o been loaded starting from memory location 3 41000 (decimal). Ifan interrupt occurs when the x CPU has been halted after executing the Halt instruction, the retum address saved in the stack will be (a) 1007 (b) 1020 (o) 1024 (@) 1028 [GATE 2004] ca ® Copyright MADE EASY[PRIME] Q.6 Consider that the memory is word addressable with word size 32 bits and the program has been loaded starting from memory location 1000 (decimal). an interrupt occurs during the ADD instruction, what willbe the retum address pushed on to the stack (@ 1007 (b) 1004 (6) 1005 (@) 1016 [GATE 2004] Q7 Let the clock cycles required for various operations be as folows. Register toffrom memory transfer: 3 cycles ‘Add with both operands in registers : 1 cycle Instruction fetch and decode: 2 cycle per word The total oycies requiredto execute the program is (29 (b) 24 (©) 23 (@) 20 [GATE 2004) Q.8 Match List- with ListHl and select the correct answer using the codes given below the lists: List List-I A. Alll=BIu] 1. Indirect Addressing B. While["A"*] 2. Indexed Addressing ©. inttemp ="X 3, Auto increment Codes: A BC @3 2 1 1 3 2 2 3 14 @1 2 3 [GATE 2005] 9 ACPUhas24-bitinstructions. A program starts, at address 300 (in decimal), Which one of the following is alegal program counter (all values in decimal) (@) 400 (b) 500 (6) 600 (@) 700 [GATE 2005] Q.10 Which of the following is/are true of the auto increment addressing mode? © Copyright MADE EASY + 4MOOqHIOM LZO0Z ALVD + ACOGHIOM 1LZ0Z ALVD MOOqHIOM LZ0Z ALVD GATE Exclusive Workbook 2021 5 Itis useful in creating self relocating code. 2, If it is included in an instruction set architecture, then an additional ALU is required for effective address calculation. 3, The amount of increments depends on the size of the data item accessed, (a) 1 only (b) 2only (c) Sonly (d) 2 and 3 only [GATE 2008] Common Data For Q.11 & Q.12 Consider a hypothetical processor is supports both 2 adress and one address instructions. Ithas 128 word memory A 16-bit instruction is placed in the one memory word. Q.11 What is the range of two address and one address instructions are supported, (a) 1to3 and 128 to 364 (©) 1 to Sand 128 to 384 (c) 0to4 and 1200 380 (6) 0108 and 64 to 256 Q.12 If two 2-address instructions are already existed. How many one address instructions can be supported. (a) 128 (0) 2 (c) 256 (a) 32 Linked Answer for Q.13 to Q.14 ‘A computer has 40-bit instruction format. It uses 1 register operand and ! memory operand. There are 128 general purpose registers and 256 M bytes of RAM Q.13 How many cifferent operations the computer can perform if the indirect bit (mode) is used as the part of the operation code (opcode). (@) 2 () 16 @7 @e I'there aren’ 2-address instructions which uses both register and memory, then how many one address instructions (which uses only memory) are possible {a) (28—n) x2? (b) (24—n) x27 (6) (2-(n-1)) x2” (6) (24 (n+ 1)) x2? 14 wwwmadeeasyprime.com6 15 até a7 a8 Electronics Engineering © Computer Organization I there are ‘n’ two address instructions which uses both register and memory, mm’ one addtess instructions which uses register operand then how many zero address instructions are possible (a) (2-1) x 2? - mi} x28 (b) [(24 =n) x 228 - mi] x2? (©) (28 — 1) x 228 m] x2 (A) [(24= 1) x 2? — mi) x2 The memory locations 1000, 1001 and 1020 have dala values 18, 1 and 16 respectively before the following program is executed MOVI R,. 1: Load Ry, 1000(R,) ADDI R,, 1000: Storel O(R,), 20; Which of the statement below is true after the programis executed? (a) Memory location 100 has value 20 (b) Memory location 1020 has value 20, (c) Memory location 1021 has value 20 (d) Memory location 1001 has value 20, [GATE 2006] Move immediate Load from memory ‘Add immediate Store immediate If we use internal data forwarding to speed up the performance of a CPU (R,, R, and R,) are registers and M[100] is amemory reference then the sequence of operations. R, > M[100] M(100]—> R, M(100] -> A, can be replaced by @) RR, (0) M[100] 9A, R,>Mf100] RR, RR (6) Ry 9M{100] (@) FR, > Ry, Ry > Ry RR, R, > M[109] [GATE 2004] Inwhich addressing mode the effective address, of the operand is generated by adding a constant value to the content of a register? (@) Absolute mode (0) Indirect mode (©) Immediate mode (d) Indexmode {ISRO 2009} wwwmadeeasyprime.com ions Ps (PRIME) Q.19 Consider a hypothetical processor with an * YOOqHIOM LZOZ ALVD + A4OOGHIOM L202 ALVD MOOqHIOM LZ0Z ALVD E a. Qu Q. ° 20 24 22 instruction of type LW R,, 20(R,). Which during execution reads a 32-bit word from memory and i in a 32-bit register R,. The elective address of the memory location is obtained by the addition of a constant 20 and the cont of register Ry. Which of the following best reflects the addressing mode implemented by this instruction fr the operand in memory {a) Immediate addressing (0) Register addressing (c) Register indirect scaled addressing (d) Base indexed addressing stores [GATE 2011] While an instruction is executed the program counter should contain the address to (a) The current instruction (0) The next sequential instruction {c) The operand {¢) The previous instruction [DRDO 2008] For which register, the effective address (6x) EA=1(0))} is (s) (2) relative base indexed (b) register indirect (c) base indexed (4) register relative A certain RISC processor has 12 register windows and 16 global registers. Each window has 8 input 16 local and 8 output register. The total number of registers in the processor is a) 312 (b) 320 (©) 296 (a) 304 [DRDO 2008] Which of the following statements about relative addressing mode is false {@) Itenables reduced instruction set (0) It allows indexing of array element with same instruction © Copyright MADE EASY[PRIME] (c) Itenabies easy relocation of data (@) It enables faster address calculation than absolute addressing [ISRO 2009] Q.24 Comparedto CISC processors, RISC processor contain (@) More register and smaller instruction set (b) Larger instruction set and less register (©) Less registers and smaller instruction set (d) More transistor elements [ISRO 2009] Q.25 Word 20 contains 40 Word 30 contains 50 Word 40 contains 60, Word 50 contains 70 Which of the following instructions loads 60 in tothe accumulator? (a) Load immediate 20 (b) Load direct 30 (©) Loadindirect 20 (d) Load indirect 30 Q.26 Consider the C struct defined below struct data { _ intmarks [100] char grade; intenumber, k struct data student The base address of student is available in register Rl. The field stuclent, grade can be accessed efficiently using (@) Post-increment addressing mode. (R1) ~ (0) Pre-decrement addressing mode. -(R1) () Register direct addressing mode. R1 (@) Index addressing mode, X(R1). where Xis an offset represented in 2's complement 16-bit representation [GATE 2017] Common Data For Q.27 & Q.28 A digital computer has memory unit with 24 baits word. The instruction set consists of 150 different operations, Allinstructions have an operation code part and an adatess part. Each instruction is stored in one word of memory. Q.27 How many bits are needed for the OP-CODE and how many bitare left for the address of the instruction © Copyright MADE EASY + 4MOOqHIOM LZO0Z ALVD + ACOGHIOM 1LZ0Z ALVD MOOqHIOM LZ0Z ALVD GATE Exclusive Workbook 2021 7 wae (©) 8,16 (6) 8.64 (a) 16,64 Q.28 Whatis the maximum available size for memory and the largest unsigned binary number that canbe accommodated in one word of memory. (a) 218, 2% 4 1 (bo) 216, 22 (e) 28, 2 (@) None of these Numerical Ques Common Data For @.29 & 2.30 Consider the following program segment. Here R,, R and R, are the general purpose registers, Instruction Operation Instruction size MOV R, {8000}; Loop: MOV A, (Fy) ADD RR, MOV (RR INC Ry DEC A; R, — [3000] 2 Re MUR] 1 RCR+R, 1 MILA 8 1 Rye Ry+t 1 RR 1 BNZ_ loop: Branch on non zero. 2 Hatt Stop 1 ‘Assume that the content of memory location 3000 is 10 and the content of the register R, is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from memory location 1000, All the numbers in decimal. Q.29 Assume that the memory is word addressable, The number of memory references for accessing the data in executing the program completely is [GATE 2007] @.30 Assume that the memory is word addressable After the execution ofthis program, the content ‘of memory location 2010 is [GATE 2007] ‘Assume that the memory is byte addressable and the word size is $2 bits, If an interrupt ‘occurs during the execution of the instruction “ING R,", what return address will be pushed on to the stack? 31 [GATE 2007] wwwmadeeasyprime.comPay 8 Electronics Engineering © Computer Organization a Q.32 Consider a three word machine instruction ADD. store instructions. The variables a,b, ¢, dand e AlRg) @B o areinitally stored in memory. The binary operators The fist operand (destination) “A(R,” uses @ usedin this expression ree can be evaluated by indexed addressing mode with A, as the index =} the machine only when the operands are in register. The second operand “@ B" uses indirect 7 ragisters, The instructions produce resultonlyina addressing mode A and B are memory |py register. no intermediate results can be stored addresses residing at the second and third © in memory. What is the minimum number of words respectively TS egstersneededto evaluate this expression Tne fist wor of the instruction species the = OP-CODE, the index register designation and = the source and destination addressing modes, During execution of ADD instruction the two operands are added and stored in the O destination (First Operand) 2S The number of memory oycles needed duting the execution cycle ofthe instruction is . [GATE 2011] [GATE 2005} . ® Q.38 The frequency of different types of instruction Q.33 Amachine support 16-bit instruction format the D> executed by a machine [s tabulated below. size of address field is 4-bit. The computer uses a expanding OP-CODE techniques and 34 two paral cesses as Reseienoy 7 r 0 bo Rogier 30 address instruction and 100 one address IS ee 3 nstructions. The number of zero address. f3 Drect 2 instructions it can support is = Merry rat v Q.34 A computer has 256 K word memory. The S ‘Assuming two cycles are consumed for an instruction format has four fields i.e., OP-CODE, operand to be read from the memory one cycle register field to represent one of the > for index arithmetic computation and zero 60 processor registers, mode field represents | G cycles if operands are available in registers or one of 7 addressing modes and memory Sinn theinstucton tse, the average operand address field. How many instructions the fateh time (in cycles) of the machine is system supports when a 32-bit instruction is | placed in the one memory cel [DRDO 2008) Linked Answer for Q.35 & Q.36 2 ‘APC-relative mode branch instructionis 3 byteslong. The address of the instruction in decimal is 342038, Ml NX Q.85 Determine the branch target address if the ‘ otras Tt. Amachine has a 32-bit architecture, with 1-word signed displacement in the instruction is 31. = long instructions, It has 64 registers, each of @.36 What the branch adores the base and <= which is 32 bits long, It needs to suppor index registers contain the values 480220 and |= 46 instructions, which have an immediate 9 respectively (Assume base with index i : “ 5 operand in addition to two register operands addressing mode is used) e s Assuming that the immediate operand is an Q.37 Consider evaluating the following expression tres |S unsigned integer, the maximum value of t onamactine withload-storearchitecturein which immediate operand is memory canbe accessed only through load and [GATE-2014, Ans: (16383)] worwmadeeasyprime.com ora © Copyright MADE EASY[PRIME] T2. Consider a processor with byte-addressable memory, Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100), andt grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E),¢. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as folows: + Store the current value of PC in the stack ‘+ Store the value of PSW register in the stack + Load the starting address of the subroutine inPC. The content of PC just before the fetch of a CALLinstruction is (SFA0),.. After execution of the CALL instruction, the value of the stack pointer is (@) (016A), (©) (0160), (©) (0170), (a) (0172),5 [GATE-2015, Ans: (d)] T3. A hypothetical processor uses the instruction format with three fields i.e. opcode, register address fields used to represent one of the 2* registers and memory address field. A 32 bit instruction is placed in the 2 addressable ce! memory. If thete exists. ‘2’ two address instructions which uses both register and memory reference how many one address register reference instructions possible in the processor. (a) (282-*2) x 2” (b) (22-12) x (6) (2-2) x2 (A) (2829-2) x 2" (Ans: (b)} T4, Considera 16 bitprocessor in which the folowing appears in main memory starting at location 38246: 3246) 39247! 38248 The first byte of the instruction specifies the opcode and type of addressing mode used. Second byte of the instruction is the address MP Nex! Instruction © Copyright MADE EASY + 4MOOqHIOM LZO0Z ALVD + ACOGHIOM 1LZ0Z ALVD MOOqHIOM LZ0Z ALVD 15, T6, GATE Exclusive Workbook 2021 9 field. Determine the effective address of the instruction to transfer the control if the mode field uses the PC-relalive addressing mode. (a) 38234 (b) 38235 (c) 98236 (@) 38248, Ans: (¢)] Consider a hypothetical process which supports, ‘wo adairess instruction format. Instruction takes, two operands 1* operand using the register addressing mode and 2" operand using the indexed addressing mode. Processor supports 2° operations and 128 registers including the index register. Base address of the operand wil be presentin the address field ofthe instruction as a constant which occupies 20 bits space. What isthe length of the instruction (a) (B4xn) bits (b) (34 + n) bits (6) (2°x34)bits (a) (2° + 34) bits Ans: (b)] ‘A computer supports 64 kB physical memory with the following contents Memory an The following instruction is executed on the two different computers (C, and C,). Which are having the above memory specifications. C, uses the litle-endian mechanism and C, uses the big-endian mechanism Jy MOV fy, @ ry: MUL Itis a 64 bit instruction with a general purpose register size of 16 bits. Register r, contains 4002} what is the output of the above instruction when itis running on C, and C, respectively. (a) OAFCH and FCOAH (b) 2312H and 1223H (¢) FCOAH and OAFCH (0) 1223H and 2312H Ans: (o)] wwwmadeeasyprime.com10 T7. Consider the following program segment used toexecute on a hypothetical processor. Consider all the registers are of 16 bit size 4 Mov I, MOV MOV 1 OR BKAK I, AND OKA 1 LOOP ‘abel ox 0005 @XOFF7H AKOBCAH x «0005 BX OFF TH AX OBCAH BX CBX (ORJAK DX «DX (AND)AX, LooP tilex =0 Label Processor clock frequency is 1 kHz. In which data transfer operations takes 6 cycles, data manipulation operations takes 4 cycles and transfer of contral operations takes 2 cycles to execute, How much ime is required to execute the program on a above CPU (a) 92msec. (b) 28msec (c) 108msec (d) 80msec (Ans: (a)] T8. Consider a processor with 64 registers and an instruction set of size twelve, Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value. Each instruction must be stored in memory ina byte-aligned fashion. a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is [GATE-2016, Ans: (500)) Consider 1 GHz clock frequency processor, uses iferentoperand accessing modes shown below: Te. Operand Accessing Mode Register immediate Direct ‘Mem indirect indexed Auto indexed Frequency (%) 20 20 20 10 7 3 Assume that 4 cycles consumed for memory reference, 2 eycles consumed for arithmetic computation and 0 cycles consumed when the ‘operand is in register or instruction itself. What isthe average operand fetch rate of the processor. (a) 290 million words/sec (b) 294.11 million words/see wwwmadeeasyprime.com Electronics Engineering © Computer Organization (6) 394.11 million words/sec (8) 390.26 million words/sec g [Ans: (b)] =I T10. Consider the following program segment used a to execute on a hypothetical processor. 8 Fy LOAD Alo) > MUI] 8 ADD hm > Rent < Ip AND yh 5 BERRA = 1, ADD By > BERt ; Js LOAD (m). ) MIloll a Tg SUB fvig hOn-® 8 HALT | HALTS x Ig OR Ry ORIIR, . Ig ADD th > Rp Fp +R, In the processor, data transfer operations are 9 64 bit instruction ALU operations are 32 bit > instructions and branch instruction are 16 bit a instructions. Program has been loaded in the memory with a N3)—starting adaress of 2000 decimal onward. I nv aninterruptis occurred during the execution of, = the halt instruction what could be the return = acidress pushed onto the stack. ° (@) 2034 (o) 2032 ey (c) 2007 (d) 2006 iH [Ans: (b)] ©. T11. Match List- with Listll and select the correct ~ answer using the codes given below the lists: . List- A. Indirect addressing 9 B. Indexed addressing QB C. Base register addressing a List 1. Array implementation 8 2. Writing relocatable code v 3, Passing array as parameter - Codes: = ABC ° @3 12 x ) 231 r (324 8 @ 13 2 [Ans: (a)] x ora © Copyright MADE EASYALU, data-path and Control Unit Two clock cycles are needed for memory read operation Multiple Choice Questions the first one for loading address in the MAR and the next one for loading dala from the memory but into Q.1 Amicro programmed control unit the MDR (@) isfaster than ahard-wired controlunt | @ 3 The instruction “add has the register (0) facilitates easy implementation of new | > transfer interpretation instrutions Fl RR + Ry the minimum number of clock (c) is useful when very small programs are to . ‘ bern ny cycles needed for execution cycle of this (@) usually refers to the control unit of a micro |S instruction is processor a @2 ©) 3 [GATE 1987] <= (4 5 Q.2_ A typical vertical micro instruction format is | (GATE 2008] characterized by = Q.4 The instructions “call R,, Sub" is a two word (a) limited encoding with limited parallelism | 5° instruction. Assuming the PC is incremented (0) limited encoding with high degree of |5 during the fetch cycle of the first word of the parallelism * instruction. Its register transfor interpretation is (6) high degree of encoding with high degree | | erst of parallelism : (@) high degree of encoding with limited | @ PoeMIPC! pevaletism g The minimum number of CPU cycles needed [DRDO 2009) =! during the execution cycle ofthis instruction is m (@) 2 ©) 3 Common Data For Q.3 to. 0.4 nN 4 5 Consider the following data path of CPU Ss [GATE 2005] 3 “I we Q.5 The instructions “call A, Sub” is a two word [ t = instruction. Assuming the PC is incremented | { s during the fetch cycle of the first word of the S 5] @al| is] fF > instruction. Its register transfer interpretation is ° RPC +1 NG % PC MIR The minimum number of CPU cycles needed The ALU, the bus and all the registers in the data path during the execution cycle ofthis instruction is are of identical size. All operations including increment (@) 2 &) 3 of the PC and the GPR are to be caied outin the ALU. 4 5 © Copyright MADE EASY mage] wwwmadeeasyprime.com12 ae a7 as ag Q.t0 Electronics Engineering © Computer Organization Consider a CPU where all instructions require 7 cycles to complete operation. There are 140 instruction in instruction set. Itis found that 125 control signals are needed to be generated by the control unit. While designing the horizontal micro programmed control unit Single address field format is used for branch control logic, What is the minimum size of the control word and control address register (a) 125,7 (b) 125,10 (©) 135,9 (a) 135,10 [GATE 2005] Amicro programmed control memory supports 256 instructions. Every instruction an average consume 8 micro operations. The system supports 16 flag conditions and 48 control signals. Ifthe horizontal micro programming is used, what is the size of each control word let 1adldress control instruction is used (@) 61 bits (0) 63bits (c) 6 bits (a) 8 bits [GATE 2008} The control field of t-address control word has {0 support 2 groups of control signals. In the group-1 itis requires to generate either 1 or none of the 63 control signals. In the group-2 at most 4 from the remaining. What will be the minimum number of bits needed for contol ie. (@ 6 () 10 (©) 67 81 Amicro instruction is to be designed to specity none/one of the three micro operations of one kind and none or upto 6 micro operation of another kind. The minimum number of bits in the micro instruction is On (0) 5 8 (d) None of these Ahard wired CU uses 10 control signals S, to Sig in various times steps T, to T, implement 4 instruction 1, to 1, as shown below: qh Te Is h Sy $3.85 | S9,54.56 S353 SaSoS10 Sto. 5153510 S557 5.53 So www madeeasyprime.com att MOOGHIOM LZOZ ALVD + 4OOGHIOM LZ0Z ALVD 12 13 MOOqHIOM LZ0Z ALVD E ions Ps (PRIME) Which of the following pairs of expressions represent the circuit for generating control signals S, and S,, respectively. (a) T+ TT & (+h) T,+(Tptl,)T, (b) T#UpHIT, 8 Uy +) T HUH Te (0) Tyllytl,) Ty & Ul lyel, Tot, +he)T loth Ts (6) Ty4lgT lly) Tool, Teall) Tytlle Hl) Ty [GATE 2005] ‘ACPU has only three instruction J,, Z, and Jy Which uses the following signals in time steps Which of the following logie functions wil generate the hard wired control fr the signal A, (2) Ty + Toy + Ty + Ty (0) (T+ Ty + T+ Tih (6) (T,+ Teh, + (To + Tey + Ty (0) (T,+ Tel + (T, + TaN + Ty [GATE 2004] Horizontal micro programming (a) does not require use of signal decodes (©) results in larger sized micro instructions than vertical micro programming (0) use one bit for each control signal (0) Allofthe above ‘An assembly language application contains 1200 assembly language instructions. Ittakes. ‘12 second torunon benchmark. The application © Copyright MADE EASYpee Baral GATE Exclusive Workbook2021 | 43 programmer then works on the assembly Instruction Speed (cycle) Occurrence (%) language code to make betta ater this the 6) ADD 8 20 application akes 10 seconds torun. Calculate © SHIFT 4 20 the speed up a LOAD 12 20 5 Ml) STORE 2 2 @ 2 ar NY) Ifthe clock frequency is 2.3 GHz, the machine (12 (a 10 8 performance in MIPS is 8 Q.14 Consider a new instruction named branch on ‘Common Data For Q.19 to Q.21 bit set (rmmemonics bbs). The instruction "bbs |= The microinstuctons storedin the control memory of reg, pos, label” jumps to label if bit in position = 4 processor have a width of 26 bits. Each micro os of register operand reg is one. A register 7 ingtruction is divided into three fields: amicro operation 's 92 bits wide and the bits are numbered 010 field of 13 bits, a next address field (X) and a MUX 31 Bitin position 0 being the least significant.’ S| soiect field (¥). Three are 8 status bits in the inputs of Consider the following emulation of this ™ ie vu instruction on a processor that does not have . - bbs implemented can temp «reg and mask 9 Co) pares Branch to label if temp is non-zero. > [—bo—+| Register Tho variable temp is a tomporary register for | =t Increment cortect emulation, the variable mask must be generated by X onal (@) mask — 0x 1 << Pos n Momery (0) mask © Ox F111 11 >> Pos = Mux (6) mask = Pos = “1 t ot (@) mask «Oxf 8 8 inputs mero [GATE 2006] = operation r re 0 Numerical Data Type) @ 212 "ow manybite are mere nx Questions ® Q.20 How many bits are there in Y? Q.21. Whatis the size ofthe control memory in number Common Data for Q.15 to. .17 2 A2nsclock cycle processors consumes 4cyclesfor gy Wards ALU operations, 3 cycles for branches and 5 cycles | > @.22 A control unit has to be support 8 groups of for memory operations. The relative frequencies of a mutually exclusive control signals. What will be these operations are 45%, 15% and 40% respectively. the minimum number of bits saved with respect NX horizontal micro programmin 0.15 Whats the average instruction execution ime S {phorizental micro progrerrmina, (in nano seconds)? = Group | Gi] G2 [G3 [G4] G5 | Gé [G7 [Ga .16 Whatis performance in MIPS? = es [ifstel7[ifalati ° Q.17 Ifthe program contains 10° instructions. What =. @.23. Aninstruction set of a processor has 125 signals is the program execution time (in sec)? which can be divided into 5 groups of mutually 8 Q.18 The instruction mix in an application and |S exclusive signais. instruction execution speed of a hypothetical ™ Group 1: 20 signals machine are shown below: Group-2: 70 Signals © Copyright MADE EASY mene wwwimadeeasyprime.comPay 14 | Electronics Engineering © Computer Organization a Group-3: 2 Signals T3, Arrange the following configuration for CPU in Group-4: 10 Signals decreasing order of operational speeds: Group-5: 23 Signals g Hardwired control, vertical micro-programming, Jow many bits ofthe control word canbe saved] horizontal micro-programming, by using vertical micro programming over | Ml (a) Hardwired control, vertical micro- horizontal programming NX programming, vertical micro-programming [GATE 2005] S (0) Hardwired control, horizontal micro- s programming, vertical micro-programming 2 Try Yourself < (6) Horizontal micro:programming, vertical 3S micro-programming, hardwired control > (4) Vertical micro-programming, horizontal T1, A benchmark program is run on an 80 MHz E> micro-programming, hardwired control processor. The executed program consists of |S [Ans: (b)] 1,00,000 instructions with the following 5 . . T4, Consider the following IF uprog instruction mix and clock cycle count . T.: X > MAR Instruction Type [Instruction Count | CPI T,: MIMAR] > MBR integerarithmetic | __ 45000 17/2 PC +13 PC. Data vansier 32000 2/3 Ty: MBR > Y Floating point 15000 2 a What are the values of X and Y variables? Control ranster 000 z | (@) IR, PC () PC.IR What is the MIPS rate of the processor with |" (©) ACC, SP (6) IR[Adar], Ace reference to the above program = 78 A micioprogram control units required to (@) 51.61 ©) © 5 generate a total of 25 control signals. Assume (¢) 428 (@) 55.16 : that during any micro instruction at most [Ans: (a)] 2 control signals are active. Minimum number 12. Consider tho folowing micro program. 3 of bits required in the control word to generate x the required control signals is TM [Ans: (10)] T,: MBR LOC;LOC-+ A, =A, > RR, LOC) | @.26 A4-stage pipeline has the stage delays as 150, 2. Ry SLOC; LOC + R= R, > R, o 120, 160 and 140 ns respectively. Registers 3. AL»LOC;A, »LOC# A, LOC 5 tat are used benaon me sie havea dly of Sins each. Assuming constant clocking rate; 4. Ry > LOG: Ry > LOC=R, > LOC m the total ime taken to process 1000 data items Inwhich of the following options, will the result ny Con this pipeline will be (in usec) cof executing the RHS be the same as executing S [GATE 2004] the LHS irrespective of the instructions that => Q.27 ACPUas 5-stage pipeline and runs at 1 GHz follow = frequency. Instruction fetch happens in the first (@) tands (&) Tanda ° s stage of pipeline. A conditional branch instruction (6) 2ands (@) 2and 4 x computes the larget address and evaluates the [GATE 2007] 5 tage of t 8 condition in the third stage of the pipeline. The 0.23 com uge]__ uous cova |S processor slops fetching new instruction Vo] ea fae] Oe aT" PS following a conditional branch until the branch vom . ‘outcome in known. A program executes 10° = instructions out of which 20% are conditions The above circuit represents. Stages. |Q branches. If each instruction takes one cycle (2) nstates (0) (n= 1) states 4 to complete on average, then total execution (c) 2rstates (a) 2°-" states m time of the program is (in sec) Q.24 Which of he folowing arenottruein apipetined 'S [GATE 2006] processor. "3 @.28 Anon pipeline system takes 50 ns to process 1, Bypassing can handle all RAW Hazards. a task. The same task can be processed in a 2. Register renaming can eliminate all register six segment pipeline with a clock cycle of 10 nS. carried WAR Hazards s Determine the speedup ratio of the pipeline for 3, Control Hazards penalties can be eliminated 100 tasks. by dynamic branch prediction. (ime ©) es 8 Common Data For @.29 to 0.30 Danas fo) ts Dand 8 Consider 5-stage pipeline which allows overlapping of allinstructions except branch instruction. The target (GATE 2008] e Numerical Data Type Questions Q.25 A5 stage pipeline is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched til the current instruction is completed. What is the throughput (in MIPS) of the system if 20% of instructions are branch instructions ignore the overhead of butfer register. Each stage is having same amount of delay. The pipeline clock is 10 ns. Branch penalty of 4 cycles wwwmadeeasyprime.com of branch instruction is not available until the branch © instruction is comploted. Let each stage dolay is 20 5 ns and there are 30% branch instruction. MM Q.29. Whatis the average instruction execution time Ny) (ignore the fact that some of them are Bcondtena?tnne x Q.30 What s the performance gain ofthe pipeline = ‘over non-pipelining? ° 5. @.81 Among the branch insvuctions 30% conditional and 70% of them does not salsy the concition $ (branch not taken), there is no stall ue to them F—_ Whatis average instruction execution time (inns)? cra © Copyright MADEEASY[PRIME] Q.32 Consider apipeline processor with 4 stages S, to execute the following loop: 1000; i++) (Fy Jp Jy Z} where 1 taken (in ns) by instructions J, to /, for stage S, to S, are given below: Sy Sp Ss Sy The output of J, for i= 2 will be available after {in ns), [GATE 2004] A5-stage pipelined processor has instruction fotch (IF), instruction decode (ID) operand fetch (OF) perform operation (PO) and write back (WB) stages. The IF, ID, OF and WB stages take 1 clock cycle each for anyinstruction. The PO stage takes 1 clock cycle for ADD and SUB, instructions. 3 clock cycle for MUL instruction and 6 clock cycle for DIV instruction respectively Operand forwarding is usedin the pipeline, What s the number of clock cycles needed to execute the following sequence of instructions. a.33 Instruction Meaning of Instruction Ig: MULR,, Ry, Ry Rp Ry* Ry 1, DIV Ry, Ry Ry R-AK, T,:ADD R,, RR, Rp Ro +R, 1,: SUB Ry, R,,R, Ry RR [GATE 2010] Try Yourself Ti. Consider a 6-stage instruction pipeline, where all stages are porfectly balanced. Assume that there is no cycle-time overhead of pipelining When an application is executing on this 6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles is [GATE-2014, Ans: (4)] © Copyright MADE EASY + 4MOOqHIOM LZO0Z ALVD + ACOGHIOM 1LZ0Z ALVD MOOqHIOM LZ0Z ALVD 12, 13, GATE Exclusive Workbook 2021 19 Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. P1: Fourstage pipeline with stage latencies 11ns, 2ns, 2s, 1 ns. 2: Four-stage pipeline with stage latencies 1ns, 1.578, 1.5 1s, 1.5ns. ive-stage pipeline with stage latencies 0.5 ns, 11ns, 11s, 0.6 ns, 1 ns. P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5ns, 1ns, 1s, 1.1 ns P3: Which processor has the highest peak clock frequency? (a) PI fo) PS (b) P2 (a) PA [GATE-2014, Ans: (c)] ‘An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (IDIRF), instruction execution (EX), memory access (MEM), and register write back (W8) with stage latencies 1 ns, 2.2 ns, 2 ns, 41ns and 0.75 ns, respectively (ns stands for nanoseconds). To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the EX stage is split into two stages (EX1, EX2) each of latency 1 ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions which execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage in the now design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. Allinstructions other than the branch instruction have an average CPI of one in both the designs. The ‘execution times of this program on the old and the new design are P and Q nanoseconds respectively. The value of P/Q is [GATE-2014, Ans: (1.54)] wwwmadeeasyprime.comPay 20 | Electronics Engineering * Computer Organization a T4, Consider anon-pipelined processor witha clock Program consists of 16instructions (Jy. Ig) rate of 2.5 gigahertz and average cycles per ¢ Inwhich J, is a unconditional branch instruction struction of four. The same processor is |} transfer the contralto ,,. Inthe pipeline branch upgraded to a pipelined processor with five I target address will be available al the end of stages; but dus to the internal pipeline delay, execution state, Each instruction spends the the clock speed is reduced to 2 gigahertz. 8 ‘same amount of time in all the pipeline stages. Assume that there are no stalls in the pipeline. |) Tne cycle time of the pipeline is 4ns. How much The speed up achieved in this pipelined > time is required to execute the above program processor is < without using the branch prediction? [GATE-2015, Ans: (3.2)] © (@) Téns (©) 60ns TS. Consider the sequence of machine instructions |B (6) Gans (9) 56ns ven below: ° [Ans: (c)] giver 8 MUL RS, RO, B1 Se T7. Consider pipeline x’ consist ofS stages named DIV R6, R2, RB as IF, ID, OF, EX and WB with the respective ADD R7, RS, RE . stage delays of 2ns, § ns, 6ns, 8ns and t ns. SUB RB, R?, RA a The alternative pipeline ‘y’ contain the same In the above sequence, RO to R8 are general Jo number of stages but EX stage is divided into purpose registers. n the instructions shown, | 4 sub stages, (EX1, EX2, EX8 and EX4) with the ist register stores the result of the operation equal delay i.e, (8 ns/4) and ID stage is divided performed on the second and the third 'S into 2 substages (ID1 and ID2) with equal delay registers, This sequence of instructions is to | of (5 ns/2). In the pipeline x and y memory be executed ina pipelined instruction processor reference instruction are not overlapped so the with the following 4 stages: (1) Instruction Fetch = penalty of memory reference instruction in the and Decode (IF), (2) Operand Fetch (OF), (3) S pipeline ‘x’ is 4 cycles and in the pipeline ‘y Perform Operation (PO) and (4) Write back the = is 8 cycles. If the program contain 30% of the Result (WB). The IF, OF and WB stages take © instruction as memory based instructions what telockoyele each for any nstustion.ThePO 2. is the value of (Sr / Sy). 8. speed up stage takes 1 clock cycle for ADD or SUB x/ speed up of y. instruction, 3 clock cycles for MUL instruction | © (a) 1.544 ) 1.16 and § clock cycles for DIV instruction. The (6) 0.859 (@ 075 pipelined processor uses operand forwarcing Tans: (¢)] of clock cycles taken for the execution of wo instructions (1, Jp, Iyg) used to execute on a above sequence of instructions is. XN pipelines A and B. In the program segment all IGATE-2016, Ans: (13)] by instructions are consumes same amount of time T6. Consider the 4 stage pipeline withthe following toexecute. stages. = Pipeline A is having 6 stages (S,, S,. S,, S, S,: Instruction fetch s S,, §,) with the respective stage delays of 2ns : Instruction decode = 6 ns, 5 ns, 2 ns, 8 ns and 1 ns. Pipeline B is S: Execute 8 designed with same number of stages but stage S,: Write back 2 5 will be divided into 4 sub stages using the equal delay 1.2. (8 ns/4). If the program www madeeasyprime.com ora © Copyright MADE EASY[PRIME] execution time of pipeline ‘A’ is x and the program execution time of pipeline 'B’ is y. What is the value of (x/y). (@) 1.16 () 26 (©) 16 ) 18 [Ans: (a)] T9. Consider an instruction pipeline with the following stages. IF : Instruction fetch ID: Instruction decode, OF : Operand fetch EX: Execute (ALU operations are performed), MA : Memory access (Data memory is accessed). WB : Write back. Tre following program segments executed on the pipeline. Ty: Load fy, 3¢P); fy M8 + U4) Ty: AAC Fay fay fi fy fot be Jy SUb ty, Fy 5 GOI Ty MUL fg Fs ty Fat hy Operand forwarding is used in the pipeline. All the instructions will takes one cycle on each stage to complete the execution. How long wi t take to complete the above instructions in the pipeline. (@) 10cycles (©) Soycies (©) Bcycles () 12eycles [Ans: (a)] T10. Consider the following code sequence having fveinstructions 10, Eachof hese instructions has the folowing format. OP Ry Ry where operation OP is performed on contents ofregisters Rand Rand the results storedin register R, 1, ADD Ry, Rp, Ry 1, MUL Bp, Ry, Ry Ig: SUB Ry, R, By 1,2 ADD Ry, Re, Ry Ig: MUL R,, Ry. Re © Copyright MADE EASY + 4MOOqHIOM LZO0Z ALVD + ACOGHIOM 1LZ0Z ALVD MOOqHIOM LZ0Z ALVD TH. 112. GATE Exclusive Workbook 2021 21 Consider the following three statements: S,: There is an anti-dependence between instructions f, and Jy S,: There is an anti-dependence between instructions J, and I, ithin an instruction pipeline an anti- dependence always creates one of more stalls. Which one of above statements is/are correct? (a) Only S, is true (©) Only 8, is true (©) Only S, and S, are true (d) Only S, and , are true [GATE-2015, Ans: (b)] Sy: The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is percent. [GATE-2016, Ans: (33.28)] Consider a3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies t,, t), and t, Such that t, = Sr, /4 = 2r, Ifthe longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is GHz, ignoring delays in the pipeline registers. [GATE-2016, Ans: (4)] wwwmadeeasyprime.com