Final Assessment Test - November 2019 Course: ECE2003- Digital Logic Design Class NBR(s): 0887 / 0891 / 0896 / 0901 / 0906 Slot: 81. Time: Three Hours Max. Marks: 100 KEEPING MOBILE PHONE/SMART WATCH, EVEN IN ‘OFF’ POSITION, IS EXAM MALPRACTICE Answer ALL Questions 1,/ @) Assume 2 10 bit binary number "0110010111" is stored in a memory. What is its content if it [6] 4g FE * i) BCD code cess 3 code ii) 84-2-1.code b) Subtract i) 12-19 “2g [a] iiya7-as o _ using 1’s complement 372). Sel he folowing orn minimum litera 5} : 7 [5] the proper don’t care condi " ) Design the eirult for the simplified Bkpiession F using NAND GIy ates j ©) Simiy he flowing Soateanexprestons EMBER conctons ‘ond spect the smi 15 j expression in products of sums form. Implement F using AOI gates F(A,B,C,D) = Ym(4,37,11,15) | +4(0.2.5) IG implement the following Booker function sng 4:1'a multiplexer and éxternel gates (5 FIA.B,CD) = 5(0,1,5, 11,12,13,14) Implemented with external gates. ii) Implement the following combinational logi le functions with the help demultiplexers and logic [5 pe lp plexers and logic 5] Fl = xy +ayz F2 = xVebye 3 = Ry + Int xy for} 4- Pasian a circuit that wll perform the folowing function: F = 4» (X + ¥ +1), ate 2-bit and output Fis 5-bit unsigned binary numbers, Use only a 2-bit are allowed. Label inputs and outputs propery. Your de where inputs X and ¥ [10] adders and no other circuit sign must be minimal j© b) Draw the state diagram for the below given Verilog HOL and d diagram developed module tee8 (ckystinp,outp); input clk,rst,inp; output reg outp; lesign a circuit with TFF for the state sis iftinp) state<=S2; & else statec! $2: iflinp) state<=53; else state<=S1; 3: iffinp) state<-50} else statec=$2;, endcase UT ys a ssign a sequential circuit with JK flipflops which counts in the following sequence: (10) 9294959796190 Vs lai-etian a Moore FEMA lwvichiT Mpfibps having » singlllPout tine and a single output-ine i A/utput of 1 is to be produced coincident with the pattern 1011 and an output of * 0 ‘produced for all the other sequences, » (10) is to be to\ {or} 10. b) Design a Mealy FSM with single input X , The output ¥ = 1, when either input sequence 010 or O11 {10} ‘has been detected on the input A consecutively, otherwise Y = 0. Draw the state diagram, state table é ‘and develop circuit diagram using delay flipflops. eee Ai