[BEEBI73 / EEEB2044 Microprocessor Systems Appendix - PIC18 Instruction Set and Special Function Registers Instruction Set Summary The PICI8 instruction set adds many enhancements 0 the previous PICmicro instruction sets, while ‘maintaining an easy migration from these PlCmicro instruction sets ‘Most instructions are a single program memory word (16-bits), but there are four instructions that require {wo program memory locations. Each single word instruction is a 16-bit word divides into an OPCODE, which specifies the instruction type and one or more operands, which further specify the operation ofthe instruction. The instruction set is highly orthogonal and is ‘grouped into four basic categories: + Byte-oriented operations + Bitoriented operations + Literal operations + Control operations The PIC1E instruction set summary in Table B lists byte-oriented, bit-oriented, literal and control ‘operations. Table A shows the opcode field descriptions. Most byte-oriented insttuctions have three operands: +. The file register (specified by f) 2. The destination of the result (specified by ‘d) 3. The accessed memory (specified by ‘a’) The file register designator ‘' specifies which file register is to be used by the instruction, ‘The destination designator ‘d’ specifies where the result of the operation is to be placed. Ifa is zero, the resultis placed in the WREG register. f'd'is one, the result is placed in the file register specified in the instruction. A bit-oriented instructions have three operands: 1. The file register (specified by f) 2. The bitin the file register (specified by b’) 3. The accessed memory (specified by ‘a’) “The bitfield designator''’ selects the number of the bit affected by the operation, while the file register designator 'f represents the number of the file in which the bit is located ‘The Iiteral instructions may use some of the folowing operands: + Aliteral value to be loaded into a file register (specified by «) + The desired FSR register to load the literal value into (speciied by ‘f) + No operand requited (specified by —) ‘The control instructions may use some of the following operands: + Aprogram memory address (specified by ‘n') +The mode of the CALL or RETURN instructions (specified by's) + The mode of the table read and table write instructions (specified by ‘m’) + No operand required (specified by —) ‘Al instructions are a single word, except for four double-word instructions. These instructions were made double-wors 10 contain the required information in 32 bits. In the second word, the 4 MSbs are ‘1's. if this second word is executed as an instruction (by itself), it will execute as a NoP. AAI single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a no. ‘The double-word instructions execute in two instruction cycies. (One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 us. If a Conditional test is true, or the program counter is. Changed as a result of an instruction, the instruction execution time is 2 ys. Two-word branch instructions (iftrue) would take 3 ps. Figure A shows the general formats that the instructions can have. All examples use the convention ‘nnh’ to represent a hexadecimal umber. The Instruction Set Summary, shown in Table B, lists the standard instructions recognized by the Microchip Assembier (MPASM™). 2uu1[BEEBI73 / EEEB2044 Microprocessor Systems Figure A: General Format for Instruction AL Byte-oriented file register operations: 15 wos os 7 0 (sae ea Pr 7 T= Drorenutsoiraion be REG ea. 22s orresutdstraton be wovegeee = Otn oreo Arcos Bark a iteraSe tose oak Bi ie repetr oo A2 —_Byteto-byte move operations (2 words) 15 wo a 1s (Souice he regio se a = TE ee ORT fo 12 Re reste (estnton) A3 —_Bitoriented fll register operations sen os 7 a a T= 3 pon he We raster pate bree kecos Bart {oreSR esl tank Storey arose 4 —Uneral operations s so 0 ode z ame lee AS Control operations GoTo latel s a7 a 5 2 a Coon ne19.8> (eral) T= BE a CAL fune_name 15 ea? 0 ae s ae se 0 ann rss Saath BRATune-name 5 10 o Bcfune_name 6 a7 o 31[BEEBI73 / EEEB2044 Microprocessor Systems Table A: OPCODE Field Descriptions a a RAM access bit/ Access Bank bit Ja = 0: RAM location in Rooess RAM / Access Bank (BSR reqlste's ignored) 8 = 3: RAM banks spected by BSR register habe Bt address within an Bi te register (0107) BSR Bonk Setct Register. Used to select the curent RAM bank ja Destination select it d= 0 tore resuttin WREG, d= 2: store result infle register face [Destination ether the WREG riser othe specified riser le ection fe [sit Register fe adress (0x00 to OsFF) a 12. Register Me address (0s000 to OFF). This the source aodress Py [12 bt Register le adress (Ox000 to OXFFF). This the destination xeress fore [Global nterupt Enable Bit 5 Literal ed, constant data or inbe nay be ether an GbR, 12: or 8 2O-b vale) abe Labet name r= [the mode of the TELPTR register for the Table Read and Table Wite instructions. Only used with Table Read) ane Table Write instructions: + No Change to register such as TELPTR with Table ads anc writes) + Postincrement register (such as TELPTR with Table reads anc wats) - Post Decrement regster (suchas TBLPTR with Table reads and wits) a Preinrement relate (cuoh ab TALPTR with Table reads and writes) rm He rtative adress (2's complement number for elatve branch instructions or the cect adaress for Calyeranch and Return instructions its OV, 2, 0G, © [ALU status bits Negative, Qvertow, 20, Digit Cary. Cary ee Program Counter Pot Program Counter Low Be Pow Program Counter igh to PpcLars Program Counter High to Latch Porare [Program Counter Uoper Byte Latch Fo Power-down bit PRODH Product of Mutipiy high bt PROD Prodvet of Mutipy lw tte = Fast Cal/Return mode select BL s= 0: Go not update intttom shadow registers ls = 2: conain regstrs loaded intytrom shadow rewsters (Fast mode) frenere iret Table Pointer (points toa Program Memory location) [rata sit Taio Latch Fro [rime out fro freporstack ce [uousod or unctanged feo watchcor Timer fence [working resister (accumuator re Dont care (Oo) HThe assembler wil generat code with x=. isthe recommenda form of use for comps Microchip sofware toot = it offset vale for incroct addressing o reports eource. ey 7b offget value or Inalect addressing of register thes destination. » tional argument nckates anindoxed accross [Mie contents of ree. = [signed to > Register bre a inthe stot eanies User defined term (font couren Page 4qil[BEEBI73 / EEEB2044 Microprocessor Systems Table B: PIC1 Instruction Set Summary Mocmoni, Opera Description Cycles] stars Atected | 16.it instruction word _Byterientog File Register Operands ‘ADOWFf.a.8 | Add WREG andr 2 N.0v,Z,06,6 ] 0010 oid mm ADOWFC —f,e,a | Ade WREG and cary bt tot a N.ov,z,06,.¢ | 010 coda mt tr anowe = t,e,a | ANDWREG witht a NZ (0001 oda ant coun ta | coor 1 z 0110 1018 tt come 4.6.2 | Complement 1 Nz 001 tide amt mH cPrseq —t.a_| Compare with WREG, skip = 102013) | Rone 0110 cots fr mr cersct —t.a | compare twitn WAEG, skip > 12013) | none 0110 o1oa ft fr corsit —t.a_| compare fwith WEG, skip < 1203) | None 0110 coda ft bece tea | Decrement a Nov,z,06,¢ | 0000 osda te et ecrs2 1.6.8 | Decrement ship ito 12013) | none 0010 t1da mmm DCFENZ —t,¢.8 | Decrement skip not 0 12013) | None 0:00 sida fff Incr t.é.a | increment 1 N.ov.2,06,¢ | cox toda mt tr morsz ——t,¢,0 | norementt, skip ro 22013) | none oon tid fit fr INFSNZ ——f,¢, | Increment, slo nat 0 12013) | Rone 0100 t0da ft fr torwe ——f,6, | ncusive OR WREG with ¢ a Nz 0001 coda rr Move tae | Mover 1 NZ 0101 ood frit Mover ts,td._ | Moves tote 2 None sn00 ff fF aun fmt tnt mower —t,a_| Move WREG of 1 None 0110 Atte me muuwe —f,—_|_ Murty WREG with 1 None (0000 oot ft fr NEGF ta | Negatet a Nov,z,06,¢ | 110 1108 mt mr Ruce t.e.0 | Rotate tft tough cary a Nz oor ida ff fit RUNGE ta. | Rotate ett fn carn a Nz 0100 oxda fmt tt RROF ,6,a | Rotate ight trough carry 1 nize 011 ooda attr RRNCE fc, | Rotateight (na cary) a Nz 0100 oda att tt ser ta | sett a None 0110 1008 ft tt SUBFWG —f,¢,0 | Subtract trem wREGUItAboxtow | 4. Nov,z,06,¢ | 101 oid mt mt suEWE —f,0,0 | Subtract WREG from a Nov.z.0c.c | oso sida tnt ft SUBWEE —f,¢.0 | Subtract WREG fromtwitnbotow | 4. Nov.z.0e,¢ | 101 toda mm mt war t.e.a | Swapnibtlesinf a None 0011 s0da fff qersz ta | Testt,shipito 102013) | None 0:10 ota ff iF XORWE __t.c.a_| Elusive OR WREG with a Nz (0001 _20da_fit_ it ‘Bit Oriented Fle Rewster Operands cr ‘ta | Stowe! 1 Rone “wood bbe" HF esr tea | atest a None 41000 ober prrsc ——1,6,0 | Bittest, skip tctear 12013) | None 1011 bona tit ft evrss —f,t,a | eittestf shpat 12013) | Rone s010 bbe fit fe ere tia | Bittoee a None 0411 ober Page S|IL[BEEBI73 / EEEB2044 Microprocessor Systems ‘Macmonic, Opera Description Cycles | Stas Altered Tei isracton word Contra Operations ee 7 Brancniteary, Ta Nene E10 0030 ana anna en 8 Branchif nogatve 12) None 3119 0220 nnn nnn exc on Brarchitnot cary 12) None 41210 0021 nnn nnn BAN on Branch f not negative 12) None 4110 0121 nnn nnn prov on Branch not overtiow 12) None 4110 0101 nnn nnn ez on Branchif not 2010 2 None 4110 0002 nan nnn ov ° Branchif overtiow 12) None 41110 0100 nnn anna BRR ‘Branch unconationally 12) None 1201 onan nnn anna ez ® Branchifzer0 12) None 4110 0000. nnn nnn cut ons | Calsubroutine 2 None 1110 1108 ike kh A111 Hk Ka Ha cuRwor (ear watchdog timer 1 0 (0000 0000 0000 0100 baw Decimal acjust WREG 1 © (9000 0000 0000 0122 coro on coro 2 None 31101121 Kk sk A111 he Ki He Nop ‘No operation 1 None (0000 0000 0000 c000 Nop: ‘No operation 2 None 1111 wx wx om Pop Pop top of return address 1 None (0000 0000 0000 0110 Pus Push top of return address 1 None (0000 0000 0000 o102 Roun Rete eat 2 None 4401 tnan nen ann Reser Softwave device RESET a a (0000 0000 2311 1132 REIRE s Retum trom iterupt enable | 2 ctercieiiec | 0000 0000 9001 00s Rew Return wth tera in WREG 2 None (0000 1100 kk kk RETURN s Return from subroutine 2 None (0000 0000 0001 ois ‘susp 60 into standby mode 1 we (0000 0000 0000 cos itera Operations "ODL Ted Werarand WRES T os a aNDLW AND literal with WREG 1 NZ (0000 1011 kkk kek ow Inclusive OR itera wih wreg | NZ (0000 1001 kkk kkk LR tk Moveiteral(azsit) — a*wors | 2 None 4110 1110 00M kkk to FSR 2 word 4111 0000. kik Kae Mowe ove iteral to B9R<3:0> a None (0000 0002 0000 kkk MovW Move itera to WREG a None (0000 1110 kkk kk MULLW Murti teat wih WREG 2 None (0000 1101 kk kk Rew k Return wth tterat in WREG 2 None (0000 1100 kkk kk suBWw ik Subsvact WREG fom tera! 1 N,0v,z,00,¢ | 0000 1000 kik tae xonLW _k Excwshe OR tteratwenwres | 2 Nz 0000 1010 Kk ‘ata momoryto and tom Program rremory Operations TaLRO* Table read 2 None ‘0000 0000 0000 1000 TaLRo*+ Table read wth postinccement None (0000 0000 0000 1002 Tatro+— Table read wth post decrement None (0000 0000 0000 1030 TeLro+* Table read with presncrement None (0000 0000 0000 1022 Tews Table wre 208) None (9000 0000 0000 1200 Touwres Table write witnpostncrement None (000 0000 0900 1101 Tauwts Table write witn post docrement None (2000 0000 0900 1210 rau Tablo write with proineremont None (0000 0000 0000 1431 Page 6|11[BEEBI73 / EEEB2044 Microprocessor Systems Table C: Summary of PIC18 Special-Function Registers ‘ddr. | Name ey | eee | @x6 | aa | axa | oe2 | ata | BRO | vaeaterrecal cower | tou | — = = Topotstack upper byte (TOS<20:16>) 00000 owe | Tost | Topotstack igh inte Toscisa> (0000 0000 oxero | Tost | Toporstackiow pte (TOS (0000 0000 owe | smart | sma | sane | — Retun stack painter 000.0000 owe | roa | — = bt 21 | Holding ester for PO<20:16> 000000 (OFFA | POLAT | Hotcing register for PC (0000 0000 owe | Pot Po tow byte <7:0> (2000.0000 owes | toumu | — = watza_ | TeLPTR<20.16> 90-00 0000 ‘OnF7 | TOLPTRH | Program memory table ponte high byte TBLPTR <15:@> (0000 0000 oxe6 | TaLPTRL | Program memary table pointe low byte (TELPTR <7.0> (0000 0000 (O15 | TABLAT | Proeram meray tabelten (0000 0000 contra | pRODH | Procvet register high byte ox ‘ora | pRODL | Procuct register low be ee ‘oz | wrcon | ciesaren] Pae/creL | TuROE | mToe | Ree | TRO [INTO | REF | 0000000 cori | wrcon2 | repu | inrenco | irene: | wea? | istepcs | two | wrap | Ra | ataa aii coro | wrcons | intae [irae [ovrae | orae [ina | mtar | intar | wvtaie | 21000000 ‘OWFEF | INDFO | Uses contents of SRO to acdress data memory - vale of SRO not chang na ‘OnFEE | POSTINCO | Uses contents of FRO to address data memory vaWe of FORO postincremented| ne ‘xF60 | PostDECO | Uses contents of FSRO to asdress data memory -value of FSRO post deremented na ‘OnFeC | Princo | Uses contents of ERO to asdrese data memory -value of FSRO predneremented na onFe8 | PLUSWO | Uses contents of SRO to acdoss data memory value of FSRO ofa by vao in WREG na owes | rsnon | — = = = Indirect data memory adress pointer Ohsbyte [| —0000 coxe8 | FsRot | indirect data memory address ponte O tow byte vox oes | wre | Working reser wom (O17 | INDFL | Uses contents of FRI to address data memory value of FORA nat changed na ‘OFE6 | POSTINI | Uses contents of FSR: to asdress data memory-vawe of FRI postincremerted m3 ‘025 | PostDeca | Uses contents of FSR: to acdese data memory value of FSRI post decremented na ‘nea | preinca | Uses contents of SRA to aadress data memory -value of FSRA predncremented na ‘oFe3 | PLuSWa | Uses contents of FERS to access data memory -value of FSRA offset by value in WREG na owe | rome | — — — = Indirect data memory adress pointer 4 h-byte | — 0000 OF: | FSRIL | inavect data memory aadress pointer 1 tow byte voor oreo | ase = = = = Bank salect register — 0000 (OFF | INDF2 | Uses contents of RZ to address data memory value of FOR2 nat changes na cove | rosTinc2 | Uses contents of FR? to access data memory vale of FSR2 postinerementee na ‘900 | POSTDEGZ | Uses contents of FSR? ta asdess data memory vale of FSR? pastdecremented na onc | PrEINc2 | Uses contents of FSR? to aadress data memory -value of FSR2 predneremented na Page 711[BEEBI73 / EEEB2044 Microprocessor Systems addr. | Name ee7 [ers | oes | ota | ats | Be2 | Btt | BO | valvecterresel ‘OxFDE | PLUSW2 | Uses contents of FER2 to aadras data memory value of FSR? offet by value n WREG na cowna | ronan | — Si = = Indiect data memory aderess peiter2h-byte | — 0000 0108 | Fst | Indirect data memory acess pointer 2 tow byte rox ows | sraus | — = = N ov z oe co | x (0107 | THROM | TinerO register high byte (0000 0000 ‘0108 | TROL | Timer0 reaister ah Byte = ‘0s | tocon | ruroon | rose | rocs | rose | Psa | rors2 | rors | torso | auaa aii coos | osccon | — — = = = — = ‘sos =) ‘owf02 | wvocon | — = imst uoen [wos [uo | wou [woo | -cocio oi | worcon | — = = = = 7 = swore | —~0 ooo | oon ven | - - wo LT por | FOR | o-tat00 cowror | twin | Timerd reister hgh ote = once | TwRIL | Thmerd register hgh byte wexae coco | ticon | rose | - ‘acess | racxeso | taoscen ] TsvNe | twracs | twrson | 0000000 conoe | twR2 | timer2 rexster 12000 0000 conrca | pra. “Tiner2 Period register wana coca | t2c0n | — T20uTes3| T20uTesd] T20uTPsi] T20uTPso] TwR2ON | T2cKeSi | T2cKPso | -000 0000 conca | sareur | Sop Receive butfer/ Transmit register = ‘orcs | ssrapo | SsP-acaress register in 20 lave mode. SSP baud rato reload register in 20 master mode (0000 0000 cower | ssestat [swe xe [ove |r s ww jus oF ‘9000 0000; owes | sscona | woor | ssrov | ssren | cxp | scpwa | ssema | ssewa | ssemo | 00000000 ‘owes | sspcona | ccen | acstar | acnor | acrec | rcen [ren | asen | cen ‘0000 0000 once | abaesh | Ayo Rocut high byto = oes | abrest | WO Resutiow bre = ‘ca | aocono | — S cass [ous2 [cxsi | caso | G0/60Ne| apon | —00 0000 coca | acona | — = veraa | verao | pores | perez | pores | ecreo | -000000 ‘wea | ancona | anew | — = = = ‘anes | ancsa | ancso | o--000 ‘onFoF | coPRan | Capture/Compare/PwM gn be vox con8e | compat | cancure/compare/PwMt iow bxte wom ‘80 | ccracon | — = poier | cio | copims | corsma | ccrina | copsmo | —20.0000 coxa | comn2H | Capture/Compare/PWMa high byte ecm ovese | corre | Capture/Compare/PWM2 iow byte a cowaa | ccrzcon | — es poze | nc2e | copawa | ccpama | ccp2na | corawo | -00 0000 ones | corns | capture/Compare/ewnis rign bj soo conre8 | comrat | Capture/Compare/PWMS iow byte = ‘owa7 | corzcon | — = pocrax | oocray | corawa | corama | copawe | ccrawo | —00 0000 ‘as | evrcon | cvmen | ovmoe [oven | ovess | cvs | ova | cvra__| evao | 00000000 sil[BEEBI73 / EEEB2044 Microprocessor Systems addr. | Name ee7 [ers | oes | ota | ats | Be2 | Btt | BO | valvecterresel ‘owes | encon | caour | ciour [caw [ou [os ema [ews | emo | 00000000 ofa | TwRaH | Tiara register high byte a (082 | TMRSL | Timerd reaister ow tte rox cowa1 | tacon | ro16 | tacce | racxes1 | tacxeso | racer | TasmNe| uracs | twRa0N | 0000 0000 ‘ow20 | esrcon [ier [oer | ov __| rspwove| — = = = (0000 — conrar | sPeRGi | UsaRTA Baud rato exter (0000 0000 oFae | RcREGI | USARTS Receive register (0000 0000 ‘oan | TaREGL | USARTI Tranem@t register (0000 0000 owac | tester osre | n0 ren [snc [— prox [taut | r90 | 0000-010 ‘owas | acstar | seen [aro | sren | onen | anven |renr | cere | axon | 0000000 onan | ceaprn | — = = — = — EEadrregistertign | —~00 oFao | cEADR | Data EEPROM Address regeter (0000 0000 ‘owas | cepara | Data EPROM Data egster (2000 0000 (onFA7 | EECON2 | Data EEPROM Control register 2 (nota physical ester = owas | cccona | ceran [ors [- FREE | wrera [wren | we RD (000 x000 onras | 1PRS = = roa | ra | twrae | copa | copse | cca | —a1 321 onraa | ARs — — Roar | Tar | Twrair | copsir | copa | copa | -00 0000 onraa | mes Ss s roa | mae | twraxe | cops | copa | ccrae | -000000 onra2 | PR = come | cep ecu [wor | trae | copap | tan oat | Re = owe | — cer acur [wor | maar | copar | 000000 onao | me. = ome | eee [sour | wore | trae | corae | 000000 oar | wrt pape [aor [ror | tmp [ssp | cceup | iwaar | true | oti onrae | mt pspr_[aor | Ror | tar | scr | cceu | twrar | TwRUF | 00000000 Fao | Pea pepe [aoe [roe | me | some | oceme | rwrae | True | 00000000 ‘ooc | wemcon | cans | — wara | waro | — = waa [wo | 00-00 ‘OF9A | TRIS) | Data direction conta reper for PORT) aaa itt (199 | TRISH | Data cretion conto ester for PORTH wut owaa | tase | — = = ‘Data dvection contol ester for PORT an 0197 | TRIS | Dota rection contol egster for PORTE ana at (0196 | TRISE | Data direction conto epeter for PORTE watt (0995 | TRISD | Dota rection conto reper for PORTO aaa coro | trISc | Data cirecion conto reper for PORTC aun onF93 | TeIs8 | Data crecion conta reper for PORTE anna ono | reisa | — TRSA6 _| Data decton convelrelster for PORTA wad tad ore | un Read PORT data latch, write PORT atch a onF90 | LaTH | Rees PORTH cata latch, woke PORTH aten = ower [urs | — = = Read PORTG data ath, wate PORTG latch = gin[BEEBI73 / EEEB2044 Microprocessor Systems addr, ee7 [ers | oes | ota | ats | Be2 | Btt | BO | valvecterresel rae | ATF Reed PORTF data late, write PORTF itch eam oan | LATE Read PORTE cata latch, write PORTE latch = ‘orFac | LATO | Rees PORTO cata atch, wrke PORTO atch rox ores | tate Read PORTC data latch, write PORTC latch wom ores | uate Read PORTE data latch, wite PORTE atch = oreo | tata = ATAS | Read PORTA ta latch, wete PORTA atch 60 cores | ports | Rees PORT pins, wite FORTH data atch reac oa onFs7_| Porth | Rees PORTH pins, wnte PORTH data ton won onrae | ponte | — = = Reed PORTG cata ath, write PORTG cata atch mo onFas | PORTE | Read PORTE pins, wite PORTF data lech vox ons | PoRTE | Read PORTE pins, wite PORTE datalatch| = cores | porto | Ras PORTO pins, wite PORTO cata atch oun onFs2 | porte | Read PORTC ins, wite PORTC data ltoh pox cnrsi | ports | Read PORTE pins, wite PORTE datalatch = rao | porta | — RAG __| Read PORTA pins writ PORTA data lath 00000 ors | twa | timer Roaster (0000 0000 oT | Pra Timers Rogster wanna ore | tacon | — ‘TaouTess] TaouTesd] TaouTPsi] taouTeSo] TwRAON | TacKPSi | TacKPSO | 000.0000 oF75 | comnat | Capture/Compare/PWM Reglstor 4 high byte poem crr7a | comrat | capture/Compara/PwM Register 4 ow byte = ont72 | ccpacon | — = pocrax | necray | copawa | ccpaa | copawa | ccrawo | 0000 0000 0972 | coeRsi | capturo/Comparo/PWM Regist § high byt woe onF71 | coerst | capture/Compare/PwM Register 5 low byte = oF70 | coescon | — = occrex | occrsy | corswa | copsma | copswa | ocrswa | 0000 0000) onFar | spane2 | USART2 Baud rao generator (0000 0000 correc | RoReG2 | USART2 Receive generator (0000 0000 ‘nro | THREG2 | USART2 Teanamn generator (0000 0000 osc | rst [core | x9 men [snc [— erch | reur | ri90 | 0000-010 corres | rostaz | sren [re — [sren | onen [oven | rere | oere | mi90 | 0000000 iol[BEEBI73 / EEEB2044 Microprocessor Systems Table D: American Standard Code for Information Interchange (ASCII) Code Table The ASCII table contains letters, numbers, contro cheracters, and other symbols. Each characteris assigned @ unique ‘Tit hexadecimal code (Hex-code) Hexcode Character __Hex-oode Character Hexcode Character __Hex-code Character ° NUL 20 sP "40 e 60, 2 OH 24 ' an a 61 a 2 six 22 ' 42 e © > a 1x 23 « 43 G 6 c 4a cor 24 $ 4a D 4 4 5 ENQ 25 % 45 E 6 e 6 ACK 26 & 46, F 6 ' 7 BEL. 27 i a7 6 or & 8 8S 28 ( 43, K 6 h 9 HT 29 1 49 © i 0A ue 2a * 4a J A i OB w 28 + 43 k ee k oc Fe 20 40 L 6 I 0D oR 20 4D M © m OE 80 2e 4. N cS a OF 81 oF Z ar ° ca ° 20 DLE 30 ° 50 P 70 P a Dea, an a 51 Q m q 2 De 32 2 52 R R r 13 Dea a a 53 s RB 8 14 ca 34 4 54 1 74 t 35 aK 35, 5 55 u 75 u 16 SYN 38 6 56 v 76 v a7 ETE 37 i 57 w 7 w 18 CAN 38 8 58 x 78 x 19 —M 3 8 59 y 73 y A SUB 3A 5A Zz 7A z 16 Esc 35 5B [ 78 ( ac 5S 3c < 5c \ 7 1 20 es. 20 = 5D 1 7D ) 3E RS 3E > 5 * Te ~ oF us ar 2 SF TE DEL.