Flexible hardware architecture for AES

cryptography algorithm

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Alaoui-Ismaili, Z.;   Moussa, A.;   El Mourabit, A.;   Amechnoue, K.;  

+Alaoui-Ismaili, Z.

Lab. LTI, Nat. Sch. of Appl. Sci. (ENSA), Tangier, Morocco 

This paper appears in: Multimedia Computing and Systems, 2009. ICMCS '09. International
Conference on
Issue Date: 2-4 April 2009
On page(s): 438 - 442
Location: Ouarzazate
Print ISBN: 978-1-4244-3756-6
References Cited: 22
INSPEC Accession Number: 10890817
Digital Object Identifier: 10.1109/MMCS.2009.5256655 
Date of Current Version: 22 September 2009

Abstract
In the numeric communication, much devoted efforts are dedicated to improve security and
safety of numeric transactions. Hardware implementation of cryptography algorithm, as the AES,
is a good solution to preserve confidentiality and accessibility to the information. In this context,
this paper proposes an optimal hardware implementation of AES algorithm. Taking advantages
of dynamic partially reconfigurable of FPGA. Implementation result of the proposed architecture
shows the interest of this new approach, and confirms the contribution of the reconfigurable
FPGA for robust and optimal implementation.