MainRoutine - Ladder Diagram Page 1

Sol_Examen:MainTask:MainProgram 15/07/2013 15:52:33

Total number of rungs in routine: 17 C:\RSLogix 5000\Projects\Sol_Examen.ACD

Partida Parada On_line

0 /

On_line

Escalamiento_TT1
On_line CPT
1 Compute
Dest Pendiente
0.0
Expression (Temp_Max-Temp_Min)/(Corriente_Max-Corriente_Min)

CPT
2 Compute
Dest Transmisor_1_de_0_a_100
0.0
Expression ((Pendiente*(Corriente_TT1-Corriente_Min))+Temp_Min)

Escalamiento_TT2
On_line CPT
3 Compute
Dest Pendiente_2
0.0
Expression (Temp_Max2-Temp_Min2)/(Corriente_Max2-Corriente_Min2)

CPT
4 Compute
Dest Transmisor_2_de_0_a_100
0.0
Expression ((Pendiente_2*(Corriente_TT2-Corriente_Min2))+Temp_Min2)

GRT CPT
5 Greater Than (A>B) Compute
Source A Transmisor_1_de_0_a_100 Dest Valor_Absoluto_Diferencial
0.0 0.0
Source B Transmisor_2_de_0_a_100 Expression (Transmisor_1_de_0_a_100-Transmisor_2_de_0_a_100)
0.0

RSLogix 5000
MainRoutine - Ladder Diagram Page 2
Sol_Examen:MainTask:MainProgram 15/07/2013 15:52:33
Total number of rungs in routine: 17 C:\RSLogix 5000\Projects\Sol_Examen.ACD

LES CPT
6 Less Than (A<B) Compute
Source A Transmisor_1_de_0_a_100 Dest Valor_Absoluto_Diferencial
0.0 0.0
Source B Transmisor_2_de_0_a_100 Expression (Transmisor_2_de_0_a_100-Transmisor_1_de_0_a_100)
0.0

EQU MOV
7 Equal Move
Source A Transmisor_1_de_0_a_100 Source 0
0.0
Source B Transmisor_2_de_0_a_100 Dest Valor_Absoluto_Diferencial
0.0 0.0

MOV
8 Move
Source Valor_Absoluto_Diferencial
0.0
Dest Dif_real
0.0

LIM MOV
9 Limit Test (CIRC) Move
Low Limit 0 Source Set_Dif
0.0
Test Set_Dif Dest Torre_de_enfriamiento.SP
0.0 0.0
High Limit 20

PID
10 Proportional Integral Derivative
PID Torre_de_enfriamiento ...
Process Variable Dif_real
Tieback 0
Control Variable Control_de_Flujo
PID Master Loop 0
Inhold Bit 0
Inhold Value 0
Setpoint 0.0
Process Variable 0.0
Output % 0.0

RSLogix 5000
MainRoutine - Ladder Diagram Page 3
Sol_Examen:MainTask:MainProgram 15/07/2013 15:52:33
Total number of rungs in routine: 17 C:\RSLogix 5000\Projects\Sol_Examen.ACD

LIM Aux
11 Limit Test (CIRC)
Low Limit 0

Test Valor_Absoluto_Diferencial
0.0
High Limit 20

Aux OUT14
12 /

LIM Aux1
13 Limit Test (CIRC)
Low Limit 0

Test Transmisor_1_de_0_a_100
0.0
High Limit 100

Aux1 TTT1_Fuera_de_Rango
14 /

LIM Aux2
15 Limit Test (CIRC)
Low Limit 0

Test Transmisor_2_de_0_a_100
0.0
High Limit 100

Aux2 TTT2_Fuera_de_Rango
16 /

(End)

RSLogix 5000