Digital Circuits and Logic Design

Lecture5-2:Implementation Technology

112341 Digital Circuits and Logic Design 2010 (KTS)

Multilevel synthesis
 Multilevel synthesis

112341 Digital Circuits and Logic Design 2010 (KTS)

 Multilevel synthesis

112341 Digital Circuits and Logic Design 2010 (KTS)

 Multilevel synthesis

112341 Digital Circuits and Logic Design 2010 (KTS)

 Multilevel synthesis

112341 Digital Circuits and Logic Design 2010 (KTS)

 Factoring

112341 Digital Circuits and Logic Design 2010 (KTS)

 Factoring

112341 Digital Circuits and Logic Design 2010 (KTS)

 Fan-in problems

112341 Digital Circuits and Logic Design 2010 (KTS)

 Fan-in problems

112341 Digital Circuits and Logic Design 2010 (KTS)

Impact on wiring complexity

112341 Digital Circuits and Logic Design 2010 (KTS)

Functional decomposition

112341 Digital Circuits and Logic Design 2010 (KTS)

 Decomposition example
• Consider the following expression
– f(w,x,y,z)=xyw’+x’z+y’z
• In this form, the function requires 1 threeinput
AND gate, 2 two-input AND gates, and
1 three-input OR gate
• COST=4 gates + 10 inputs = 14
• COST=20 if NOT gates (and their inputs) are
included
• Rewrite f into the following form
– f(w,x,y,z)=(xy)w’+(x’+y’)z
• Let g(x,y)=xy and note that g’=x’+y’
112341 Digital Circuits and Logic Design 2010 (KTS)
Decomposition example

112341 Digital Circuits and Logic Design 2010 (KTS)

 Practical issues

112341 Digital Circuits and Logic Design 2010 (KTS)

 Circuit delay Time

112341 Digital Circuits and Logic Design 2010 (KTS)

Propagation and Contamination Delay

112341 Digital Circuits and Logic Design 2010 (KTS)

 Propagation and Contamination Delay

The propagation delay, tpd, is the maximum

time from when an input changes until the
output or outputs reach their final value.

The contamination delay, tcd, is the minimum

time from when an input changes until any
output starts to change its value.

112341 Digital Circuits and Logic Design 2010 (KTS)

 Critical and Short Path

112341 Digital Circuits and Logic Design 2010 (KTS)

 Critical and Short Path

The propagation delay of a combinational

circuit is the sum of the propagation delays
through each element on the critical path

The contamination delay is the sum of the

contamination delays through each element
on the short path.

112341 Digital Circuits and Logic Design 2010 (KTS)

Ex. : Multiplexer Propagation Delay

112341 Digital Circuits and Logic Design 2010 (KTS)

Ex. : Multiplexer Propagation Delay

Y
112341 Digital Circuits and Logic Design 2010 (KTS)
Ex. : Multiplexer Propagation Delay

112341 Digital Circuits and Logic Design 2010 (KTS)

Time of
glitch
a single input
transition
can cause
multiple output
transitions.
These are
called glitches
112341 Digital Circuits and Logic Design 2010 (KTS)
 Glitch

The transition across the

boundary of two prime
implicants in the K-map
indicates a possible
glitch.

Input change crosses implicant boundary

112341 Digital Circuits and Logic Design 2010 (KTS)

 Glitch

K-map without glitch Circuit without glitch

112341 Digital Circuits and Logic Design 2010 (KTS)

 Glitch

We can eliminate the glitch by adding

redundant implicants to the K-map to
cover these boundaries. This of course
comes at the cost of extra hardware.

112341 Digital Circuits and Logic Design 2010 (KTS)

 Glitch

However, simultaneous transitions on

multiple variables can also cause glitches.
These glitches cannot be fixed by adding
hardware.
Because the vast majority of interesting
systems have simultaneous transitions on
multiple variables, glitches are a fact of life
in most circuits.
112341 Digital Circuits and Logic Design 2010 (KTS)