42PJ550 Manual de Serviço

Internal Use Only
North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
PLASMA TV
SERVICE MANUAL
CHASSIS : PD01A
MODEL : 42PJ550 42PJ550-ZD

CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL62881205(1002-REV00) Printed in Korea

CONTENTS
CONTENTS ............................................................................................................................... 2
SAFETY PRECAUTIONS ...........................................................................................................3
SPECIFICATION.........................................................................................................................4
ADJUSTMENT INSTRUCTION ..................................................................................................7
TROUBLESHOOTING GUIDE .................................................................................................12
BLOCK DIAGRAM ...................................................................................................................23
EXPLODED VIEW ...................................................................................................................24
SVC. SHEET ................................................................................................................................
Copyright ©2010 LG Electronics Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the Do not use a line Isolation Transformer during this check.
servicing of a receiver whose chassis is not isolated from the AC Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor
power line. Use a transformer of adequate power rating as this between a known good earth ground (Water Pipe, Conduit, etc.)
protects the technician from accidents resulting in personal injury and the exposed metallic parts.
from electrical shocks. Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
It will also protect the receiver and it's components from being Reverse plug the AC cord into the AC outlet and repeat AC voltage
damaged by accidental shorts of the circuitry that may be measurements for each exposed metallic part. Any voltage
inadvertently introduced during the service operation. measured must not exceed 0.75 volt RMS which is corresponds to
0.5mA.
If any fuse (or Fusible Resistor) in this monitor is blown, replace it In case any measurement is out of the limits specified, there is
with the specified. possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1W), keep the resistor 10mm away from PCB.
Keep wires away from high voltage or high temperature parts. Leakage Current Hot Check circuit
Due to high vacuum and large surface area of picture tube, AC Volt-meter
extreme care should be used in handling the Picture Tube.
Do not lift the Picture tube by it's Neck.
Good Earth Ground

such as WATER PIPE,
Leakage Current Cold Check(Antenna Cold Check) CONDUIT etc.
To Instrument's 0.15uF
With the instrument AC plug removed from AC source, connect an
exposed
electrical jumper across the two AC plug prongs. Place the AC METALLIC PARTS
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone 1.5 Kohm/10W
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1MΩ and 5.2MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
V Application Range
This spec is applied to the PLASMA TV used PD01A Chassis.
V Specification
Each part is tested as below without special appointment.
(1) Temperature : 25 °C ± 5 °C (77 °F ± 9 °F), CST : 40 ± 5
(2) Relative Humidity: 65 % ± 10 %
(3) Power Voltage: Standard Input voltage (100 V - 240 V ~, 50 / 60 Hz)
* Standard Voltage of each product is marked by models.
(4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with
BOM.
(5) The receiver must be operated for about 20 minutes prior to the adjustment.
V Test Method
(1) Performance : LGE TV test method followed.
(2) Demanded other specification
Safety : CE, IEC specification
EMC : CE, IEC
V Module Specification
(1) 42” HD
No Item Specification Remark
1 Display Screen Device 106 cm (42 inch) Wide Color Display Module PDP
2 Aspect Ratio 16:9
3 PDP Module PDP42 T1####,
RGB Closed(Well) Type, Glass Filter(38 %)
Pixel Format: 1365 horiz. By 768 ver.
4 Operating Environment 1) Temp. : 0 deg ~ 40 deg
2) Humidity : 20 % ~ 80 % LGE SPEC.
5 Storage Environment 3) Temp. : -20 deg ~ 60 deg
4) Humidity : 10 % ~ 90 %
6 Input Voltage AC 100 V - 240 V ~, 50 / 60 Hz Maker LG
V Model General Specification
No Item Specification Remarks

1 Market Albania, Austria, Belgium, Bosnia, Bulgaria, 36 Country
Coratia, Czech, Denmark, Estonia, Finland,
France, Germany, Greece, Hungary, Ireland,
Italy, Kazakhstan, Latvia, Lithuania,
Luxembourg, Morocco, Netherlands, Norway,
Poland, Portugal, Romania, Russia, Serbia,
Slovenia, Spain, Sweden, Slovakia,
Switzerland, Turkey, Ukraine, UK
2 Broadcasting system 1) PAL/SECAM BG EU (PAL Market)
2) PAL/SECAM DK
3) PAL Ⅰ/Ⅱ
4) SECAM L/L’
5) DVB T
6) DVB C
3 Receiving system Analog : Upper Heterodyne
Digital : COFDM, QAM
4 Scart Jack (2EA) PAL, SECAM Scart 1 Jack is Full scart and support
RF-OUT(Analoge)
Scart 2 jack is Half scart and support
MNT-OUT.
5 Video Input (1EA) PAL, SECAM, NTSC Side AV except PJ20, PK20
6 Component Input (1EA) Y/Cb/Cr, Y/ Pb/Pr rear
7 RGB Input RGB-PC Analog (D-Sub 15Pin) except PJ20, PK20
8 HDMI Input (4EA) HDMI-PC HDMI1/DVI, HDMI2, HDMI3
HDMI-DTV 1ea : PJ20
2ea : PK30, PK20, PJ60, PJ50, PJ30
3ea : PK50, PK70
9 Audio Input (3 EA) RGB/DVI Audio, Component, AV L/R Input
10 SPDIF Out(1 EA) SPDIF Out
11 USB For SVC, S/W Download, X-Studio, DivX PJ30 doesn’t support Divx
PK20, PJ20 only for SVC
12 Bluetooth Bluetooth Phone(JPEG, MP3), Only 50/60PK550
Bluetooth Headset(mono, stereo) Profile : A2DP, BIP, FTP, GAVDP, HSP, OPP
V Chroma & Brightness (Optical)
(1) (With 38 % Glass Filter) 42T1 module
No Item Min Typ Max Unit Remark

1. White peak brightness 315 - cd/m2 (*) Peak Brightness Mode
-1/100 white Window pattern
(Typically 1% Window size)
-100IRE (255Gray)
-Picture: Vivid (Medium)
-Input: HDMI-PC(1920*1080 60Hz)
*Peak Brightness Condition may Slightly
different between sets.
148 161 -25/100 white Window pattern
2. White average brightness 46 50 cd/m2 - 100% Window White Pattern
- 100IRE(255Gray)
- Picture: Vivid(Medium )
3. Brightness uniformity -10 0 +10 % - 85IRE(216Gray) 100% Window White Pattern
- Picture: Vivid(Medium)
4. Color White X 0.270 0.285 0.300 - White : 85IRE(216Gray) 100% Window
Coordinate Y 0.283 0.293 0.303 White Pattern
Red X 0.635 0.640 - - R/G/B : 100IRE(255Gray) 100% Window
Y 0.318 0.330 0.345 White Pattern
Green X 0.242 0.300 0.305 - Picture: Vivid(Medium )
Y 0.595 0.600 - - 100% Window
Blue X - 0.150 0.158
Y - 0.065 0.075
5. Color coordinate uniformity -0.01 Average +0.01 - 85IRE 100% Window White Pattern
- Picture: Vivid(Medium)
6. Contrast ratio at dark room 100k: 1 1,000k: 1 -1/100 white window pattern(Peak mode)
-100IRE(255Gray)
-Picture: Vivid(Medium)
-Input: HDMI-PC (1920*1080 60Hz)
7. Color Cool X 0.261 0.276 0.291 - 85IRE 100% Window White Pattern
Temperature Y 0.268 0.283 0.298 Warm : ColorGamut => WIDE
Medium X 0.270 0.285 0.300 Cool : Color temperature C30
Y 0.278 0.293 0.308 Meduum : Color temperature 0
Warm X 0.298 0.313 0.328 Warm : Color temperature W30
Y 0.314 0.329 0.344
ADJUSTMENT INSTRUCTION
1. Application [Caution]
- Use ‘power on’ button of a service R/C to power on TV set.
This spec. sheet is applied to all of the PD01A chassis. - Do not connect any external input cable if there is no any
specifics.
2. Specification 3. Update S/W using Auto Download

[Caution: The module keeping condition] through the USB
- The module keeping condition: The normal temperature
condition(more than 15 °C) Caution: S/W version of USB file (xxx.epk) must be bigger than
--> Immediately the line supply. one which is downloaded previously.
- The module keeping condition: 0 °C
--> The module must be kept for more than 2 hours at the (1) Insert the USB stick to the USB socket
normal temperature. (2) A downloaded file in USB stick will be detected
- The module keeping condition: -20 °C automatically.
--> The module must be kept for more than 3 hours at the (3) If S/W version of USB file (xxx.epk) is bigger than one
normal temperature. which is downloaded previously, the message, “Copying
- The case of Gu-mi factory at the winter season. files from memory”, will appear.
--> The module must be kept for more than 5 minutes at (4) If an update procedure was completed, TV set will be
the heating zone(40 °C ~ 45 °C). turned off and on automatically.
(5) If TV set is turned on, check an updated version.
(1) The adjustment is according to the order which is * If a downloaded version is more bigger than one of which
designated and which must be followed, according to the TV set had, TV set can lost channel data. In this case,
plan which can be changed only on agreeing. you have to scan channels again.
(2) If there is no specific designation, the adjustment must be
performed in the circumstance of 25 °C ± 5 °C of
temperature and 65 % ± 10 % of relative humidity.
(3) The input voltage of the set must keep 100 V ~ 240 V, 4. After Downloading S/W, Adjust
50 / 60 Hz.
(4) Input signal Unit: Product Specification Standard. TOOL OPTION
(5) The set must be operated for about 5 minutes prior to the
adjustment. (1) Push “IN-START” button on a service R/C.
(2) Select “Tool Option 1” and Push “OK” button.
OAfter turning on RGB Full Window pattern in HEAT-RUN (3) Put the number of a below table in order of a suffix of the
Mode, the receiver must be operated. “Tool Option(X)”.
O Enter into HEAT-RUN MODE (Each model has a different number.)
1) Press the ‘POWER ON’ button on R/C for adjustment.
2) Press the ‘ADJ’ button on R/C and enter EZ ADJUST Model Tool Option1 Tool Option2 Tool Option3 Tool Option4
Select “7. Test Pattern” by using D/E(CH +/-) and press 42PJ250-ZC 25088 546 2252 3360
ENTER(V)
Select “White” by using F / G (VOL +/-) and press 42PJ350-ZA 25024 1574 35020 3360
ENTER(V) 42PJ550-ZD 24960 1574 51404 3360
42PJ650-ZA 24896 1574 51408 3360
- Set heat run should be activated without a signal generator.
- Single color patterns (RED / BLUE / GREEN) of HEAT RUN 50PJ250-ZC 37376 546 2252 3360
MODE are used to check a plasma panel. 50PJ350-ZA 37312 1574 35020 3360
50PJ550-ZD 37248 1574 51404 3360
- Caution: If you turn on a still screen more than 20 minutes
(Especially digital pattern, cross hatch pattern), an after 50PJ650-ZA 37184 1574 51408 3360
image may be made in the black level part of the screen. 50PK250-ZA 37120 1570 2252 3360
50PK350-ZB 37056 1574 51404 3360
50PK550-ZE 36992 2598 55500 11552
50PK750-ZA 36928 2598 51408 11552
60PK250-ZA 49408 1570 2252 3360
60PK550-ZE 49280 2598 55500 11552
5. ADC Calibration Procedure 6. EDID Download Procedure
(1) Input the component (480i/Horizontal Color Bar) signal to a (1) Push “ADJ” button on a service R/C.
TV set. (2) Enter EDID auto download mode by selecting ‘8. EDID
1) Input Signal Timing : Component 480i D/L’.
(Other external connection is unnecessary except the
component before executing ADC calibration.)
2) Input Signal Pattern
<Horizontal Color Bar pattern>

@ MODEL: 209 in Pattern Generator(480i Mode)
@ PATTERN : 65 in Pattern Generator(MSPG-925 (3) If you select ‘Start’ on a dialog box of the screen, EDID
SERISE) download will be begun automatically.
(4) Press ‘EXIT’ button on a service R/C.
(2) Push “ADJ” button on a service R/C. (5) EDID Data
(3) Enter internal ADC mode by selecting ‘5. ADC Calibration’. 1) HDMI (HD Models, 256 bytes)
(4) If you select ‘Start’ on a dialog box of the screen, ADC
calibration will be begun.
Caution: Don’t connect any external input cable except the

component input(480i/Horizontal_Color_Bar) to adjust
ADC calibration
2) RGB (HD Models, 128 bytes)
O Auto ADC Calibration Map(RS-232C)
NO Item CMD1 CMD2 Data0
Enter Adjust When transfer the ‘Made

A A 0 0
Adjust MODE ‘Mode In’ In’, Carry the command.
Automatically adjustment
ADC
ADC Adjust A D 1 0 (The use of a internal
Adjust
pattern)
# Adjust Sequence O EDID Data detailing (ⓐ, ⓑ, ⓒ, ⓓ, ⓔ, ⓕ)

- aa 00 00 [Enter Adjust Mode]
- xb 00 40 [Component1 Input (480i)]
- ad 00 10 [Adjust 480i Comp1]
- xb 00 60 [RGB Input (1024*768)]
- ad 00 10 [Adjust 1024*768 RGB]
- aa 00 90 End Adjust mode
ⓐ Product ID 8. POWER Supply Unit PCB Ass’y
MODEL EDID MODEL PRODUCT_ID FUNCTION Va/Vs Voltage Adjustment
ALL Model LG DTV 0001(0x01, 0x00) Analog
Caution: Both Vs and Va voltage adjustment are necessary.
ALL Model LG DTV 0001(0x01, 0x00) Digital
8-1. Model name:

ⓑ Serial No 42PJ250-ZC, 42PJ350-ZA, 42PJ550-ZD, 42PJ650-ZA
=> Controlled on production line 50PJ250-ZC, 50PJ350-ZA, 50PJ550-ZD, 50PJ650-ZA
50PK250-ZA, 50PK350-ZB, 50PK550-ZE, 50PK750-ZA
ⓒ Month, Year 60PK250-ZA, 60PK550-ZE
=> Controlled on production line:
8-2. Va/Vs Adjustment Procedure

(1) Connect positive(+) terminal of DMM to Vs/Va pin, connect
negative(-) terminal to GND.
(2) Turning ‘Vs/Va Adjust’ and adjust Vs/Va voltages to a
ⓓ Model Name value which is written on a right/top label of a module.
(deviation ; ±0.5V)
ⓔ Checksum
=> Changeable by total EDID data
FHD HD
HDMI1 0xE2 0xB4 0xAF 0xB4
HDMI2 0xE2 0xA4 0xAF 0xA4
HDMI3 0xE2 0x94 0xAF 0x94
HDMI4 - - - -
RGB 0x62 0x2F
ⓕ HDMI Port No.
O Auto EDID Download Map(RS-232C)

NO Item CMD1 CMD2 Data0
[Caution]
Enter - Each Power Supply Unit PCB assembly must be checked by
Download When transfer the ‘Made
download A A 0 0 check JIG set. (Because power PCB Ass’y damages to PDP
‘Mode In’ In’, Carry the command.
MODE Module, especially be careful)
EDID data and Automatically download - Set up “RF mode(noise)” before a voltage adjustment.
Model option Download A E 00 10 (The use of a internal - Test equipment: DMM 1EA
download Data)
9. White Balance Adjustment

7. PCMCIA CARD Check Caution: Press the POWER ON KEY on R/C before W/B
You must adjust DTV 29 Channel and insert PCMCIA CARD adjustment.
to socket.
- If PCMCIA CARD works normally, video signals will appear O Test Equipment
on screen. Color Analyzer (CS-1000, CA-100+(CH.10), CA-210(CH.10))
But it works abnormally, “No CA module” will appear on
screen. O Please adjust CA-100+ / CA-210 by CS-1000 before
measuring
[ Caution: Set up “RF mode” before launching products. You should use Channel 10 which is Matrix compensated
(White, Red, Green, Blue revised) by CS-1000 and adjust
in accordance with White balance adjustment coordinate.
9-1. Color Temperature Standards According (2) Start White-Balance adjustment, then the full white window
pattern will appear on the screen.
to CSM and Module(TBD) (3) Adjust in the place where the influx of light like floodlight
around is blocked.
CSM PLASMA
(illumination is less than 10ux).
Cool 11000K (4) Measure and adjust after sticking the Color Analyzer (CA-
Medium 9300K 100+, CA210 ) to the side of the module.
Warm 6500K
O Auto W/B Adjustment Map(RS-232C)
RS-232C COMMAND
9-2. Change Target Luminance and Range [ CMD ID DATA ]
Wb 00 00 White Balance Start
of the Auto Adjustment W/B Equipment Wb 00 FF White Balance End
- 42PJ250-ZC(42T1), 42PJ350-ZA(42T1),
42PJ550-ZD(42T1), 42PJ650-ZA(42T1),
RS-232C COMMAND CENTER
- 50PJ250-ZC(50T1), 50PJ350-ZA(50T1), [CMD ID DATA] (DEFAULT)
Min MA X
50PJ550-ZD(50T1), 50PJ650-ZA(50T1)
Cool Med Warm Cool Med Warm
- 50PK250-ZA(50R1), 50PK350-ZB(50R1),
50PK550-ZE(50R1), 50PK750-ZA(50R1) R Gain jg Ja jd 00 192 192 192 255
- 60PK250-ZA(60R1), 60PK550-ZE(60R1) G Gain jh Jb je 00 192 192 192 255
B Gain ji Jc jf 00 192 192 192 255
Target luminance 50
R Cut 64 64 64 128
Range 20 50H3
G Cut 64 64 64 128
60H3
B C ut 64 64 64 128
9-3. White Balance Adjustment Coordinate
and Color Temperature
9-5. Manual W/B Adjustment
(1) Execute the zero calibration of CA-100+ / CA-210.
(2) Press the ‘ADJ’ button on a service R/C and enter EZ
ASJUST by selecting ‘6. White Balance’.
(3) Then, 216 gray pattern will appear on the screen.
(4) Change the R/G/B-Gain as passing in 3 color coordinates
and temperatures, COOL, MEDIUM and WARM.
< Temperature: COOL >
- R-Cut / G-Cut / B-Cut is set to 64
- Control R-Gain and G-Gain.
- Each gain is limited to 192
< Temperature: MEDIUM >

- Control R-Gain and G-Gain.
[ PC (for communication through RS-232C) ? UART Baud
rate : 115200 bps < Temperature: WARM >
- Control G-Gain and B-Gain.
9-4. Automatic W/B Adjustment
(1) Internal PATTERN should be used when W/B is adjusted. (5) Press ‘EXIT’ button on a service R/C
Connect to auto controller like below.
Copyright ©2010 LG Electronics Inc. All rights reserved. - 10 - LGE Internal Use Only
<Notice> Module Heat-Run Condition for W/B 10-3. Command Set
(1) The adjustment must be performed in the circumstance of
25 °C ± 5 °C of temperature and 65 % ± 10 % of relative
humidity if there is no any specifics.
(2) Before an W/B adjustment, the module which will be used
should be placed in the circumstance of 15 °C ~ 25 °C for [Description]
above 2 hours. FOS Default write : <7mode data> write
(3) If a module was placed in the circumstance of below 15 Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart,
°C, it should be placed in the circumstance of 15 °C ~ 25 0, Phase
°C for above 2 hours or be run for above 5 minutes in an Data write : Model Name and Serial Number write in
aging environment of 60 °C. EEPROM,.
(4) Before an W/B adjustment, TV set should be run for 5
minutes at least.
11. CI+ Key Download

10. Serial Number Download
11-1. Download Procedure
10-1. Download Procedure (1) Press "Power on" button of a service R/C.(Baud rate :
(1) Press “Power on” button of a service R/C.(Baud rate : 115200 bps)
115200 bps) (2) Connect RS232-C Signal Cable.
(2) Connect RS232-C Signal Cable. (3) Write CI+ Key through RS-232-C.
(3) Write Serial number through RS-232C. (4) Check whether the key was downloaded or not at ‘In Start’
(4) Check the serial number at the Diagnostics of ‘SETUP’ menu. (Refer to below)
menu. (Refer to below).
12. Check Information (Serial No. & Model name)

Caution : Don’t download HDMI/RGB EEPROM to write a (1) Push the menu button in DTV mode.
model name. Model name dois unnecessary (2) Select the SETUP -> Diagnostics -> To set
because this model use ‘Tool Option’ to call a model (3) Check the Serial Number
name.
10-2. Signal TABLE
CMD : A0h
LENGTH : 85~94h (1~16 bytes)
ADH : EEPROM Sub Address high (00~1F)
ADL : EEPROM Sub Address low (00~FF)
Data : Write data
CS : CMD + LENGTH + ADH + ADL + Data_1 + ... +
Data_n
Delay : 20ms
TROUBLESHOOTING GUIDE
BLOCK DIAGRAM
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
400 Do not modify the original design without permission of manufacturer.
601
900
604
602
910
520
206
207
204
200
590
501
580
A12
240
201
203
120
205
A9
302
202
304
305
A10
301
303
LV1
300
570
A2
+3.3V_ST
S6_Reset
DEBUG
IC100 X100
C111
TMUE312GAB
LGE3369A (Saturn6 Non RM) 12MHz
4
SW100
5
IC102 18pF
PCM_D[0-7] R193
+3.3V NAND512W3A2CN6E +3.3V 1M
NAND FLASH MEMORY R114 D4 HWRESET B3
C112
XIN
3
100 A3
C102 XOUT
NC_1 NC_29 PCM_D[0] AC16 18pF
1 48 4.7uF R116 PCMD0/CI_D0
/PF_CE0 10V PCM_D[1] AA15 E6
NC_2 NC_28 10 PCMD1/CI_D1 TESTPIN/GND
H : Serial Flash 2 47 S6_Reset PCM_D[2] AA16
L : NAND Flash PCM_A[0-7] PCMD2/CI_D2
NC_3 NC_27 PCM_D[3] AC6
/PF_CE1 3 46 PCMD3/CI_D3
KDS181
H : 16 bit PCM_D[4] Y10 AE11 33 R1224 SPI_DI
NC_4 NC_26 C101 PCMD4/CI_D4 SPI_DI
3.9K
D100
1K
L : 8 bit 4 45 R115 Y11 AF12

AR102 62K 0.1uF PCM_D[5]
PCMD5/CI_D5 SPI_DO
33 R1230 SPI_DO
NC_5 I/O7 PCM_A[7] PCM_D[6] Y12 AE12 33 R1225 SPI_CS
5 44 PCMD6/CI_D6 /SPI_CS
PCM_A[0-14] PCM_D[7] Y13 AD11 33 R1226 SPI_CK
NC_6 I/O6 PCM_A[6] PCMD7/CI_D7 SPI_CK
R1240
R111
6 43
RB I/O5 PCM_A[5] PCM_A[0] AB16
/F_RB 7 42 PCM_A[1] PCM_A0/CI_A0
AC15
R I/O4 PCM_A[4] PCM_A[2] PCM_A1/CI_A1
/PF_OE 8 41 AC14
22 PCM_A[3] PCM_A2/CI_A2
E NC_25 AB14
/PF_CE0 9 40 PCM_A[4] PCM_A3/CI_A3
AC12 B5
NC_7 NC_24 PCM_A[5] PCM_A4/CI_A4 USB_DP_1 BT_DP
C105
1K
10 39 AB8 A5
10uF 6.3V BT_DM
READY
PCM_A[6] PCM_A5/CI_A5 USB_DM_1

0.1uF
NC_8 NC_23 AC13 AC10 USB

C103
11 38 PCM_A[7] PCM_A6/CI_A6 USB_DM_2 USB_DM

AA9 AB10
R112
VDD_1 VDD_2 PCM_A[8] PCM_A7/CI_A7 USB_DP_2 USB_DP

12 37 AB5 R196 R197
PCM_A[9] PCM_A8/CI_A8 15K
VSS_1 VSS_2 C106 0.1uF AA4 15K
+3.3V READY 13 36 PCM_A9/CI_A9 READY READY
PCM_A[10] V4
R105 NC_9 NC_22 PCM_A[11] PCM_A10/CI_A10
1K 14 35 Y4
PCM_A[12] PCM_A11/CI_A11
NC_10 NC_21 AB9
15 34 PCM_A[13] PCM_A12/CI_A12 R131 100
AA7 DBG_TX
CL NC_20 PCM_A[14] PCM_A13/CI_A13 +5V_ST
16 33 AD6 R130 100 AC_DET
/PF_CE1 AR103
R103
PCM_A14/CI_A14
10K
AL I/O3 PCM_A[3] PM GPIO Assignment Recommended by MStar

PF_ALE 17 32
AA14 E5 R1294 10K
W I/O2 PCM_A[2] PCM_RST PCM_RST/CI_RST GPIO_PM0/GPIO134 LED_R
/PF_WE 18 31
/PCM_CD
AB18 F5 R182 100 READY R195 AC_DET
PCM_CD/CI_CD GPIO_PM1/GPIO135
WP I/O1 PCM_A[1] Y5 G5 R185 100 10K
PF_WP 19 30 /PCM_OE /PCM_OE GPIO_PM2/GPIO136 READY MODULE_ON
AB15 H5 100
R1239
/PCM_REG R160 DISP_EN

NC_11 I/O0 PCM_A[0] PCM_REG/CI_CLK GPIO_PM3/GPIO137
20 29 AA10 F6 R186 100 RL_ON/PWR_ONOFF
/PCM_WAIT
1K
PCM_WAIT/CI_WACK GPIO_PM4/GPIO138 R134

NC_12 NC_19 22 /PCM_IRQA
AC8 G6
READY
21 28 /PCM_IRQA GPIO_PM5/INT1/GPIO139 27K DBG_RX
AC7 H6 100 R187
NC_13 NC_18 /PCM_WE /PCM_WE GPIO_PM6/INT2/GPIO140 ISP_TXD
22 27 AA5 AC17 +3.3V
/PCM_IOWR PCM_IOWR/CI_WR GPIO131/LDE/SPI_WPn1 BT_ON/OFF
R1203
R1202
NC_14 NC_17 W4 AB17 SC1_VIDEO_MUTE
AR171 /PCM_IORD
4.7K
4.7K
23 26 PCM_IOR/CI_RD GPIO130/LCK
T4 AF11 R159 100 Flash_WP_1
NC_15 NC_16 /PCM_CE /PCM_CE GPIO132/LHSYNC/SPI_WPn
24 25 /PF_CE0 AE6 AA18 R1235 22 SDA1
/PF_CE0 GPIO60/PCM2_RESET/RX1
/PF_CE1 AF6 AA17 R1236 22 SCL1
/PF_CE1 GPIO62/PCM2_CD_N/TX1
/PF_OE AA12 +3.3V
22 /PF_OE
/PF_WE AR101 AA11
/PF_WE
R1205
R1204
PF_ALE AC9
4.7K
4.7K
PF_ALE
PF_WP Y14 +3.3V
PF_AD15
/F_RB +3.3V AB11 E7 R1237 22
F_RBZ LHSYNC2/I2S_OUT_MUTE/RX1 SUB_SCL
22
R1279
AC18 R1286 0
READY
4.7K
LVSYNC/GPIO133 5V_HDMI_2
22 F8 C6 R1238 22
EEPROM EEPROM_SCL R162
UART2_TX/SCKM GPIO79/LVSYNC2/TX1 SUB_SDA
R102
+3.3V
R101
IC103 +3.3V +3.3V_ST +3.3V EEPROM_SDA R163 22 D11 F9
1K
UART2_RX/SDAM UART2_RX/GPIO84 H/W Version Opiton(F9)
1K
R1278
Serial FLASH MEMORY MX25L4005AM2C-12G PDP_SDA R164 22 AB21 F10
4.7K
USB_OCD
READY
DDCR_DA
R1233
UART2_TX/GPIO85
L102
L101
22 AC21 A6 100 R1277

4.7K
for BOOT PDP_SCL R165

DDCR_CK UART1_RX/GPIO86 MOD_ROM_RX
IC105 B6 100 R1276
CS# VCC C116 C117 MOD_ROM_TX
M24M01-HRMN6TP UART1_TX/GPIO87
SPI_CS 1 8 100pF 100pFR140 22 J1 AF5
R133
4.7K
ISP_RXD C108 C107 PCM_5V_CTL

50V 50V DDCA_CLK GPIO42/PCM2_CE_N
+3.3V 22 J2 AF10 10pF 10pF
0.1uF
READY
ISP_TXD R141 SIDE_CVBS_DET

NC VCC
DDCA_DA GPIO43/PCM2_IRQA_N 50V 50V
C104
SO HOLD# 1 8 DBG_RX R1297 100 W5 READY READY CI_TS_DATA[0-7]

SPI_DO 2 7
R104
UART_RX2
10K
C100
R135
DBG_TX R1296 100 V5 AA8 CI_TS_DATA[0]

0.1uF UART_TX2 TS0_D0
E1 WP Y8 CI_TS_DATA[1]
0
R124
3.3K
2 7
R125
3.3K
WP# SCLK TS0_D1

3 6 SPI_CK Y9 CI_TS_DATA[2]
E2 SCL
TS0_D2
3 6 AB7 CI_TS_DATA[3]
EEPROM_SCL TS0_D3
Flash_WP_1 GND SI AA6 CI_TS_DATA[4]
4 5 SPI_DI TS0_D4
VSS SDA AB6
4 5 CI_TS_DATA[5]
EEPROM_SDA TS0_D5
U4 CI_TS_DATA[6]
TS0_D6
AC5 CI_TS_DATA[7]
TS0_D7
AC4 CI_TS_SYN
TS0_SYNC
AD5 CI_TS_VAL
TS0_VLD
AB4 CI_TS_CLK
TS0_CLK
AB19 BUF_TS_DATA[0]
TS1_D0
AA20 BUF_TS_SYN
TS1_SYNC
AB13 AC19
HDCP EEPROM +5V MCU BOOT STRAP BLUETOOTH PWM0
PWM0 TS1_VLD BUF_TS_VAL_ERR
+5V PWM1 AB12 AA19 BUF_TS_CLK
PWM1 TS1_CLK
KEY_BUZZER AD12
G
PWM2
R1287 100 READY AA13 C10
10 : BOOT 51 PWM3 ET_TXD0 SC2_DET
11 : BOOT RISC 1uF B11
ET_TXD1 SC_RE2
S
IC107 +3.3V
D
A4 A9
CAT24WC08W-T +3.3V C115 SAR0
R1298
KEY1 ET_TX_CLK SC_RE1

RTR030P02
R1256 B4 C11 R1267 100+3.3V

Q104
10K
4.7K KEY2 SAR1 ET_RXD0 R1283 0 CI_EN

A0 1 VCC 100 R1242 F4 C9 5V_HDMI_3
8 LED_B
R110 R198 1K 0 R106 SAR2 ET_RXD1
A1 2 4.7K
E4 B10 R190 22 R1270
7 WP SB_MUTE SAR3 ET_TX_EN 4.7K
READY C4 A10 R191 0
PWM0 R1263 +3.3V 5V_HDMI_1 5V Tolerance
A2 3 SCL 22 R199 1K
47K IR IRIN ET_MDC
B9
6 R1257 EEPROM_SCL R1266 +3.3V ET_MDIO /FE_RESET
R1201 1K 47K R136 A11
R1292
READY
R1300
VSS SDA ET_COL SC1_DET

4 5 PWM1 0
R137
EEPROM_SDA AC11 R1269

10K
R1258 22 C114 R1200 C /CI_CD2 GPIO44 4.7K

1K R1265 READY
0.1uF +3.3V
B 4.7K BT_ON/OFF SC2_MUTE R156 100 D9
4.7K
4.7K
READY
READY
2SC3052 GPIO96
AMP_RST D10
R1271 GPIO88
Q103 +3.3V 4.7K D7
E HD GPIO90/I2S_OUT_MUTE
R1241
P101 E11
10K
12507WS-08L XC5000_RESET GPIO91

R132 0 E8
/CI_CD1 GPIO97
1
E10
ST_AMP_MUTE R1268 GPIO98
4.7K D6
2 GPIO99
READY
READY
FHD D5
4.7K
4.7K
COMP_DET GPIO103/I2S_OUT_SD3
BT_DM 3
C5
DSUB_DET GPIO102
4
R1275
R1299
BT_DP 5
B/T_HP_LOUT_AMP 7
8
P_17V
9
L103
470
C113
R1290
0.1uF
50V
E
ISA1530AC1
B Q102
C
+3.3V
R1284
47K
R1293
10K
10uF
C110
16V
C A7 R192 100
Q107 GPIO67 USB_CTL
B/T_HP_LOUT B B8 R155 100 SC1_MUTE
2SC3052
10uF
C109
GPIO68
25V
R1289
E 750
R1291
15K
R1285 B/T_HP_LOUT_AMP
220
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS MSD3368EV Platform 09/09/24
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. FLASH/NVRAM/GPIO 1 10
Copyright © 2010 LG Electronics Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
+1.26V_VDDC
Audio Mute C240

470uF
C246
0.1uF
C257
0.1uF
C264
0.1uF
C275
0.1uF
C281
0.1uF
C2000
0.1uF
C2003
0.1uF
C2005
0.1uF
16V
D202
ENKMC2838-T112
A1 +1.26V_VDDC
SB_MUTE
C
SCART2_MUTE
A2
SC2_MUTE C2032 C2033 C2034 C2035 C2036 C2037 C2038 C2039 C2040 C2041
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
D203
ENKMC2838-T112
A1
SB_MUTE
C
SCART1_MUTE
A2
SC1_MUTE
D201 +3.3V
ENKMC2838-T112 +3.3V_VDDP
A1 L210
SB_MUTE MLB-201209-0120P-N2
C
AMP_MUTE
A2
ST_AMP_MUTE
C250 C253 C258 C2026 C2004
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
+1.8V_DDR
C245 C248 C259 C266 C277 C283 C291 C296

C2010 C243
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
IC100 220uF 220uF
6.3V 6.3V
LGE3369A (Saturn6 Non RM)
F1 RXACKP AE16
CK+_HDMI1 LVA0P RXE0+
F2 RXACKN AD16
CK-_HDMI1 LVA0M RXE0-
G2 RXA0P AD15
D0+_HDMI1 LVA1P RXE1+ IC100
D0-_HDMI1
G3 RXA0N AF16
RXE1-
+1.26V_VDDC
H3 RXA1P
LVA1M
AF15 LGE3369A (Saturn6 Non RM)
D1+_HDMI1 LVA2P RXE2+
G1 RXA1N AE15
D1-_HDMI1 LVA2M RXE2-
H1 RXA2P AD13
D2+_HDMI1 LVA3P RXE3+ E16 VDDC_1 D16
H2 RXA2N AF14 GND_2
D2-_HDMI1 LVA3M RXE3- E17 VDDC_2 D17
A1 DDCD_A_DA AF13 GND_3
DDC_SDA_1 LVA4P RXE4+ E18 D18
B2 DDCD_A_CK AE13 VDDC_3
DDC_SCL_1 GND_4
LVA4M RXE4- F7 VDDC_4 D19
R258 1K A2 HOTPLUG_A GND_5
HPD1 L9 D20
LVDS OUT
AE14 VDDC_5
GND_6
LVACKP RXECK+ L10 VDDC_6 H18
C3 RXBCKP AD14 GND_7
CK+_HDMI2 LVACKM RXECK- L11 VDDC_7 H19
B1 RXBCKN GND_8
CK-_HDMI2 VDDC_8 H20
C1 RXB0P AE20
D0+_HDMI2 LVB0P RXO0+ VDDC_9 J20
C2 RXB0N AD20
D0-_HDMI2 LVB0M RXO0- L12 VDDC_10 K20
D2 RXB1P AD19 GND_9
D1+_HDMI2 LVB1P RXO1+ L13 VDDC_11 L20
D3 RXB1N AF20 GND_10
D1-_HDMI2 LVB1M RXO1- L14 VDDC_12 M20
E3 RXB2P AF19 GND_11
D2+_HDMI2 LVB2P RXO2+ L15 VDDC_13 P7
D1 RXB2N AE19 GND_12
D2-_HDMI2 LVB2M RXO2- L16 VDDC_14 R7
E1 DDCD_B_DA AD17 GND_13
DDC_SDA_2 LVB3P RXO3+ L17 T7
F3 DDCD_B_CK AF18 GND_14 VDDC_15
DDC_SCL_2 LVB3M RXO3- L18 T22
HDMI
1K E2 HOTPLUG_B AF17 GND_15 VDDC_16

HPD2 R203
LVB4P RXO4+ M9 GND_16 U7
AE17 VDDC_17
LVB4M RXO4- U20
AE8 RXCCKP VDDC_18
CK+_HDMI3 M10 GND_17 U22
AD8 RXCCKN AE18 VDDC_19
CK-_HDMI3 LVBCKP RXOCK+ M11 GND_18 V7
AD9 RXC0P AD18 VDDC_20
D0+_HDMI3 LVBCKM RXOCK- M12 V22
AF8 RXC0N GND_19 VDDC_21
D0-_HDMI3 M13 W11
AF9 RXC1P GND_20 VDDC_22
D1+_HDMI3 M14 W12
AE9 RXC1N GND_21 VDDC_23
D1-_HDMI3 M15 W19
AE10 RXC2P AA3 C229 2.2uF GND_22 VDDC_24
D2+_HDMI3 AUR0 SC1_RIN M16 W20
AD10 RXC2N Y1 C230 2.2uF GND_23 VDDC_25
D2-_HDMI3 AUL0 SC1_LIN M17 W22
AE7 DDCD_C_DA AE1 C2006 2.2uF GND_24 VDDC_26
DDC_SDA_3 AUR1 Y22
AF7 DDCD_C_CK AF3 C2007 2.2uF VDDC_27
DDC_SCL_3 AUL1 M18
HPD3 R285 1K AD7 HOTPLUG_C AE3 C2008 2.2uF GND_25 +3.3V_VDDP
AUR2 SC2_RIN N4
HDMI_CEC
R204 100 J3 CEC AUL2 AE2 C2009 2.2uF
SC2_LIN AUDIO IN N9
GND_26
H9
AA1 C2011 2.2uF GND_27 VDDP_1
AUR3 SIDE_RIN N10 H10
AB1 C2012 2.2uF GND_28 VDDP_2
AUL3 SIDE_LIN N11 H11
AB2 C2013 2.2uF GND_29 VDDP_3
AUR4 COMP_RIN N12 H12
N2 HSYNC0/SC1_ID AC2 C2014 2.2uF GND_30 VDDP_4
SC1_ID AUL4 COMP_LIN N13 N20
SCART_RGB
R210 47 N1 VSYNC0/SC1_FB AB3 C2015 2.2uF GND_31 VDDP_5

SC1_FB AUR5 PC_RIN N14 P20
R211 47 C200 0.047uF P2 RIN0P/SC1_R AC3 C2016 2.2uF GND_32 VDDP_6
SC1_R AUL5 PC_LIN W9
R212 47 C201 0.047uF R3 GIN0P/SC1_G VDDP_7
SC1_G N15 W10
R213 47 C202 0.047uF R1 BIN0P/SC1_B GND_33 VDDP_8
SC1_B N16 +3.3V_AVDD
R214 470 C203 1000pF P3 SOGIN0/SC1_CVBS GND_34
SC1_CVBS_IN N17 L209
R215 47 C204 0.047uF P1 RINM W3 C231 0.1uF R241 47 GND_35 MLB-201209-0120P-N2
SIF0P TUNER_SIF N18 W7
R216 47 C205 0.047uF T3 BINM W2 C232 0.1uF R242 47 GND_36 AVDD_AU
SIF0M P4 +1.8V_DDR
R217 47 C206 0.047uF R2 GINM GND_37
P9 C284 C293
GND_38
R243 R244 P10 G12
F11 R282 0 GND_39 AVDD_DDR_1 0.1uF 0.1uF
10K 10K SPDIF_IN PSU_ERR_DET G13
R246 22 K3 HSYNC1/DSUB_HSYNC E9 R230 100 AVDD_DDR_2
DSUB_HSYNC SPDIF_OUT SPDIF_OUT H13
R245 22 K2 VSYNC1/DSUB_VSYNC AVDD_DDR_3
DSUB_VSYNC P11 H14
R218 47 C212 0.047uF L1 RIN1P/DSUB_R GND_40 AVDD_DDR_4
DSUB
DSUB_R P12 H15

R219 47 C207 0.047uF L3 GIN1P/DSUB_G GND_41 AVDD_DDR_5
DSUB_G P13 H16
R220 47 C213 0.047uF K1 BIN1P/DSUB_B GND_42 AVDD_DDR_6
DSUB_B P14 W14
R221 470 C208 1000pF L2 SOGIN1 AF1 GND_43 AVDD_DDR_7
AUOUTR0/HP_ROUT P15 W15
AF2 R288 100 BLUETOOTH GND_44 AVDD_DDR_8
AUDIO OUT
AUOUTL0/HP_LOUT B/T_HP_LOUT P16 W16

AD3 R239 100 GND_45 AVDD_DDR_9
AUOUTR1/SC1_ROUT SC1_Rout P17 W17
R222 47 C214 0.047uF V1 RIN2P/COMP_PR+ AD1 R240 100 GND_46 AVDD_DDR_10 +3.3V
COMP_Pr SC1_Lout P18 W18
COMP
AUOUTL1/SC1_LOUT
R223 47 C215 0.047uF V2 GIN2P/COMP_Y+ AC1 R250 100 SC2_Rout GND_47 AVDD_DDR_11
COMP_Y AUOUTR2/SC2_ROUT L205
0.01uF
R224 47 C216 0.047uF U1 BIN2P/COMP_PB+ AD2 R251 100 SC2_Lout MLB-201209-0120P-N2

C2042
COMP_Pb R4 H17
R287
AUOUTL2/SC2_LOUT
0.01uF
0.01uF
0.01uF
0.01uF
22K
R225 470 C209 1000pF V3 SOGIN2 GND_48 AVDD_MEMPLL_1

C2020
C2021
C2022
C2023
R9 T20
R254
R255
R256
R257
22K
22K
22K
R238 100 J5 VSYNC2 GND_49 AVDD_MEMPLL_2 C262 C269 C285

22K
SC2_ID R10 V20 C273

GND_50 AVDD_MEMPLL_3
R11
A8 R231 22 GND_51 0.1uF 0.1uF 0.1uF 0.1uF
I2S_OUT_MCK AUDIO_MASTER_CLK R12 +3.3V
B7 R232 22 GND_52
R205 47 C210 0.047uF U3 CVBS1/SC1_CVBS I2S_OUT_WS MS_LRCK R13
SC1_CVBS_IN C7 R233 22 GND_53
0.047uF U2 CVBS2/SC2_CVBS R14
CVBS
R206 47 C211 I2S_OUT_BCK MS_SCK L207

SC2_CVBS_IN D8 R234 22 GND_54 MLB-201209-0120P-N2
R226 47 C217 0.047uF T1 CVBS3/SIDE_CVBS I2S_OUT_SD MS_LRCH R15 R20
SIDE_CVBS_IN C8 R279 100 GND_55 AVDD_LPLL
R227 47 C218 0.047uF T2 VCOM1 I2S_IN_SD C236 C237 C238 C239 +3.3V_AVDD_MPLL
22pF 22pF 22pF 22pF R16 C2030 C279 C288
READY READY READY READY GND_56
R17 H7
R207 C219 0.1uF
S-VID
47 0.047uF M1 CVBS4/S-VIDEO_Y +3.3V C235 GND_57 AVDD_MPLL 0.1uF 0.1uF

R18
R208 47 C220 0.047uF M2 CVBS6/S-VIDEO_C K4 C223 0.1uF GND_58 C255 C2025 C263
VCLAMP 0.1uF T5
H4 C233 GND_59 10uF 0.1uF
REFP T9 6.3V
R235 47 C2024 0.047uF N3 CVBS5 J4 GND_60 0.1uF
REFM 0.1uF T10
R236 47 C2019 0.047uF M3 CVBS7 G4 R229 390 GND_61
REXT C234 T11 +3.3V_AVDD
1% 0.1uF GND_62
T12 L206
R228 100 C221 0.047uF W1 CVBS0/RF_CVBS Check GND_63 MLB-201209-0120P-N2
TV/MNT
TUNER_CVBS J7
R209 100 C222 0.047uF Y3 VCOM0 AE5 C224 0.1uF AVDD_33_1
AUCOM T13 K7
AE4 GND_64 AVDD_33_2 C241 C242 C286
AUVRM T14 L7
Y2 CVBSOUT0/SC2_MNTOUT AF4 C225 10uF GND_65 AVDD_33_3
DTV/MNT_VOUT AUVRP T15 M7 0.1uF 0.1uF 0.1uF
AA2 CVBSOUT1 AD4 C226 0.1uF GND_66 AVDD_33_4
TP203 AUVAG T16 N7
C227 1uF GND_67 AVDD_33_5 +3.3V
T17
C228 4.7uF GND_68
T18
GND_69 L208
U5 W8
GND_70 AVDD_DM
W13 +3.3V MLB-201209-0120P-N2
GND_71 C287 C292
Y21 L202
GND_72 MLB-201209-0120P-N2
AA23 H8
GND_73 AVDD_USB 0.1uF 0.1uF
C2044 C2043 C256 C272
10uF 2.2uF
Close to IC 6.3V 10V 0.1uF 0.1uF
as close as possible

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS MSD3368EV Platform
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. AV IN_OUT/LVDS/POWER 2 10
AV IN_OUT/LVDS/POWER

DDR2 1.8V By CAP - Place these Caps near Memory
+1.8V_DDR +1.8V_S_DDR
L300
MLB-201209-0120P-N2
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C325
C327
C329
10uF
C330
C331
C332
C334
C336
C337
C338
C339
C340
C341
0.1uF
0.1uF
C302
C324
C326
C328
C342
C323
C314
10uF
C303
10uF
10uF
C304
C305
C306
C307
C308
C310
C312
C313
C315
C316
C317
C318
C319
C320
0.1uF 0.1uF
+1.8V_S_DDR
+1.8V_S_DDR +1.8V_S_DDR
1K 1%
R345
R301
R321
1K 1%
1%
1K
C335 1000pF
0.1uF
0.1uF
C300 1000pF
C333 0.1uF
R302 1K 1%
1%
1%
1000pF
R322
R343
IC100
IC300 IC301
1K
C311
1K
C301
C309
HYB18TC1G160C2F-2.5 LGE3369A (Saturn6 Non RM) HYB18TC512160B2F-2.5
SDDR_D[0] DQ0 G8 J2 VREF AR300 D15 VREF J2 G8 DQ0 TDDR_D[0]

SDDR_A[5] ADDR2_A[5] A_MVREF
SDDR_D[1] DQ1 G2 AR303 G2 DQ1 TDDR_D[1]
SDDR_A[3] ADDR2_A[3] BDDR2_A[9] TDDR_A[9]
SDDR_D[2] DQ2 H7 H7 DQ2 TDDR_D[2]
M8 A0 SDDR_A[0] SDDR_A[1] ADDR2_A[1] ADDR2_A[0] C13 T26 BDDR2_A[0] BDDR2_A[3] TDDR_A[3] TDDR_A[0] A0 M8
SDDR_D[3] DQ3 H3 A_DDR2_A0 B_DDR2_A0 H3 DQ3 TDDR_D[3]
A1 SDDR_A[1] SDDR_A[10] 56 56 ADDR2_A[10] ADDR2_A[1] A22 AF26 BDDR2_A[1] BDDR2_A[1] TDDR_A[1] TDDR_A[1] A1
DQ4 M3 M3 DQ4
SDDR_D[4] H1 A_DDR2_A1 B_DDR2_A1 H1 TDDR_D[4]
M7 A2 SDDR_A[2] ADDR2_A[2] B13 T25 BDDR2_A[2] BDDR2_A[10] 56 TDDR_A[10] TDDR_A[2] A2 M7
SDDR_A[0-12]
TDDR_D[0-15]
SDDR_D[5] DQ5 AR301 A_DDR2_A2 B_DDR2_A2 DQ5 TDDR_D[5]
ADDR2_A[0-12]
H9 AR304 H9
SDDR_D[0-15]
N2 A3 SDDR_A[3] SDDR_A[9] ADDR2_A[9] ADDR2_A[3] C22 AF23 BDDR2_A[3] TDDR_A[3] A3 N2

SDDR_D[6] DQ6 F1 A_DDR2_A3 B_DDR2_A3 F1 DQ6 TDDR_D[6]
N8 A4 SDDR_A[4] SDDR_A[12] ADDR2_A[12] ADDR2_A[4] A13 T24 BDDR2_A[4] TDDR_A[4] A4 N8
BDDR2_A[5] TDDR_A[5]
TDDR_A[0-12]
SDDR_D[7] DQ7 A_DDR2_A4 B_DDR2_A4 DQ7 TDDR_D[7]
BDDR2_A[0-12]
F9 A5 A23 AE23 BDDR2_A[5] A5 F9
N3 SDDR_A[5] SDDR_A[7] ADDR2_A[7] ADDR2_A[5] BDDR2_A[12] TDDR_A[12] TDDR_A[5] N3
SDDR_D[8] DQ8 C8 A_DDR2_A5 B_DDR2_A5 C8 DQ8 TDDR_D[8]
N7 A6 SDDR_A[6] AR302 ADDR2_A[6] C12 R26 BDDR2_A[6] 56 TDDR_A[6] A6 N7
SDDR_D[9] DQ9 SDDR_A[0] ADDR2_A[0] A_DDR2_A6 B_DDR2_A6 BDDR2_A[7] TDDR_A[7] DQ9 TDDR_D[9]
C2 A7 B23 AD22 BDDR2_A[7] A7 C2
P2 SDDR_A[7] ADDR2_A[7] AR305 TDDR_A[7] P2
SDDR_D[10] DQ10 D7 SDDR_A[2] ADDR2_A[2] A_DDR2_A7 B_DDR2_A7 BDDR2_A[0] TDDR_A[0] D7 DQ10 TDDR_D[10]
P8 A8 SDDR_A[8] ADDR2_A[8] B12 R25 BDDR2_A[8] TDDR_A[8] A8 P8
SDDR_D[11] DQ11 D3 SDDR_A[4] ADDR2_A[4] A_DDR2_A8 B_DDR2_A8 BDDR2_A[2] TDDR_A[2] D3 DQ11 TDDR_D[11]
P3 A9 SDDR_A[9] ADDR2_A[9] C23 AC22 BDDR2_A[9] TDDR_A[9] A9 P3
SDDR_D[12] DQ12 D1 SDDR_A[6] 56 ADDR2_A[6] A_DDR2_A9 B_DDR2_A9 BDDR2_A[4] TDDR_A[4] D1 DQ12 TDDR_D[12]
M2 A10/AP SDDR_A[10] ADDR2_A[10] B22 AD23 BDDR2_A[10] TDDR_A[10] A10/AP M2
SDDR_D[13] DQ13 SDDR_A[11] R319 56 ADDR2_A[11] A_DDR2_A10 B_DDR2_A10 BDDR2_A[6] 56 TDDR_A[6] DQ13 TDDR_D[13]
D9 A11 R24 BDDR2_A[11] A11 D9
P7 SDDR_A[11] ADDR2_A[11] A12 TDDR_A[11] P7
SDDR_D[14] DQ14 B1 SDDR_A[8] R320 56 ADDR2_A[8] A_DDR2_A11 B_DDR2_A11 BDDR2_A[11] R325 56 TDDR_A[11] B1 DQ14 TDDR_D[14]
R2 A12 SDDR_A[12] ADDR2_A[12] A24 AE22 BDDR2_A[12] TDDR_A[12] A12 R2
SDDR_D[15] DQ15 B9 A_DDR2_A12 B_DDR2_A12 BDDR2_A[8] R326 56 TDDR_A[8] B9 DQ15 TDDR_D[15]
+1.8V_S_DDR +1.8V_S_DDR
L2 BA0 SDDR_BA[0] 56 R303 ADDR2_BA[0] C24 AC23 BDDR2_BA[0] R327 56 TDDR_BA[0] BA0 L2
A_DDR2_BA0 B_DDR2_BA0
L3 BA1 SDDR_BA[1] 56 R304 ADDR2_BA[1] B24 AC24 BDDR2_BA[1] R328 56 TDDR_BA[1] BA1 L3
VDD5 A1 A_DDR2_BA1 B_DDR2_BA1 A1 VDD5
L1 BA2 SDDR_BA[2] 56 R305 ADDR2_BA[2] D24 AB22
VDD4 E1 A_DDR2_BA2 B_DDR2_BA2 E1 VDD4
R351 22 R306 ADDR2_MCLK B14 V25 BDDR2_MCLK R330 22
VDD3 J9 0 A_DDR2_MCLK B_DDR2_MCLK CK J8 J9 VDD3
READY
READY
READY
R300
R344
150
150
VDD2 M9 J8 CK SDDR_CK CK K8 M9 VDD2
VDD1 R1 K8 CK /SDDR_CK 22 R307 /ADDR2_MCLK A14 V24 /BDDR2_MCLK R331 22 CKE K2 R1 VDD1
/A_DDR2_MCLK /B_DDR2_MCLK
K2 CKE SDDR_CKE 56 R308 ADDR2_CKE D23 AB23 BDDR2_CKE R332 56 TDDR_CKE
A_DDR2_CKE B_DDR2_CKE READY
READY +1.8V_S_DDR +1.8V_S_DDR TDDR_ODT
R346 4.7K R348 4.7K ODT K9
READY
VDDQ10 A9 K9 ODT READY SDDR_ODT 56 R309 ADDR2_ODT D14 U26 BDDR2_ODT R333 56 R349 4.7K CS L8 A9 VDDQ10
R347 4.7K A_DDR2_ODT B_DDR2_ODT
VDDQ9 C1 L8 CS RAS K7 C1 VDDQ9
VDDQ8 RAS D13 U25 /BDDR2_RAS /TDDR_RAS CAS VDDQ8
C3 QIMONDA 1G K7 /SDDR_RAS 56 R310 /ADDR2_RAS R334 56 L7 QIMONDA 512M C3
/A_DDR2_RAS /B_DDR2_RAS /TDDR_CAS
VDDQ7 C7 L7 CAS /SDDR_CAS 56 R311 /ADDR2_CAS D12 U24 /BDDR2_CAS R335 56 WE K3 C7 VDDQ7
/A_DDR2_CAS /B_DDR2_CAS /TDDR_WE
VDDQ6 C9 K3 WE /SDDR_WE 56 R312 /ADDR2_WE D22 AB24 /BDDR2_WE R336 56 C9 VDDQ6
/A_DDR2_WE /B_DDR2_WE
VDDQ5 E9 E9 VDDQ5
TDDR_DQS0_P LDQS F7
VDDQ4 G1 G1 VDDQ4
F7 LDQS SDDR_DQS0_P 56 R313 ADDR2_DQS0_P B18 AB26 BDDR2_DQS0_P R337 56 UDQS B7
VDDQ3 G3 A_DDR2_DQS0 B_DDR2_DQS0 G3 VDDQ3
B7 UDQS SDDR_DQS1_P 56 R314 ADDR2_DQS1_P C17 AA26 BDDR2_DQS1_P R338 56 TDDR_DQS1_P
VDDQ2 G7 A_DDR2_DQS1 B_DDR2_DQS1 G7 VDDQ2
VDDQ1 G9 TDDR_DQM0_P LDM F3 G9 VDDQ1
F3 LDM SDDR_DQM0_P 56 R315 ADDR2_DQM0_P C18 AC25 BDDR2_DQM0_P R339 56 UDM B3
A_DDR2_DQM0 B_DDR2_DQM0
B3 UDM SDDR_DQM1_P 56 R316 ADDR2_DQM1_P A19 AC26 BDDR2_DQM1_P R340 56 TDDR_DQM1_P
A_DDR2_DQM1 B_DDR2_DQM1
VSS5 A3 TDDR_DQS0_N LDQS E8 A3 VSS5
VSS4 E3 E8 LDQS SDDR_DQS0_N 56 R317 ADDR2_DQS0_N A18 AB25 BDDR2_DQS0_N R341 56 UDQS A8 E3 VSS4
A_DDR2_DQSB0 B_DDR2_DQSB0
VSS3 J3 A8 UDQS SDDR_DQS1_N 56 R318 ADDR2_DQS1_N B17 AA25 BDDR2_DQS1_N R342 56 TDDR_DQS1_N J3 VSS3
A_DDR2_DQSB1 B_DDR2_DQSB1
VSS2 N1 N1 VSS2
AR306 AR310 NC4 L1
VSS1 P9 SDDR_D[11] ADDR2_D[11] ADDR2_D[0] B15 W25 BDDR2_D[0] BDDR2_D[11] TDDR_D[11] P9 VSS1
R3 NC4 A_DDR2_DQ0 B_DDR2_DQ0 NC5 R3
SDDR_D[12] ADDR2_D[12] ADDR2_D[1] A21 AE26 BDDR2_D[1] BDDR2_D[12] TDDR_D[12]
R7 NC5 A_DDR2_DQ1 B_DDR2_DQ1 NC6 R7
SDDR_D[9] ADDR2_D[9] ADDR2_D[2] A15 W24 BDDR2_D[2] BDDR2_D[9] TDDR_D[9]
IC300-*1 A_DDR2_DQ2 B_DDR2_DQ2 IC301-*1
HY5PS1G1631CFP-S6
VREF J2 G8
G2
DQ0
DQ1
SDDR_D[14] 56 ADDR2_D[14] ADDR2_D[3] B21 AF24 BDDR2_D[3] BDDR2_D[14] TDDR_D[14] VREF
H5PS5162FFR-S6C
J2 G8
G2
DQ0
DQ1
VSSQ10 VSSQ10
H7 DQ2 H7 DQ2
A_DDR2_DQ3 B_DDR2_DQ3
A0 M8 A0 M8
H3 DQ3 H3 DQ3
A1 M3 A1 M3
DQ4 DQ4
B2 AR311 B2
A2 H1 A2 H1
M7 DQ5 M7 DQ5
H9 H9
AR307 56
A3 N2 A3 N2
F1 DQ6 F1 DQ6
A4 A4
NC1 C21 AF25 NC1

N8 DQ7 N8 DQ7
A5 F9 A5 F9
N3 N3
ADDR2_D[4] BDDR2_D[4]
C8 DQ8 C8 DQ8
A6 N7 A6 N7
DQ9 DQ9
A2 A2
A7 C2 A7 C2
P2 DQ10 P2 DQ10
D7 D7
SDDR_D[4] ADDR2_D[4] BDDR2_D[4] TDDR_D[4]

A8 P8 A8 P8
D3 DQ11 D3 DQ11
A9 A9
VSSQ9 VSSQ9
P3 DQ12 P3 DQ12
D1 D1
A10/AP M2 A10/AP M2
D9 DQ13 D9 DQ13
A11 P7 A11 P7
DQ14 DQ14
B8 B8
A12 B1 A12 B1
R2 DQ15 R2 DQ15
B9 B9
NC2 C14 V26 NC2

BA0 L2 BA0 L2
ADDR2_D[5] BDDR2_D[5]
BA1 L3 BA1 L3
A1 VDD5 A1 VDD5
BA2
E2 E2
BDDR2_D[0-15]
L1 VDD4 VDD4
E1 E1

J9 VDD3 CK J8 J9 VDD3
CK VDD2 CK VDD2
VSSQ8 VSSQ8
J8 M9 K8 M9
CK K8 R1 VDD1 CKE K2 R1 VDD1
CKE K2
A7 A7 ODT K9
ADDR2_D[0-15]
ODT K9 A9 VDDQ10 CS L8 A9 VDDQ10

CS
RAS
CAS
WE
L8
K7
L7
K3
HYNIX 1G
C1
C3
C7
C9
VDDQ9
VDDQ8
VDDQ7
VDDQ6
R8 NC3 ADDR2_D[6] C20 AE25 BDDR2_D[6] NC3 R8

RAS
CAS
WE
K7
L7
K3
HYNIX 512M
C1
C3
C7
C9
VDDQ9
VDDQ8
VDDQ7
VDDQ6
LDQS
UDQS
F7
B7
E9
G1
G3
VDDQ5
VDDQ4
VDDQ3
VDDQ2
VSSQ7 SDDR_D[1] ADDR2_D[1] A_DDR2_DQ6 B_DDR2_DQ6 BDDR2_D[1] TDDR_D[1] VSSQ7
LDQS
UDQS
F7
B7
E9
G1
G3
VDDQ5
VDDQ4
VDDQ3
VDDQ2
D2 D2
G7 G7
G9 VDDQ1 LDM F3 G9 VDDQ1
LDM F3 UDM B3
C15 W26
UDM B3
LDQS
UDQS
E8
A8
A3
E3
J3
VSS5
VSS4
VSS3
VSS2
SDDR_D[6] 56 ADDR2_D[6] ADDR2_D[7] BDDR2_D[7] BDDR2_D[6] 56 TDDR_D[6]

LDQS
UDQS
E8
A8
A3
E3
J3
VSS5
VSS4
VSS3
VSS2
VSSQ6 VSSQ6
N1 NC4 N1
L1
P9 VSS1 P9 VSS1
NC5 R3 NC5 R3
NC6 NC6
D8 D8
R7 R7
B2 VSSQ10 B2 VSSQ10
NC1 NC1
C16 Y26
A2 VSSQ9 A2 VSSQ9
NC2 B8 NC2 B8
E2 E2
AR308 ADDR2_D[8] BDDR2_D[8] AR312

A7 VSSQ8 A7 VSSQ8
NC3 R8 NC3 R8
D2 VSSQ7 D2 VSSQ7
D8 VSSQ6 D8 VSSQ6
VSSDL E7 VSSQ5 VSSDL E7 VSSQ5
J7 J7
VDDL J1
F2
F8
H2
H8
VSSQ4
VSSQ3
VSSQ2
VSSQ1 VSSQ5 E7 VSSDL SDDR_D[15] ADDR2_D[15] A_DDR2_DQ8 B_DDR2_DQ8 BDDR2_D[15] TDDR_D[15] VSSDL E7 VSSQ5 VDDL J1
F2
F8
H2
H8
VSSQ4
VSSQ3
VSSQ2
VSSQ1
J7 ADDR2_D[9] C19 AD25 BDDR2_D[9] J7

VSSQ4 F2 SDDR_D[8] ADDR2_D[8] A_DDR2_DQ9 B_DDR2_DQ9 BDDR2_D[8] TDDR_D[8] +1.8V_S_DDR F2 VSSQ4
IC300-*2
+1.8V_S_DDR ADDR2_D[10] B16 Y25 BDDR2_D[10] IC301-*2
EDE1116AEBG-8E-F
VREF J2 G8
G2
DQ0
DQ1
VSSQ3 F8 SDDR_D[10] ADDR2_D[10] A_DDR2_DQ10 B_DDR2_DQ10 BDDR2_D[10] TDDR_D[10] F8 VSSQ3 EDE5116AJBG-8E-E
VREF J2 G8
G2
DQ0
DQ1
ADDR2_D[11] B20 AE24 BDDR2_D[11]

H7 DQ2 H7 DQ2
A0 M8 A0 M8
H3 DQ3 H3 DQ3
A1 M3 A1 M3
H1 DQ4 H1 DQ4
A2 M7 A2 M7
H9 DQ5 H9 DQ5
A3 N2 A3 N2
F1 DQ6 F1 DQ6
A4 A4
VSSQ2 56 VSSQ2
N8 DQ7 N8 DQ7
F9 F9
A5 N3 A5 N3

C8 DQ8 C8 DQ8
A6 N7 A6 N7
DQ9 DQ9
H2 H2
A7 C2 A7 C2
P2 DQ10 P2 DQ10
A8 D7 A8 D7
P8 DQ11 P8 DQ11
A9 D3 A9 D3
ADDR2_D[12] A20 AD26 BDDR2_D[12]

P3 DQ12 P3 DQ12
A10 D1 A10 D1
M2 DQ13 M2 DQ13
A11 D9 A11 D9
P7 DQ14 P7 DQ14
AR309 AR313
A12 B1 A12 B1
R2 DQ15 R2 DQ15
B9 B9
BA0
BA1
BA2
L2
L3
A1 VDD_5
VSSQ1 VDDL A_DDR2_DQ12 B_DDR2_DQ12 56 VDDL VSSQ1 BA0

BA1
L2
L3
A1 VDD_5
H8 J1 J1 H8
L1 VDD_4 VDD_4
E1 E1

J9 VDD_3 CK J8 J9 VDD_3
CK VDD_2 CK VDD_2
ADDR2_D[13] A16 Y24

J8 M9 K8 M9
CK K8 R1 VDD_1 CKE K2 R1 VDD_1
CKE
ODT
CS
K2
K9
L8
A9
C1
VDDQ_10
VDDQ_9
BDDR2_D[13] ODT
CS
RAS
K9
L8
K7
A9
C1
VDDQ_10
VDDQ_9
RAS
CAS
WE
K7
L7
K3
ELPIDA 1G C3
C7
C9
E9
VDDQ_8
VDDQ_7
VDDQ_6
VDDQ_5
SDDR_D[0] ADDR2_D[0] A_DDR2_DQ13 B_DDR2_DQ13 BDDR2_D[0] TDDR_D[0]

CAS
WE
LDQS
L7
K3
ELPIDA 512M C3
C7
C9
E9
VDDQ_8
VDDQ_7
VDDQ_6
VDDQ_5
ADDR2_D[14] B19 AD24 BDDR2_D[14]

VDDQ_4 F7 VDDQ_4
LDQS G1 UDQS G1
F7 VDDQ_3 B7 VDDQ_3
UDQS G3 G3
B7 VDDQ_2 VDDQ_2
G7 G7
G9 VDDQ_1 LDM F3 G9 VDDQ_1
LDM F3 UDM B3
UDM B3
LDQS
UDQS
E8
A8
A3
E3
J3
VSS_5
VSS_4
VSS_3
VSS_2
SDDR_D[2] ADDR2_D[2] A_DDR2_DQ14 B_DDR2_DQ14 BDDR2_D[2] TDDR_D[2]

LDQS
UDQS
E8
A8
A3
E3
J3
VSS_5
VSS_4
VSS_3
VSS_2
ADDR2_D[15] A17 AA24 BDDR2_D[15]

N1 NC_4 N1
VSS_1 L1 VSS_1
NC_5 P9 NC_5 P9
R3 R3
NC_6 R7 NC_6 R7
B2 VSSQ_10 B2 VSSQ_10
NC_1 A2 NC_1 A2
B8 VSSQ_9 B8 VSSQ_9
NC_2 E2 NC_2 E2
A7 VSSQ_8 A7 VSSQ_8
NC_3 R8 NC_3 R8
D2 VSSQ_7 D2 VSSQ_7
D8 VSSQ_6 D8 VSSQ_6
VSSDL
VDDL
J7
J1
E7
F2
F8
H2
H8
VSSQ_5
VSSQ_4
VSSQ_3
VSSQ_2
VSSQ_1
SDDR_D[5] ADDR2_D[5] BDDR2_D[5] 56 TDDR_D[5] VSSDL
VDDL
J7
J1
E7
F2
F8
H2
H8
VSSQ_5
VSSQ_4
VSSQ_3
VSSQ_2
VSSQ_1
56
IC300-*3 IC301-*3
K4T1G164QE-HCE7 K4T51163QG-HCE7
VREF J2 G8 DQ0 VREF J2 G8 DQ0

G2 DQ1 G2 DQ1
H7 DQ2 H7 DQ2
A0 M8 A0 M8
H3 DQ3 H3 DQ3
A1 M3 A1 M3
H1 DQ4 H1 DQ4
A2 M7 A2 M7
H9 DQ5 H9 DQ5
A3 N2 A3 N2
F1 DQ6 F1 DQ6
A4 N8 A4 N8
F9 DQ7 F9 DQ7
A5 N3 A5 N3
C8 DQ8 C8 DQ8
A6 N7 A6 N7
C2 DQ9 C2 DQ9
A7 P2 A7 P2
D7 DQ10 D7 DQ10
A8 P8 A8 P8
D3 DQ11 D3 DQ11
A9 P3 A9 P3
D1 DQ12 D1 DQ12
A10/AP M2 A10/AP M2
D9 DQ13 D9 DQ13
A11 P7 A11 P7
B1 DQ14 B1 DQ14
A12 R2 A12 R2
B9 DQ15 B9 DQ15
BA0 L2 BA0 L2
BA1 L3 BA1 L3
A1 VDD_5 A1 VDD_5
BA2 L1
E1 VDD_4 E1 VDD_4
J9 VDD_3 CK J8 J9 VDD_3
CK J8 M9 VDD_2 CK K8 M9 VDD_2
CK K8 R1 VDD_1 CKE K2 R1 VDD_1
CKE K2
ODT K9
ODT K9 A9 VDDQ_10 CS L8 A9 VDDQ_10
CS L8 C1 VDDQ_9 RAS K7 C1 VDDQ_9
RAS K7 SS 1G C3 VDDQ_8 CAS L7 SS 512M C3 VDDQ_8
CAS L7 C7 VDDQ_7 WE K3 C7 VDDQ_7
WE K3 C9 VDDQ_6 C9 VDDQ_6
E9 VDDQ_5 E9 VDDQ_5
LDQS F7
G1 VDDQ_4 G1 VDDQ_4
LDQS F7 UDQS B7
G3 VDDQ_3 G3 VDDQ_3
UDQS B7
G7 VDDQ_2 G7 VDDQ_2
G9 VDDQ_1 LDM F3 G9 VDDQ_1
LDM F3 UDM B3
UDM B3
A3 VSS_5 LDQS E8 A3 VSS_5

LDQS E8 E3 VSS_4 UDQS A8 E3 VSS_4
UDQS A8 J3 VSS_3 J3 VSS_3
N1 VSS_2 N1 VSS_2
NC_4 L1
P9 VSS_1 P9 VSS_1
NC_5 R3 NC_5 R3
NC_6 R7 NC_6 R7
B2 VSSQ_10 B2 VSSQ_10
NC_1 A2 NC_1 A2
B8 VSSQ_9 B8 VSSQ_9
NC_2 E2 NC_2 E2
A7 VSSQ_8 A7 VSSQ_8
NC_3 R8 NC_3 R8
D2 VSSQ_7 D2 VSSQ_7
D8 VSSQ_6 D8 VSSQ_6
VSSDL E7 VSSQ_5 VSSDL E7 VSSQ_5
J7 J7
F2 VSSQ_4 F2 VSSQ_4
F8 VSSQ_3 F8 VSSQ_3
H2 VSSQ_2 H2 VSSQ_2
VDDL J1 H8 VSSQ_1 VDDL J1 H8 VSSQ_1

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. DDR2 3 10
DDR2

DVB-CI SLOT
+5V_CI_ON
CI_DATA[0-7]
DVB-CI TS INPUT
CI_DATA[0-7]
+5V
C505
10uF
AR506 FE_TS_DATA[7]
6.3V 33
R505
EAG41860102 CI_MDI[7] FE_TS_DATA[6]

10K
CI_MDI[6]
FE_TS_DATA[0-7]
P500 FE_TS_DATA[5]
CI_MDI[5] FE_TS_DATA[4]
/CI_CD1
C501 10067972-000LF CI_MDI[4]
0.1uF
16V 35
R511 100 36 CI_DATA[3]
37 3 CI_DATA[4]
R517
AR500
10K
33 38 4 CI_DATA[5]
CI_TS_DATA[4]
39 5 CI_DATA[6]
CI_TS_DATA[5] AR507 FE_TS_DATA[3]
40 6 CI_DATA[7] 33
CI_TS_DATA[6] CI_MDI[3] FE_TS_DATA[2]
CI_TS_DATA[7] 41 7 R515 47
/PCM_CE CI_MDI[2] FE_TS_DATA[1]
42 8 CI_ADDR[10]
CI_MDI[1] FE_TS_DATA[0]
R508 10K 43 9 CI_OE CI_MDI[0]
44 10 CI_ADDR[11]
CI_IORD FE_TS_DATA[0-7]
45 11 CI_ADDR[9] +5V
CI_IOWR
46 12 CI_ADDR[8]
CI_ADDR[13]
R518
47 13
10K
CI_MDI[0]
48 14 CI_ADDR[14]
CI_MDI[1]
CI_MDI[2] 49 15 CI_WE
50 16 R516 100
CI_MDI[3] /PCM_IRQA
C503 0.1uF 51 17
R513 100 R514 0 C509
52 18 C508
GND 0.1uF
READY 53 19 READY 0.1uF
CI_MDI[4] 16V
GND
CI_MDI[5] 54 20
55 21 CI_ADDR[12]
CI_MDI[6]
CI_ADDR[7] GND
CI_MDI[7] 56 22
R509 10K 57 23 CI_ADDR[6]
PCM_RST
R503 47 58 24 CI_ADDR[5] DVB-CI HOST I/F
R500 47 59 25 CI_ADDR[4]
/PCM_WAIT
AR503 60 26 CI_ADDR[3]
REG
33 61 27 CI_ADDR[2] /PCM_CD
CI_TS_CLK
CI_TS_VAL 62 28 CI_ADDR[1]
R530
CI_TS_SYN 63 29 CI_ADDR[0] 0
CI_DATA[0] CI_EN
64 30
65 31 CI_DATA[1]
CI_ADDR[0-14] IC501
CI_TS_DATA[0] 66 32 CI_DATA[2] +3.3V_CI
33 C511
CI_TS_DATA[1] 67 33 0.1uF
CI_TS_DATA[2] 68 34 1OE VCC 16V
100
AR504 1 20
READY
TOSHIBA
R529 33 G2
2 69 G1
1 0ITO742440D
CI_TS_DATA[3]
1A1 2OE
R512
R510 100 PCM_A[0] 2 19

/CI_CD2
AR514
R507
+5V GND
10K
2Y4 1Y1
CI_ADDR[7] 3 18 CI_ADDR[0]
GND
1A2 2A4
PCM_A[1] 4 17 PCM_A[7]
R506 GND
2Y3 1Y2
10K C502 5 16
CI_ADDR[6] CI_ADDR[1]
0.1uF
16V TC74LCX244FT
1A3 READY 2A3
PCM_A[2] 6 15 PCM_A[6]
BUF_TS_SYN AR515
2Y2 1Y3
BUF_TS_VAL_ERR 7 14
CI_ADDR[5] CI_ADDR[2]
BUF_TS_CLK
1A4 2A2
PCM_A[3] 8 13 PCM_A[5]
2Y1 1Y4
CI_ADDR[4] 9 12 CI_ADDR[3]
GND 2A1
10 11 PCM_A[4]
DVB-CI SERIAL BUFFER TS
+3.3V_CI
CI_DATA[0] AR508 PCM_D[0]

33
CI_DATA[1] PCM_D[1]
DVB-CI DETECT
CI_DATA[0-7]
CI_DATA[2] PCM_D[2]
IC502 CI_DATA[3] R527 33 PCM_D[3]

+3.3V_CI +3.3V_CI
74LVC541A(PW) AR509
PCM_D[0-7]
READY
IC500
CI_DATA[4] 33 PCM_D[4]
KIC7SZ32FU
CI_DATA[5] PCM_D[5]
0.1uF
C512
IN_B 1 5 VCC CI_DATA[6] PCM_D[6]

/CI_CD2 OE1 VCC
1 20 CI_DATA[7] PCM_D[7]
R520
C510
10K
IN_A 2
/CI_CD1 16V CI_EN
GND 3 4 OUT_Y 0.1uF
A0 OE2
FE_TS_CLK 2 19
GND
R519 R521 READY CI_DATA[0-7] PCM_D[0-7]
/PCM_CD A1 Y0
FE_TS_VAL_ERR 3 18
READY
47 47
R525
AR513
A2 Y1 33
0
FE_TS_SYN 4 17 BUF_TS_CLK
AR510
BUFFER
BUF_TS_VAL_ERR 33
A3 Y2 BUF_TS_SYN CI_ADDR[8] PCM_A[8]
FE_TS_SERIAL 5 16 BUF_TS_DATA[0] CI_ADDR[9] PCM_A[9]
CI POWER ENABLE CONTROL CI_ADDR[10] PCM_A[10]
R522
10K A4 Y3 CI_ADDR[11] PCM_A[11]
+5V_CI_ON
6 15
+5V_CI Q501 L500 R523
RSR025P03 MLB-201209-0120P-N2 10K A5 Y4
S
7 14
D AR511
33
A6 Y5 CI_ADDR[12] PCM_A[12]
8 13
C500
C506 C507 CI_ADDR[13] PCM_A[13]

33K
G C504
R524
0.1uF 10uF 0.1uF

0.1uF CI_ADDR[14] PCM_A[14]
R504
22K
16V 16V
16V 16V A7 Y6
9 12
R501
READY
10K
R528 33
REG /PCM_REG
GND Y7
10 11
C AR512
R502 33
10K B Q500 CI_OE /PCM_OE
PCM_5V_CTL 2SC3052 CI_WE /PCM_WE
E CI_IORD /PCM_IORD
CI_IOWR /PCM_IOWR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. CI 4 10
DVB-CI SLOT

5V_HDMI1
20 R612
0
HPD1
20
1K R615
READY
19 C600
0.1uF 5V_HDMI1 +5V_ST
18 5V_HDMI1 5V_HDMI2 5V_HDMI3
16V
READY
R600
17
1K
R664
R660
R662
10K
10K
10K
DDC_SDA_1
A2
A1
16
IC600 ENKMC2838-T112 5V_HDMI_1 5V_HDMI_2 5V_HDMI_3
15 DDC_SCL_1
AT24C02BN-10SU-1.8 D600
R665
R661
R663
C
33K
33K
33K
14
CEC_REMOTE A0 VCC
13
1 8
CK-_HDMI1 C603
12
EAG59023302
0.1uF
A1 WP R626 R629
11 2 7
CK+ 18K 18K
10 CK+_HDMI1
REAR_H REAR_H
D0- A2 SCL
9 D0-_HDMI1 3 6
D0_GND R623 22 DDC_SCL_1
8
GND SDA
D0+ 4 5
7 D0+_HDMI1 R621 22
DDC_SDA_1
D1-
6 D1-_HDMI1
D1_GND
5
D1+
4 D1+_HDMI1
D2-
3 D2-_HDMI1
D2_GND
2
D2+
1 D2+_HDMI1
JK600
GND UI_HW_PORT1
5V_HDMI2
20 R613
0
HPD2
20
1K R616
READY
19 C601
0.1uF
18 16V
READY
R601
17 5V_HDMI2 +5V_ST
1K
16 DDC_SDA_2
15 DDC_SCL_2
IC602
+3.3V_HDMI_ST
A2
A1
14 AT24C02BN-10SU-1.8
ENKMC2838-T112
CEC_REMOTE D602
13
C
CK-_HDMI2 A0 VCC
12 1 8
EAG59023301
11 C607
CK+ A1 WP 0.1uF R649
10 2 7 R646 R632
CK+_HDMI2 18K 18K
D0- 330K R637
9
READY
D0-_HDMI2 A2 SCL 27K
MMBD301LT1G
D0_GND 3 6 DDC_SCL_2
8
R645 22
D0+ R624
7 D0+_HDMI2 GND SDA D605
4 5 DDC_SDA_2 0
D1- READY 30V
6 R642 22 R659
D1-_HDMI2
D1_GND 0
5 CEC_REMOTE HDMI_CEC
D1+ GND B D
4 D1+_HDMI2
S
D2- D604
3 D2-_HDMI2 READY
D2_GND BSS83
2
D2+ Q600
1 D2+_HDMI2 READY
G
JK601
UI_HW_PORT2
GND
SIDE HDMI
5V_HDMI3
JACK_GND R636
0 5V_HDMI3 +5V_ST
HPD3
1K R638
20
READY
19 C605
A2
A1
0.1uF
18 16V ENKMC2838-T112
READY
R631
D603
17
1K
IC603
16 DDC_SDA_3
AT24C02BN-10SU-1.8
15 DDC_SCL_3
14 A0 VCC
1 8
CEC_REMOTE
13 C608
A1 WP 0.1uF R648
SIDE_H 12 CK-_HDMI3 2 7 18K R650
18K
EAG42463001
11 SIDE_H
CK+ A2 SCL
10 CK+_HDMI3 3 6 DDC_SCL_3
D0- R643 22
9
D0-_HDMI3 GND SDA
D0_GND 4 5 DDC_SDA_3
8
R644 22
D0+
7
D0+_HDMI3
D1-
6 GND
D1-_HDMI3
D1_GND
5
D1+
4
D1+_HDMI3
D2-
3
D2-_HDMI3
D2_GND
2
D2+
1
D2+_HDMI3
UI_HW_PORT3
GND
JK603

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 5 10
HDMI

AVSS
Audio Amp
This parts are Located
R717 on AVSS area. +3.3V
R715
0
470
2200pF
4700pF
C733
L702
1uF
22K
AVSS 0.033uF +3.3V_AVDD_AMP
0.047uF
P_17V
120-ohm
C720
C702 4700pF 50V
AVSS
C713
C703
C730
R707
C736 R718
L701
0.047uF 470 +3.3V_DVDD
Separate DGND AND AVSS 120-ohm
C714 C735
C721 C775
GVDD_OUT_1
330uF 330uF
PLL_FLTP
PLL_FLTM
PVDD_A_2
PVDD_A_1
0.1uF 0.1uF 25V 25V
SSTIMER
VR_ANA
OC_ADJ
BST_A
OUT_A
AVSS
9 NC
8
1
+3.3V_AVDD_AMP SPK_L+
12
11
10
AVDD 48 PGND_AB_2 P_17V C725
13 L705 0.01uF
C704
C723 C728 TESTOUT 47 PGND_AB_1 2S AD-9060 2F 0.1uF
10uF 16V 0.1uF 14 R704
C740 3.3
MCLK 15
46 OUT_B 1S 1F 0.68uF
AUDIO_MASTER_CLK AVSS R705
R713 T-AD_9060 3.3
R702 200 OSC_RES 16
45 PVDD_B_2 DEV C726 C727
22 50V 0.1uF
18K C732 0.033uF 0.01uF
1% R714 DVSS_1 44 PVDD_B_1 0.01uF
17 C701 @netLa
SPK_L-
VR_DIG 43 BST_B
+3.3V R712 PDN

18
TAS5709PHPR 42 BST_C
WAFER-ANGLE
AC_DET 19
1K
C712 C718
C722
4.7uF
LRCLK 20
IC701 41 PVDD_C_2 SPK_L+
4
1000pF 0.1uF 10V
R725
10K R710 50V SCLK 40 PVDD_C_1
50V
0.033uF C734 SPK_R+
21 C729 0.01uF SPK_L-
C 0 L704 C717 3
R716 B R711
SDIN 22
39 OUT_C 2S AD-9060 2F 0.1uF
AMP_MUTE Q701
READY 33K R706
R709 SPK_R+
10K 2SC3052
22 SDA 38 PGND_CD_2 C739 3.3 2
E MS_LRCK 23 1S 1F 0.68uF
R703 R719
22 SCL 37 PGND_CD_1 3.3 SPK_R-
24 T-AD_9060 1
MS_SCK R708 DEV C710
0.1uF
C715
22 0.01uF P700
MS_LRCH
25
26
27
28
29
30
31
32
33
34
35
36
@netLa
SPK_R-
SDA1
PVDD_D_1
PVDD_D_2
AGND
VREG
RESET
STEST
GVDD_OUT_2
BST_D
OUT_D
GND
DVSS_2
DVDD
SCL1
P_17V
C709
1000pF
C719 C706
C708
0.1uF 0.1uF
1uF
+3.3V_DVDD C738 0.033uF

50V
AMP_RST C737
0.1uF
C711 C707
10uF 16V 0.1uF
TV_L/ROUT
TV_LOUT
Audio Out Amp
MNT/DTV OUT IC702
Q703 R794 LM324D
2SC3052
MUTE Ctrl 2K
1/16W
5% R728
2K 1 14
R729
2K
1 14 DTV/MNT_ROUT
Q706 TV_LOUT
RT1P141C-T112 C779 R785 R790 16V
33K 2 13 33K 10uF
TV_ROUT SCART1_MUTE
10uF 2 13
16V C778
R783
R791
3 1
10K
10K
5%
P_17V 3 12
1/16W C762 C770 C772
2 3 12
Q704 R780 R787
0.1uF 5.6K 5.6K
2SC3052 R701 2K SC1_Lout 33pF 33pF
SC2_Rout
4 11
4 11
R781 R786
5.6K 5 10 5.6K
C774 5 10 SC2_Lout
SC1_Rout
0.1uF
50V R779 R782
DTV/MNT_LOUT 33K 6 9 33K
6 9
R784
R789
10K
10K
Q711 R798 C769 7 8 C771
R727 7 8 R726
2SC3052
2K
1/16W 2K 33pF 33pF 2K
5% DTV/MNT_LOUT
RT1P141C-T112 TV_ROUT
16V
C776
Q709 10uF 10uF
DTV/MNT_ROUT SCART2_MUTE 16V C777
3 1
5%
R797
1/16W 2 C773
Q710 0.1uF
2SC3052 2K

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. AUDIO 6 10
AUDIO

P800 +5V
SMAW200-H18S1 +5V_ST +5V_ST P_+5V
+5V
L817
C854
P_17V 0.1uF
L801 C862 C865 C857
MLB-201209-0120P-N2 Q806 10uF 0.1uF 220uF
1 2 R856 R834
SI4925BDY 16V 16V
+5V_GENERAL
C817 10K 10K L808
C818 P_+5V
100uF READY
3 4 25V
0.1uF
50V
S1 1 8 D1_2
READY
C864 C866
5 6 G1 2 7 D1_1 10uF 0.1uF
C858
220uF
C890 16V 16V
L800 16V
C820
7 8 C813
MLB-201209-0120P-N2
10uF
C804
470uF 0.1uF
10uF
6.3V
R835
560
S2 3 6 D2_2
L818
+5V_CI
16V 16V
READY
9 10 PSU_ERR_DET RL_ON/PWR_ONOFF
Q803
2SC3052 C G2 4 5 D2_1
B
11 12 L821
C809
16V +5V_ST R829
C833
10uF
C867
10uF
C869
0.1uF
C859
+5V_ST MLB-201209-0120P-N2 0.1uF 10K 47uF
READY R828 E 16V 16V 16V 16V
R837
13 14 C839
120K
2K R801 C837 C835 C834 READY
100uF 10uF
10uF 0.1uF
RL_ON/PWR_ONOFF
100
15 16 16V 16V 6.3V
C805 READY
AC_DET
+5V_ST
0.1uF
16V
17 18 C812
16V
0.1uF
R838
10K R803
READY 100
MODULE_ON 19
C807
0.1uF
16V
+3.3V_TU
L806
MLB-201209-0120P-N2
C826 C885 C828

0.1uF 0.1uF 68uF
16V 16V 10V
+5V
GND
IC804
Stand-by +3.3V AZ1085S-3.3TR/E1
MAX 3A
+3.3V_CI
L814 40 mA
INPUT OUTPUT MLB-201209-0120P-N2
3 2
$0.122
1
ADJ/GND
C852
+3.3V_ST 0.1uF
16V
+3.3V_AVDD_MPLL
+5V_ST +3.3V_ST
C829 C831
10uF 0.1uF
IC802 R858 16V GND
+3.3V
0
R866
AP2121N-3.3TRE1
650 mA
0
C815
VIN VOUT 0.1uF
3 2
16V 0
1 R862
C802 C803 GND C806 C892 C808 +3.3V_HDMI_ST C850 C897 C844 C891
10uF 0.1uF 10uF 10uF 0.1uF 10uF 220uF 0.1uF 10uF
16V 16V 16V 6.3V 16V 6.3V 16V 6.3V
R859
READY 0 READY
C816
0.1uF
16V
GND GND
+3.3V_AVDD
320 mA
S6 core 1.26 volt
+5V +3.3V_AVDD
+3.3V_AVDD
50 mA +5V_GENERAL
IC803
AP1117E18G-13 +1.8V_TU 465 mA @85% efficiency
R865
L805
IN 3 1 ADJ/GND
0
IC801 2
AP1117E33G-13 C814 OUT C822 C889 C827 C824 C825 P_+5V
0.1uF 10uF 10uF 0.1uF 0.1uF 100uF
16V 6.3V 6.3V 16V 16V 16V
IN ADJ/GND READY READY
3 1
R831 MAX 3A
10uF
2 L802 Replaced Part

READY
OUT C888 C811 READY 10K +1.26V_VDDC

C800 C801 10uF 0.1uF MLB-201209-0120P-N2 R827
C842
C810
10uF 0.1uF 6.3V 16V C841

100uF 16V C899 READY
16V 16V 100uF 10K
16V R2 = R1/(Vout/0.8-1) 0.1uF
16V
IC805
READY R824 MP2212DN
50V 360K R1 TP1451
100pF
C870 1%
450 mA FB EN/SYNC 1600 mA
+3.3V
+1.8V_DDR +1.8V_DDR
R825
1 8
L813
620K R2 3.6uH R802
IC800 GND SW_2 0
2 7
AZ1085S-ADJTR/E1 1%
R864
NR8040T3R6N 1/4W
C OUT
IN SW_1
0
INPUT 3 2 OUTPUT Placed on SMD-TOP 3 6 C894 C896

C843 C856
10uF 10uF 0.1uF 10uF
1 6.3V 6.3V 6.3V
C893 C880 C877 BS VCC READY
C878 ADJ/GND 4 5 C830
C883 10uF 10uF 0.1uF
10uF 0.1uF 6.3V C838 C898 10nF
6.3V 16V
6.3V 16V R861 READY 10uF 10uF 50V
75
1%
R860
R830
33
1%
10
C836
1% 1uF
10V

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER 7 10
POWER

+3.3V_AVDD
Full SCART 1 R918
10K
Half SCART 2
+3.3V_AVDD
SC1_DET
R919
1K
D916 C909
30V 0.1uF
READY 16V R949
10K
[SCART2 PIN 8]P_17V
C923 SC2_DET
R948
0.1uF 1K
16V R969
SHIELD SC1_CVBS_IN SHIELD 3K
R915 C908
23 C904 0 220pF
R913 47pF 23
75 50V SC2_CVBS_IN
50V READY R945
MLB-201209-0120P-N2
22 C924
AV_DET D904 22 C9220 220pF
30V
AV_DET D918 P_17V R939 47pF R968
21 GND 30V 75 50V 10K
COM_GND READY 21 50V READY C
COM_GND READY
20
L900
SYNC_IN 20 B Q902
SYNC_IN R965
FE_VOUT 2SC3052
19 R908 19 4.7K R972
SYNC_OUT SYNC_OUT
D906 75 R912 C907 E
C933 12K
47K
18 100uF
R982
SYNC_GND2 D903 30V 470K 18 0.1uF
R990
470
16V SYNC_GND2
30V READY 50V C
17
SYNC_GND1 READY 17 E
SYNC_GND1 B Q901
16 R914
SC1_FB
16
2SA1504S SC_RE1
2SC3052
RGB_IO 22 RGB_IO C Q903 B R967
15 SC1_R R989
R_OUT D902
15 Q905 B 330 C C C928 1K E
R907 R_OUT
14 30V R904 75
2SC3052 READY 10uF
RGB_GND READY 75 14
RGB_GND
READY R987 Q904 B 16V C
2SC3052 DTV/MNT_VOUT
13 E 0
DEV R_GND 13
R_GND
R984 SC_RE2
B Q900
DEV R928 390 E 2SC3052 REC_8
R981
R988
12
15K
12 D92975 C921 R966
READY
R985
D2B_OUT
330
120
D2B_OUT R929 47uF
SC1_G 30V 470K 1K E
11 25V
G_OUT D901 R905 11 READY
R903 0 G_OUT
30V
. 10 75 . 10 D935
READY C917 KDS184
. 9 . 47uF A2
9 25V
SC1_ID C
SC_ID 8 R916 SC2_ID 8 A1
D917 62K R917 REC_8
B 7 SC1_B
30V 11K . 7 D930
D915 R902 30V
6 READY
LIN 30V 75 6 SC2_ID
L_IN READY R946
READY 62K
GND 5 GND 5 R947
11K
TP1467
GND 4 R911 4
GND R941
10K
10K
L_OUT 3 SC1_LIN
L_OUT 3 SC2_LIN
C903
R_IN 2 R901 330pF R910 R_IN 2
D908 C901 12K D928 C920 R943
470K 50V R927 C915
5.6V OPT 5.6V OPT 330pF 12K
R_OUT 1 R_OUT 1 470K
50V
TP1466
JK900 R906 JK903 R940

10K
SC1_RIN 10K
SC2_RIN
C902
D907
R900 330pF R909 R942
5.6V 12K C914 C919
470K C900 50V D927 12K
OPT OPT 330pF
5.6V R926 50V
470K
R996
1K
TV_LOUT
R994
C932 1K
DTV/MNT_LOUT
D905 6800pF R980
5.6V 50V 470K
READY C931
READY 6800pF R978
D926 50V 470K
5.6V READY
R993
1K READY
TV_ROUT
R995
C929 R976 1K
470K DTV/MNT_ROUT
6800pF
D900 READY
50V C930
5.6V
READY 6800pF R979
50V 470K
D920 READY
5.6V
READY
+3.3V_CI P_+5V
USB IC900
AP2181SG-XX
L901
R991
IC902
10K
NC GND NL17SZ08DFT2G
8 1
SIDE CVBS OUT_2

7 2
IN_1
5 1
USB_CTL
0.1uF
DEV
C927
OUT_1 IN_2
6 3 2
READY
AC_DET
COMPONENT R954
10K
COMP_RIN
C934
470uF
FLG
5 4
EN
4 3
R999
R992
16V
470K
10K
10K
R961
12K
R944 0
D914
C906
R951
1000pF
KJA-UB-4-0004
JK905
50V
1
100
USB DOWN STREAM

USB_OCD
R970
2
USB_DM
R953
JK901 10K
PPJ234-01 COMP_LIN
3
USB_DP
470K
R960
12K
6E [RD]E-LUG C905
R950
D932
R
D913
1000pF D933
50V CDS3C05HDMI1
CDS3C05HDMI1
4
5E [RD]O-SPRING_2 5.6V 5.6V
5
L
4E [RD]CONTACT
5D [WH]O-SPRING
NON_20TOOL
Pr [RD]O-SPRING_1
5C
COMP_Pr
5A [YL]E-LUG R938
D912
[RD]E-LUG-S
R959
7C 0
1%
SIDE_CVBS_IN
75
4A [YL]O-SPRING +3.3V_AVDD
C916
Pb
5B [BL]O-SPRING
D931
30V
R937 47pF
3A [YL]CONTACT 75 50V
7B [BL]E-LUG-S
R963
10K
4B [WH]O-SPRING
4A [GN]CONTACT
COMP_Pb R973
R958
3C 1K
[RD]CONTACT SIDE_CVBS_DET
SPDIF OPTIC JACK
1%
[GN]O-SPRING
75
5A
Y
D911
C911
D919
30V
4C 0.1uF
[RD]O-SPRING
6A [GN]E-LUG 16V
5C +5V_GENERAL +5V_GENERAL
[RD]E-LUG
R957 PPJ235-01
0 R933
GND COMP_Y JK902 10K
IC901
NL17SZ00DFT2G
SIDE_LIN
D910
A VCC
R964
R956
READY C913 1K
1%
1 5
SPDIF_OUT
D922
75
100pF
470K
+3.3V_AVDD C910 READY

R923
B JK904
12K
R932
2 READY
R998
4.7pF GND Y 100 JST1223-001
3 4
R952
R930 READY
10K
10K R997 GND
1
SIDE_RIN
Fiber Optic
R955 0
1K C912
D921
470K
COMP_DET
R922
100pF
12K
VCC
R931
2
READY D934
D909
30V
C926
0.1uF VINPUT
50V
3
4
FIX_POLE

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. JACK 8 10

D1007
D1002
D1003
D1004
D1008
+5V_VGA
NON_20TOOL
JK1001
SPG09-DB-010
C1001 R1018
0.1uF 22
16V
DSUB_R
6 RED_GND C1015
GND_2 4.7pF
1 11 RED
GREEN_GND
7 DDC_SDA/UART_TX
DDC_DATA R1017
2 12 GREEN 22
DSUB_G
BLUE_GND
8 +3.3V_AVDD
H_SYNC
R1016
3 13 BLUE
C1014
4.7pF
10K
NC
9
V_SYNC
4 14 GND_1 R1019 +5V_VGA +5V_ST
SYNC_GND
1K
10 DSUB_DET
DDC_CLOCK
5 15
READY
D1009
DDC_GND C1013
A1
A2
ENKMC2838-T112
30V
0.1uF
16V IC1001 D1012
16
AT24C02BN-10SU-1.8
C
SHILED
R1015
22 NON_20TOOL
DSUB_B
C1012 C1022
4.7pF 1 8 R1024 R1029 0.1uF
DSUB_HSYNC 4.7K
C1017
4.7K
R1014 R1023
12pF
2 7
1K 100 R1032
0
3 6 DDC_SCL/UART_RX
R1033
DSUB_VSYNC 4 5
0
C1016
DDC_SDA/UART_TX
R1013
12pF
C1018 C1021
1K 18pF 18pF
50V 50V ISP_RXD
ISP_TXD
DDC_SCL/UART_RX
R1005 R1007 R1010 R1011 R1012

LVDS FFC WAFER
4.7K
GND 75 75 75 4.7K PC AUDIO
JK1000
PEJ027-01
NON_20TOOL
3 E_SPRING
ROM DOWNLOAD FOR PDP 52

6A T_TERMINAL1
51 B_TERMINAL1
PC_SER_CLK
P401 7A
PC_RIN
50 R1028
PC_SER_DATA
SMAW200-H26S1 4 R_SPRING
D1010
C1020
100pF
10K
49 5.6V R1027
50V R1022
PDP_SCL T_SPRING 470K 12K
48 5
DISP_EN
R1003 47 B_TERMINAL2
7B
10 PC_LIN
PC_SER_DATA PDP_SDA
46 R1026
C1003 C1004
R442 1 2 6B T_TERMINAL2 D1011 C1019
100pF 10K
27K 45 50V R1021
270pF 220pF READY 5.6V R1025
50V 50V 44 MOD_ROM_TX 3 4 MOD_ROM_RX
470K 12K
R1001 READY READY
10 43 5 6
42
C1000 C1002
270pF 220pF D1000 D1001 7 8
50V 50V 41
READY READY
RXO0- 40 PDP_SCL 9 10 PDP_SDA
PC_SER_CLK RXO0+
39
RXO0-
11 12 RXO0+
RXO1- 38
RXO1+ RXO1-
13 14 RXO1+
37
RXO2- 36 RXO2-
15 16 RXO2+
RXO2+
35
RXOCK-
17 18 RXOCK+
34
RXO3-
19 20 RXO3+
RXOCK-
RXOCK+
33
21 22 SUB Board I/F
RS232C 32 RXO4- RXO4+ P402
12507WS-12L
31
PC_SER_CLK 23 24 PC_SER_DATA
+3.3V_ST RXO3- 30 100 R403
RXO3+
DISP_EN 25 26 L405
MLB-201209-0120P-N2
29 HD 1
R404 IR
27K +3.3V_ST
R443 4.7K
RXO4- 28 0 R402 C407
READY C403 10pF
RXO4+ READY 680pF 2
27 @optio
READY
C1007 C1008
C1009
27 R408
10K
R409
10K L404
0.1uF 0.1uF 26 MLB-201209-0120P-N2
50V 50V 0.1uF 3
50V KEY1
C1010 25 C402 L403
0.1uF C406
10pF MLB-201209-0120P-N2
50V RXE0- 24 10pF
KEY2 4
DOUT2
RIN2
RXE0+ C401
C2-
C2+
C1-
C1+
23 10pF L401 C405

V-
V+
RXE1- 22
LVDS LED_R
MLB-201209-0120P-N2
10pF 5
8
RXE1+ C404
21 10pF
C1027 6
IC1000 10pF
RXE2- 20
$0.179 READY
MAX3232CDR R1035
RXE2+ 22
19 7
SUB_SCL
18 R1034
10
11
12
13
14
15
16
C102922
9
RXECK- 8
17 SUB_SDA 10pF
READY
ROUT2
DIN2
DIN1
ROUT1
RIN1
DOUT1
GND
VCC
RXECK+
16 C1028
+3.3V_ST 9
+3.3V +5V +3.3V_ST 10pF
15 READY
R1037 20TOOL C1011 L402
MLB-201209-0120P-N2
NORMAL
10 0.1uF RXE3- 14 10
GLASS
L408
L406
PC_SER_CLK 50V
R1039 0 RXE3+ C400
SUB_SCL 13
R445 4.7K
R1038 20TOOL +3.3V_ST 10uF
10 R1040 0
SUB_SDA RXE4- 6.3V 11
PC_SER_DATA C1031 C1030 12
READY
R1002 R1004 10pF 10pF RXE4+ L400 C1025
R1008
50V 50V 11 MLB-201209-0120P-N2 10uF

D1014 D1015 4.7K 4.7K R1006 12
100
20TOOL 20TOOL 100 READY READY LED_B 6.3V

D1005 READY 10 C408
10pF
C1026 13
DBG_TX 9
10pF
DBG_RX
1N4148W_DIODES
BU400 READY
8
D1006 READY +3.3V PKM13EPY-4002-B0
C1005 220pF 50V 7
C1006 220pF 50V 6

BUZZER
1
D1013
100V
5
BUZZER
MOD_ROM_RX
JK1002 4 2
SPG09-DB-009
MOD_ROM_TX C
3 R1036
22 B Q1001
6
2 KEY_BUZZER
10
BUZZER 2SC3052
BUZZER
1 E
1
TF05-51S
P403

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. RGB,RS232,LVDS 9
10

DVB-CI DETECT
+3.3V_TU +3.3V_TU
/FE_RESET
IC1100
C1141 NL17SZ08DFT2G
READY 0.1uF
R1142 16V IN_B VCC
FE_TS_VAL 1 5
10
IN_A
FE_TS_ERR 2 C1101
(TUNER RESET GPIO OPTION) 0.1uF
GND OUT_Y
XC5000_RESET TU_RESET 3 4 16V
10
R1127
GND
16V FE_TS_VAL_ERR
0.1uF R1110
C1147 47
TUNER RESET C1159
0.1uF
: ACTIVE LOW (SOFT RESET) 16V
0.1uF
C1164 D_3.3V
TU_RESET
0.1uF
0.1uF
+1.8V_TU
0.1uF
1000pF
0.1uF
4.99K
+3.3V_TU +3.3V_TU
+3.3V_TU
C1156
+1.8V_TU
C1148
1%
C1115
C1117
C1163
R1152
C1165 0.1uF C_+3.3V +1.2V
C1162 C1123
15pF 15pF
50V 50V
VDDA_8
VDDC_9
VDDA_7
VDDC_8
VDDC_7
VREF_P
VREF_N
VDDC_6
R1153
X1101
GND_9
RESET
R1138
REXT
VI2C
1K
1K
VDDAH_OSC
VSSAH_OSC
TUNER_SHIELD 20.25MHz
I2C_SCL2
I2C_SDA2
KCN-ET-5-0094
I2S_DA
I2S_CL
VDDL_4
VSSL_4
VSSH_4
VDDH_4
48
47
46
45
44
43
42
41
40
39
38
37
JK1101
L1111 C1134 1000pF VDDA_1 1 36 GND_8 A_1.2V A_3.3V
TDI
TCK
TMS
TDO
56pF C1126 39pF0603CS-6N8XGLW2%
XO
XI
C1120 IN1 SDA R1155 100
1 2 35 SDA1
GND_1 SCL C_+3.3V
0603CS-R39XGLW
2 6.8nH 3 34 C1108 R1150 100 SCL1

0603CS-R27XGLW
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
IN2 VDDD_2 C1121 18pF
4 33 C1131 C1152
IC1104
L1108
270nH
RCLAMP1521P D1102
C1103
6.8pF
READY
GND_2 EXTREF I2S_WS PDN C1139 0.1uF

L1116
390nH
5 32 0.1uF 18pF 18pF 1 48

50V
2%
READY
2%
C1109 0.1uF L1114 EXTCHOKE X1 50V 50V VDDL_1 PDP C1140 0.1uF
XC5000 47
R1123
RCLAMP0502B D1101 6 31 2
4.7K
C1 GND_3 GND_7 X1102 VSSL_1 VDDAL_AFE2
820nH 2% 7 30 3 46
A C1146 1008CS-821XGLC VDDA_2 X2 31.875MHz GPIO1 45 VSSAL_AFE2
8 29 4
C2 120pF C1167 0.1uF VDDA_3 ADDRSEL R1115 47 MSTRT 44 SIF
9 28 C1173 FE_TS_SYN 5
C1158 0.1uF VDDC_1 DDI2 18pF R1121 MERR CVBS
10 27 C1151 47 6 IC1103 43
1000pF
FE_TS_ERR
C1172
GND_4 11 26 VDDC_5 R1126 47 VSSH_1 7 42 VDDAH_CVBS
FE_TS_SERIAL DRX3913K-XK
50V
C1171 0.1uF VDDC_2 12 25 DDI1 0.1uF VDDH_1 8 41 VSSAH_CVBS
R1102 47 MCLK INP
9 40 TUNER_IF_P
13
14
15
16
17
18
19
20
21
22
23
24
+1.8V_TU FE_TS_CLK R1103 47 MVAL INN

FE_TS_VAL 10 39 TUNER_IF_N
FE_TS_DATA[0] R1144 47 MD0 VSSAH_AFE1
38
VDDC_3
VDDA_4
VAGC
VIF
VDDA_5
SIF
GND_5
VDDC_4
VDDA_6
GND_6
VDDD_1
TESTMODE
11
1000pF
50V
FE_TS_DATA[1] R1148
C1160
+3.3V_TU L1101
47 MD1 12 37 VDDAH_AFE1
MLB-201209-0120P-N2 FE_TS_DATA[2] R1129 MD2 VDDAL_AFE1
47 13 36 R1107
FE_TS_DATA[3] R1132 MD3 VSSAL_AFE1 6.8K
+1.8V_TU 47 14 35
VSSL_2 IF_AGC
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
15 34 IF_AGC
VDDL_2 16 33 RF_AGC
C1119 C1181
0.1uF 0.027uF
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C1176
C1116
C1129
C1169
C1124
C1182
C1118
0.1uF
16V
VSSH_2
VDDH_2
MD4
MD5
MD6
MD7
I2C_SCL1
I2C_SDA1
VSSH_3
VDDH_3
VDDL_3
VSSL_3
VSYNC
GPIO2
SAW_SW
RSTN
To separate chassis ground R1130
1K C_+3.3V
IF_AGC
R1166 0 R1174 0 R1182 0 C1133 FE_TS_DATA[4] R1109 47
0.1uF FE_TS_DATA[5] R1111
16V 47 R1116
+5V FE_TS_DATA[6] R1143 4.7K
R1167 0 R1175 0 R1183 0 47
FE_TS_DATA[7] R1140 47 READY
R1108
R1168 0 R1176 0 R1184 0 /FE_RESET
C1106 100
R1122 0.1uF Place the Buffer close to Tuner
R1169 0 R1177 0 R1185 0 390 16V C1102
C_+3.3V 0.1uF
R1114 R1136 16V
TUNER_SIF READY 100 100
R1170 0 R1178 0 R1128
4.7K 50V 50V
R1135 E FE_TS_DATA[0-7] 18pF 18pF
C1113 C1175
R1171 0 R1179 0 680 Q1103 READY READY
ISA1530AC1 R1139
L1105 B 4.7K
MLF1608A2R7J READY
R1172 0 R1180 0 2.7uH 5% C1161 C
6.8pF
50V
R1173 0 R1181 0 +5V
SCL1
SDA1
R1159 C1183
390 0.1uF
16V
TUNER_IF_N
+1.2V A_1.2V
E
L1112
Q1108 MLB-201209-0120P-N2
ISA1530AC1
B
C +3.3V_TU C1105 C1143 C1142
C1136
+5V 0.1uF 0.1uF C1174
[SCART1 TV VOUT] 10uF
6.3V
16V 16V 0.1uF
16V
0.1uF
16V
P_17V
L1118
L1103
MLB-201209-0120P-N2 C1180 C1185 C1186 C1187
68uF 0.1uF 0.1uF 0.1uF
10V 16V 16V 16V
C1157 C1138 C1168 READY
C1178 A_3.3V
470
R1154
0.1uF 0.1uF 10uF R1101

0.1uF +3.3V_TU
50V 50V 25V 16V
390
E L1113
ISA1530AC1 MLB-201209-0120P-N2
TUNER_CVBS
B Q1101
C 16V
+5V 16V 16V 16V 16V 16V
0.1uF
R1133 +1.2V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C1149
C E
47K R1164 R1112 C1112 C1114 C1132 C1144 C1130
330 B Q1110 680 Q1102
C1170
L1117
2SC3052 ISA1530AC1
47uF C READY READY L1110 B +3.3V_TU
16V Q1105
B E MLF1608A2R7J C1104
2SC3052 2.7uH 5% C
6.8pF IC1102
R1165
50V C1145
CVBS_SCART_OUT E R1145 FE_VOUT R1118 0.1uF AZ1117H-1.2TRE1
+3.3V_TU C_+3.3V
R1151 390 390 +3.3V_TU D_3.3V
0
16V
15K
IN OUT L1107
R1141 CVBS_SCART_OUT
READY
R1163
R1137 MLB-201209-0120P-N2 L1115

180 390 C1122 MLB-201209-0120P-N2
330
ADJ/GND C1107
100uF 0.1uF
C1188 C1150 C1111
E 16V 50V
100uF 0.1uF 10uF C1125
Q1106 C1110 C1177 C1179
16V 50V 16V C1137 C1153
ISA1530AC1 READY 0.1uF 0.1uF 0.1uF 0.1uF
B 16V 16V 16V 0.1uF 0.1uF
16V
16V 16V
C
SC1_VIDEO_MUTE
Q1104 R1131 +5V
2K
Q1107
2SC3052
C1166
1 3
0.1uF
16V 2
C1184
R1157 0.1uF
390 16V
(SC1_TV_VOUT_MUTE GPIO OPTION)
TUNER_IF_P
E
Q1109
ISA1530AC1
B
C

TUNER
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 10 10


42PJ550 Manual de Serviço

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42PJ550 Manual de Serviço

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Internal Use Only

North/Latin America http://aic.lgservice.com

MODEL : 42PJ550 42PJ550-ZD

P/NO : MFL62881205(1002-REV00) Printed in Korea

SAFETY PRECAUTIONS ...........................................................................................................3

ADJUSTMENT INSTRUCTION ..................................................................................................7

TROUBLESHOOTING GUIDE .................................................................................................12

BLOCK DIAGRAM ...................................................................................................................23

EXPLODED VIEW ...................................................................................................................24

SVC. SHEET ................................................................................................................................

IMPORTANT SAFETY NOTICE

General Guidance Leakage Current Hot Check (See below Figure)

Good Earth Ground

No Item Specification Remark

No Item Specification Remarks

No Item Min Typ Max Unit Remark

2. Specification 3. Update S/W using Auto Download

<Horizontal Color Bar pattern>

Caution: Don’t connect any external input cable except the

NO Item CMD1 CMD2 Data0

Enter Adjust When transfer the ‘Made

# Adjust Sequence O EDID Data detailing (ⓐ, ⓑ, ⓒ, ⓓ, ⓔ, ⓕ)

8-1. Model name:

8-2. Va/Vs Adjustment Procedure

ⓕ HDMI Port No.

O Auto EDID Download Map(RS-232C)

9. White Balance Adjustment

< Temperature: MEDIUM >

11. CI+ Key Download

12. Check Information (Serial No. & Model name)

10-2. Signal TABLE

L : 8 bit 4 45 R115 Y11 AF12

PCM_A[6] PCM_A5/CI_A5 USB_DM_1

NC_8 NC_23 AC13 AC10 USB

11 38 PCM_A[7] PCM_A6/CI_A6 USB_DM_2 USB_DM

VDD_1 VDD_2 PCM_A[8] PCM_A7/CI_A7 USB_DP_2 USB_DP

AL I/O3 PCM_A[3] PM GPIO Assignment Recommended by MStar

/PCM_REG R160 DISP_EN

PCM_WAIT/CI_WACK GPIO_PM4/GPIO138 R134

22 AC21 A6 100 R1277

for BOOT PDP_SCL R165

ISP_RXD C108 C107 PCM_5V_CTL

ISP_TXD R141 SIDE_CVBS_DET

SO HOLD# 1 8 DBG_RX R1297 100 W5 READY READY CI_TS_DATA[0-7]

DBG_TX R1296 100 V5 AA8 CI_TS_DATA[0]

WP# SCLK TS0_D1

KEY1 ET_TX_CLK SC_RE1

R1256 B4 C11 R1267 100+3.3V

4.7K KEY2 SAR1 ET_RXD0 R1283 0 CI_EN

VSS SDA ET_COL SC1_DET

EEPROM_SDA AC11 R1269

R1258 22 C114 R1200 C /CI_CD2 GPIO44 4.7K

12507WS-08L XC5000_RESET GPIO91

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright © 2010 LG Electronics Inc. All rights reserved.

Audio Mute C240

C245 C248 C259 C266 C277 C283 C291 C296

1K E2 HOTPLUG_B AF17 GND_15 VDDC_16

R210 47 N1 VSYNC0/SC1_FB AB3 C2015 2.2uF GND_31 VDDP_5

DSUB_R P12 H15

AUOUTL0/HP_LOUT B/T_HP_LOUT P16 W16

R224 47 C216 0.047uF U1 BIN2P/COMP_PB+ AD2 R251 100 SC2_Lout MLB-201209-0120P-N2

R225 470 C209 1000pF V3 SOGIN2 GND_48 AVDD_MEMPLL_1

R238 100 J5 VSYNC2 GND_49 AVDD_MEMPLL_2 C262 C269 C285