6.

(UNIT 4)(GATE 2019) In the circuit shown, what are the values of F for EN = 0 and
EN = 1, respectively?

[Ans. B]

(A) 0 and D
(B) Hi-Z and D
(C) 0 and 1
(D) Hi-Z and D
7. (UNIT 4)(GATE 2017) In the latch circuit shown, the NAND gates have non-zero,
but unequal propagation delay. The present input condition is: P = Q = ‘0’. If the
input condition is changed simultaneously to P = Q = ‘1’, the outputs X and Y are

[Ans. B]

(A) X = ‘1’, Y = ‘1’

(B) Either X = ‘1’, Y = ‘0’ or Y = ‘1’
(C) Either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’
(D) X = ‘0’, Y = ‘0’
(E) (UNIT 4)(GATE 2017) Consider the circuit shown in the figure.
 The Boolean expression F implemented by the circuit is
Ans:

18. (UNIT 3)(GATE 2016) Consider the following circuit which uses a 2-to-1 multiplexer
as shown in the figure below. The Boolean expression for output F in terms of A and
B is 

Ans: