5 4 3 2 1

hϴϮ/^;ϭϰΗͬϭϱ͘ϲΗͿ hůƚƌĂͬ^ůŝŵ Ϭϭ
Wϲ>^d<hW

D
/ŶƚĞů^ŚĂƌŬĂLJh>dWůĂƚĨŽƌŵůŽĐŬŝĂŐƌĂŵ >zZϭ͗dKW
>zZϮ͗^'E D

sZDZϯdžϰ >zZϯ͗/Eϭ;,ŝŐŚͿ
DĂdžϭ'ƐͬϮ'Ɛ >zZϰ͗/EϮ;>ŽǁͿ
ϵϬϬDŚnj W'ϭϴ >zZϱ͗^s
>zZϲ͗Kd
/ŶƚĞů^ŚĂƌŬĂLJh>d ELW
Zϯ>^K/DDϭ
Zϯ>
DĂdžŝŵĂϴ'Ɛ
WƌŽĐĞƐƐŽƌ͗ĂƵůŽƌĞ
W'ϭϮ 3&,(*HQ NVIDIA N14P-GV2
WŽǁĞƌ͗ϭϱ;tĂƚƚͿ ;/DQH S3 Package 23*23mm
Zϯ>^K/DDϮ
Zϯ> WĂĐŬĂŐĞ͗'ϭϭϲϴ
DĂdžŝŵĂϴ'Ɛ : W'ϭϰΕϭϳ
W'ϭϯ ^ŝnjĞ͗ϰϬyϮϰ;ŵŵͿ
RTD2132R >s^;ϭ,Ϳ
^dͲϭƐƚ, ϮϳD,nj WĂĐŬĂŐĞ͗Y&EͲϯϮ W'ϮϬ
^dϬϲ'ͬƐ W'ϭϲ
WĂĐŬĂŐĞ͗ϵ͘ϱ;ŵŵͿ W'ϭϵ
WŽǁĞƌ͗ W'Ϯϰ ĞW
W'ϮϬ
C C
eDP X1
ŵ^d ^dϭϲ'ͬƐ
WĂĐŬĂŐĞ͗ϭϮ͘ϳ;ŵŵͿ
,D/ŽŶŶ
WŽǁĞƌ͗ W'Ϯϰ
W'ϮϬ
DP Port 1
^dK ^dϮϲ'ͬƐ
WĂĐŬĂŐĞ͗;ŵŵͿ h^ϯ͘ϬWŽƌƚdžϮ
h^ϯ͘Ϭ/ŶƚĞƌĨĂĐĞh^ϯ͘ϬWŽƌƚϭ͕Ϯ;h^Ϯ͘ϬWŽƌƚϬ͕ϱͿ
WŽǁĞƌ͗ W'Ϯϰ
W'Ϯϱ
Ɛŵƚ h^Ϯ͘Ϭ/ŶƚĞƌĨĂĐĞ
W'ϮΕϭϬ
^LJƐƚĞŵ/K^
^W/ZKD ^W//ŶƚĞƌĨĂĐĞ
W'ϳ
njĂůŝĂ

h^Ϯ͘ϬWŽƌƚdžϭ;>ĞĨƚƐŝĚĞͿ ĂŵĞƌĂ
WŽƌƚϭ WŽƌƚϮ
W'Ϯϭ W'ϮϬ
>W/ŶƚĞƌĨĂĐĞ W/'ĞŶϭdžϭ>ĂŶĞ
B B

Ŷ<ϵϬϭϬY&ϭ
ƵĚŝŽŽĚĞĐ ĂƌĚZĞĂĚĞƌ >EŽŶƚƌŽůůĞƌ ,ĂůƚDŝŶŝĂƌĚ
'Ͳ^ĞŶƐŽƌ ŵďĞĚĚĞĚŽŶƚƌŽůůĞƌ >ϯϮϮϳͲ'Z Zd^ϱϮϯϳͲ'Z ϭϬͬϭϬϬZd>ϴϭϳϲ,Ͳ' /ŶƚĞůZĂŵďŽWĞĂŬ
^Dh^
,WϯϮdZ
W'Ϯϲ WŽǁĞƌ͗ WŽǁĞƌ͗ WŽǁĞƌ͗
WŽǁĞƌ͗ t>EͬdŽŵďŽ
WĂĐŬĂŐĞ͗>YW&ϭϮϴ WĂĐŬĂŐĞ͗DY&E WĂĐŬĂŐĞ͗>YW&ϰϴ WĂĐŬĂŐĞ͗K&Eϰϴ
<ĞLJďŽĂƌĚ
W'Ϯϱ
^ŝnjĞ͗ϭϰdžϭϰ;ŵŵͿ ^ŝnjĞ͗ϲdžϲ;ŵŵͿ ^ŝnjĞ͗ϳdžϳ;ŵŵͿ ^ŝnjĞ͗ϲdžϲ;ŵŵͿ
dŽƵĐŚWĂĚ W'Ϯϳ W'Ϯϭ W'Ϯϯ /Ŷƚ W'ϮϮ W'Ϯϲ
dWͲϭϱ'Ϯϰ
W'Ϯϰ &E
Speaker
W'Ϯϭ
W'Ϯϰ
ŽŵďŽ:ĂĐŬ
ŝW,KEƚLJƉĞ
W'Ϯϭ
A A

Digital MIC 352-(&78

W'Ϯϭ
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom
ůŽĐŬŝĂŐƌĂŵ 1A

Date: Monday, May 06, 2013 Sheet 1 of 40

5 4 3 2 1
 
5 4 3 2 1

U19A U19B

DPB_LANE0_N C54 PROC_DETECT# D61

<20> IN_D2# DDI1_TXN0 TP89 PROC_DETECT#

MISC
DPB_LANE1_N B58
<20> IN_D1# DDI1_TXN1
DPB_LANE2_N B55 CATERR# K61
<20> IN_D0# DDI1_TXN2 TP91 CATERR#
DPB_LANE3_N A57
<20> IN_CLK# DDI1_TXN3 +1.35VSUS
DPB_LANE0_P C55 EC_PECI N62
<20> IN_D2 DDI1_TXP0 <27> EC_PECI PECI
DPB_LANE1_P C58
<20> IN_D1 DDI1_TXP1
DPB_LANE2_P A55
<20> IN_D0 DDI1_TXP2
DPB_LANE3_P B57
<20> IN_CLK DDI1_TXP3
D R183 D
C51 470_4
C53 DDI2_TXN0
C49 DDI2_TXN1 SI modify to short pad

PCI EXPRESS* - GRAPHICS

A53 DDI2_TXN2
DDI2_TXN3

THERMAL
C50 AV15 SM_DRAMRST# R184 *0_4/S
DDI2_TXP0 SM_DRAMRST# DDR3_DRAMRST# <12,13>
B54
DDI2_TXP1

DDR3
B50 AU60 SM_RCOMP_0 R527 200/F_4
B53 DDI2_TXP2 SM_RCOMP0 AV60 SM_RCOMP_1 R528 121/F_4
DDI2_TXP3 R415 56.2/F_4 PROCHOT# K63 SM_RCOMP1 AU61 SM_RCOMP_2 R526 100/F_4
<27,32> H_PROCHOT# PROCHOT# SM_RCOMP2
eDP_COMPIO and ICOMPO signals should be shorted
near balls and routed with typical impedance <25 mohms AV61
SM_PG_CNTL1 DDR_PG_CNTL <13>
eDP_RCOMP D20
EDP_DISP_UTIL A43 EDP_RCOMP
<6> EDP_DISP_UTIL EDP_DISP_UTIL

INT_eDP_AUXP B45
<19> INT_eDP_AUXP EDP_AUXP TP21
INT_eDP_AUXN A45 J62
<19> INT_eDP_AUXN EDP_AUXN PRDY# XDP_PRDY#_CPU <11>
K62
PREQ# XDP_PREQ#_CPU <11>

eDP
TP25
INT_eDP_TXP0 B46 R397 10K/F_4 E60 XDP_TCK0
<19> INT_eDP_TXP0 eDP_TXP0 PROC_TCK XDP_TCK0 <11>
B47 E61 XDP_TMS_CPU
eDP_TXP1 PROC_TMS XDP_TMS_CPU <11>
C46 PROCPWRGD C61 E59 XDP_TRST#_CPU
eDP_TXP2 TP86 PROCPW RGD PROC_TRST# XDP_TRST#_CPU <7,11>
B49

PWR MANAGEMENT
eDP_TXP3 F63 XDP_TDI_CPU

JTAG & BPM

PROC_TDI XDP_TDI_CPU <11>
F62 XDP_TDO_CPU
PROC_TDO XDP_TDO_CPU <11>
INT_eDP_TXN0 C45
<19> INT_eDP_TXN0 eDP_TXN0
A47
C C47 eDP_TXN1 C
A49 eDP_TXN2
eDP_TXN3
J60
BPM#0 XDP_BPM0 <11>
H60
BPM#1 XDP_BPM1 <11>
*HSW_ULT_DDR3L H61 BPM#2
BPM#2 TP90
H62 BPM#3
BPM#3 TP17
K59 BPM#4
BPM#4 TP24
H63 BPM#5
BPM#5 TP20
K60 BPM#6
BPM#6 TP28
J61 BPM#7
BPM#7 TP22
+VCCIOA_OUT R109 24.9/F_4 eDP_RCOMP

eDP_COMPIO and ICOMPO signals should be shorted

*HSW_ULT_DDR3L
near balls and routed with typical impedance <25 mohms

Processor pull-up (CPU)

H_PROCHOT# R419 62_4 +V1.05S_VCCST

+V1.05S_VCCST
XDP_TDO_CPU R411 51_4

XDP_TMS_CPU R410 *51_4

DEL or not?
B XDP_TDI_CPU R412 *51_4 B

XDP_TRST#_CPU R539 *51_4

XDP_TCK0 R101 51_4

A A

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom
h>dϭͬϵ;ĞWͬ/Ϳ 1A

Date: Friday, April 26, 2013 Sheet 2 of 40

5 4 3 2 1
 5 4 3 2 1


<12> M_A_DQ[63:0]
<13> M_B_DQ[63:0]
<12> M_A_DQSN[7:0]
<12> M_A_DQSP[7:0]
<13> M_B_DQSN[7:0]
<13> M_B_DQSP[7:0]

Haswell ULT Processor (DDR3L)

D D

U19D

U19C M_A_DQ32 AY31

M_A_DQ33 AW31 SB_DQ0
M_A_DQ0 AH63 M_A_DQ34 AY29 SB_DQ1
M_A_DQ1 AH62 SA_DQ0 M_A_DQ35 AW29 SB_DQ2 AN38
SA_DQ1 SB_DQ3 SB_CLK0 M_B_CLKP0 <13>
M_A_DQ2 AK63 M_A_DQ36 AV31 AM38 M_B_CLKN0 <13>
M_A_DQ3 AK62 SA_DQ2 AV37 M_A_DQ37 AU31 SB_DQ4 SB_CLK#0 AY49
SA_DQ3 SA_CLK0 M_A_CLKP0 <12> SB_DQ5 SB_CKE0 M_B_CKE0 <13>
M_A_DQ4 AH61 AU37 M_A_CLKN0 <12> M_A_DQ38 AV29
M_A_DQ5 AH60 SA_DQ4 SA_CLK#0 AU43 M_A_DQ39 AU29 SB_DQ6
SA_DQ5 SA_CKE0 M_A_CKE0 <12> SB_DQ7
M_A_DQ6 AK61 M_A_DQ40 AY27
M_A_DQ7 AK60 SA_DQ6 M_A_DQ41 AW27 SB_DQ8 AL38
SA_DQ7 SB_DQ9 SB_CLK1 M_B_CLKP1 <13>
M_A_DQ8 AM63 M_A_DQ42 AY25 AK38 M_B_CLKN1 <13>
M_A_DQ9 AM62 SA_DQ8 AY36 M_A_DQ43 AW25 SB_DQ10 SB_CLK#1 AU50
SA_DQ9 SA_CLK1 M_A_CLKP1 <12> SB_DQ11 SB_CKE1 M_B_CKE1 <13>
M_A_DQ10 AP63 AW36 M_A_CLKN1 <12> M_A_DQ44 AV27
M_A_DQ11 AP62 SA_DQ10 SA_CLK#1 AW43 M_A_DQ45 AU27 SB_DQ12
SA_DQ11 SA_CKE1 M_A_CKE1 <12> SB_DQ13
M_A_DQ12 AM61 M_A_DQ46 AV25
M_A_DQ13 AM60 SA_DQ12 M_A_DQ47 AU25 SB_DQ14
M_A_DQ14 AP61 SA_DQ13 M_B_DQ32 AM29 SB_DQ15
M_A_DQ15 AP60 SA_DQ14 M_B_DQ33 AK29 SB_DQ16 AW49
M_B_DQ0 AP58 SA_DQ15 M_B_DQ34 AL28 SB_DQ17 SB_CKE2
M_B_DQ1 AR58 SA_DQ16 AY42 M_B_DQ35 AK28 SB_DQ18
M_B_DQ2 AM57 SA_DQ17 SA_CKE2 M_B_DQ36 AR29 SB_DQ19
M_B_DQ3 AK57 SA_DQ18 M_B_DQ37 AN29 SB_DQ20
M_B_DQ4 AL58 SA_DQ19 M_B_DQ38 AR28 SB_DQ21
M_B_DQ5 AK58 SA_DQ20 M_B_DQ39 AP28 SB_DQ22 AV50
M_B_DQ6 AR57 SA_DQ21 M_B_DQ40 AN26 SB_DQ23 SB_CKE3
M_B_DQ7 AN57 SA_DQ22 AY43 M_B_DQ41 AR26 SB_DQ24
M_B_DQ8 AP55 SA_DQ23 SA_CKE3 M_B_DQ42 AR25 SB_DQ25
M_B_DQ9 AR55 SA_DQ24 M_B_DQ43 AP25 SB_DQ26 AM32
SA_DQ25 SB_DQ27 SB_CS#0 M_B_CS#0 <13>
M_B_DQ10 AM54 M_B_DQ44 AK26 AK32 M_B_CS#1 <13>
M_B_DQ11 AK54 SA_DQ26 AP33 M_B_DQ45 AM26 SB_DQ28 SB_CS#1
SA_DQ27 SA_CS#0 M_A_CS#0 <12> SB_DQ29
M_B_DQ12 AL55 AR32 M_A_CS#1 <12> M_B_DQ46 AK25
C
M_B_DQ13 AK55 SA_DQ28 SA_CS#1 M_B_DQ47 AL25 SB_DQ30 C

M_B_DQ14 AR54 SA_DQ29 M_A_DQ48 AY23 SB_DQ31

AN54 SA_DQ30 AW23 SB_DQ32 TP59
M_B_DQ15 M_A_DQ49
M_A_DQ16 AY58 SA_DQ31 M_A_DQ50 AY21 SB_DQ33 AL32
AW58 SA_DQ32 TP61 AW21 SB_DQ34 SB_ODT0
M_A_DQ17 M_A_DQ51
M_A_DQ18 AY56 SA_DQ33 AP32 M_A_DQ52 AV23 SB_DQ35
M_A_DQ19 AW56 SA_DQ34 SA_ODT0 M_A_DQ53 AU23 SB_DQ36
M_A_DQ20 AV58 SA_DQ35 M_A_DQ54 AV21 SB_DQ37
M_A_DQ21 AU58 SA_DQ36 M_A_DQ55 AU21 SB_DQ38
M_A_DQ22 AV56 SA_DQ37 M_A_DQ56 AY19 SB_DQ39
M_A_DQ23 AU56 SA_DQ38 M_A_DQ57 AW19 SB_DQ40
M_A_DQ24 AY54 SA_DQ39 M_A_DQ58 AY17 SB_DQ41 AW30 M_A_DQSN4
M_A_DQ25 AW54 SA_DQ40 M_A_DQ59 AW17 SB_DQ42 SB_DQSN0 AV26 M_A_DQSN5
M_A_DQ26 AY52 SA_DQ41 AJ61 M_A_DQSN0 M_A_DQ60 AV19 SB_DQ43 SB_DQSN1 AN28 M_B_DQSN4

DDR SYSTEM MEMORY B

M_A_DQ27 AW52 SA_DQ42 SA_DQSN0 AN62 M_A_DQSN1 M_A_DQ61 AU19 SB_DQ44 SB_DQSN2 AN25 M_B_DQSN5
M_A_DQ28 AV54 SA_DQ43 SA_DQSN1 AM58 M_B_DQSN0 M_A_DQ62 AV17 SB_DQ45 SB_DQSN3 AW22 M_A_DQSN6
M_A_DQ29 AU54 SA_DQ44 SA_DQSN2 AM55 M_B_DQSN1 M_A_DQ63 AU17 SB_DQ46 SB_DQSN4 AV18 M_A_DQSN7
AV52 SA_DQ45 SA_DQSN3 AV57 AR21 SB_DQ47 SB_DQSN5 AN21
DDR SYSTEM MEMORY A

M_A_DQ30 M_A_DQSN2 M_B_DQ48 M_B_DQSN6

M_A_DQ31 AU52 SA_DQ46 SA_DQSN4 AV53 M_A_DQSN3 M_B_DQ49 AR22 SB_DQ48 SB_DQSN6 AN18 M_B_DQSN7
M_B_DQ16 AK40 SA_DQ47 SA_DQSN5 AL43 M_B_DQSN2 M_B_DQ50 AL21 SB_DQ49 SB_DQSN7
M_B_DQ17 AK42 SA_DQ48 SA_DQSN6 AL48 M_B_DQSN3 M_B_DQ51 AM22 SB_DQ50
M_B_DQ18 AM43 SA_DQ49 SA_DQSN7 M_B_DQ52 AN22 SB_DQ51
M_B_DQ19 AM45 SA_DQ50 M_B_DQ53 AP21 SB_DQ52
M_B_DQ20 AK45 SA_DQ51 M_B_DQ54 AK21 SB_DQ53 AV30 M_A_DQSP4
M_B_DQ21 AK43 SA_DQ52 M_B_DQ55 AK22 SB_DQ54 SB_DQSP0 AW26 M_A_DQSP5
M_B_DQ22 AM40 SA_DQ53 AJ62 M_A_DQSP0 M_B_DQ56 AN20 SB_DQ55 SB_DQSP1 AM28 M_B_DQSP4
M_B_DQ23 AM42 SA_DQ54 SA_DQSP0 AN61 M_A_DQSP1 M_B_DQ57 AR20 SB_DQ56 SB_DQSP2 AM25 M_B_DQSP5
M_B_DQ24 AM46 SA_DQ55 SA_DQSP1 AN58 M_B_DQSP0 M_B_DQ58 AK18 SB_DQ57 SB_DQSP3 AV22 M_A_DQSP6
M_B_DQ25 AK46 SA_DQ56 SA_DQSP2 AN55 M_B_DQSP1 M_B_DQ59 AL18 SB_DQ58 SB_DQSP4 AW18 M_A_DQSP7
M_B_DQ26 AM49 SA_DQ57 SA_DQSP3 AW57 M_A_DQSP2 M_B_DQ60 AK20 SB_DQ59 SB_DQSP5 AM21 M_B_DQSP6
M_B_DQ27 AK49 SA_DQ58 SA_DQSP4 AW53 M_A_DQSP3 M_B_DQ61 AM20 SB_DQ60 SB_DQSP6 AM18 M_B_DQSP7
M_B_DQ28 AM48 SA_DQ59 SA_DQSP5 AL42 M_B_DQSP2 M_B_DQ62 AR18 SB_DQ61 SB_DQSP7
M_B_DQ29 AK48 SA_DQ60 SA_DQSP6 AL49 M_B_DQSP3 M_B_DQ63 AP18 SB_DQ62
M_B_DQ30 AM51 SA_DQ61 SA_DQSP7 SB_DQ63
B M_B_DQ31 AK51 SA_DQ62 B
SA_DQ63 M_B_A[15:0] <13>
<13> M_B_BS#0
AL35 AP40 M_B_A0
AM36 SB_BA0 SB_MA0 AR40 M_B_A1
M_A_A[15:0] <12> <13> M_B_BS#1 SB_BA1 SB_MA1
<12> M_A_BS#0
AU35 AU36 M_A_A0 <13> M_B_BS#2
AU49 AP42 M_B_A2
AV35 SA_BA0 SA_MA0 AY37 M_A_A1 SB_BA2 SB_MA2 AR42 M_B_A3
<12> M_A_BS#1 SA_BA1 SA_MA1 SB_MA3
<12> M_A_BS#2
AY41 AR38 M_A_A2 <13> M_B_CAS#
AM33 AR45 M_B_A4
SA_BA2 SA_MA2 AP36 M_A_A3 AM35 SB_CAS# SB_MA4 AP45 M_B_A5
SA_MA3 <13> M_B_RAS# SB_RAS# SB_MA5
<12> M_A_CAS#
AU34 AU39 M_A_A4 <13> M_B_WE#
AK35 AW46 M_B_A6
AY34 SA_CAS# SA_MA4 AR36 M_A_A5 SB_WE# SB_MA6 AY46 M_B_A7
<12> M_A_RAS# SA_RAS# SA_MA5 SB_MA7
<12> M_A_WE#
AW34 AV40 M_A_A6 AY47 M_B_A8
SA_WE# SA_MA6 AW39 M_A_A7 SB_MA8 AU46 M_B_A9
SA_MA7 AY39 M_A_A8 SB_MA9 AK36 M_B_A10
SA_MA8 AU40 M_A_A9 SB_MA10 AV47 M_B_A11
SA_MA9 AP35 M_A_A10 SB_MA11 AU47 M_B_A12
SA_MA10 AW41 M_A_A11 SB_MA12 AK33 M_B_A13
SA_MA11 AU41 M_A_A12 SB_MA13 AR46 M_B_A14
SA_MA12 AR35 M_A_A13 SB_MA14 AP46 M_B_A15
SA_MA13 AV42 M_A_A14 SB_MA15
SA_MA14 AU42 M_A_A15
SA_MA15
AP49 SM_VREF SM_VREF <12>
SM_VREF_CA
SM_VREF_DQ0
AR51 SMDDR_VREF_DQ0_M3 SMDDR_VREF_DQ0_M3 <12> ^Dd
AP51 SMDDR_VREF_DQ1_M3 SMDDR_VREF_DQ1_M3 <13> *HSW_ULT_DDR3L
SM_VREF_DQ1
*HSW_ULT_DDR3L
ϮϬŵŝůƐǁŝĚƚŚ

A A

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom
h>dϮͬϵ;Zϯ/ͬ&Ϳ 1A

Date: Monday, May 06, 2013 Sheet 3 of 40

5 4 3 2 1
 5 4 3 2 1

POWER

U19F

32A 1.4A
+1.35VSUS CFG0-19 need Reserve TP U19E

+VCC_CORE CFG0 TP53 CFG0 AC60

Close to CPU <11> CFG0
CFG1 TP51 CFG1 AC62 CFG0 A51 TP80
C36 AH26 <11> CFG1 AC63 CFG1 RSVD_TP B51
CFG2 TP63 CFG2 TP83
C40 VCC VDDQ AJ31 <11> CFG2 AA63 CFG2 RSVD_TP
CFG3 TP96 CFG3
C44 VCC VDDQ AJ33 <11> CFG3 AA60 CFG3
CFG4 TP58 CFG4
C48 VCC VDDQ AJ37 <11> CFG4 Y62 CFG4 L60
C560 C561 C559 C562 C556 C563 CFG5 TP48 CFG5 TP27
C52 VCC VDDQ AN33 <11> CFG5 Y61 CFG5 RSVD_TP
C469 C224 C221 C201 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 CFG6 TP54 CFG6
C56 VCC VDDQ AP43 <11> CFG6 Y60 CFG6
22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 CFG7 TP41 CFG7
E23 VCC VDDQ AR48 <11> CFG7 V62 CFG7 N60
CFG8 TP35 CFG8
E25 VCC VDDQ AY35 <11> CFG8 V61 CFG8 RSVD W23
CFG9 TP34 CFG9
E27 VCC VDDQ AY40 <11> CFG9 V60 CFG9 RSVD Y22
CFG10 TP49 CFG10
E29 VCC VDDQ AY44 <11> CFG10 U60 CFG10 RSVD
CFG11 TP43 CFG11
E31 VCC VDDQ AY50 Direct tie to CPU VCC/VSS-Ball <11> CFG11
CFG12 TP36 CFG12 T63 CFG11 AY15 PROC_OPI_RCOMP
D VCC VDDQ <11> CFG12 CFG12 PROC_OPI_RCOMP D
E33 CFG13 TP31 CFG13 T62
E35 VCC <11> CFG13 T61 CFG13
C234 C199 C222 C471 CFG14 TP30 CFG14
E37 VCC <11> CFG14 T60 CFG14
22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 CFG15 TP42 CFG15

RESERVED
E39 VCC <11> CFG15 AA62 CFG15
C552 C550 C554 C551 CFG16 TP16 CFG16
E41 VCC <11> CFG16 AA61 CFG16 AV62
2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 CFG17 TP15 CFG17 R523
E43 VCC <11> CFG17 U63 CFG17 RSVD D58
CFG18 TP37 CFG18 49.9/F_4
E45 VCC <11> CFG18 U62 CFG18 RSVD
CFG19 TP39 CFG19
E47 VCC <11> CFG19 CFG19
E49 VCC R448
C223 C214 C235 C466 E51 VCC 49.9/F_4 CFG_RCOMP V63
22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 E53 VCC +1.05V +VCCIO_OUT CFG_RCOMP
E55 VCC P22
E57 VCC D63 R458 *0_8 A5 VSS N21
F24 VCC VSS P62 RSVD VSS
F28 VCC VSS T59 E1
F32 VCC RSVD AD60 D1 RSVD
F36 VCC RSVD AD59 C516 J20 RSVD
C212 C237 C475 C492 F40 VCC RSVD AA59 4.7U/6.3V_6 H18 RSVD P20
22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 F44 VCC RSVD AE60 RSVD RSVD
F48 VCC RSVD AC59 R385 TD_IREF B12 R20
F52 VCC RSVD AG58 8.2K/F_4 TD_IREF RSVD
F56 VCC RSVD U59
G23 VCC RSVD V59 AV63
G25 VCC RSVD TP108 AU63 RSVD_TP
G27 VCC TP104 RSVD_TP
C236 C213 C200 C211 G29 VCC
VCC
HSW ULT POWER +V1.05S_VCCST
22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 G31
G33 VCC C63
VCC TP88 RSVD_TP
G35 Layout note: need routing TP87
C62
G37 VCC R431 B43 RSVD_TP
G39 VCC A59 together and ALERT need RSVD
G41 VCC VCCIO_OUT +VCCIO_OUT
between CLK and DATA.
75/F_4
SVID ALERT
G43 VCC E20 *HSW_ULT_DDR3L
VCC VCCIOA_OUT +VCCIOA_OUT
C245 C187 C198 G45 H_CPU_SVIDALRT# R422 43_4 VR_SVID_ALERT# <32>
22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 G47 VCC
C VCC C
G49
G51 VCC C518 *0.1U/10V_4
G53 VCC
G55 VCC
G57 VCC
H23 VCC
VCC VIDALERT#
L62 H_CPU_SVIDALRT#
+3VPCU
IO Thrm Protect
C178 C179 C182 J23 N63 VR_SVID_CLK
22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 K23 VCC VIDSCLK L63 H_CPU_SVIDDAT
K57 VCC VIDSOUT SVID CLK
L22 VCC H59 PWR_DEBUG
M23 VCC PWR_DEBUG# PWR_DEBUG <11>
VR_SVID_CLK
For 65 degree, 1.8v limit, (SW)
VCC VR_SVID_CLK <32>
M57 TP14 R78
P57 VCC
U57 VCC F60 16.5K/F_4
VCC VR_EN H_VR_ENABLE_MCP <32> +V1.05S_VCCST
C486 C467 C468 C502 W57 C59 THRM_MOINTOR <27>
*22U/6.3VS_8 *22U/6.3VS_8 *22U/6.3VS_8 *22U/6.3VS_8 AB57 VCC VR_READY
VCC Place PU resistor

2
AD57 IMVP_PWRGD_R IMVP_PWRGD_R <27> close to VR
AG57 VCC C145
C24 VCC R398 10K_4 SI modifyR105 *0_4/S IMVP_PWRGD <6,32> 0.1U/10V_4

1
C28 VCC R414
C32 VCC AC22 D1 *RB501V-40 130/F_4 SVID DATA R76
VCC VCCST AE22 2 1
VCCST +V1.05S_VCCST
AE23 H_CPU_SVIDDAT R421 *0_4/S VR_SVID_DATA <32> 3.3K/F_4
F59 VCCST
VCC For 75 degree, 1.2v limit, (HW)
B59 H_VCCST_PWRGD_R R399 *0_4/S H_VCCST_PWRGD THRM_MOINTOR1 <27>
VCCST_PWRGD
L59
RSVD

2
J58 SI modify to short pad R509
N58 RSVD C135
RSVD
SI modify to short pad *0_4/S
AC58 0.1U/10V_4

1
AB23 RSVD P60 TP44 +V1.05S_VCCST
AD23 RSVD RSVD_TP P61 TP40
AA23 RSVD RSVD_TP N59 TP32 THER_CPU
AE59 RSVD RSVD_TP N61 TP38
B RSVD RSVD_TP B
AT2 R402 R504
RSVD
AU44
AV44 RSVD ϭϬϬͲцϭйƉƵůůͲƵƉƚŽsŶĞĂƌƉƌŽĐĞƐƐŽƌ͘ 10K_4 100K_4 NTC

D15 RSVD R408 100/F_4 +VCC_CORE

F22 RSVD
H22 RSVD E63
RSVD VCC_SENSE VCC_SENSE <32>
J21
N23 RSVD E62 D14 1 2 RB501V-40
RSVD VSS_SENSE VSS_SENSE <32> <11,27,29,30,31> HWPG H_VCCST_PWRGD <11> +1.05V +V1.05S_VCCST
R23
T23 RSVD R413 100/F_4
U10 RSVD R459 *0_8/S
AL1 RSVD
AM11 RSVD C508
AP7 RSVD C514 C513
RSVD *10P/50V_4 SI modify to short pad
AU10
AU15 RSVD *1U/6.3V_4 *22U/6.3V_8
RSVD

AW14 TP111
RSVD AY14 TP110
RSVD

+V1.05S_VCCST

*HSW_ULT_DDR3L
R401
150/F_4

PWR_DEBUG

Processor Strapping The CFG signals have a default value of '1' if not terminated on the board.
R400
A *10K_4 A
1 0 Circuit
CFG3
Disable: Enable: Set DFX Enable in DFX interface MSR CFG3 R452 *1K_4
(Physcial Debug Enable)
DFX Privacy
CFG4
Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP CFG4 R143 1K_4
(DP Presence Strap)
+VCCIOA_OUT <2> 352-(&78
+VCCIO_OUT <6>
4XDQWD&RPSXWHU,QF
+1.5V <10,21,24,26,30>
Size Document Number Rev
+1.35VSUS <2,12,13,24,31>
+1.05V <7,10,11,26,27,30,33,35>
Custom
ϬϰͲͲh>dϯͬϵ;WKtZͲϭͿ 1A
+VCC_CORE <32>
Date: Friday, April 26, 2013 Sheet 4 of 40
5 4 3 2 1
 5 4 3 2 1


U19I
U19H
U19G
D33 H17
A11 AJ35 D34 VSS VSS H57
A14 VSS VSS AJ39 AP22 AV59 D35 VSS VSS J10
A18 VSS VSS AJ41 AP23 VSS VSS AV8 D37 VSS VSS J22
A24 VSS VSS AJ43 AP26 VSS VSS AW 16 D38 VSS VSS J59
A28 VSS VSS AJ45 AP29 VSS VSS AW 24 D39 VSS VSS J63
A32 VSS VSS AJ47 AP3 VSS VSS AW 33 D41 VSS VSS K1
A36 VSS VSS AJ50 AP31 VSS VSS AW 35 D42 VSS VSS K12
A40 VSS VSS AJ52 AP38 VSS VSS AW 37 D43 VSS VSS L13
A44 VSS VSS AJ54 AP39 VSS VSS AW 4 D45 VSS VSS L15
A48 VSS VSS AJ56 AP48 VSS VSS AW 40 D46 VSS VSS L17
D A52 VSS VSS AJ58 AP52 VSS VSS AW 42 D47 VSS VSS L18 D
A56 VSS VSS AJ60 AP54 VSS VSS AW 44 D49 VSS VSS L20
AA1 VSS VSS AJ63 AP57 VSS VSS AW 47 D5 VSS VSS L58
AA58 VSS VSS AK23 AR11 VSS VSS AW 50 D50 VSS VSS L61
AB10 VSS VSS AK3 AR15 VSS VSS AW 51 D51 VSS VSS L7
AB20 VSS VSS AK52 AR17 VSS VSS AW 59 D53 VSS VSS M22
AB22 VSS VSS AL10 AR23 VSS VSS AW 60 D54 VSS VSS N10
AB7
AC61
VSS
VSS
VSS
VSS
VSS
VSS
AL13
AL17
AR31
AR33
VSS
VSS
VSS
VSS
VSS
VSS
AY11
AY16
D55
D57
VSS
VSS
VSS
VSS VSS
VSS
VSS
N3
P59
AD21 AL20 AR39 AY18 D59 P63
AD3 VSS VSS AL22 AR43 VSS VSS AY22 D62 VSS VSS R10
AD63 VSS VSS AL23 AR49 VSS VSS AY24 D8 VSS VSS R22
AE10 VSS VSS AL26 AR5 VSS VSS AY26 E11 VSS VSS R8
AE5 VSS VSS AL29 AR52 VSS VSS AY30 E17 VSS VSS T1
AE58 VSS VSS AL31 AT13 VSS VSS AY33 F20 VSS VSS T58
AF11 VSS VSS AL33 AT35 VSS VSS AY4 F26 VSS VSS U20
AF12 VSS VSS AL36 AT37 VSS VSS AY51 F30 VSS VSS U22
AF14 VSS VSS AL39 AT40 VSS VSS AY53 F34 VSS VSS U61
AF15 VSS VSS AL40 AT42 VSS VSS AY57 F38 VSS VSS U9
AF17 VSS VSS AL45 AT43 VSS VSS AY59 F42 VSS VSS V10
AF18 VSS VSS AL46 AT46 VSS VSS AY6 F46 VSS VSS V3
AG1 VSS VSS AL51 AT49 VSS VSS B20 F50 VSS VSS V7
AG11 VSS VSS AL52 AT61 VSS VSS B24 F54 VSS VSS W 20
AG21 VSS VSS AL54 AT62 VSS VSS B26 F58 VSS VSS W 22
AG23 VSS VSS AL57 AT63 VSS VSS B28 F61 VSS VSS Y10
AG60 VSS VSS AL60 AU1 VSS VSS B32 G18 VSS VSS Y59
AG61
AG62
VSS
VSS
VSS VSS
VSS
VSS
VSS
AL61
AM1
AU16
AU18
VSS
VSS
VSS
VSS VSS
VSS
VSS
B36
B4
G22
G3
VSS
VSS
VSS
VSS
VSS
VSS
Y63
V58
AG63 AM17 AU20 B40 G5 AH46
AH17 VSS VSS AM23 AU22 VSS VSS B44 G6 VSS VSS V23
C AH19 VSS VSS AM31 AU24 VSS VSS B48 G8 VSS VSS AH16 C
AH20 VSS VSS AM52 AU26 VSS VSS B52 H13 VSS VSS
AH22 VSS VSS AN17 AU28 VSS VSS B56 VSS
AH24 VSS VSS AN23 AU30 VSS VSS B60
AH28 VSS VSS AN31 AU33 VSS VSS C11
AH30 VSS VSS AN32 AU51 VSS VSS C14
AH32 VSS VSS AN35 AU53 VSS VSS C18
AH34 VSS VSS AN36 AU55 VSS VSS C20
AH36 VSS VSS AN39 AU57 VSS VSS C25
AH38 VSS VSS AN40 AU59 VSS VSS C27 DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3
AH40 VSS VSS AN42 AV14 VSS VSS C38 DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NTCF_AY2 DAISY_CHAIN_NTCF_A3 A4 TEST_A4 TP79
AH42 VSS VSS AN43 AV16 VSS VSS C39 TP109 TEST_AY60 AY60 DAISY_CHAIN_NTCF_AY3 DAISY_CHAIN_NTCF_A4 A60 TEST_A60 TP85
AH44 VSS VSS AN45 AV20 VSS VSS C57 DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NTCF_AY60 DAISY_CHAIN_NTCF_A60 A61 DC_TEST_A61_B61
AH49 VSS VSS AN46 AV24 VSS VSS D12 DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NTCF_AY61 DAISY_CHAIN_NTCF_A61 A62 TEST_A62 TP84
AH51 VSS VSS AN48 AV28 VSS VSS D14 TEST_B2 B2 DAISY_CHAIN_NTCF_AY62 DAISY_CHAIN_NTCF_A62 AV1 TEST_AV1 TP102
AH53 VSS VSS AN49 AV33 VSS VSS D18 TP78 DC_TEST_A3_B3 B3 DAISY_CHAIN_NTCF_B2 DAISY_CHAIN_NTCF_AV1 AW 1 TEST_AW1 TP105
AH55 VSS VSS AN51 AV34 VSS VSS D2 DC_TEST_A61_B61 B61 DAISY_CHAIN_NTCF_B3 DAISY_CHAIN_NTCF_AW 1 AW 2 DC_TEST_AY2_AW2
AH57 VSS VSS AN52 AV36 VSS VSS D21 DC_TEST_B62_B63 B62 DAISY_CHAIN_NTCF_B61 DAISY_CHAIN_NTCF_AW 2 AW 3 DC_TEST_AY3_AW3
AJ13 VSS VSS AN60 AV39 VSS VSS D23 B63 DAISY_CHAIN_NTCF_B62 DAISY_CHAIN_NTCF_AW 3 AW 61DC_TEST_AY61_AW61
AJ14 VSS VSS AN63 AV41 VSS VSS D25 DC_TEST_C1_C2 C1 DAISY_CHAIN_NTCF_B63 DAISY_CHAIN_NTCF_AW 61 AW 62DC_TEST_AY62_AW62
AJ23 VSS VSS AN7 AV43 VSS VSS D26 C2 DAISY_CHAIN_NTCF_C1 DAISY_CHAIN_NTCF_AW 62 AW 63TEST_AW63 TP107
AJ25 VSS VSS AP10 AV46 VSS VSS D27 DAISY_CHAIN_NTCF_C2 DAISY_CHAIN_NTCF_AW 63
AJ27 VSS VSS AP17 AV49 VSS VSS D29
AJ29 VSS VSS AP20 AV51 VSS VSS D30
VSS VSS AV55 VSS VSS D31
VSS VSS
^Dd
*HSW_ULT_DDR3L
*HSW_ULT_DDR3L

B *HSW_ULT_DDR3L B

A A

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom
h>dϰͬϵ;Z^s͕'EͿ 1A

Date: Monday, May 06, 2013 Sheet 5 of 40

5 4 3 2 1
 5 4 3 2 1

Lynx Point-LP Platform Controller Hub (LVDS,DDI)

U19M Ϭϲ

SIDEBAND
PCH_LVDS_BLON A9
<19> PCH_LVDS_BLON EDP_BKLEN
PCH_DISP_ON C6
<19> PCH_DISP_ON EDP_VDDEN
PCH_DPST_PWM B8
D
<19> PCH_DPST_PWM EDP_BKLCTL D

R379 *0_4 B9 SDVO_CLK

<2> EDP_DISP_UTIL DDPB_CTRLCLK SDVO_CLK <20>
C9 SDVO_DATA

EDP
DDPB_CTRLDATA SDVO_DATA <20>

INT. HDMI
Need Check!
C5
DDPB_AUXN B5
DDPB_AUXP C8 HDMI_HPD_CON
DDPB_HPD HDMI_HPD_CON <20>

U19L
DSWVRMEN <7>
SUSWARN# R480 *0_4 SUSACK# For DS3 -->Ra
for DS3 AW 7 DSWVRMEN
SINon-DS3
modify to -->Rb

System Power Management

DSW VRMEN short pad
Ra
SI modify to short pad R543 *0_4/S DPWROK_EC
DPWROK_EC <27>
R472 *0_4/S SUSACK# AK2 AV5 DPWROK R542 *0_4 RSMRST#
<27> SUSACK#_EC SUSACK# DPW ROK

DISPLAY
Rb D9
DDPC_CTRLCLK D11
SYS_RESET# AC3 AJ5 PCIE_WAKE# DDPC_CTRLDATA
<11> SYS_RESET# SYS_RESET# W AKE# PCIE_WAKE# <22,23,26,27>
C531 *0.1U/10V_4 B6
AG2 V5 CLKRUN# DDPC_AUXN A6
<11> SYS_PWROK SYS_PW ROK CLKRUN#/ GPIO32 CLKRUN# <24,27> DDPC_AUXP A8
DDPC_HPD
EC_PWROK AY7 AG4 SUS_STAT# TP50
<27> EC_PWROK PCH_PW ROK SUS_STAT# / GPIO61 (SUS)
C C
EC_PWROK AB5 AE6 PCH_SUSCLK_L R116 *0_4/S
APW ROK SUSCLK / GPIO62 (SUS) PCH_SUSCLK <27>

TP26
PLTRST# AG7 AP5
PLTRST# SLP_S5# / GPIO63 ( DSW ) SLP_S5# <11>

AJ6
SLP_S4# SUSC# <11,27>
for DS3 RSMRST# AW 6
<27> RSMRST# RSMRST#
R479 *0_4/S SUSWARN# AV4 AT4
<27> SUSWARN#_EC SUSW ARN#/SUSPW RDNACK/GPIO30(SUS) SLP_S3# SUSB# <11,27>

SI modify to short pad TP55

R164 *0_4/S DNBSWON#_R AL7 AL5 for DS3
<11,27> DNBSWON# PW RBTN# SLP_A# SLP_A# <11>
D6 INT_eDP_HPD_Q
EDP_HPD
R138 *0_4/S AC_PRESENT_R AJ8 AP4 SLP_SUS# R142 *0_4/S SLP_SUS#_EC
<27> AC_PRESENT_EC ACPRESENT / GPIO31(DSW ) SLP_SUS# SLP_SUS#_EC <27>
SI modify to short pad
PM_BATLOW# AN4
BATLOW # / GPIO72(DSW )
PCH_SLP_S0_N AF3 AJ7 SLP_LAN# TP69
<11,27> PCH_SLP_S0_N SLP_S0# SLP_LAN#
PCH_SLP_WLAN_N AM5
TP62 SLP_W LAN#/ GPIO29(DSW )
*HSW_ULT_DDR3L *HSW_ULT_DDR3L

B B

PCH Pull-high/low(CLG) PLTRST#(CLG) System PWR_OK(CLG)

+3VS5 <7,8,9,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34> +3V
<9,10,11,24,26,29,30,33,35> +3VS5
PM_BATLOW# R156 10K_4
Check Q2010 Rise/Fall time less than 100ns
PCIE_WAKE# R131 1K_4 PLTRST#
PLTRST# <11,14,22,23,24,26,27>
R453 100K_4
Change to 1k for LAN wake from OBFF state issue
+3VS5

+3V_DEEP_SUS
Reserve EDP_HPD opposites circuit! C522 *0.1U/10V_4

SUSACK# R471 10K_4 for DS3 SI modify to short pad +VCCIO_OUT

SUSWARN# R478 10K_4

5
Check SUSWARN# need PU? R449 *0_4/S
2
IMVP_PWRGD <4,32>
PWRBTN# internally PU in PCH to 3.3V_DSW R468 DG V0.7 -> 10K SYS_PWROK 4
DNBSWON#_R R163 *10K_4 *10K/F_4 1 EC_PWROK
AC_PRESENT_R R137 *10K_4 Q33 *2N7002 SCH V0.7 -> 1K
+3VS5
U17

3
+3V INT_eDP_HPD_Q 1 3 INT_eDP_HPD R497 *0_4/S *TC7SH08FU R430
10K_4
3

A A
SYS_PWROK R481 *1K_4 SI modify to short pad
2

+5V
CLKRUN# R121 8.2K/F_4 2
ULT_EDP_HPD <19,20>
SYS_RESET# R119 10K_4 R447 *0_4/S

R123 *1K_4
R442
*100K_4
R500
*100K_4 Q36 R501
352-(&78
4XDQWD&RPSXWHU,QF
1

*2N7002 100K_4 SI modify to short pad

RSMRST# R541 10K_4 RTD2132R Vender request PD 100kohm

DPWROK_EC R544 100K_4 Size Document Number Rev

Custom
h>dϱͬϵ;WŽǁĞƌDĂŶŐĞƌͿ 1A

Date: Friday, April 26, 2013 Sheet 6 of 40

5 4 3 2 1
 5 4 3 2 1

Ϭϳ
Lynx Point-LP Platform Controller Hub
(HDA,JTAG,SATA) RTC Clock 32.768KHz SI modify to short pad
U19J
R494 *0_4/S
AW 5 AU14 +1.05V +1.05VS5 CLKGEN_RTC_X1 <26>
RTC_X1
RTCX1 LAD0 LAD0 <24,26,27>
AW 12
LAD1 LAD1 <24,26,27>
RTC_X2 AY5 AY12 R476 *0_4 R473 *51_4 JTAGX_PCH C530 *18P/50V_4 RTC_X1
RTCX2 LAD2 LAD2 <24,26,27>
AW 11
LAD3 LAD3 <24,26,27>

2
1
RTC_RST# AU7 R469 51_4 JTAG_TMS_PCH
<11> RTC_RST# RTCRST# AV12
LFRAME# LFRAME# <24,26,27>
SRTC_RST# AV6 R460 51_4 JTAG_TDI_PCH Y4 R483
SRTCRST# *32.768KHZ *10M_4
D
+3V_RTC R521 1M_4 SM_INTRUDER# AU6 R487 51_4 JTAG_TDO_PCH D

3
4
INTRUDER#

LPC
RTC
C534 *18P/50V_4 RTC_X2
PCH_INVRMEN AV7 R477 *51_4 JTAG_TCK_PCH
INTVRMEN
Close to Chipset
J5 SATA_RXN0
ACZ_BCLK AW 8
HDA_BCLK / I2S0_SCLK
SATA_RN0/ PERN6_L3
SATA_RP0/ PERP6_L3
H5
B15
SATA_RXP0
SATA_TXN0
SATA_RXN0
SATA_RXP0
<24>
<24>
no stuff If use green Clock
AV11 SATA_TN0/ PETN6_L3 A15 SATA_TXN0 <24>
ACZ_SYNC SATA_TXP0
HDA_SYNC/ I2S0_SFRM SATA_TP0/ PETP6_L3 SATA_TXP0 <24> HDD0 (SATA3 6.0Gb/s)
J8 SATA_RXN1 30mils
ACZ_RST# AU8
SATA_RN1/ PERN6_L2
SATA_RP1/ PERP6_L2
H8
A17
SATA_RXP1
SATA_TXN1
SATA_RXN1
SATA_RXP1
<24>
<24>
RTC Circuitry(RTC) +3V_RTC
HDA_RST#/ I2S_MCLK SATA_TN1/ PETN6_L2 B17 SATA_TXP1
SATA_TXN1 <24> mSATA (SATA4 6Gb/s) R341
SATA_TP1/ PETP6_L2 SATA_TXP1 <24>
RTC_RST#
AY10 J6 SATA_RXN2
<21> ACZ_SDIN0 HDA_SDIN0/ I2S0_RXD SATA_RN2/ PERN6_L1 SATA_RXN2 <23>
H6 SATA_RXP2 20K/F_4
SATA_RP2/ PERP6_L1 SATA_RXP2 <23>

AUDIO
AU12 B14 SATA_TXN2
HDA_SDIN1/ I2S1_RXD SATA_TN2/ PETN6_L1 C15 SATA_TXP2
SATA_TXN2 <23> ODD (SATA3 6.0Gb/s) RTC Power trace width 20mils. C462
AU11 SATA_TP2/ PETP6_L1 SATA_TXP2 <23>
ACZ_SDOUT 1U/6.3V_4
HDA_SDO/ I2S0_TXD F5 +3V_RTC_0 R347
AW 10 SATA_RN3/ PERN6_L0 E5 20K/F_4
HDA_DOCK_EN# / I2S1_TXD SATA_RP3/ PERP6_L0 +3VPCU
C17 R346 SRTC_RST#
AV10 SATA_TN3/ PETN6_L0 D17 +3V_RTC_0 *1K_4 +3V_RTC_1
HDA_DOCK_RST/ I2S1_SFRM SATA_TP3/ PETP6_L0 D9

1
AY8 *BAT54C C464
I2S1_SCLK CN18 C463
BAT_CONN *1U/6.3V_4 1U/6.3V_4
TP97

2
XDP_TRST#_CPU AU62 V1 ACC_LED#
C <2,11> XDP_TRST#_CPU PCH_TRST# SATA0GP/ GPIO34 ACC_LED# <21> C
JTAG_TCK_PCH AE62 U1 SIO_EXT_SMI#
TP95 Uninstall for Green-CLK
<11> JTAG_TCK_PCH PCH_TCK SATA1GP/ GPIO35 SIO_EXT_SMI# <27> RTC_RST# R345 *0_6 SRTC_RST#
JTAG_TDI_PCH AD61 V6 PCI_SERR#
<11> JTAG_TDI_PCH PCH_TDI SATA2GP/ GPIO36 PCI_SERR# <27>
TP93
JTAG_TDO_PCH AE61 AC1 SATA3GP
<11> JTAG_TDO_PCH PCH_TDO SATA3GP/ GPIO37 TP101
HDA Bus(CLG) GPIO Pull UP
+3V
JTAG

JTAG_TMS_PCH AD62
<11> JTAG_TMS_PCH AL11 PCH_TMS C12 SATA_RCOMP R391 3.01K/F_4 ACC_LED# R454 10K_4
RSVD SATA_RCOMP +V1.05S_ASATA3PLL
AC4 SIO_EXT_SMI# R106 10K_4
RSVD R533 33_4 ACZ_SYNC PCI_SERR# R420 10K_4
<21> ACZ_SYNC_AUDIO
AE63
SATA

JTAGX_PCH SATA3GP R474 10K_4

<11> JTAGX_PCH AV2 JTAGX
DG recommended that SATA AC coupling capacitors should be R535 33_4 ACZ_RST#
RSVD <21> ACZ_RST#_AUDIO
TP70 SI modify to short pad close to the connector (<100 mils) for optimal signal quality.
R530 33_4 ACZ_SDOUT
<21> ACZ_SDOUT_AUDIO
PCH_SPI1_CLKAA3 A12 SATA_IREF R362 *0_6/S
SPI_CLK SATA_IREF R532 33_4 ACZ_BCLK
<21> BIT_CLK_AUDIO
PCH_SPI_CS0# Y7 R450 10K_4
SPI_CS0# +3V
Y4 C553
AC2 SPI_CS1# U3 *10P/50V_4
SPI_CS2# SATALED# SATA_LED# <21>
PCH_SPI1_SI AA2
SPI_MOSI L11 R181 *1K_4 ACZ_SYNC
RSVD +3V_DEEP_SUS
SPI

PCH_SPI1_SO AA4 K10

SPI_MISO RSVD
PCH_SPI_IO2 Y6
PCH_SPI_IO3 AF1 SPI_IO2
SPI_IO3

B
PCH Strap Table *HSW_ULT_DDR3L
B

Pin Name Strap description Sampled Configuration Circuit

0 = Default (weak pull-down 20K) Vender Size P/N
SPKR No reboot mode setting PWROK 1 = Setting to No-Reboot mode +3V R455 *1K_4 SPKR
SPKR <9>
PCH SPI ROM(CLG)
MXIC 8MB AKE3EZN0Z00 (MX25L6473EM2I-10G)
0 = "top-block swap" mode R376 *1K_4
SDIO_D0 /GPIO66 Top-Block Swap PWROK 1 = Default (weak pull-up 20K) R375 *1K_4 Winbond 8MB AKE3EFP0N07 (W25Q64FVSSIQ)
GPIO66_ULT <9>

PCH_INVRMEN
GigaDevice 8MB AKE3EGN0Q01 (GD25B64BSIGR)
INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up +3V_RTC R519 330K_4
Socket DFHS08FS023
Flash Descriptor Security 0 = Default (weak pull-down 20K) ACZ_SDOUT PCH_SPI_CS0#_R
HDA_SDO /I2S0_TXD Only for Interposer PWROK 1 = Can be Overridden R182 1K_4
<27> GPIO33_EC TP12
PCH_SPI1_CLK_R
TP19
PCH_SPI1_SI_R SI modify to short pad
GNT0# Boot Location TP66-71 need place to TOP TP11 PCH_SPI1_SO_R
TP10
GSPI0_MOSI /GPIO86 Boot BIOS Selection PWROK 1 LPC BIOS_WP# +3V_DEEP_SUS R438 *0_4/S
TP13
0 SPI(Default) HOLD#
TP18
U15
PCH_SPI_CS0# R386 15/F_4 PCH_SPI_CS0#_R 1 8 +3VSPI
PCH_SPI1_CLK R441 15/F_4 PCH_SPI1_CLK_R 6 CE# VDD
0 = ME Crypto Transport Layer Security PCH_SPI1_SI R436 PCH_SPI1_SI_R 5 SCK
GPIO15 TLS Confidentiality PWROK 15/F_4 R451 3.3K/F_4
cipher suite with no confidentiality(Default) PCH_SPI1_SO R387 15/F_4 PCH_SPI1_SO_R 2 SI 7HOLD#
R125 *1K_4 SO HOLD# R440 15/F_4
1 = Intel ME Crypto TLS cipher suite with +3V_DEEP_SUS GPIO15_ULT <9> R457/R453/R450/R451/R546/R548 close to U15 pin 3 4
confidentiality C521 W P# VSS
DSWVRMEN Deep Sx Well 22P/50V_4 GD25B64BSIGR C520
R520 330K_4 AKE3EGN0Q01 0.1U/10V_4
On-Die Voltage +3V_RTC DSWVRMEN <6>
ALWAYS Should be always pull-up
A Regulator Enable C620 1U/10V_4 +3VSPI R389 3.3K/F_4 A
PCH_SPI_IO2 R388 15/F_4 BIOS_WP# SI modify
PCH_SPI_IO3
+3V <6,8,9,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34>
+5V <6,20,21,23,24,25,26,33>

<27> PCH_SPI_CS0#_R
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
+1.05V <4,10,11,26,27,30,33,35> 352-(&78
<27>
<27>
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
+3VS5
+3VPCU
<6,9,10,11,24,26,29,30,33,35>
<4,21,24,25,26,27,28,29> 4XDQWD&RPSXWHU,QF
<27> PCH_SPI1_SO_R +3V_RTC <10,26>
+V1.05S_ASATA3PLL <10>
Size Document Number Rev
Custom
h>dϲͬϵ;^dͬ,Ϳ 1A

Date: Friday, April 26, 2013 Sheet 7 of 40

5 4 3 2 1
 5 4 3 2 1

Ϭϴ
Lynx Point-LP Platform Controller Hub
PCI/USBOC# Pull-up(CLG)
(HDA,JTAG,SATA)
+3V U19N
DGPU_PWR_EN R428 *10K_4 U19K
G17
TS_INTB# R432 10K_4 F17 PERN1 / USB3RN3
PIRQC# R103 10K_4 C30 PERP1 / USB3RP3 AN2 SMBALERT#
PIRQD# R423 10K_4 C31 PETN1 / USB3TN3 SMBALERT# / GPIO11(SUS)
PETP1 / USB3TP3

SMBUS
AP2 SMB_PCH_CLK
GPIO77_ULT R403 10K_4 F15 SMBCLK
<23> PCIE_RXN2_CARD PERN2/ USB3RN4
GPIO52_ULT
GPIO53_ULT
R418
R416
10K_4
10K_4 ĂƌĚƌĞĂĚĞƌ <23>
<23>
PCIE_RXP2_CARD
PCIE_TXN2_CARD C192 0.1U/10V_4 PCIE_TXN2_CARD_C
G15
B31 PERP2/ USB3RP4 SMBDATA
AH1 SMB_PCH_DAT

GPIO55_ULT R111 10K_4 C193 0.1U/10V_4 PCIE_TXP2_CARD_C A31 PETN2/ USB3TN4

<23> PCIE_TXP2_CARD PETP2/ USB3TP4
D DGPU_HOLD_RST# R104 10K_4 AL2 SML0ALERT# D
DGPU_HOLD_RST# R102 *100K_4 G11 SML0ALERT# / GPIO60(SUS)
<26> PCIE_RXN3_WLAN PERN3
F11 AN1 SMB_ME0_CLK

C- Link
WLAN <26> PCIE_RXP3_WLAN
C494 0.1U/10V_4 PCIE_TXN3_WLAN_C C29 PERP3 SML0CLK
<26> PCIE_TXN3_WLAN PETN3
<26> PCIE_TXP3_WLAN C493 0.1U/10V_4 PCIE_TXP3_WLAN_C B30 AK1 SMB_ME0_DAT
+3V_DEEP_SUS PETP3 SML0DATA
for DS3 AF2 <22> PCIE_RXN4_LAN PCIE_RXN4_LAN F13

PCI-E*
SMBALERT# R498 10K_4 CL_CLK PCIE_RXP4_LAN G13 PERN4 AU4 SML1ALERT#
<22> PCIE_RXP4_LAN PERP4 SML1ALERT# / PCHHOT# / GPIO73(SUS) TP68
USB_OC1# R171 10K_4 AD2 LAN <22> PCIE_TXN4_LAN C496 0.1U/10V_4 PCIE_TXN4_LAN_C B29
USB_OC2# R172 10K_4 CL_DATA C495 0.1U/10V_4 PCIE_TXP4_LAN_C A29 PETN4 AU3 SMB_ME1_CLK
<22> PCIE_TXP4_LAN PETP4 SML1CLK / GPIO75(SUS)
USB_OC3# R173 10K_4 AF4
USB_OC4# R484 10K_4 CL_RST# F10 AH3 SMB_ME1_DAT
<14> PEG_RXN0 SI modify to short pad
E10 PERN5_L0 SML1DATA / GPIO74(SUS)
<14> PEG_RXP0 PERP5_L0 PCH_XTAL24_IN <26>
<14> PEG_TXN0 C183 0.22U/10V_4 PEG_TXN0_C C23 R369 *0_4/S TP82
C184 0.22U/10V_4 PEG_TXP0_C C22 PETN5_L0
<14> PEG_TXP0 PETP5_L0 C501 *12P/50V_4
<14> PEG_RXN1 F8
(USBP0) PERN5_L1

1
2
USB2.0(M/B-1) <14> PEG_RXP1 E8
PERP5_L1
USB2.0/USB3.0 COMBO 1st <14> PEG_TXN1 C188 0.22U/10V_4 PEG_TXN1_C B23 A25 XTAL24_IN R392
C189 0.22U/10V_4 PEG_TXP1_C A23 PETN5_L1 XTAL24_IN B25 XTAL24_OUT *1M_4 *24MHZ +-30PPM
USB2.0 Small board <14>
(USBP1) PEG_TXP1 PETP5_L1 XTAL24_OUT Y3
USB2.0/USB3.0 COMBO 2nd <14> PEG_RXN2 H10

3
4
G20 AN8 G10 PERN5_L2 C500 *12P/50V_4
<25> USB30_RX1- USB3RN1 USB2N0 USBP0- <25> <14> PEG_RXP2 PERP5_L2
H20 AM8 USBP0+ <25> <14> PEG_TXN2 C190 0.22U/10V_4 PEG_TXN2_C B21
<25> USB30_RX1+ USB3RP1 USB2P0 PETN5_L2
C33 AR7 USBP1- <21> <14> PEG_TXP2 C191 0.22U/10V_4 PEG_TXP2_C C21 TP81
<25> USB30_TX1- USB3TN1 USB2N1 PETP5_L2
B34 AT7 USBP1+ <21> B35 CK_XDP_N_R RP1 2 1
<25> USB30_TX1+ USB3TP1 USB2P1 CLKOUT_ITPXDP# CK_XDP_N <11>
AR8 USBP2- <20> A35 CK_XDP_P_R *0_4P2R_4 4 3
USB2N2 CLKOUT_ITPXDP_P CK_XDP_P <11>
AP8 USBP2+ <20> <14> PEG_RXN3 E6
USB2P2 PERN5_L3
h^ϯ͘Ϭ USB2N3
AR10
AT10
Camera (USBP2) <14>
<14>
PEG_RXP3
PEG_TXN3 C185 0.22U/10V_4 PEG_TXN3_C
F6
B22 PERP5_L3
RP1 install for XDP EC34 18P/50V_4

E18 USB2P3 AM15 C186 0.22U/10V_4 PEG_TXP3_C A21 PETN5_L3

<25> USB30_RX2- USB3RN2 USB2N4 <14> PEG_TXP3 PETP5_L3
F18 AL15 USB2.0(M/B-2) (USBP5) AN15 CLK_PCI_EC_R R525 22_4 CLK_24M_KBC <27>
<25> USB30_RX2+ USB3RP2 USB2P4 CLKOUT_LPC_0
B33 AM13 USBP5- <25> SI modify R98 *0_4/S PCIE_IREF B27 AP15 CLK_PCI_LPC_R CLK_24M_DEBUG <26>
C <25> USB30_TX2- USB3TN2 USB2N5 PCIE_IREF CLKOUT_LPC_1 C
A33 AN13 USBP5+ <25> R99 3.01K/F_4 PCIE_RCOMP A27 R524 22_4
<25> USB30_TX2+ USB3TP2 USB2P5 <10> +V1.05S_AUSB3PLL PCIE_RCOMP
AP11 USBP6- <26> E15 EMI(near PCH)
USB2N6 AN11 E13 RSVD
USB2P6 USBP6+ <26> WLAN RSVD
AR13 EC33 18P/50V_4
USB2N7 AP13
USB2P7 Touch Screen C43 R5103 22_4
CLK_PCI_TPM <24>
USBP7- <26> CLKOUT_PCIE0N
USBP7+ <26> C42 EMI(near PCH)
CLKOUT_PCIE0P
20111130 Modify USB3.0 for HM70 PCIE_CLKREQ0# U2 EC44 *18P/50V_4
PCIECLKRQ0# / GPIO18
GPIO77_ULT U6
Cardreader CLK_PCIE_CRN B41
R384
PIRQA#/ GPIO77 <23> CLK_PCIE_CRN CLKOUT_PCIE_N1
TS_INTB# P4 SI modify <23> CLK_PCIE_CRP CLK_PCIE_CRP A41 C26 XCLK_BIASREF +V1.05S_AXCK_LCPLL <10>
PIRQC# N4 PIRQB#/ GPIO78 CLKOUT_PCIE_P1 DIFFCLK_BIASREF
PIRQD# N2 PIRQC#/ GPIO79 PCIE_CLKREQ_CR# Y5

CLOCK SIGNALS
PIRQD#/ GPIO80 <23> PCIE_CLKREQ_CR# PCIECLKRQ1# / GPIO19 3.01K/F_4
SI modify to short pad CLK_PCIE_WLANN C41
<26> CLK_PCIE_WLANN CLKOUT_PCIE_N2
GPIO52_ULT L1 WLAN <26> CLK_PCIE_WLANP CLK_PCIE_WLANP B42
R417 *0_4/S DGPU_PWR_EN_R L3 GPIO52 CLKOUT_PCIE_P2
<15,34,35> DGPU_PWR_EN GPIO54
<26> PCIE_CLKREQ_WLAN# PCIE_CLKREQ_WLAN# AD1
DGPU_HOLD_RST# R5 PCIECLKRQ2# / GPIO20
<14> DGPU_HOLD_RST# GPIO51
GPIO53_ULT L4 <22> CLK_PCIE_LANN CLK_PCIE_LANN B38
PCI

GPIO55_ULT U7 GPIO53 CLK_PCIE_LANP C37 CLKOUT_PCIE_N3 K21

GPIO55 TIE TRACES TOGETHER
LAN <22> CLK_PCIE_LANP CLKOUT_PCI_P3 RSVD
CLOSE TO PINS WITH LENGTH PCIE_CLKREQ_LAN# N1 M21
TO RESISTOR <22> PCIE_CLKREQ_LAN# PCIECLKRQ3# / GPIO21 RSVD
USB

<14> CLK_VGA_N CLK_VGA_N A39 C35 R380 10K/F_4

AJ10 USB_BIAS R140 CLK_VGA_P B39 CLKOUT_PCIE_N4 TESTLOW_C35
USBRBIAS# AJ11 22.6/F_4
VGA <14> CLK_VGA_P CLKOUT_PCIE_P4 C34 R381 10K/F_4
USBRBIAS PCIE_CLKREQ_VGA# U5 TESTLOW_C34
<14> PCIE_CLKREQ_VGA# PCIECLKRQ4# / GPIO22
AN10 AK8 R531 10K/F_4
PCI_PME# AD4 RSVD AM10 B37 TESTLOW_AK8
TP46 PME# RSVD CLKOUT_PCIE_N5
A37 AL8 R141 10K/F_4
AL3 USB_OC1# TP65 CLKOUT_PCIE_P5 TESTLOW_AL8
B B
OC0# / GPIO40(SUS) AT1 USB_OC2# TP66 PCIE_CLKREQ5# T2
OC1# / GPIO41(SUS) AH2 USB_OC3# TP64 PCIECLKRQ5# / GPIO23
OC2# / GPIO42(SUS) SI modify
AV3 USB_OC4# TP100
OC3# / GPIO43(SUS)
*HSW_ULT_DDR3L

*HSW_ULT_DDR3L

SMBus/Pull-up(CLG) CLK_REQ/Strap Pin(CLG) +3V

+3V SMBus/Pull-up(CLG)
PCIE_CLKREQ0# R443 10K_4
Q34
PCIE_CLKREQ5# R115 10K_4
5 PCIE_CLKREQ_WLAN# R482 10K_4
PCIE_CLKREQ_LAN# R425 10K_4
4 3 SMB_ME1_CLK PCIE_CLKREQ_CR# R445 10K_4
<13,19,27> MBCLK2
PCIE_CLKREQ_VGA# R114 10K_4
for DS3
2 +3V_DEEP_SUS R499 2.2K_4 SMB_PCH_CLK
R486 2.2K_4 SMB_PCH_DAT
1 6 SMB_ME1_DAT
<13,19,27> MBDATA2
R168 2.2K_4 SMB_ME0_CLK
R493 2.2K_4 SMB_ME0_DAT
*2N7002DW R178 2.2K_4 SMB_ME1_CLK
A +3V R485 2.2K_4 SMB_ME1_DAT A

Q35
R179 10K_4 SML1ALERT#
+3V R495 4.7K_4 5 R492 1K_4 SML0ALERT#

4 3 SMB_PCH_DAT
<11,12,13,19,24> SMB_RUN_DAT

+3V R461 4.7K_4 2 352-(&78

<11,12,13,19,24> SMB_RUN_CLK
1 6 SMB_PCH_CLK 4XDQWD&RPSXWHU,QF
Size Document Number Rev
2N7002DW <6,7,9,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34> +3V Custom
h>dϳͬϵ;W/ͬh^ͬ><Ϳ 1A
<6,7,9,10,11> +3V_DEEP_SUS
Date: Friday, April 26, 2013 Sheet 8 of 40
5 4 3 2 1
 5 4 3 2 1

ͽΪΟΩ͑΁ΠΚΟΥ͞ͽ΁͑΁ΝΒΥΗΠΣΞ͑ʹΠΟΥΣΠΝΝΖΣ͑͹ΦΓ

Ϭϵ
RP6
RP7 10 1 I2C0_SCL
͙͹͵Ͳ͝ͻ΅Ͳ͸͝΄Ͳ΅Ͳ͚ Haswell (GPIO) UART1_RXD
10
9
1
2
SDIO_D2
SDIO_D1
GSPI1_MOSI
GSPI0_MISO
9
8
2
3
I2C1_SCL
I2C0_SDA
U19O SI modify to short pad I2C1_SDA 8 3 SDIO_CMD GSPI1_MISO 7 4 SDIO_D3
TP67 GSPI0_CLK 7 4 SDIO_CLK UART0_TXD 6 5
SIO_EXT_SCI# AU2 D60 PCH_THRMTRIP# R405 *0_4/S GSPI1_CLK 6 5
<27> SIO_EXT_SCI# GPIO8(SUS) THRMTRIP# PM_THRMTRIP# <27>
10K_10P8R_6
BT_OFF AM3 10K_10P8R_6
<26> BT_OFF GPIO9(SUS) +3V
TP57 +3V
RF_OFF AM2 V4 EC_RCIN#
<26> RF_OFF GPIO10(SUS) RCIN#/ GPIO82 EC_RCIN# <27>
TP52 RP5

CPU/MISC
LAN_DISABLE# AM7 T4 SERIRQ R113 10K_4 10 1 UART1_RST
LAN_PHY_PW R_CTRL / GPIO12(DSW ) SERIRQ +3V
for DS3 UART0_RXD 9 2 UART0_RTS
SERIRQ <24,27>
D R175 10K_4 GPIO13_ULT AT3 UART1_CTS 8 3 UART0_CTS D
+3V_DEEP_SUS GPIO13(SUS) R522 GSPI0_CS 7 4 UART1_TXD
GPIO14_ULT AH4 AW 15 PCH_OPI_RCOMP 49.9/F_4 GSPI1_CS 6 5
TP103 GPIO14(SUS) PCH_OPI_RCOMP
AD6 AF20 10K_10P8R_6
<7> GPIO15_ULT GPIO15(SUS) RSVD
+3V
Reserve
<23> ZERO_ODD_DP# R631 *0_4 ODD_PRSNT#_R Y1 AB21
GPIO16 RSVD
SI modify TP92
T3
<16,27,36> DGPU_PWROK GPIO17
GPIO24_ULT AD5
GPIO24 (SUS) GPIO Pull-up/Pull-down(CLG) +3V_DEEP_SUS
GPIO25_ULT AM4 R6 GSPI0_CS
GPIO25(DSW ) GSPI0_CS/ GPIO83 SIO_EXT_SCI# R174 10K_4
GPIO26_ULT AN3 L6 GSPI0_CLK BT_OFF R177 10K_4

GPIO
GPIO26(SUS) GSPI0_CLK/ GPIO84 RF_OFF R139 10K_4
TP5038 GPIO27_ULT AN5 N6 GSPI0_MISO GPIO13_ULT R176 10K_4
GPIO27(DSW ) GSPI0_MISO/ GPIO85 GPIO14_ULT R489 10K_4
GPIO28_ULT AD7 L8 GPIO86_ULT TP33
GPIO28(SUS) GSPI0_MOSI/ GPIO86 GPIO24_ULT R488 10K_4
DEVSLP0 P2 GPIO26_ULT R180 10K_4
DEVSLP0/ GPIO33 R7 GSPI1_CS GPIO28_ULT R126 10K_4
DEVSLP1 L2 GSPI1_CS/ GPIO87 GPIO44_ULT R491 10K_4
<24> DEVSLP1 DEVSLP1/ GPIO38 L5 GSPI1_CLK ACCEL_INTA# R490 10K_4
DEVSLP2 N5 GSPI1_CLK/ GPIO88
DEVSLP2/ GPIO39 N7 GSPI1_MISO
GPIO44_ULT AK4 GSPI1_MISO/ GPIO89
GPIO44(SUS) K2 GSPI1_MOSI +3V
BOARD_ID4 AG5 GSPI1_MOSI/ GPIO90
TP for DG GPIO45(SUS)
C ACCEL_INTA# AG3 J1 UART0_RXD GPIO49_ULT R475 10K_4 C
TP29 <26> ACCEL_INTA# GPIO46(SUS) UART0_RXD/ GPIO91 GPIO50_ULT R433 10K_4

SERIAL IO
BOARD_ID5 AB6
GPIO47(SUS) UART0_TXD/ GPIO92
K3 UART0_TXD SI modify ODD_PRSNT#_R R470 10K_4
DGPU_PWROK R424 10K_4
BT_COMBO_EN# U4 J2 UART0_RTS DEVSLP0 R407 10K_4
<26> BT_COMBO_EN# GPIO48 UART0_RTS/ GPIO93 DEVSLP1 R429 10K_4
TP99 GPIO49_ULT Y3 G1 UART0_CTS DEVSLP2 R396 10K_4
GPIO49 UART0_CTS/ GPIO94 BT_COMBO_EN# R112 10K_4
GPIO50_ULT P3 GPIO70_ULT R383 10K_4
GPIO50 K4 UART1_RXD EC_RCIN# R444 10K_4
BOARD_ID0 AG6 UART1_RXD/ GPIO0 GPIO12 LAN_DISABLE#
GPIO56(SUS) G2 UART1_TXD SUS -->Check list
BOARD_ID1 AP1 UART1_TXD/ GPIO1 +3V -->Datasheet GPIO76_ULT R434 10K_4
GPIO57(SUS) J3 UART1_RST MPHY_PWREN R465 100K_4
BOARD_ID2 AL4 UART1_RST/ GPIO2 MPHY_PWREN R464 *10K_4
GPIO58(SUS) J4 UART1_CTS
TP106 BOARD_ID3 AT5 UART1_CTS/ GPIO3
GPIO59(SUS)
GPIO70_ULT C4 F2 I2C0_SDA
SDIO_POW ER_EN/ GPIO70 I2C0_SDA/ GPIO4
MPHY_PWREN Y2 F3 I2C0_SCL +3VS5
<33> MPHY_PWREN HSIOPC/ GPIO71 I2C0_SCL/ GPIO5
G4 I2C1_SDA GPIO25_ULT R134 10K_4
TP94 GPIO76_ULT P1 I2C1_SDA/ GPIO6 GPIO27_ULT R161 10K_4
BMBUSY# / GPIO76 F1 I2C1_SCL LAN_DISABLE# R136 10K_4
SI modify to short pad I2C1_SCL/ GPIO7
R456 *0_4/S SPKR V2
<21> ACZ_SPKR SPKR/ GPIO81 E3 SDIO_CLK
SDIO_CLK/ GPIO64
F4 SDIO_CMD
Close to EC
B SDIO_CMD/ GPIO65 B
<7> SPKR D3 +V1.05S_VCCST
SDIO_D0/ GPIO66 GPIO66_ULT <7>
E4 SDIO_D1 PM_THRMTRIP# R135 1K_4
SDIO_D1/ GPIO67
C3 SDIO_D2
SDIO_D2/ GPIO68
E2 SDIO_D3
SDIO_D3/ GPIO69
*HSW_ULT_DDR3L

BOARD_ID5 BOARD_ID4 BOARD_ID3 BOARD_ID2 BOARD_ID1 BOARD_ID0

Model UMA: 0 14": 0 R132 10K_4 BOARD_ID0 R133 *10K_4
DIS: 1 15": 1 +3V_DEEP_SUS

U83 DIS-14 1 0 0 0 0 0 R158 10K_4 BOARD_ID1 R159 *10K_4

U83 UMA-15 0 1 0 0 0 0 R155 10K_4 BOARD_ID2 R154 *10K_4

0 0 0 0 0 0 R160 10K_4 BOARD_ID3 R167 *10K_4 DIS UMA

A A
Stuff Ra Rb
0 0 0 0 0 0 R463 10K_4 BOARD_ID4 R466 *10K_4
NC Rb Ra <6,7,8,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34> +3V
Rb <6,10,11,24,26,29,30,33,35> +3VS5
0 0 0 0 0 0 R128 *10K_4 BOARD_ID5 Ra R127 10K_4

0 0 0 0 0 0
352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom
h>dϴͬϵ;'W/KͬD/^Ϳ 1A

Date: Friday, April 26, 2013 Sheet 9 of 40

5 4 3 2 1
 5 4 3 2 1

+1.05V

VCC1_05=1.741A +V1.05S_CORE_PCH U19P

POWER
Lynx Point-LP Platform Controller Hub
(HDA,JTAG,SATA)(POWER) ϭϬ
1U/6.3V_4 C248 J11 +V3.3A_DSW_PRTCSUS
VCC1_05 +3V_DEEP_SUS
H11 AH11
1U/6.3V_4 C241 H15 VCC1_05 VCCSUS3_3 C258 1U/6.3V_4
AE8 VCC1_05 CORE RTC
VCC1_05 VCCRTC < 1mA +3V_RTC
10U/6.3VS_6 C204 AF22 AG10
VCC1_05 VCCRTC C564 1U/6.3V_4
D C5612 *0.47U/6.3V_4 D
TP56 AE7 +VCCRTCEXT C233 0.1U/10V_4 C565 0.1U/10V_4 L26 2.2uH/500mA_6
20mil
+3VS5 DCPRTC +1.05V_MODPHY +V1.05S_ASATA3PLL
C249 Place close to AG19 C247 0.1U/10V_4
1U/6.3V_4 Pin AG19 and AG20 +PCH_VCCDSW AG20 DCPSUSBYP SPI Y8VCCSPI=18mA C227 *0.1U/10V_4 L25 2.2uH/500mA_6
20mil
DCPSUSBYP VCCSPI +V1.05S_AUSB3PLL
SI modify SI modify to short pad
+V3.3M_PSPI R117 *0_4/S +3V_DEEP_SUS
+V1.05M_ASW AE9
+1.05V VCCASW +V1.05DX_MODPHY_PCH
AF9 R118 *0_4
VCCASW +3V
C244 1U/6.3V_4 AG8 2.2uH/500mA_6
+1.05V VCCASW +V1.05S_AXCK_DCB L4
+1.05V
C528 *22U/6.3VS_8 J18 C209 1U/6.3V_4
VCCCLK K19
VCCASW=658mA +V1.05M_FHV0 AG14 VCCCLK C217 47U/6.3VS_8
+V1.05M_FHV1 AG13 VCCASW A20
VCCASW VCCACLKPLL C216 47U/6.3VS_8
ICC
AD10 +V1.05S_AXCK_LCPLL L27 2.2uH/500mA_6
TP47 DcpSus1=109mA +V1.05A_SUS_PCH AD8 DCPSUS1 C503 1U/6.3V_4
+1.05V VCCACLKPLL=31mA
DCPSUS1
C206 1U/6.3V_4 +V1.05DX_MODPHY_PCH K9 J17 C488 47U/6.3VS_8
L10 VCCHSIO VCCCLK
C197 1U/6.3V_4
VCCHSIO=1.838A M9 VCCHSIO C483 47U/6.3VS_8
VCCHSIO
C208 *1U/6.3V_4 +V1.05S_SSCF100 R110 *0_6/S +1.05V VCCCLK=200mA
+V1.05S_AIDLE N8
+1.05V VCC1_05 VCCMPHY
P9 R21 C202 1U/6.3V_4 SI modify
VCC1_05 VCCCLK T21
C225 *1U/6.3V_4 VCCCLK
+V1.05S_SSCFF R122 *0_6/S
C
+1.05V C
C499 1U/6.3V_4 +V1.05S_AUSB3PLL B18 K18 C210 1U/6.3V_4
VCCUSB3PLL RSVD
C489 22U/6.3VS_8 M20
RSVD
C484 22U/6.3VS_8 V21
VCCSATA3PLL=42mA RSVD
C504 1U/6.3V_4 +V1.05S_ASATA3PLL B11

C498 22U/6.3VS_8
VCCSATA3PLL
VCCSUS3_3
VCCSUS3_3
AE20 +V3.3A_PSUS
AE21
+V3.3A_PSUS for DS3
+3VS5 +3V_DEEP_SUS
C490 22U/6.3VS_8
R462 *0_6
SI Change to 22uF for Intel recommend USB3 THERMAL SENSOR VCCTS1_5=3mA
TP23 DcpSus3=10mA +V1.05A_VCCUSB3SUS J13 J15 +V1.5S_ATS
+1.5V
DCPSUS3 VCCTS1_5 C524
+V3.3S_PTS +3V R446
K14 100K_4 1U/6.3V_4
HDA VCC3_3 K16 VCC3_3=41mA C203 0.1U/10V_4 U18
VCC3_3
VCCHDA=11mA 5 1
+V3.3DX_1.5DX_ADO IN OUT
+V3.3DX_1.5DX_PAZSUS_PCH AH14 OPI
VCCHDA 2.2uH PN CV-2205JZ00 SI modify SI modify to short pad 4 2
to short pad IN GND
C243 1U/6.3V_4 Y20 VCCAPLL=57mA L5 *0_6/S +1.05V
RSVD AA21 R426 *0_4/S 3 C526
VCCAPLL <27> SLP_SUS_ON ON/OFF
W 21 C229 1U/6.3V_4 0.1U/10V_4
VRM VCCAPLL
+V1.05S_APLLOPI C231 *47U/6.3VS_8 IC(5P) G5243AT11U
TP60 DcpSus2=25mA +V1.05A_USB2SUS AH13 SERIAL IO C517
DCPSUS2 C232 *47U/6.3VS_8 *10P/50V_4
B B
GPIO/ LCC U8 VCCSDIO=17mA
VCCSDIO T9 +V3.3S_1.8S_SDIO_PCH
VCCSDIO +3V
VCCSUS3_3=63mA +V3.3A_PSUS AC9
AA9 VCCSUS3_3
+3V_DEEP_SUS VCCSUS3_3
C242 22U/6.3VS_8 SUS OSCILLATOR C218 1U/6.3V_4

DcpSus4=1mA
AB8 +V1.05A_AOSCSUS TP45
VCCDSW3_3=114mA+3.3V_A_DSW_P AH10 DCPSUS4
VCCDSW 3_3
+3VS5
C250 *1U/6.3V_4 C239 1U/6.3V_4
USB2

+V3.3S_PCORE V8
+3V VCC3_3
W9 AC20
C205 22U/6.3VS_8 VCC3_3 RSVD
+1.05V
AG16 +V1.05S_DUSB
VCC1_05
AG17 C246 1U/6.3V_4
VCC1_05
^Dd
*HSW_ULT_DDR3L

+V3.3DX_1.5DX_ADO

SI modify to short pad

R129 *0_4/S +1.5V
R5105 *0_4 +3V
A A

<6,7,8,9,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34> +3V 352-(&78

<6,20,21,23,24,25,26,33> +5V
<8>
<7>
+V1.05S_AUSB3PLL
+V1.05S_ASATA3PLL 4XDQWD&RPSXWHU,QF
<8> +V1.05S_AXCK_LCPLL
<4,7,11,26,27,30,33,35> +1.05V <7,26> +3V_RTC
<6,9,11,24,26,29,30,33,35> +3VS5 <2,4,12,13,24,31> +1.35VSUS Size Document Number Rev
<13,21,24,25,29,31,32,33,34,36> +5VS5
Custom
h>dϵͬϵ;WKtZͲϮͿ 1A

Date: Monday, May 06, 2013 Sheet 10of 40

5 4 3 2 1
 5 4 3 2 1

<2>
<2>
XDP_PREQ#_CPU
XDP_PRDY#_CPU

<4> CFG0
CFG1
R496 1K_4
31
32
33
34
35
36
CN6
31
32
33
34
35
30
29
28
27
26
30
29
28
27
26
25
OBSFN_C0
OBSFN_C1

CFG8
CFG9
CFG17
CFG16

CFG8
CFG9
<4>
<4>

<4>
<4>
ϭϭ
<4> CFG1 36 25
37 24
CFG2 38 37 24 23 CFG10
<4> CFG2 38 23 CFG10 <4>
CFG3 39 22 CFG11 CFG11 <4>
<4> CFG3 39 22
40 21
OBSFN_B0 41 40 21 20 OBSFN_D0
D <2> XDP_BPM0 CFG19 <4> D
OBSFN_B1 42 41 20 19 OBSFN_D1
<2> XDP_BPM1 42 19 CFG18 <4>
43 18
CFG4 44 43 18 17 CFG12
<4> CFG4 44 17 CFG12 <4>
CFG5 45 16 CFG13 CFG13 <4>
<4> CFG5 45 16
46 15
CFG6 47 46 15 14 CFG14
<4> CFG6 47 14 CFG14 <4>
CFG7 48 13 CFG15 CFG15 <4>
<4> CFG7 48 13
49 12
H_VCCST_PW RGD R406 1K_4 VCCST_PW RGD_XDP 50 49 12 11 +1.05V
<4> H_VCCST_PW RGD 50 11 CK_XDP_P <8>
DNBSW ON# 51 10 CK_XDP_N <8>
52 51 10 9
+1.05V 52 9
53 8 XDP_RST
<4> PW R_DEBUG 53 8
C228 0.1U/10V_4 H_SYS_PW ROK_XDP 54 7 XDP_DBRESET_N C238 0.1U/10V_4
55 54 7 6
56 55 6 5 XDP_TDO
<8,12,13,19,24> SMB_RUN_DAT 56 5
57 4 XDP_TRST#
<8,12,13,19,24> SMB_RUN_CLK 57 4
XDP_TCK1 58 3 XDP_TDI
XDP_TCK0 59 58 3 2 XDP_TMS
<2> XDP_TCK0 59 2
60 1 R100 1K_4 CFG3
60 1
*SEC_BSH-030-01-L-D-A-TR

C C

XDP_DBRESET_N R120 1K_4 +3V H_SYS_PW ROK_XDP R170 *1K_4 +3V_DEEP_SUS

C215 C255
0.1U/10V_4 0.1U/10V_4

+3V

C566
0.1U/10V_4

U22
14
VCC
XDP_TDO 2 3 XDP_TDO_CPU <2>
1A 1B
B APS 1 B
+3V_DEEP_SUS +3VS5 <4,27,29,30,31> HW PG 1OE
SI modify to short pad XDP_TDI_R 5 6
2A 2B XDP_TDI_CPU <2>
SI modify to short pad 4
CN8 2OE
1 R157 *0_4/S +3V_DEEP_SUS XDP_TMS 9 8
1 2 R145 *0_4/S 3A 3B XDP_TMS_CPU <2>
2 SUSB# <6,11,27>
3 R144 *0_4 +3VS5 10
3 4 R146 *0_4/S 3OE
4 SLP_S5# <6>
5 R147 *0_4/S SUSC# <6,27> XDP_TRST# 12 11
5 6 R148 *0_4/S 4A 4B XDP_TRST#_CPU <2,7>
6 SLP_A# <6>
7 13
7 8 4OE
8 15
9 R149 *0_4/S DPAD
9 RTC_RST# <7>
10 7
10 11 R150 *0_4/S GND
11 DNBSW ON# <6,27>
12 *SN74CBTLV3126RGYR
12 13 R151 *0_4/S
13 SYS_RESET# <6>
14 SI modify to short pad
14 15 R152 *0_4
15 PCH_SLP_S0_N <6,27>
16 XDP_TDI R515 *0_4/S XDP_TDI_R
16 17 SI modify to short pad
17 18 R153 *0_4/S
18 SUSB# <6,11,27> +V1.05S_VCCST R511 *51_4
R166 *0_4/S H_SYS_PW ROK_XDP
*ACES_88511-180N <6> SYS_PW ROK
R510 *0_4 XDP_TDO
SI modify to short pad
R505 *0_4/S XDP_TCK0
<7> JTAGX_PCH
R124 1K_4 XDP_RST
A <6,14,22,23,24,26,27> PLTRST# A
R538 *0_4/S XDP_TMS
<7> JTAG_TMS_PCH
R516 *0_4/S XDP_TDI
<7> JTAG_TDI_PCH
R512 *0_4/S XDP_TDO
352-(&78
<7> JTAG_TDO_PCH
XDP_TDI_R R513 *0_4 R506 *0_4 XDP_TCK0

R502 *0_4/S XDP_TCK1

4XDQWD&RPSXWHU,QF
<7> JTAG_TCK_PCH ULT
Size Document Number Rev
1A
HSW XDP & APS
Friday, AprilDate:
26, 2013 11
Sheet of
40
5 4 3 2 1
 5 4 3 2 1

<3> M_A_A[15:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
98
97
96
95
JDIM2A
A0
A1
A2
DQ0 7
5
DQ1 15
DQ2 17
M_A_DQ5
M_A_DQ4
M_A_DQ6
M_A_DQ2
M_A_DQ[63:0] <3>
2.48A +1.35VSUS

75
76
81
JDIM2B
VDD1
VDD2
VSS16
VSS17
44
48
49
ϭϮ
M_A_A4 92 A3 DQ3 4 M_A_DQ1 82 VDD3 VSS18 54
M_A_A5 91 A4 DQ4 6 M_A_DQ0 87 VDD4 VSS19 55
M_A_A6 90 A5 DQ5 16 M_A_DQ7 88 VDD5 VSS20 60
M_A_A7 86 A6 DQ6 18 M_A_DQ3 93 VDD6 VSS21 61
M_A_A8 89 A7 DQ7 21 M_A_DQ13 94 VDD7 VSS22 65
M_A_A9 85 A8 DQ8 23 M_A_DQ12 99 VDD8 VSS23 66
D M_A_A10 107 A9 DQ9 33 M_A_DQ14 100 VDD9 VSS24 71 D
M_A_A11 84 A10/AP DQ10 35 M_A_DQ15 105 VDD10 VSS25 72
M_A_A12 83 A11 DQ11 22 M_A_DQ9 106 VDD11 VSS26 127

PC2100 DDR3 SDRAM SO-DIMM

M_A_A13 119 A12/BC# DQ12 24 M_A_DQ8 111 VDD12 VSS27 128
M_A_A14 80 A13 DQ13 34 M_A_DQ11 112 VDD13 VSS28 133
M_A_A15 78 A14 DQ14 36 M_A_DQ10 117 VDD14 VSS29 134
A15 DQ15 39 M_A_DQ21 118 VDD15 VSS30 138

PC2100 DDR3 SDRAM SO-DIMM

109 DQ16 41 M_A_DQ20 123 VDD16 VSS31 139
<3> M_A_BS#0 BA0 DQ17 51 VDD17 VSS32
108 M_A_DQ19 124 144
<3> M_A_BS#1 BA1 DQ18 53 VDD18 VSS33
79 M_A_DQ23 145
<3> M_A_BS#2 BA2 DQ19 40 VSS34
114 M_A_DQ17 199 150
<3> M_A_CS#0 S0# DQ20 42 +3V VDDSPD VSS35
121 M_A_DQ16 151
<3> M_A_CS#1 S1# DQ21 50 VSS36
101 M_A_DQ18 77 155
<3> M_A_CLKP0 CK0 DQ22 52 NC1 VSS37
103 M_A_DQ22 122 156
<3> M_A_CLKN0 CK0# DQ23 57 NC2 VSS38
102 M_A_DQ24 R198 10K/F_4 125 161
<3> M_A_CLKP1 CK1 DQ24 59 +3V NCTEST VSS39
104 M_A_DQ25 162
<3> M_A_CLKN1 CK1# DQ25 67 VSS40
73 M_A_DQ31 PM_EXTTS#0 198 167
<3> M_A_CKE0 CKE0 DQ26 69 <13> PM_EXTTS#0 EVENT# VSS41
74 M_A_DQ27 30 168
<3> M_A_CKE1 CKE1 DQ27 56 <2,13> DDR3_DRAMRST# RESET# VSS42
115 M_A_DQ28 172
<3> M_A_CAS# CAS# DQ28 58 SI modify to short pad VSS43
110 M_A_DQ29 C320 *0.1U/10V_4 173
<3> M_A_RAS# RAS# DQ29 68 VSS44
113 M_A_DQ30 SMDDR_VREF_DQ0_M1 R204 *0_6/S +SMDDR_VREF_DQ0 1 178
<3> M_A_WE# W E# DQ30 70 VREF_DQ VSS45
R207 10K/F_4 DIMM0_SA0 197 M_A_DQ26 +SMDDR_VREF_DIMM 126 179
SA0 DQ31 129 <12,13> +SMDDR_VREF_DIMM VREF_CA VSS46
R208 10K/F_4 DIMM0_SA1 201 M_A_DQ36 184
SMB_RUN_CLK 202 SA1 DQ32 131 M_A_DQ33 VSS47 185
<8,11,13,19,24> SMB_RUN_CLK 200 SCL DQ33 141 2 VSS48 189
SMB_RUN_DAT M_A_DQ34
<8,11,13,19,24> SMB_RUN_DAT SDA DQ34 143 M_A_DQ35 3 VSS1 VSS49 190
116 DQ35 130 M_A_DQ32 8 VSS2 VSS50 195

(204P)
<13> M_A_ODT0 ODT0 DQ36 132 VSS3 VSS51
120 M_A_DQ37 9 196
<13> M_A_ODT1 ODT1 DQ37 140 VSS4 VSS52
M_A_DQ38 13
11 DQ38 142 M_A_DQ39 14 VSS5
C 28 DM0 DQ39 147 M_A_DQ44 19 VSS6 C
46 DM1 DQ40 149 M_A_DQ45 20 VSS7

(204P)
63 DM2 DQ41 157 M_A_DQ46 25 VSS8
136 DM3 DQ42 159 M_A_DQ42 26 VSS9 203
DM4 DQ43 146 VSS10 VTT1 +0.75V_DDR_VTT
153 M_A_DQ40 31 204
170 DM5 DQ44 148 M_A_DQ41 32 VSS11 VTT2
187 DM6 DQ45 158 M_A_DQ47 37 VSS12 205
DM7 DQ46 160 M_A_DQ43 38 VSS13 GND 206
<3> M_A_DQSP[7:0] 12 DQ47 163 43 VSS14 GND
M_A_DQSP0 M_A_DQ49
M_A_DQSP1 29 DQS0 DQ48 165 M_A_DQ52 VSS15
M_A_DQSP2 47 DQS1 DQ49 175 M_A_DQ50
M_A_DQSP3 64 DQS2 DQ50 177 M_A_DQ51 DDR3-DIMM0_H=4.0_STD
M_A_DQSP4 137 DQS3 DQ51 164 M_A_DQ55 ddr-ddrsk-20401-tp4b-204p-ldv
M_A_DQSP5 154 DQS4 DQ52 166 M_A_DQ48 DGMK4000326
M_A_DQSP6 171 DQS5 DQ53 174 M_A_DQ54 IC SOCKET DDR3 SODIMM(204P,H4.0,STD)
M_A_DQSP7 188 DQS6 DQ54 176 M_A_DQ53
<3> M_A_DQSN[7:0] DQS7 DQ55 181
M_A_DQSN0 10 M_A_DQ59
M_A_DQSN1 27 DQS#0 DQ56 183 M_A_DQ56
M_A_DQSN2 45 DQS#1 DQ57 191 M_A_DQ63
M_A_DQSN3 62 DQS#2 DQ58 193 M_A_DQ58
DQS#3 DQ59 180
WhƌĂĐŬĞƚ
M_A_DQSN4 135 M_A_DQ57
M_A_DQSN5 152 DQS#4 DQ60 182 M_A_DQ60
M_A_DQSN6 169 DQS#5 DQ61 192 M_A_DQ62
M_A_DQSN7 186 DQS#6 DQ62 194 M_A_DQ61
DQS#7 DQ63 <6,7,8,9,10,11,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34> +3V
EZIW
DDR3-DIMM0_H=4.0_STD <2,4,13,24,31> +1.35VSUS
ddr-ddrsk-20401-tp4b-204p-ldv <13,31> +0.75V_DDR_VTT
DGMK4000326 <12,13> +SMDDR_VREF_DIMM
IC SOCKET DDR3 SODIMM(204P,H4.0,STD)
B B

Place these Caps near So-Dimm0. +1.35VSUS

1uF/10uF 4pcs on each side of connector VREF DQ0 M1 Solution
+1.35VSUS +0.75V_DDR_VTT
For EMI RESERVE <13,31> DDR_VTTREF
DDR_VTTREF R200 *0_6
C324 1U/6.3V_4 C333 1U/6.3V_4 R202
1.8K/F_4
+1.35VSUS C330 1U/6.3V_4 C328 1U/6.3V_4
+VA +1.35VSUS SMDDR_VREF_DQ0_M3 R203 2/F_6 SMDDR_VREF_DQ0_M1
C325 1U/6.3V_4 C318 1U/6.3V_4 <3> SMDDR_VREF_DQ0_M3

1
EC5 *120P/50V_4 EC14 *120P/50V_4 +1.35VSUS
C311 1U/6.3V_4 C322 1U/6.3V_4 C317
EC6 *120P/50V_4 EC15 *120P/50V_4 R205 0.022U/25V_4 R201

2
C313 1U/6.3V_4 C319 10U/6.3V_6 1.8K/F_4
EC45 EC7 *120P/50V_4 EC16 *120P/50V_4 24.9/F_4 R215
2200P/50V_4 C312 1U/6.3V_4 1.8K/F_4
EC35 120P/50V_4 EC4 *0.1U/10V_4
C310 1U/6.3V_4 DDR_VTTREF R214 *0_6 +SMDDR_VREF_DIMM
EC10 *120P/50V_4 EC13 *0.1U/10V_4 +SMDDR_VREF_DIMM
C309 1U/6.3V_4
EC8 *120P/50V_4 EC43 *0.1U/10V_4 C335 *0.1U/10V_4 <3> SM_VREF R217 2/F_6
R213

1
SI add for EMI EC9 *120P/50V_4 EC42 *0.1U/10V_4 C329 10U/6.3V_6 C332 *2.2U/6.3V_6 1.8K/F_4
C347
C327 10U/6.3V_6 0.022U/25V_4
R220

2
A +SMDDR_VREF_DQ0 A
+0.75V_DDR_VTT C326 10U/6.3V_6
C307 *0.1U/10V_4
EC12 *120P/50V_4 C314 10U/6.3V_6
C316 *2.2U/6.3V_6 24.9/F_4
EC11 *120P/50V_4 C315 10U/6.3V_6

C340 10U/6.3V_6 +3V 352-(&78

C323 10U/6.3V_6 C302 0.1U/10V_4
4XDQWD&RPSXWHU,QF
C343 10U/6.3V_6 C308 2.2U/6.3V_6 Size Document Number Rev
Custom
Zϯ/DDϬͲ^d;ϰ͘Ϭ,Ϳ 1A

Date: Friday, April 26, 2013 Sheet 12of 40

5 4 3 2 1
 5 4 3 2 1

<3> M_B_A[15:0]
M_B_A0
M_B_A1
M_B_A2
98
97
96
JDIM1A
A0
A1
DQ0
DQ1
5
7
15
M_B_DQ22
M_B_DQ23
M_B_DQ21
M_B_DQ[63:0] <3>

2.48A
+1.35VSUS

75
76
81
JDIM1B
VDD1
VDD2
VSS16
VSS17
44
48
49
ϭϯ
M_B_A3 95 A2 DQ2 17 M_B_DQ18 82 VDD3 VSS18 54
M_B_A4 92 A3 DQ3 4 M_B_DQ16 87 VDD4 VSS19 55
M_B_A5 91 A4 DQ4 6 M_B_DQ17 88 VDD5 VSS20 60
M_B_A6 90 A5 DQ5 16 M_B_DQ20 93 VDD6 VSS21 61
M_B_A7 86 A6 DQ6 18 M_B_DQ19 94 VDD7 VSS22 65
M_B_A8 89 A7 DQ7 21 M_B_DQ4 99 VDD8 VSS23 66
D M_B_A9 85 A8 DQ8 23 M_B_DQ5 100 VDD9 VSS24 71 D
M_B_A10 107 A9 DQ9 33 M_B_DQ6 105 VDD10 VSS25 72
M_B_A11 84 A10/AP DQ10 35 M_B_DQ7 106 VDD11 VSS26 127

PC2100 DDR3 SDRAM SO-DIMM

M_B_A12 83 A11 DQ11 22 M_B_DQ2 111 VDD12 VSS27 128
M_B_A13 119 A12/BC# DQ12 24 M_B_DQ3 112 VDD13 VSS28 133
M_B_A14 80 A13 DQ13 34 M_B_DQ1 117 VDD14 VSS29 134
M_B_A15 78 A14 DQ14 36 M_B_DQ0 118 VDD15 VSS30 138
A15 DQ15 39 M_B_DQ9 123 VDD16 VSS31 139

PC2100 DDR3 SDRAM SO-DIMM

109 DQ16 41 M_B_DQ8 124 VDD17 VSS32 144
<3> M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ11 145
<3> M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ10 199 150
<3> M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ12 151
<3> M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ13 77 155
<3> M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ15 122 156
<3> M_B_CLKP0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ14 125 161
<3> M_B_CLKN0 CK0# DQ23 NCTEST VSS39
102 57 M_B_DQ26 162
<3> M_B_CLKP1 CK1 DQ24 VSS40
104 59 M_B_DQ27 PM_EXTTS#0 198 167
<3> M_B_CLKN1 CK1# DQ25 <12> PM_EXTTS#0 EVENT# VSS41
73 67 M_B_DQ29 30 168
<3> M_B_CKE0 CKE0 DQ26 <2,12> DDR3_DRAMRST# RESET# VSS42
74 69 M_B_DQ28 SI modify to short pad 172
<3> M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ30 C321 *0.1U/10V_4 173
<3> M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ31 SMDDR_VREF_DQ1_M1 R199 *0_6/S +SMDDR_VREF_DQ1 1 178
<3> M_B_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_B_DQ24 126 179
<3> M_B_WE# W E# DQ30 <12> +SMDDR_VREF_DIMM VREF_CA VSS46
R189 10K/F_4 DIMM1_SA0 197 70 M_B_DQ25 184
R190 10K/F_4 DIMM1_SA1 201 SA0 DQ31 129 M_B_DQ32 VSS47 185
+3V 202 SA1 DQ32 131 2 VSS48 189
M_B_DQ33
<8,11,12,19,24> SMB_RUN_CLK 200 SCL DQ33 141 M_B_DQ38 3 VSS1 VSS49 190
<8,11,12,19,24> SMB_RUN_DAT SDA DQ34 143 8 VSS2 VSS50 195
M_B_DQ34

(204P)
M_B_ODT0 116 DQ35 130 M_B_DQ36 9 VSS3 VSS51 196
M_B_ODT1 120 ODT0 DQ36 132 M_B_DQ37 13 VSS4 VSS52
ODT1 DQ37 140 M_B_DQ35 14 VSS5
C 11 DQ38 142 M_B_DQ39 19 VSS6 C
28 DM0 DQ39 147 M_B_DQ40 20 VSS7
46 DM1 DQ40 149 M_B_DQ43 25 VSS8

(204P)
63 DM2 DQ41 157 M_B_DQ47 26 VSS9 203
DM3 DQ42 VSS10 VTT1 +0.75V_DDR_VTT
136 159 M_B_DQ46 31 204
153 DM4 DQ43 146 M_B_DQ41 32 VSS11 VTT2
170 DM5 DQ44 148 M_B_DQ42 37 VSS12 205
187 DM6 DQ45 158 M_B_DQ44 38 VSS13 GND 206
DM7 DQ46 160 M_B_DQ45 43 VSS14 GND
<3> M_B_DQSP[7:0] DQ47 VSS15
M_B_DQSP2 12 163 M_B_DQ52
M_B_DQSP0 29 DQS0 DQ48 165 M_B_DQ51
M_B_DQSP1 47 DQS1 DQ49 175 M_B_DQ54 DDR3-DIMM1_H=4.0_RVS
M_B_DQSP3 64 DQS2 DQ50 177 M_B_DQ48 ddr-ddrrk-20401-tp4b-204p-ruv
M_B_DQSP4 137 DQS3 DQ51 164 M_B_DQ49 DGMK4000263
M_B_DQSP5 154 DQS4 DQ52 166 M_B_DQ55 IC SOCKET DDR3 SODIMM (204P, H4.0, RVS)
M_B_DQSP6 171 DQS5 DQ53 174 M_B_DQ50
M_B_DQSP7 188 DQS6 DQ54 176 M_B_DQ53
<3> M_B_DQSN[7:0] 10 DQS7 DQ55 181
M_B_DQSN2 M_B_DQ63
M_B_DQSN0 27 DQS#0
DQS#1
DQ56
DQ57
183 M_B_DQ62 Local Thermal Sensor
M_B_DQSN1 45 191 M_B_DQ59
M_B_DQSN3 62 DQS#2 DQ58 193 M_B_DQ60 U3 C271 *0.01U/16V_4
M_B_DQSN4 135 DQS#3 DQ59 180 M_B_DQ56
M_B_DQSN5 152 DQS#4 DQ60 182 M_B_DQ57 MBCLK2 8 1
DQS#5 DQ61 <8,19,27> MBCLK2 SCLK VCC +3V
M_B_DQSN6 169 192 M_B_DQ61
M_B_DQSN7 186 DQS#6 DQ62 194 M_B_DQ58
<8,19,27> MBDATA2
MBDATA2 7 2 DDR_THERMDA DDR3 Thermal Sensor
DQS#7 DQ63 SDA DXP

3
PM_EXTTS#0 6 3
DDR3-DIMM1_H=4.0_RVS ALERT# DXN C272 2 Q2
ddr-ddrrk-20401-tp4b-204p-ruv R185 *10K/F_4 4 5 *2200P/50V_4 *METR3904-G
+3V OVERT# GND
DGMK4000263

1
B IC SOCKET DDR3 SODIMM (204P, H4.0, RVS) DDR_THERMDC B
*EMC1412-1-ACZL-TR
Need Check PN(EOD)
DĂŝŶ͗>ϬϬϭϰϭϮϬϬϯ DϭϰϭϮͲϭͲ>ͲdZ;ϵϴŚͿ
ϮŶĚ͗>ϬϬϬϰϯϭϬϭϰ dDWϰϯϭ'<Z;ϵϴŚͿ

+5VPCU
Place these Caps near So-Dimm1. +1.35VSUS
+5VS5 +1.35VSUS 2N7002
1uF/10uF 4pcs on each side of connector VREF DQ1 M1 Solution
Q3
R212
100K_4 3 1 R209 66.5/F_4 +1.35VSUS +0.75V_DDR_VTT +SMDDR_VREF_DIMM
M_A_ODT0 <12>
R218 R187
220K_4 R210 66.5/F_4 C303 1U/6.3V_4 C280 *0.1U/10V_4 1.8K/F_4
M_A_ODT1 <12>
Q5 C293 1U/6.3V_4
2

DTC144EUA R195 66.5/F_4 M_B_ODT0 C306 1U/6.3V_4 C279 *2.2U/6.3V_6 DDR_VTTREF R192 *0_6 SMDDR_VREF_DQ1_M1
<12,31> DDR_VTTREF
3

DDR_VTT_PG_CTRL C297 1U/6.3V_4

R194 66.5/F_4 M_B_ODT1 C341 1U/6.3V_4
2 C336 C289 1U/6.3V_4
C304 1U/6.3V_4 +SMDDR_VREF_DQ1 R188
0.1U/10V_4 C295 1U/6.3V_4 SMDDR_VREF_DQ1_M3 R191 2/F_6 1.8K/F_4
<3> SMDDR_VREF_DQ1_M3
2

C301 1U/6.3V_4 C296 *0.1U/10V_4

1

1
C288 10U/6.3V_6
1 3 R216 *0_4 C300 1U/6.3V_4 C298 *2.2U/6.3V_6 C290
51216S3 <31> +3V 0.022U/25V_4

2
Q4 C305 1U/6.3V_4 R193 24.9/F_4
2N7002K C281 0.1U/10V_4
A C299 1U/6.3V_4 A
C282 2.2U/6.3V_6
DDR_PG_CNTL C287 10U/6.3V_6
DDR_PG_CNTL <2>
R219 C292 10U/6.3V_6
*2M/F_4
C284 10U/6.3V_6
C283 10U/6.3V_6
352-(&78
C286
C285
10U/6.3V_6
10U/6.3V_6
4XDQWD&RPSXWHU,QF
<2,4,12,24,31> +1.35VSUS C291 10U/6.3V_6 Size Document Number Rev
<12,31> +0.75V_DDR_VTT C294 10U/6.3V_6 Custom
Zϯ/DDϭͲZs^;ϰ͘Ϭ,Ϳ 1A
<6,7,8,9,10,11,12,14,15,16,17,19,20,21,22,23,24,25,26,27,32,33,34> +3V Date: Friday, April 26, 2013 Sheet 13of 40
5 4 3 2 1
 1 2 3 4 5 6 7 8

+1.05V_GFX
Near GPU
C8102
C8128
22U/6.3VS_6
22U/6.3VS_6
U8011A

1/14 PCI_EXPRESS

NVDD = 32.22 ~ 26.66 A +VGACORE

ϭϰ
C8135 10U/6.3VS_6 PEX_WAKE AB6 C8521 *0.1U/10V_4
C8106 10U/6.3VS_6 Under GPU U8011E
C8070 4.7U/6.3V_6 AA22 PEX_IOVDD 11/14 NVVDD
AB23 PEX_IOVDD PEX_RST AC7 VGA_RST# R8391 100/F_4 C8105 0.1U/10V_4 K10 VDD
PEGX_RST# <17>
AC24 C8518 0.1U/10V_4 K12
C8110 1U/6.3V_4 AD25
PEX_IOVDD
PEX_IOVDD PEX_CLKREQ AC6 PEX_CLKREQ# R8360 10K/F_4 +3V_GFX C8088 0.1U/10V_4 K14
VDD
VDD U8011C VDD33 = 56mA
A C8111 1U/6.3V_4 AE26 PEX_IOVDD C8512 0.1U/10V_4 K16 VDD 14/14 XVDD/VDD33 A
AE27 PEX_IOVDD PEX_REFCLK AE8 C8118 4.7U/6.3V_6 K18 VDD
CLK_VGA_P <8>
Under GPU PEX_REFCLK AD8 C8112 4.7U/6.3V_6 L11 VDD AD10 NC VDD33 G10
CLK_VGA_N <8> +3V_GFX
C8113 4.7U/6.3V_6 L13 VDD AD7 NC VDD33 G12
AC9 PEG_RXP0_C C8167 0.22U/10V_4 C8081 4.7U/6.3V_6 L15 B19 G8
PEX_IOVDD + PEX_IOVDDQ = 1.042A PEX_TX0
PEX_TX0 AB9 PEG_RXN0_C C8168 0.22U/10V_4
PEG_RXP0 <8>
C8519 4.7U/6.3V_6 L17
VDD
VDD
NC VDD33
VDD33 G9
PEG_RXN0 <8>
C8514 4.7U/6.3V_6 M10 VDD
PEX_RX0 AG6 C8517 4.7U/6.3V_6 M12 VDD F11 3V3AUX_NC Near GPU
+1.05V_GFX PEG_TXP0 <8>
C8117 22U/6.3VS_6 AA10 PEX_IOVDDQ PEX_RX0 AG7 C8523 4.7U/6.3V_6 M14 VDD C8115 4.7U/6.3V_6
PEG_TXN0 <8>
C8094 22U/6.3VS_6 AA12 PEX_IOVDDQ C8100 4.7U/6.3V_6 M16 VDD V5 FERMI_RSVD1_NC 1
C8101 2 1U/10V_6
C8121 10U/6.3VS_6 AA13 PEX_IOVDDQ PEX_TX1 AB10 PEG_RXP1_C C8155 0.22U/10V_4 C8107 4.7U/6.3V_6 M18 VDD V6 FERMI_RSVD2_NC
AA16 AC10 PEG_RXN1_C C8156 PEG_RXP1 <8> N11
C8109 10U/6.3VS_6 PEX_IOVDDQ PEX_TX1 0.22U/10V_4 C8087 4.7U/6.3V_6 VDD
AA18 PEG_RXN1 <8> N13
C8090 4.7U/6.3V_6 PEX_IOVDDQ VDD C8132 0.1U/10V_4
AA19 PEX_IOVDDQ PEX_RX1 AF7 2 1 N15 VDD C8131 0.1U/10V_4
PEG_TXP1 <8>
Near GPU AA20 AE7 C8096 N17 C8126 0.1U/10V_4

+
PEX_IOVDDQ PEX_RX1 PEG_TXN1 <8> VDD
AA21 PEX_IOVDDQ 330u_2.5V_3528 P10 VDD CONFIGURABLE
AB22 PEX_IOVDDQ PEX_TX2 AD11 PEG_RXP2_C C8154 0.22U/10V_4 P12 VDD POWER CHANNELS
AC23 AC11 PEG_RXN2_C C8153 PEG_RXP2 <8> P14
PEX_IOVDDQ PEX_TX2 0.22U/10V_4 VDD * nc on substrate Under GPU
AD24 PEG_RXN2 <8> P16
Under GPU PEX_IOVDDQ VDD
C8089 1U/6.3V_4 AE25 PEX_IOVDDQ PEX_RX2 AE9 P18 VDD G1 XPWR_G1
PEG_TXP2 <8>
C8079 1U/6.3V_4 AF26 PEX_IOVDDQ PEX_RX2 AF9 R11 VDD G2 XPWR_G2
PEG_TXN2 <8>
AF27 PEX_IOVDDQ C8085 22U/6.3VS_6 R13 VDD G3 XPWR_G3
PEX_TX3 AC12 PEG_RXP3_C C8170 0.22U/10V_4 C8529 47U/6.3VS_8 R15 VDD G4 XPWR_G4
AB12 PEG_RXN3_C C8169 PEG_RXP3 <8> R17 G5
PEX_TX3 0.22U/10V_4 VDD XPWR_G5
PEG_RXN3 <8>
C8099 4.7U/6.3V_6 T10 VDD G6 XPWR_G6
PEX_RX3 AG9 C8114 4.7U/6.3V_6 T12 VDD G7 XPWR_G7
PEG_TXP3 <8>
PEX_RX3 AG10 C8515 4.7U/6.3V_6 T14 VDD
PEG_TXN3 <8>
C8516 4.7U/6.3V_6 T16 VDD
PEX_TX4 AB13 C8084 4.7U/6.3V_6 T18 VDD V1 XPWR_V1
AC13 U11 V2
B PEX_PLL_HVDD + PEX_TX4
Near GPU U13
VDD
VDD
XPWR_V2
B

PEX_SVDD_3V3 = 143mA PEX_RX4 AF10

AE10
U15
U17
VDD
PEX_RX4 VDD
V10 VDD
PEX_TX5 AD14 V12 VDD W1 XPWR_W1
+3V_GFX
AA8 PEX_PLL_HVDD PEX_TX5 AC14 V14 VDD W2 XPWR_W2
C8122 0.1U/10V_4 AA9 PEX_PLL_HVDD V16 VDD W3 XPWR_W3
C8120 4.7U/6.3V_6 PEX_RX5 AE12 V18 VDD W4 XPWR_W4
C81304.7U/6.3V_6 PEX_RX5 AF12
Near GPU AB8 PEX_SVDD_3V3
PEX_TX6 AC15 bga595-nvidia-n13p-gv2-s-a2 bga595-nvidia-n13p-gv2-s-a2 COMMON

AB15 COMMON
PEX_TX6

PEX_RX6 AG12
PEX_RX6 AG13

PEX_TX7 AB16
PEX_TX7 AC16

PEX_RX7 AF13
PEX_RX7 AE13
sϯϯ
PEX_TX8 AD17 нϯ͘ϯsͺ'&y
NC
NC PEX_TX8 AC17
+3V
PEX_RX8 AE15
NC
NC PEX_RX8 AF15

<34> VGPU_CORE_SENSE
F2 VDD_SENSE NC PEX_TX9 AC18 Power up Ess ƚхϬ
AB18
C
NC PEX_TX9
C8528 sequence нsͺ'&yͺKZ C

<34> VSS_GPU_SENSE
F1 GND_SENSE NC PEX_RX9 AG15 U8014 0.1U/10V_4 ƚхϬ
NC PEX_RX9 AG16 MC74VHC1G08DFT2G &sY

5
PEX_TX10 AB19 2 нϭ͘ϱsͺ'&y
NC <6,11,22,23,24,26,27> PLTRST#
PEX_TX10 AC19 4 PEGX_RST#
NC
AF16
<8> DGPU_HOLD_RST#
1 Wyͺs ƚхϬ
NC PEX_RX10
PEX_RX10 AE16 нϭ͘Ϭϱsͺ'&y
NC

3
R8388 ƚхсϬ
NC PEX_TX11 AD20
AC20
100K/F_4 /&W;&Ϳͺ/Ks
NC PEX_TX11
нϭ͘Ϭϱsͺ'&y
NC PEX_RX11 AE18
PEX_RX11 AF18
NC

PEX_TX12 AC21
NC
PEX_TX12 AB21
NC

*200/F_4 R8335 PEX_TSTCLK AF22 PEX_TSTCLK_OUT NC PEX_RX12 AG18

PEX_TSTCLK# AE22 PEX_TSTCLK_OUT PEX_RX12 AG19 +3V_GFX
NC
CX300T30001 Change to 0ohm
+1.05V_GFX R8051 0_6 NC PEX_TX13 AD23 Power down
AE23
Near GPU
NC PEX_TX13
R8361
PCIE_CLKREQ_VGA#
sequence
<8>
4.7U/6.3V_6 C8068 PEX_PLLVDD AA14 PEX_PLLVDD PEX_RX13 AF19 4.7K_4
NC
3

1U/6.3V_4 C8069 AA15 PEX_PLLVDD NC PEX_RX13 AE19

0.1U/10V_4 C8097 NC PEX_TX14 AF24 CLKREQ_C1 2 Q8028

Under GPU PEX_TX14 AE24 DTC144EUA
NC
3

D D
PEX_PLLVDD = 130mA NC PEX_RX14 AE21
1

PEX_RX14 AF21 PEX_CLKREQ# 2

NC
10K/F_4 R8346 TESTMODE AD9 TESTMODE
PEX_TX15 AG24 Q8029
NC
NC PEX_TX15 AG25 DTC144EUA
352-(&78
1

AG21
4XDQWD&RPSXWHU,QF
NC PEX_RX15
NC PEX_RX15 AG22

GF117 GF119
2.49K/F_4 R8333 PEX_TERMP AF25 PEX_TERMP Size Document Number Rev
Custom N14M-GS (PCIE I/F) /NVDD 2A
bga595-nvidia-n13p-gv2-s-a2 COMMON Date: Friday, April 26, 2013 Sheet 14 of 40
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

ϭϱ
U8011B
2/14 FBA VMA_DQ[63:0]
VMA_DQ[63:0] <18>
R8379 10K/F_4 PS_FB_CLAMP F3 NC GF119 FBA_D0 E18 VMA_DQ0
FBA_D1 F18 VMA_DQ1
FB_CLAMP FBA_D2 E16 VMA_DQ2
GF117
FB_CLAMP R8380 0_4 F17 VMA_DQ3
FBA_D3
FBA_D4 D20 VMA_DQ4 FBVDDQ + FBVDD = 3.116A U8011F
FBA_D5 D21 VMA_DQ5 13/14 GND
FBA_D6 F20 VMA_DQ6 +1.5V_GFX U8011D A2 GND GND M13
FBA_D7 E21 VMA_DQ7 12/14 FBVDDQ AB17 GND GND M15
FBA_D8 E15 VMA_DQ8 AB20 GND GND M17
FBA_D9 D15 VMA_DQ9 C8474 0.1U/10V_4 B26 FBVDDQ AB24 GND GND N10
FBA_ODT_L FBA_CMD2 R8007 10K/F_4 FBA_D10 F15 VMA_DQ10 C8074 0.1U/10V_4 C25 FBVDDQ AC2 GND GND N12
FBA_D11 F13 VMA_DQ11 E23 FBVDDQ AC22 GND GND N14
A FBA_ODT_H FBA_CMD18 R8001 10K/F_4 FBA_D12 C13 VMA_DQ12 E26 FBVDDQ AC26 GND GND N16 A
FBA_D13 B13 VMA_DQ13 1
C8076 21U/10V_6 F14 FBVDDQ AC5 GND GND N18
FBA_RST# FBA_CMD5 R8002 10K/F_4 FBA_D14 E13 VMA_DQ14 1
C8051 21U/10V_6 F21 FBVDDQ AC8 GND GND P11
FBA_D15 D13 VMA_DQ15 C8077 4.7U/6.3V_6 G13 FBVDDQ AD12 GND GND P13
FBA_CKE_L FBA_CMD3 R8012 10K/F_4 FBA_D16 B15 VMA_DQ16 C8086 10U/6.3V_6 G14 FBVDDQ AD13 GND GND P15
FBA_D17 C16 VMA_DQ17 C8480 22U/6.3VS_6 G15 FBVDDQ A26 GND GND P17
FBA_CKE_H FBA_CMD19 R8000 10K/F_4 FBA_D18 A13 VMA_DQ18 G16 FBVDDQ AD15 GND GND P2
FBA_D19 A15 VMA_DQ19 G18 FBVDDQ AD16 GND GND P23
FBA_D20 B18 VMA_DQ20 G19 FBVDDQ AD18 GND GND P26
FBA_D21 A18 VMA_DQ21 G20 FBVDDQ AD19 GND GND P5
FBA_D22 A19 VMA_DQ22 G21 FBVDDQ AD21 GND GND R10
FBA_D23 C19 VMA_DQ23 H24 FBVDDQ AD22 GND GND R12
FBA_D24 B24 VMA_DQ24 H26 FBVDDQ AE11 GND GND R14
FBA_D25 C23 VMA_DQ25 J21 FBVDDQ AE14 GND GND R16
FBA_D26 A25 VMA_DQ26 K21 FBVDDQ AE17 GND GND R18
FBA_D27 A24 VMA_DQ27 L22 FBVDDQ AE20 GND GND T11
FBA_D28 A21 VMA_DQ28 L24 FBVDDQ AB11 GND GND T13
FBA_D29 B21 VMA_DQ29 L26 FBVDDQ AF1 GND GND T15
FBA_D30 C20 VMA_DQ30 M21 FBVDDQ AF11 GND GND T17
FBA_D31 C21 VMA_DQ31 N21 FBVDDQ AF14 GND GND U10
FBA_D32 R22 VMA_DQ32 R21 FBVDDQ AF17 GND GND U12
C27 FBA_CMD0 FBA_D33 R24 VMA_DQ33 T21 FBVDDQ AF20 GND GND U14
<18> FBA_CMD0
TP8064 FBA_CMD1 C26 FBA_CMD1 FBA_D34 T22 VMA_DQ34 V21 FBVDDQ AF23 GND GND U16
E24 FBA_CMD2 FBA_D35 R23 VMA_DQ35 W 21 FBVDDQ AF5 GND GND U18
<18> FBA_CMD2
F24 FBA_CMD3 FBA_D36 N25 VMA_DQ36 AF8 GND GND U2
<18> FBA_CMD3
D27 FBA_CMD4 FBA_D37 N26 VMA_DQ37 AG2 GND GND U23
<18> FBA_CMD4
D26 FBA_CMD5 FBA_D38 N23 VMA_DQ38 AG26 GND GND U26
<18> FBA_CMD5
F25 FBA_CMD6 FBA_D39 N24 VMA_DQ39 AB14 GND GND U5
<18> FBA_CMD6
F26 FBA_CMD7 FBA_D40 V23 VMA_DQ40 B1 GND GND V11
<18> FBA_CMD7
F23 FBA_CMD8 FBA_D41 V22 VMA_DQ41 B11 GND GND V13
<18> FBA_CMD8
B G22 FBA_CMD9 FBA_D42 T23 VMA_DQ42 B14 GND GND V15 B
<18> FBA_CMD9
G23 FBA_CMD10 FBA_D43 U22 VMA_DQ43 B17 GND GND V17
<18> FBA_CMD10
G24 FBA_CMD11 FBA_D44 Y24 VMA_DQ44 B20 GND GND Y2
<18> FBA_CMD11
F27 FBA_CMD12 FBA_D45 AA24 VMA_DQ45 B23 GND GND Y23
<18> FBA_CMD12
G25 FBA_CMD13 FBA_D46 Y22 VMA_DQ46 B27 GND GND Y26
<18> FBA_CMD13
G27 FBA_CMD14 FBA_D47 AA23 VMA_DQ47 B5 GND GND Y5
<18> FBA_CMD14
G26 FBA_CMD15 FBA_D48 AD27 VMA_DQ48 B8 GND
<18> FBA_CMD15
M24 FBA_CMD16 FBA_D49 AB25 VMA_DQ49 E11 GND
<18> FBA_CMD16
TP8000 FBA_CMD17 M23 FBA_CMD17 FBA_D50 AD26 VMA_DQ50 E14 GND
K24 FBA_CMD18 FBA_D51 AC25 VMA_DQ51 E17 GND
<18> FBA_CMD18
K23 FBA_CMD19 FBA_D52 AA27 VMA_DQ52 E2 GND
<18> FBA_CMD19
M27 FBA_CMD20 FBA_D53 AA26 VMA_DQ53 E20 GND
<18> FBA_CMD20
M26 FBA_CMD21 FBA_D54 W 26 VMA_DQ54 E22 GND
<18> FBA_CMD21
M25 FBA_CMD22 FBA_D55 Y25 VMA_DQ55 E25 GND
<18> FBA_CMD22
K26 FBA_CMD23 FBA_D56 R26 VMA_DQ56 E5 GND
<18> FBA_CMD23
K22 FBA_CMD24 FBA_D57 T25 VMA_DQ57 E8 GND
<18> FBA_CMD24
J23 FBA_CMD25 FBA_D58 N27 VMA_DQ58 H2 GND
<18> FBA_CMD25
J25 FBA_CMD26 FBA_D59 R27 VMA_DQ59 H23 GND
<18> FBA_CMD26
J24 FBA_CMD27 FBA_D60 V26 VMA_DQ60 H25 GND
<18> FBA_CMD27
K27 FBA_CMD28 FBA_D61 V27 VMA_DQ61 FB_CAL_PD_VDDQ D22 FB_CAL_PD_VDDQ R8046 40.2/F_4 H5 GND
<18> FBA_CMD28 +1.5V_GFX
K25 FBA_CMD29 FBA_D62 W 27 VMA_DQ62 K11 GND
<18> FBA_CMD29
J27 FBA_CMD30 FBA_D63 W 25 VMA_DQ63 K13 GND
<18> FBA_CMD30
TP8065 FBA_CMD31 J26 FBA_CMD31 FB_CAL_PU_GND C24 FB_CAL_PU_GND R8050 42.2/F_4 K15 GND
K17 GND
FBA_DQM0 D19 VMA_DM0 L10 GND
D14 VMA_DM1 VMA_DM[7:0] <18> B25 FB_CAL_TERM_GND L12
FBA_DQM1 FB_CALTERM_GND R8047 51.1/F_4 GND
FBA_DQM2 C17 VMA_DM2 L14 GND
FBA_DQM3 C22 VMA_DM3 L16 GND
P24 VMA_DM4 bga595-nvidia-n13p-gv2-s-a2 L18
FBA_DQM4 GND
FBA_DQM5 W 24 VMA_DM5 COMMON L2 GND
C
FBA_DQM6 AA25 VMA_DM6 L23 GND
C
F22 FBA_DEBUG0 FBA_DQM7 U25 VMA_DM7 L25 GND
J22 FBA_DEBUG1 L5 GND GND AA7
M11 GND GND AB7
FBA_DQS_WP0 E19 VMA_WDQS0
C15 VMA_WDQS1 VMA_WDQS[7:0] <18>
FBA_DQS_WP1
D24 FBA_CLK0 FBA_DQS_WP2 B16 VMA_WDQS2
<18> VMA_CLK0
D25 FBA_CLK0 FBA_DQS_WP3 B22 VMA_WDQS3 bga595-nvidia-n13p-gv2-s-a2 COMMON
<18> VMA_CLK0#
N22 FBA_CLK1 FBA_DQS_WP4 R25 VMA_WDQS4
<18> VMA_CLK1
M22 W 23 VMA_WDQS5
<18> VMA_CLK1# FBA_CLK1 FBA_DQS_WP5
FBA_DQS_WP6 AB26 VMA_WDQS6
For support GC6
FBA_DQS_WP7 T26 VMA_WDQS7
+3V
Change Default setting from DGPU_PWR_EN for tuning sequence
D18 FBA_WCK01 FBA_DQS_RN0 F19 VMA_RDQS0
C18 C14 VMA_RDQS[7:0] <18>
FBA_WCK01 FBA_DQS_RN1 VMA_RDQS1
D17 FBA_WCK23 FBA_DQS_RN2 A16 VMA_RDQS2 PV shortpad U8013 C8522
D16 FBA_WCK23 FBA_DQS_RN3 A22 VMA_RDQS3 R8401 *0_4/S NL17SZ32DFT2G 0.1U/10V_4
<8,34,35> DGPU_PWR_EN

5
T24 FBA_WCK45 FBA_DQS_RN4 P25 VMA_RDQS4
U24 FBA_WCK45 FBA_DQS_RN5 W 22 VMA_RDQS5 R8402 *0_4 2
<34,35> DGPU_VC_EN
V24 FBA_WCK67 FBA_DQS_RN6 AB27 VMA_RDQS6 4
DGPU_FB_EN <36>
V25 FBA_WCK67 FBA_DQS_RN7 T27 VMA_RDQS7 1
<17,27> FB_CLAMP
FB_PLLAVDD = 55mA

3
L8010 PBY160808T-300Y-N +FB_PLLAVDD F16 FB_PLLAVDD R8390
+1.05V_GFX
<27> FB_CLAMP1 R8381 *0_4 100K/F_4
C8071 22U/6.3VS_6 P22 FB_PLLAVDD
C8075 0.1U/10V_4
C8091 0.1U/10V_4 H22 FB_DLLAVDD GF119
D C8082 0.1U/10V_4 D

FB_PLLAVDD GF117 Need Check footprint & PN!

FB_DLLAVDD = 15mA
352-(&78
^Dd
FB_VREF_PROBE D23 4XDQWD&RPSXWHU,QF
bga595-nvidia-n13p-gv2-s-a2 COMMON Size Document Number Rev
Custom N14M-GS (MEMORY/GND) 2A

Date: Monday, May 06, 2013 Sheet 15 of 40

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

ϭϲ
U8011G U8011J
4/14 IFPAB
7/14 IFPEF
GF117 GF119
GF119
AC4 GF117
NC IFPA_TXC
AC3 DVI-DL DVI-SL/HDMI DP
NC IFPA_TXC
GF119 GF117 IFPE_AUX J3
GF119 GF117 NC I2CY_SDA I2CY_SDA
AA6 IFPAB_RSET NC NC I2CY_SCL I2CY_SCL IFPE_AUX J2
IFPA_TXD0 Y3 J7 IFPEF_PLLVDD
NC NC
IFPA_TXD0 Y4
NC
IFPE_L3 J1
NC TXC TXC
V7 IFPAB_PLLVDD IFPE_L3 K1
NC NC TXC TXC
NC IFPA_TXD1 AA2 K7 IFPEF_PLLVDD NC
W7 IFPAB_PLLVDD IFPA_TXD1 AA3 IFPE_L2 K3
NC NC NC TXD0 TXD0
A
IFPE_L2 K2 U8011K A
NC TXD0 TXD0 +3V_GFX
3/14 DACA
IFPA_TXD2 AA1 K6 IFPEF_RSET IFPE_L1 M3
NC NC NC TXD1 TXD1 GF119
NC IFPA_TXD2 AB1 IFPE_L1 M2 GF117
GF117 GF119
NC TXD1 TXD1
W5 DACA_VDD I2CA_SCL B7 I2CA_SCL R8386 2.2K_4
NC NC
IFPE_L0 M1 I2CA_SDA A7 I2CA_SDA R8383 2.2K_4
NC TXD2 TXD2 NC
IFPA_TXD3 AA5 IFPE_L0 N1 AE2 DACA_VREF
NC NC TXD2 TXD2 TSEN_VREF
IFPA_TXD3 AA4
NC
AF2 DACA_RSET NC NC DACA_HSYNC AE3
IFPE NC DACA_VSYNC AE4
IFPB_TXC AB4
NC
IFPB_TXC AB5
NC
NC HPD_E HPD_E GPIO18 C2 DACA_RED AG3
GF119 GF117 NC
W6 IFPA_IOVDD IFPB_TXD4 AB2 DACA_GREEN AF4
NC NC NC
IFPB_TXD4 AB3
NC GF119 GF117
Y6 IFPB_IOVDD DACA_BLUE AF3
NC NC
H6 IFPE_IOVDD NC
NC IFPB_TXD5 AD2 GF119
IFPB_TXD5 AD3 J6 IFPF_IOVDD GF117
NC NC DVI-DL DVI-SL/HDMI DP
H4 bga595-nvidia-n13p-gv2-s-a2 COMMON
NC I2CZ_SDA IFPF_AUX
IFPB_TXD6 AD1 NC I2CZ_SCL IFPF_AUX H3
NC
NC IFPB_TXD6 AE1

NC TXC IFPF_L3 J5
IFPB_TXD7 AD5 NC TXC IFPF_L3 J4
NC
IFPB_TXD7 AD4
NC
NC TXD3 TXD0 IFPF_L2 K5
NC IFPF_L2 K4
TXD3 TXD0
B B
NC TXD4 TXD1 IFPF_L1 L4
IFPF NC TXD4 TXD1 IFPF_L1 L3
NC GPIO14 B3
IFPAB NC
NC
TXD5
TXD5
TXD2
TXD2
IFPF_L0
IFPF_L0
M5
M4
bga595-nvidia-n13p-gv2-s-a2 COMMON

U8011H
5/14 IFPC
IFPC NC HPD_F GPIO19 F7
GF119 GF117
T6 IFPC_RSET GF117 GF119
NC

DVI/HDMI DP

M7 N5 bga595-nvidia-n13p-gv2-s-a2 COMMON
IFPC_PLLVDD NC NC I2CW_SDA IFPC_AUX
N7 IFPC_PLLVDD NC I2CW_SCL IFPC_AUX N4
NC

IFPC_L3 N3 PLLVDD = 38mA

NC TXC
NC IFPC_L3 N2
TXC
+1.05V_GFX L8012 PBY160808T-300Y-N NV_PLLVDD
IFPC_L2 R3 C8125 0.1U/10V_4
NC TXD0
IFPC_L2 R2 C8161 22U/6.3VS_6
NC TXD0

TXD1 IFPC_L1 R1
NC
NC TXD1 IFPC_L1 T1
U8011M C8508
T3
SP_PLLVDD = 17mA
NC IFPC_L0 9/14 XTAL_PLL
TXD2
C
IFPC_L0 T2 L8013 HCB1608KF-181T15 SP_PLLVDD C
NC TXD2 +1.05V_GFX

4
3
C8123 0.1U/10V_4 L6 PLLVDD *18P/50V_4
C8124 0.1U/10V_4 M6 SP_PLLVDD 27M_XTAL_IN_R Y8002
C8172 4.7U/6.3V_6 27M_XTAL_OUT *27MHZ +-10PPM
P6 IFPC_IOVDD NC GPIO15 C3 C8159 22U/6.3VS_6 N6 VID_PLLVDD
NC GF119
C8509

1
2
bga595-nvidia-n13p-gv2-s-a2 COMMON
NC GF117
VID_PLLVDD = 41mA
*18P/50V_4
U8011I
6/14 IFPD R8054 10K/F_4 XTAL_SSIN A10 XTALSSIN XTALOUTBUFF C10 BXTALOUT R8053 10K/F_4
GF119 GF117
U6 GF117 GF119 R8367 0_4 27M_XTAL_IN_R C11 B10 27M_XTAL_OUT
IFPD_RSET NC <26> CLK_27M_XTAL_IN XTALIN XTALOUT
DVI/HDMI DP bga595-nvidia-n13p-gv2-s-a2 COMMON

T7 IFPD_PLLVDD I2CX_SDA IFPD_AUX P4

NC NC
NC I2CX_SCL IFPD_AUX P3
R7 IFPD_PLLVDD NC +3V_GFX
IFPD_L3 R5
NC TXC
IFPD_L3 R4
NC TXC
DGPU_PGOK-1
IFPD_L2 T5 +3V R8403
NC TXD0
IFPD_L2 T4 *4.7K_4
NC TXD0
3

TXD1 IFPD_L1 U4 R8070 4.7K_4 DGPU_POK4 2 Q8035

NC +1.05V_GFX
IFPD NC TXD1 IFPD_L1 U3 METR3904-G R8071
DGPU_PWROK <9,27,36>
4.7K_4
1

D
IFPD_L0 V4 C8157 D
NC TXD2
3
IFPD_L0 V3 *1000P/50V_4
NC TXD2
2 Q8033 R8405
3

DTC144EUA 100K/F_4
R6 IFPD_IOVDD GPIO17 D4 R8404 4.7K_4 DGPU_POK2 2 Q8034
352-(&78
GF119 NC +1.5V_GFX
METR3904-G
1

C8158
4XDQWD&RPSXWHU,QF
NC GF117
1

C8536 1000P/50V_4
*1000P/50V_4

Size Document Number Rev

bga595-nvidia-n13p-gv2-s-a2 COMMON Custom N14M-GS (DISPLAY) 2A

Date: Friday, April 26, 2013 Sheet 16 of 40

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

ϭϳ
+3V_GFX +3V_GFX
U8011L Default: HYNIX
10/14 MISC2

R8365 R8356 R8075 R8072 4.99k CS24992FB26

TP8004 E10 VMON_IN0 R8363 4.99K/F_4 4.99K/F_4 45.3K/F_4 R8074 *30.1K/F_4 R8073 R8076 10k CS31002FB26
TP8007 F10 VMON_IN1 ROM_CS D12 ROM_CS TP8002 *10K/F_4 *10K/F_4 *10K/F_4 *10K/F_4 15k CS31502FB24
20k CS32002FB29
DEL VID pin for NVD request ROM_SI B12 ROM_SI 24.9k CS32492FB16
ROM_SO A12 ROM_SO ROM_SI STRAP0 30.1k CS33012FB18
STRAP0 D1 STRAP0 ROM_SCLK C12 ROM_SCLK ROM_SO STRAP1 34.8k CS33482FB22
STRAP1 D2 STRAP1 ROM_SCLK STRAP2 45.3k CS34532FB18
A STRAP2 E4 STRAP2 STRAP3 A
STRAP3 E3 STRAP3 STRAP4
STRAP4 D3 STRAP4

2
GF119 R8362 R8364 R8357 R8067 R8066 R8064 R8065 R8063
GF117
15K/F_4 *20K/F_4 *15K/F_4 *24.9K/F_4 45.3K/F_4 4.99K/F_4 45.3K/F_4
C1 STRAP5_NC 15K/F_4
NC
BUFRST D11

1
R8068 40.2K/F_4 F6 MULTISTRAP_REF0_GND PGOOD D10 NV_PWG R8055 10K/F_4

GF119 GF117

EϭϯWͲ'sϮEs,tKKdsŽůƚĂŐĞсϬ͘ϴϳϱs F4 MULTISTRAP_REF1_GND NC
CEC E9
s/сϭϭϬϬϭϬ F5 MULTISTRAP_REF2_GND NC
+3V_GFX +3V +3V +3V_GFX +3V_GFX

bga595-nvidia-n13p-gv2-s-a2 COMMON

R8082 R8389 R8334 R8336 R8353

10K/F_4 10K/F_4 10K/F_4 10K/F_4 10K/F_4

GPU_GPIO0_R FB_CLAMP_TGL_REQ#_EC
<27> FB_CLAMP_TGL_REQ#_EC
U8011N

3
8/14 MISC1
I2CS_SCL D9 GPUT_CLK
D8 GPUT_CLK <27>
I2CS_SDA GPUT_DATA
GPUT_DATA <27>
2 2
I2CC_SCL A9 DGPU_EDIDCLK R8373 2.2K_4 +3V_GFX 2N7002K 2N7002K
B
I2CC_SDA B9 DGPU_EDIDDATA R8374 2.2K_4 B

3
Q8032 Q8025

1
TP8003 THERM- E12 THERMDN GF117 GF119
I2CB_SCL C9 N12E_SCL R8376 2.2K_4 2 2 FB_CLAMP_TGL_REQ#
NC +3V_GFX FB_CLAMP <15,27>
TP8001 THERM+ F12 THERMDP I2CB_SDA C8 N12E_SDA R8378 2.2K_4
NC
2N7002K 2N7002K
TP8069 JTAG_TCK AE5 JTAG_TCK
Q8030 Q8027

1
TP8068 JTAG_TMS AD6 JTAG_TMS
TP8067 JTAG_TDI AE6 JTAG_TDI
TP8066 JTAG_TDO AF6 JTAG_TDO
JTAG_TRST# AG4 JTAG_TRST GPIO0 C6 GPU_GPIO0 R8077 0_4 GPU_GPIO0_R VRAM Configuration Table
GPIO1 B2
GPIO2 D6 RAMCFG
GPIO3 C7 [3:0] DESCRIPTION Vendor Vendor P/N QCI P/N
GPIO4 F9
GPIO5 A3 0000 ...
GPIO6 A4 FB_CLAMP_TGL_REQ# 0000 DDR3 128Mx16x4, 64bit, 2Gb,900MHz Micron MT41J128M16JT-107G:K AKD5MGSTL06 AKD5MGSTL08
GPIO7 B6 0110 DDR3 128Mx16x4, 64bit, 2Gb,900MHz HYNIX H5TQ2G63DFR-11C AKD5MGWTW16 AKD5MGWTW13
GPIO8 A6 VGA_OVT# 0111 DDR3 128Mx16x4, 64bit, 2Gb,900MHz SAMSUNG K4W2G1646E-BC11 AKD5MGGT520 AKD5MGGT522
GPIO9 F8 ALERT
GPIO10 C5
GPIO11 E7
GPU_VID <34>
GPIO12 D7 PWR_LEVEL 2 1
B4 PSI DGPU_PROCHOT_EC# <27,34>
D8009 RB500V-40
GPIO ASSIGNMENTS
GPIO13 PSI <34>

GF117 GF119
D5 GPU_GPIO16 TP8005
C
NC GPIO16
GPIO20 E6 GPIO I/O PIN USAGE C
NC
GPIO21 C4
NC
0 IN FB_CLAMP_MON FB Clamp monitor
1 OUT MEM_VDD_CTL Memory VDD VID
bga595-nvidia-n13p-gv2-s-a2 COMMON
2 OUT LCD_BL_PWM Panel Backlight PWM
+3V_GFX
3 OUT LCD_VCC PANEL POWER ENABLE
<14> PEGX_RST#
PWR_LEVEL R8060 10K/F_4
4 OUT LCD_BLEN PANEL BACKLIGHT ENABLE
5 OUT Reserved --
2

PSI R8382 10K/F_4

VGA_OVT# 1 3 6 OUT FB_CLAMP_TGL_REQ Active low FB Clamp toggle request

DGPU_OVT# <27>
VGA_OVT# R8385 10K/F_4
7 OUT 3D VISION 3D VISION LEFT/RIGHT signal
Q8031
*2N7002K ALERT R8083 10K/F_4
8 I/O OVERT ACTIVE LOW THERMAL OVER TEMP
9 I/O ALERT ACTIVE LOW THERMAL ALERT
JTAG_TRST# R8366 10K/F_4
10 OUT MEM VREF_CTL MEMMORY VREF CONTROL
11 OUT PWR_VID GPU CORE_VDD PWM Control signal
12 IN PWR_LEVEL AC Power detect or power supply overdraw input
13 OUT PSI Phase Shedding
D D

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom N14M-GS (GPIO/STRAPS) 2A

Date: Friday, April 26, 2013 Sheet 17 of 40

1 2 3 4 5 6 7 8
 5 4 3 2 1

ϭϴ
烉AKD5PGWTW08---AKD5PGWTW07
HYU 256Mx16, PN烉
CHANNEL A: 256MB/512MB DDR3 烉AKD5MZDTW03---AKD5MZDTW02
HYU 128Mx16, PN烉
QBC TOP B/S
<15>
<15>
VMA_DQ[63..0]
VMA_DM[7..0]
烉AKD5PZDT501---AKD5PZDT500
SAM 256Mx16, PN烉
<15> VMA_WDQS[7..0] 烉AKD5MGGT535---AKD5MGGT534
SAM 128Mx16, PN烉
<15> VMA_RDQS[7..0]
VRAM8001 VRAM8003 VRAM8000 VRAM8002

VREFC_VMA1 M8 E3 VMA_DQ11 VREFC_VMA1 M8 E3 VMA_DQ25 VREFC_VMA3 M8 E3 VMA_DQ40 VREFC_VMA3 M8 E3 VMA_DQ62

VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ9 VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ28 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ45 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ59
VREFDQ DQL1 F2 VMA_DQ14 VREFDQ DQL1 F2 VMA_DQ27 VREFDQ DQL1 F2 VMA_DQ42 VREFDQ DQL1 F2 VMA_DQ60
N3 DQL2 F8 VMA_DQ8 FBA_CMD9 N3 DQL2 F8 VMA_DQ29 FBA_CMD9 N3 DQL2 F8 VMA_DQ46 FBA_CMD9 N3 DQL2 F8 VMA_DQ56
D <15> FBA_CMD9 P7 A0 DQL3 H3 P7 A0 DQL3 H3 P7 A0 DQL3 H3 P7 A0 DQL3 H3 D
VMA_DQ12 FBA_CMD11 VMA_DQ26 FBA_CMD11 VMA_DQ43 FBA_CMD11 VMA_DQ61
<15> FBA_CMD11 P3 A1 DQL4 H8 P3 A1 DQL4 H8 P3 A1 DQL4 H8 P3 A1 DQL4 H8
VMA_DQ10 FBA_CMD8 VMA_DQ31 FBA_CMD8 VMA_DQ47 FBA_CMD8 VMA_DQ58
<15> FBA_CMD8 N2 A2 DQL5 G2 N2 A2 DQL5 G2 N2 A2 DQL5 G2 N2 A2 DQL5 G2
VMA_DQ15 FBA_CMD25 VMA_DQ24 FBA_CMD25 VMA_DQ41 FBA_CMD25 VMA_DQ63
<15> FBA_CMD25 A3 DQL6 A3 DQL6 A3 DQL6 A3 DQL6
P8 H7 VMA_DQ13 FBA_CMD10 P8 H7 VMA_DQ30 FBA_CMD10 P8 H7 VMA_DQ44 FBA_CMD10 P8 H7 VMA_DQ57
<15> FBA_CMD10 P2 A4 DQL7 P2 A4 DQL7 P2 A4 DQL7 P2 A4 DQL7
FBA_CMD24 FBA_CMD24 FBA_CMD24
<15> FBA_CMD24 R8 A5 FBA_CMD22 R8 A5 FBA_CMD22 R8 A5 FBA_CMD22 R8 A5
<15> FBA_CMD22 R2 A6 D7 R2 A6 D7 R2 A6 D7 R2 A6 D7
VMA_DQ5 FBA_CMD7 VMA_DQ16 FBA_CMD7 VMA_DQ34 FBA_CMD7 VMA_DQ54
<15> FBA_CMD7 T8 A7 DQU0 C3 T8 A7 DQU0 C3 T8 A7 DQU0 C3 T8 A7 DQU0 C3
VMA_DQ1 FBA_CMD21 VMA_DQ23 FBA_CMD21 VMA_DQ36 FBA_CMD21 VMA_DQ48
<15> FBA_CMD21 R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8
VMA_DQ6 FBA_CMD6 VMA_DQ18 FBA_CMD6 VMA_DQ32 FBA_CMD6 VMA_DQ55
<15> FBA_CMD6 A9 DQU2 A9 DQU2 A9 DQU2 A9 DQU2
L7 C2 VMA_DQ2 FBA_CMD29 L7 C2 VMA_DQ21 FBA_CMD29 L7 C2 VMA_DQ38 FBA_CMD29 L7 C2 VMA_DQ51
<15> FBA_CMD29 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7
VMA_DQ4 FBA_CMD23 VMA_DQ19 FBA_CMD23 VMA_DQ33 FBA_CMD23 VMA_DQ53
<15> FBA_CMD23 N7 A11 DQU4 A2 N7 A11 DQU4 A2 N7 A11 DQU4 A2 N7 A11 DQU4 A2
VMA_DQ3 FBA_CMD28 VMA_DQ22 FBA_CMD28 VMA_DQ37 FBA_CMD28 VMA_DQ50
<15> FBA_CMD28 T3 A12/BC DQU5 B8 VMA_DQ7 FBA_CMD20 T3 A12/BC DQU5 B8 VMA_DQ17 FBA_CMD20 T3 A12/BC DQU5 B8 VMA_DQ35 FBA_CMD20 T3 A12/BC DQU5 B8 VMA_DQ52
<15> FBA_CMD20 T7 A13 DQU6 A3 T7 A13 DQU6 A3 T7 A13 DQU6 A3 T7 A13 DQU6 A3
VMA_DQ0 FBA_CMD4 VMA_DQ20 FBA_CMD4 VMA_DQ39 FBA_CMD4 VMA_DQ49
<15> FBA_CMD4 M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7
FBA_CMD14 FBA_CMD14 FBA_CMD14
<15> FBA_CMD14 A15 A15 A15 A15

M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2

<15> FBA_CMD12 N8 BA0 VDD#B2 D9 +1.5V_GFX N8 BA0 VDD#B2 D9 N8 BA0 VDD#B2 D9 +1.5V_GFX N8 BA0 VDD#B2 D9
FBA_CMD27 FBA_CMD27 FBA_CMD27
<15> FBA_CMD27 M3 BA1 VDD#D9 G7 M3 BA1 VDD#D9 G7 M3 BA1 VDD#D9 G7 M3 BA1 VDD#D9 G7
FBA_CMD26 FBA_CMD26 FBA_CMD26
<15> FBA_CMD26 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
J7 VDD#N1 N9 VMA_CLK0 J7 VDD#N1 N9 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9
<15> VMA_CLK0 CK VDD#N9 CK VDD#N9 <15> VMA_CLK1 CK VDD#N9 CK VDD#N9
K7 R1 VMA_CLK0# K7 R1 K7 R1 VMA_CLK1# K7 R1
<15> VMA_CLK0# CK VDD#R1 CK VDD#R1 <15> VMA_CLK1# CK VDD#R1 CK VDD#R1 +1.5V_GFX
K9 R9 FBA_CMD3 K9 R9 K9 R9 FBA_CMD19 K9 R9
<15> FBA_CMD3 CKE VDD#R9 CKE VDD#R9 +1.5V_GFX <15> FBA_CMD19 CKE VDD#R9 CKE VDD#R9

K1 A1 FBA_CMD2 K1 A1 K1 A1 FBA_CMD18 K1 A1
<15> FBA_CMD2 L2 ODT VDDQ#A1 A8 L2 ODT VDDQ#A1 A8 <15> FBA_CMD18 L2 ODT VDDQ#A1 A8 L2 ODT VDDQ#A1 A8
FBA_CMD0 FBA_CMD16
C <15> FBA_CMD0 J3 CS VDDQ#A8 C1 FBA_CMD30 J3 CS VDDQ#A8 C1 <15> FBA_CMD16 FBA_CMD30 J3 CS VDDQ#A8 C1 FBA_CMD30 J3 CS VDDQ#A8 C1 C
<15> FBA_CMD30 K3 RAS VDDQ#C1 C9 K3 RAS VDDQ#C1 C9 K3 RAS VDDQ#C1 C9 K3 RAS VDDQ#C1 C9
FBA_CMD15 FBA_CMD15 FBA_CMD15
<15> FBA_CMD15 L3 CAS VDDQ#C9 D2 FBA_CMD13 L3 CAS VDDQ#C9 D2 FBA_CMD13 L3 CAS VDDQ#C9 D2 FBA_CMD13 L3 CAS VDDQ#C9 D2
<15> FBA_CMD13 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
VMA_WDQS1 F3 VDDQ#F1 H2 VMA_WDQS3 F3 VDDQ#F1 H2 VMA_WDQS5 F3 VDDQ#F1 H2 VMA_WDQS7 F3 VDDQ#F1 H2
VMA_RDQS1 G3 DQSL VDDQ#H2 H9 VMA_RDQS3 G3 DQSL VDDQ#H2 H9 VMA_RDQS5 G3 DQSL VDDQ#H2 H9 VMA_RDQS7 G3 DQSL VDDQ#H2 H9
DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9

VMA_DM1 E7 A9 VMA_DM3 E7 A9 VMA_DM5 E7 A9 VMA_DM7 E7 A9

VMA_DM0 D3 DML VSS#A9 B3 VMA_DM2 D3 DML VSS#A9 B3 VMA_DM4 D3 DML VSS#A9 B3 VMA_DM6 D3 DML VSS#A9 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
VMA_WDQS0 C7 VSS#G8 J2 VMA_WDQS2 C7 VSS#G8 J2 VMA_WDQS4 C7 VSS#G8 J2 VMA_WDQS6 C7 VSS#G8 J2
VMA_RDQS0 B7 DQSU VSS#J2 J8 VMA_RDQS2 B7 DQSU VSS#J2 J8 VMA_RDQS4 B7 DQSU VSS#J2 J8 VMA_RDQS6 B7 DQSU VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9
<15> FBA_CMD5 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMA_ZQ1 L8 VSS#T1 T9 VMA_ZQ2 L8 VSS#T1 T9 VMA_ZQ3 L8 VSS#T1 T9 VMA_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9

B1 B1 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R8022 VSSQ#B9 D1 R8028 VSSQ#B9 D1 R8019 VSSQ#B9 D1 R8326 VSSQ#B9 D1
Should be 240 VSSQ#D1 Should be 240 VSSQ#D1 Should be 240 VSSQ#D1 Should be 240 VSSQ#D1
Ohms +-1% 243/F_4 D8 Ohms +-1% 243/F_4 D8 Ohms +-1% 243/F_4 D8 Ohms +-1% 243/F_4 D8
VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
B J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 B
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
VRAM _DDR3_HYNIX_256MX16 VRAM _DDR3_HYNIX_256MX16 VRAM _DDR3_HYNIX_256MX16 VRAM _DDR3_HYNIX_256MX16

+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

VMA_CLK0
R8329 R8036 R8003 R8041
1.33K/F_4 1.33K/F_4 VMA_CLK1 1.33K/F_4 1.33K/F_4

R8027
160/F_4 VREFC_VMA1 VREFD_VMA1 VREFC_VMA3 VREFD_VMA3
R8031
VMA_CLK0# 160/F_4
R8327 C8475 R8035 C8044 R8005 C8028 R8038 C8046
1.33K/F_4 0.1U/10V_4 1.33K/F_4 0.1U/10V_4 1.33K/F_4 0.1U/10V_4 1.33K/F_4 0.1U/10V_4
VMA_CLK1#

+1.5V_GFX
+1.5V_GFX

A C8007 10U/6.3V_6 C8009 10U/6.3V_6 +1.5V_GFX A

+1.5V_GFX C8478 1U/6.3V_4 C8466 10U/6.3V_6 C8467 10U/6.3V_6

C8020 1U/6.3V_4
+1.5V_GFX C8468 10U/6.3V_6 C8486 1U/6.3V_4 C8471 0.1U/10V_4 C8008 10U/6.3V_6
C8479 1U/6.3V_4 C8487 0.1U/10V_4
C8052
C8010
1U/6.3V_4
1U/6.3V_4
C8049
C8462
1U/6.3V_4
1U/6.3V_4
C8464
C8473
1U/6.3V_4
1U/6.3V_4
C8465 0.1U/10V_4
C8031 0.1U/10V_4
352-(&78
C8482
C8485
1U/6.3V_4
1U/6.3V_4
C8476
C8030
1U/6.3V_4
1U/6.3V_4
C8011
C8043
1U/6.3V_4
1U/6.3V_4
C8463
C8027
0.1U/10V_4
0.1U/10V_4
C8470
C8056
0.1U/10V_4
0.1U/10V_4
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom DGPU Memory (DDR3) 2A

Date: Friday, April 26, 2013 Sheet 18 of 40

5 4 3 2 1
 5 4 3 2 1

ϭϵ
ůŽƐĞƚŽ>s^KEE
INT_eDP_TXP0 C20 0.1U/10V_4 LANE0P
<2> INT_eDP_TXP0
dŽ>s^ŽŶǀĞƌƚĞƌ PCH_LA_DATAP0_R R248 0_4
PCH_LA_DATAP0 <20>
<2> INT_eDP_TXN0
INT_eDP_TXN0 C26 0.1U/10V_4 LANE0N
&ƌŽŵ>s^ŽŶǀĞƌƚĞƌ PCH_LA_DATAN0_R R249 0_4
PCH_LA_DATAN0 <20>

R2 *0_4 eDP_TXP0
dŽĞW eDP_TXP0 C10 *0.1U/10V_4
R252 *1M/F_4 R4 *0_4 eDP_TXN0
&ƌŽŵWh eDP_TXN0 C9 *0.1U/10V_4

INT_eDP_AUXN C28 0.1U/10V_4 eDP_AUXN_2132

<2> INT_eDP_AUXN
dŽ>s^ŽŶǀĞƌƚĞƌ
D D
INT_eDP_AUXP C31 0.1U/10V_4 eDP_AUXP_2132
<2> INT_eDP_AUXP
&ŽƌĞW͕ĐůŽƐĞƚŽhϳ
+3V R254 *1M/F_4 &ƌŽŵ>s^ŽŶǀĞƌƚĞƌ PCH_EDIDDATA_R R251 0_4 PCH_EDIDDATA <20>
R6 *0_4 eDP_AUXN PCH_EDIDCLK_R R253 0_4 PCH_LVDS_BLON R241 *0_4 2132_LVDS_BLON
PCH_EDIDCLK <20>
<6> PCH_LVDS_BLON 2132_LVDS_BLON <19,20>
R9 *0_4 eDP_AUXP dŽĞW <6> PCH_DISP_ON
PCH_DISP_ON
PCH_DPST_PWM
R247
R245
*0_4
*0_4
2132_DISP_ON
2132_DPST_PWM
2132_DISP_ON <19,20>
<6,19> PCH_DPST_PWM 2132_DPST_PWM <19,20>
eDP_AUXN C8 *0.1U/10V_4
&ƌŽŵWh
&ŽƌWKŶůLJ͗ƐƚƵĨĨZĞƐŝƐƚŽƌ eDP_AUXP C7 *0.1U/10V_4

&Žƌ>s^ŽŶůLJƐƚƵĨĨĂƉ

PCH_EDIDDATA_R

PCH_EDIDCLK_R
+1.2V_2132 ůŽƐĞWŝŶϯ
C24 L22
SCA_SDA
+3V +3.3V_2132_A
TI160808U600
SCA_SCL
0.1U/10V_4 C377 C33 C375
ULT_EDP_HPD DPRX_HPD
Note:
10U/6.3V_6 0.1U/10V_4 0.1U/10V_4
<6,20> ULT_EDP_HPD
PCH_LA_DATAN0_R
entire trace of +3.3V_2132_A should
R256 1K/F_4
C be wider than 80-mil C
PCH_LA_DATAP0_R L21
+3V +3.3V_2132
TI160808U600

33 C374 C373 C367

32

31

30

29

28

27

26

25
U7 10U/6.3V_6 0.1U/10V_4 0.1U/10V_4

TXO0-
SPI_CEB/IRQB/MIICSCL

SPI_SI/SCLK/MIICSCL

TXO0+
SPI_SO/SCSB/MIICSDA

SPI_CK/SDIO/MIICSDA

VCCK
GND

HPD
eDP_AUXN_2132 1 24
AUX-CH_N TXO1- PCH_LA_DATAN1 <20>
eDP_AUXP_2132 2 23
AUX-CH_P TXO1+ PCH_LA_DATAP1 <20>
3 22
+3.3V_2132_A DP_V33 TXO2- PCH_LA_DATAN2 <20>
4 21
DP_GND TXO2+ PCH_LA_DATAP2 <20>
LANE0P 5 20
LANE0P TXOC- PCH_LA_CLK# <20> SCA_SCL pull high => EEPROM mode
LANE0N 6
LANE0N
RTD2132R
TXOC+
19
PCH_LA_CLK <20>
SCA_SDA pull low = > EEPROM Free mode
7 18
+1.2V_2132 DP_V12 PVCC +3.3V_2132
SWR_VCCK

R17
Panel_VCC
SWR_VDD

8 17 C372
CIICSDA1

PWMOUT
CIICSCL1

DP_REXT BL_EN
SWR_LX

ĚĚƌĞƐƐсϬdžϴ
C376 0.1U/10V_4
PWMIN

12K/F_4
0.1U/10V_4
/Ed
+3V
RTD2132R H=1mm(max) 2132_LVDS_BLON <19,20>
RTD2132R-CG
9

10

11

12

13

14

15

16

B B

+3V R13 *4.7K_4 CSCL1 PCH_DPST_PWM

PCH_DPST_PWM <6,19>
R1 100K/F_4
R7 *4.7K_4 CSDA1 U8 C379
8 7 *0.1U/10V_4
2132_DISP_ON <19,20> 5 VCC WP 3
+1.2V_2132 SCA_SDA R25 *0_4 SCA_SDA_R
2132_DPST_PWM <19,20> 6 SDA A2 2
L20 SCA_SCL R20 *0_4 SCA_SCL_R
4.7UH/850mA/TLPC3010C-4R7M 4 SCL A1 1
Note: GND A0
+1.2V_2132 +3.3V_2132 Close to Pin8
ůŽƐĞWŝŶϭϮфϮϬϬŵŝů entire trace of Panel VCC should PCH_EDIDDATA R28 *0_4
*SGT-M24C64-WMN6TP
be wider than 80-mil
ϲϬϭϰͬϲϬϭϱ C369
0.1U/10V_4
C378
10U/6.3V_6
R8 *0_8 C23
22U/6.3V_8
C32
0.1U/10V_4
PCH_EDIDCLK R23 *0_4

ĐůŽƐĞфϮϬϬŵŝů Note:
Note: entire trace of +TRAVIS3.3V should ZdϮϭϯϮ^схZϮϱ͕ZϮϬ
LDO mode change to 0ohm and 10u ϲϬϭϲͬϲϬϭϳ be wider than 80-mil
Pin11/Pin12 +1.2V_2132 entire trace of
ĐůŽƐĞфϮϬϬŵŝů ZdϮϭϯϮZсхZϮϴ͕ZϮϯ
should be wider than 80-mil
ůŽƐĞWŝŶϭϯ

CSCL1
MODE_CFG0(PIN30)
*0_4 R15
SMB_RUN_CLK <8,11,12,13,24> SCA_SCL
+3V R24 4.7K_4

*0_4/S R16 R26 *4.7K_4 SCA_SDA 0 1

MBCLK2 <8,13,27>

A 0 X EP MODE A
SI modify to short pad R21 R29 MODE_CFG1(PIN31)
CSDA1 *0_4 R12 ROM ONLY MODE EEPROM MODE
SMB_RUN_DAT <8,11,12,13,24> 1
*4.7K_4 4.7K_4
*0_4/S R11
352-(&78
MBDATA2 <8,13,27>
Reserve

Change Default setting to EC

4XDQWD&RPSXWHU,QF
Size Document Number Rev
EE PROM R15,R12 Custom LVDS converter RTD2132R 1A

5
EC OPTION 4
R16,R11 3 2
Date: Friday, April 26, 2013
1
Sheet 19 of 40
 5 4 3 2 1

LVDS Conn.
ϮϬ
+3VLCD_CON
ϴϬŵŝůĞƚƌĂĐĞ
R250 *0_8/S

CN1
+3V C365 SI modify to short pad 1K/F_4 R226 PCH_DPST_PWM_R
+LCDVCC <19> 2132_DPST_PWM
4.7U/6.3V_6

32
+3VLCD_CON 30
R225 C349
C22 U6 100K/F_4 29
22P/50V_4 +3V 28
PCH_DPST_PWM_R
*1U/6.3V_4 5 1 L19 C364 *10U/6.3V_6 C368 BLON_CON 27
IN OUT *TI160808U600 PCH_EDIDCLK 26
D 4 2 C362 *0.01U/16V_4 1000P/50V_4 PCH_EDIDDATA 25 D
IN GND 24
3 C359 0.1U/10V_4 PCH_LA_DATAN0 23
<19> 2132_DISP_ON ON/OFF <19> PCH_LA_DATAN0 22
^Dd <19> PCH_LA_DATAP0 PCH_LA_DATAP0
21
&ŽƌWKŶůLJ͗^ƚƵĨĨZĚ 20 35
*IC(5P) G5243AT11U &Žƌ>s^KŶůLJ͗^ƚƵĨĨZĐ <19> PCH_LA_DATAN1
PCH_LA_DATAN1
19
R3 ZĐ 0_4 <19> PCH_LA_DATAP1
PCH_LA_DATAP1
18
100K/F_4
ͺD/ R230
<19> PCH_LA_DATAN2
PCH_LA_DATAN2 17
L13 FCM1608KF-301T02 DIGITAL_D1_R R233 *0_4 EDP_HPD_R<19> PCH_LA_DATAP2 16
<21> DIGITAL_D1 <6,19> ULT_EDP_HPD PCH_LA_DATAP2 15 34
<21> DIGITAL_CLK L11 FCM1608KF-301T02 DIGITAL_CLK_R
14
R227 100K/F_4 C13 *33P/50V_4 DIGITAL_D1
ZĚ <19> PCH_LA_CLK# 13
<19> PCH_LA_CLK 12
C4 *33P/50V_4 DIGITAL_CLK
C350 22P/50V_4 C6 100P/50V_4 DIGITAL_D1_R USBP2-_C 11
Can't change to short D3 C3 100P/50V_4 DIGITAL_CLK_R USBP2+_C 10 33
R235 0_4 RB500V-40 BLON_CON 9
<27> EMU_LID 8
DIGITAL_D1_R
DIGITAL_CLK_R 7
6
R237 1K/F_4 5
<19> 2132_LVDS_BLON +3V +3V 4
C352 0.01U/16V_4 3
R229 4.7K/_4
Ra +VIN_BLIGHT 2
<19> PCH_EDIDDATA 1
C357 *4.7U/6.3V_6

31
R242
100K/F_4 R228 4.7K/_4
Rb C351 1000P/50V_4
<19> PCH_EDIDCLK
LVDS CONN
R255 *100K_4
Rc
C
DFWF30MR004 C
lvds-lvd-a30sfyg-30p-r
h^DZ FOX DFWF30MR007 EOD
+VIN_BLIGHT
+3V SI del 0ohm
L9
For LVDS stuff Ra=4.7k,Rb=4.7k,Rc un-stuff L12
+VIN_BLIGHT
+VIN
2132_LVDS_BLON R238 *1K_4 For eDP reserve Ra=100k,Rc=100k,Rb un-stuff <8> USBP2-
2 1 USBP2-_C *0_8/S
3 4 USBP2+_C
<8> USBP2+
C2 *4.7U/25V_8
2132_DPST_PWM R246 *1K_4 C360
MCM2012B900GBE 0.1U/50V_6 C348 0.1U/50V_6
Only for eDP reserve SI modify
C1 0.01U/25V_4

HDMI Conn. ,D/^DƵƐ/ƐŽůĂƚŝŽŶ +3V D/^ŽůƵƚŝŽŶ IN_D2 C167 0.1U/10V_4 C_TX2_HDMI+ 1

CN16
SHELL1
20
Q32 <2> IN_D2 D2+
R393 2.2K_4 C_TX2_HDMI+ R82 121/F_4 C_TX2_HDMI- 2
+3V D2 Shield
5 IN_D2# C169 0.1U/10V_4 C_TX2_HDMI- 3
<2> IN_D2# D2-
C_TX1_HDMI+ R93 121/F_4 C_TX1_HDMI- IN_D1 C176 0.1U/10V_4 C_TX1_HDMI+ 4
<2> IN_D1 D1+
HDMI_SCL_R 4 3 HDMI_SCLK 5
<6> SDVO_CLK D1 Shield
C_TX0_HDMI+ R96 121/F_4 C_TX0_HDMI- IN_D1# C177 0.1U/10V_4 C_TX1_HDMI- 6
<2> IN_D1# D1-
IN_D0 C180 0.1U/10V_4 C_TX0_HDMI+ 7
<2> IN_D0 D0+
2 C_TXC_HDMI+ R352 121/F_4 C_TXC_HDMI- 8
IN_D0# C181 0.1U/10V_4 C_TX0_HDMI- 9 D0 Shield
<2> IN_D0# D0-
HDMI_SDA_R 1 6 HDMI_SDATA IN_CLK C465 0.1U/10V_4 C_IN_CLK C_TXC_HDMI+ 10
<6> SDVO_DATA <2> IN_CLK CK+
B 11 B
IN_CLK# C470 0.1U/10V_4 C_IN_CLK# C_TXC_HDMI- 12 CK Shield
+3V <2> IN_CLK# CK-
R390 2.2K_4 C_IN_CLK R351 *0_4/S C_TXC_HDMI+ RB500V-40 13
2N7002DW C_IN_CLK# R354 *0_4/S C_TXC_HDMI- D13 2 1 5V_HSMBCK R395 2.2K_4 14 CE Remote
+5V_HDMIC NC
ůŽƐĞƚŽ,D/ĐŽŶŶĞĐƚŽƌ
2 1 5V_HSMBDT R394 2.2K_4 HDMI_SCLK 15
D12 RB500V-40 HDMI_SDATA 16 DDC CLK
SI del choke and chage 0ohm C506 *10P/50V_4 17 DDC DATA
C509 *10P/50V_4 18 GND
19 +5V
+5V_HDMIC HP DET 21
SHELL2
+3V HDMI_HPD L28 *0_6/S HDMI_DET_C HDMI CONN

SI modify C491
VC2
DGPU_CL_HDMIP R81 470/F_4 C_TX2_HDMI+ R363 *TVM0G5R5M220R
R83 470/F_4 C_TX2_HDMI- 1M_4 220P/50V_4
3

+3V Q31 R92 470/F_4 C_TX1_HDMI+ SI modify

2

2N7002K R94 470/F_4 C_TX1_HDMI-

40 mils F1 FUSE1A6V_POLY
2 R95 470/F_4 C_TX0_HDMI+ HDMI_HPD_CON 1 3 HDMI_HPD 2 1 +5V_HDMIC
<6> HDMI_HPD_CON +5V +5V_HDMIC
R97 470/F_4 C_TX0_HDMI-
Q30 R374 C507 0.1U/10V_4
R349 470/F_4 C_IN_CLK 2N7002 20K/F_4
R357 470/F_4 C_IN_CLK# VC3 SSM14 spec is 40V 1A
1

*TVM0G5R5M220R
R378 1 2 100K/F_4
<6,7,8,9,10,11,12,13,14,15,16,17,19,21,22,23,24,25,26,27,32,33,34> +3V
Change to 470 for EMI
<4,7,21,24,25,26,27,28,29> +3VPCU
C505 0.1U/10V_4 <6,21,23,24,25,26,33> +5V
A +VIN A
<24,28,29,30,31,32,33,34,35,36> +VIN
ůŽƐĞƚŽYϯϭ +5V_HDMIC <23,28,33,35> +12VALW
<13,21,24,25,29,31,32,33,34,36> +5VS5

C485
352-(&78
*0.01U/16V_4 4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom
>ͬ,D/ͬĂŵĞƌĂͬͲD/ 1A
for EMI request
Date: Monday, May 06, 2013 Sheet 20of 40
5 4 3 2 1
 A B C D E

+5V_AVDD

21
L40 +5V
Close to PIN1 >40mils trace <6,20,23,24,25,26,33> +5V
HCB1608KF-181T15_6

1
<6,7,8,9,10,11,12,13,14,15,16,17,19,20,22,23,24,25,26,27,32,33,34> +3V
C609 C605
*AZ2015-01H <10,24,26,30> +1.5V
L38 +3V_DVDD 10U/6.3VS_6 0.1U/10V_4
+3V C581

2
HCB1608KF-181T15_6 L36 +3V_DVDD-IO
+1.5V
HCB1608KF-181T15_6
C584 C592 C593
Close to PIN26
1U/6.3V_4 10U/6.3VS_6 0.1U/10V_4 L5014 AGND C581 need check!
+3V
*HCB1608KF-181T15_6 C601 C602 L5015 *HCB1608KF-181T15_6 +3V
0.1U/10V_4 10U/6.3VS_6
+1.5V_AVDD L37 +1.5V
C588 HCB1608KF-181T15_6
U24 10U/6.3VS_6
+5V
72'LJLWDO0,& C594 10P/50V_4
SI modify to short pad
1
DVDD AVDD1
26
40
AGND
Close to PIN40 +5V_AVDD
U23
R547 *0_4/S DMIC0 2 AVDD2 5 1
<20> DIGITAL_D1 GPIO0/ DMIC-DATA Vout Vin
R548 100/F_4 DMIC_CLK_R 3 25 4
<20> DIGITAL_CLK GPIO1 / DMIC-CLK AVSS1 AGND BYP
38 C345 C346 C579 C577 C578

Analog
C596 10P/50V_4 AVSS2 *2.2U/6.3V_6 *0.1U/10V_4 2 3 0.1U/10V_4 0.047U/10V_4 1U/6.3V_4
4 27 C598 10U/6.3VS_6 C580 GND EN
DVSS LDO1-CAP AGND
39 C595 10U/6.3VS_6 *1U/6.3V_4 *TPS793475DBVR
ACZ_SDOUT_AUDIO 5 LDO2-CAP HPA01091DBVR
<7> ACZ_SDOUT_AUDIO SDATA-OUT AGND
R549 0_4 HD_BCLK 6 28 C603 0.1U/10V_4 R545 10K_4 +5V
<7> BIT_CLK_AUDIO BCLK VREF
Close to PIN28 Vset=1.242V
10U/6.3VS_6 C599 7 C600 2.2U/6.3V_6
Close to PIN7 LDO3-CAP AGND
R550 33_4 HD_SDIN0 8 32 HPOUT_L AGND SHIELD
<7> ACZ_SDIN0 SDATA-IN HPOUT-L (PORT I)
33 HPOUT_R AGND SHIELD
+3V_DVDD-IO 9 HPOUT-R (PORT I)
DVDD-IO
AGND SHIELD
24
<7> ACZ_SYNC_AUDIO
ACZ_SYNC_AUDIO 10
SYNC
LINE2-L
LINE2-R
23 Close to Speaker

Digital
<7> ACZ_RST#_AUDIO
11
RESETB
^ƉĞĂŬĞƌϰŽŚŵ͗ϰϬŵŝůƐ
C939 *0.1U/10V_4 22 INT SPEAKER CONN
AMP_BEEP 12 LINE1-L (PORTC) 21 L_SPK+ L17 TI160808U600 L_SPK+_R
PCBEEP LINE1-R (PORTC) L_SPK- L16 TI160808U600 L_SPK-_R 1
C597 2.2U/6.3V_6 34 R_SPK- L15 TI160808U600 R_SPK-_R 2
CPVEE 20 R_SPK+ L14 TI160808U600 R_SPK+_R 3
MIC1-R (PORTB) 19 4
35 MIC1-L (PORTB) SI modify CN2
CBN 31
CAP- 37 MIC1-VREFO-L 30 MUTE_LED_CNTL R5108 *0_4/S C356 C355 C354 C353
CBP MIC1-VREFO-R MUTE_LED_CNTL_M <25>
C334
2.2U/6.3V_6 36 1000P/50V_4 1000P/50V_4
CAP+ CPVDD 18 MIC_R1 C629 *2.2U/6.3V_6 1000P/50V_4 1000P/50V_4
MIC2-R (PORTF) 17 MIC_L1 C608 2.2U/6.3V_6 R556 1K/F_4 EXT_MIC_L
+3V_DVDD MIC2-L (PORTF)
+3V_DVDD +5V_AVDD
42
4.7U/6.3V_6 C331 SPK-L+ 29 VREFOUT_C
L_SPK+ 43 SPDIF-OUT/GPIO2 MIC2-VREFO
SPK-L- 16
1 L_SPK- 44 MONO-OUT R553 1
Close to Pin 34,35,36 SPK-R- 10K_4
R_SPK- 45

SenseA

SenseB
PVDD1

PVDD2

JDREF
SPK-R+
72,QWHUQDO6SHDNHUV C604 check value C606
PDB

R_SPK+
NC

0.1U/10V_4 0.1U/10V_4
AMP_BEEP AMP_BEEP_L R551 100K/F_4 AMP_BEEP_R2
ALC3227 x QFN48
49

41

46

47

48

13

14

15

3
+5V_DVDD
L35 +5V_DVDD R552
+5V
C607 10K_4 2
ACZ_SPKR <9>
HCB1608KF-181T15_6 0.1U/10V_4 C589 Close to Pin 41 0.01U/25V_4
R554 20K/F_4 2N7002
10U/6.3VS_6 C582
AGND Check layout Q6
SENSE_A_1 R555 39.2K/F_4 SENSE_A mount location

1
+5V_DVDD
0.1U/10V_4 C587
Close to Pin 46 Close to codec AGND
AGND AGND EC17 1000P/50V_4
10U/6.3VS_6 C583

COMBO_GPI R546 22K/F_4 EXT_MIC_L EC36 1000P/50V_4

PD# C342 *1000P/50V_4
C585 4.7U/6.3V_6 AGND C339 *1000P/50V_4 EC18 1000P/50V_4
C338 *1000P/50V_4
EC37 1000P/50V_4
ĨŽƌŝŶƚĞů,^th>d
+1.5V

Q7
BA039040000 +3V_DVDD
USB 2.0 AND AUDIO COMBO JACK EC40 1000P/50V_4

BA039040020 AGND 1
R221 HPOUT_L
HPOUT_R 2
*2.2K_4 3
AGND AGND
EXT_MIC_L 4
R222 SI modify AGND
5
6
Close to CODEC
2

Q7 1K/F_4 7 ƉůĂĐĞƚŽŶĞĂƌhϮϰŽƌƵŶĚĞƌhϮϰ
*MMBT3904-7-F SENSE_A R5107 *0_4/S SENSE_R
ACZ_RST#_AUDIO 1 3 8 R206 *0_8/S
<25,27> USBPW_ON# 9
C590 *1000P/50V_4 +5VS5
PD# C586 10U/6.3V_8 10
11
+3VPCU 12
1 2 R223
<27> VOLMUTE# +3V 13
10K_4 <24> DEEP_PWRLED# AGND
D2 RB500V-40 SI del 0ohm 14
<7> SATA_LED# 15
MCM2012B900GBE <7> ACC_LED# 16
ACZ_SDIN0 EC38 *33P/50V_4 4 3 USBP1-_C 17
<8> USBP1- 18 CN9
1 2 USBP1+_C
<8> USBP1+ 19 Audio CONN
R211 2.2K_4 EXT_MIC_L
VREFOUT_C L8 20
ACZ_SDOUT_AUDIO EC19 *10P/50V_4 USBPW_ON#

C337
*1U/6.3V_4 ACZ_SYNC_AUDIO EC20 *10P/50V_4 C591
352-(&78
0.1U/25V_4 4XDQWD&RPSXWHU,QF
AGND BIT_CLK_AUDIO EC39 *33P/50V_4
Size Document Number Rev
FOR EMI Custom Azalia ALC 3227 1A

Date: Friday, April 26, 2013 Sheet 21 of 40

A B C D E
 5 4 3 2 1


For EMI 0 ~ 22 ohm

+1.05V_LAN
R42 +3V if ISOLATEB pin
LAN_XTAL1 *10/F_4 XTAL1 pull-low,the LAN
TP113
R39 2.49K/F_4 LANRSET chip will not drive
LAN_AMBLED# it's PCI-E outputs
XTAL2 R43 *0_4/S LAN_XTAL25_IN <26> +3V_LAN R19 ( excluding
TP112
1K_4
PCIE_WAKE# pin )
Y1
SI modify to short pad
ISOLATEB
TP114

VDD10
XTAL2
XTAL1
1 3 XTAL2

RSET

LED0

2
D 2 4 LAN_WLED# D
R18
*25MHZ +-10PPM
15K/F_4
C56 C59 U1

32
31
30
29
28
27
26
25

1
*10P/50V_4 *10P/50V_4
SI modify

LED1/GPO
LED2(LED1)
AVDD33

AVDD10
CKXTAL2
CKXTAL1
LED0
RSET
33
GND
WůĞĂƐĞĂĚĚϵ'Es/Ɛ
Switch Mode:Stuff L23 For RTL 8176
LDO Mode:Stuff R259 For RTL8166
ĐŽŶŶĞĐƚŝŽŶǁŝƚŚƚŚĞƌŵĂůW
Trace<30 mil
Width > 60 mil Power trace Layout ⮔ ⹎ > 60mil Place Cc,Cd,Ce,Cf MDI0+
MDI0-
1
2 MDIP0 REGOUT(NC)
24
23
+1.05V_LAN_REGOUT
DVDDL
+1.05V_LAN_REGOUT
+1.05V_LAN MDIN0 VDDREG(VDD33) +3V_LAN
4.7UH,+-20%,650MA_1210 close to each VDD10 pin-- 3, 8, 22, 30 VDD10 3 22 VDD10
>60mil L23
+1.05V_LAN
MDI1+ 4 AVDD10(NC) DVDD10(NC) 21 PCIE_WAKE#
+1.05V_LAN
+1.05V_LAN_REGOUT
>60mil MDI1- 5 MDIP1
RTL8176EH LANW AKEB 20 ISOLATEB
PCIE_WAKE# <6,23,26,27>
MDIN1 ISOLATEB
6 19 3 PLTRST# <6,11,14,23,24,26,27>
R259 *0_8 7 MDIP2(NC) PERSTB 18 /PCIE_RXN4_LAN_L C41 0.1U/10V_4
8 MDIN2(NC) HSON 17 7PCIE_RXP4_LAN_L PCIE_RXN4_LAN <8>
VDD10 C38 0.1U/10V_4
+1.05V_LAN AVDD10 HSOP 5 PCIE_RXP4_LAN <8>
6
nj Đ Ě Ğ Ĩ Ő

AVDD33(NC)
7

REFCLK_N
MDIN3(NC)

REFCLK_P
MDIP3(NC)
C622

CLKREQB

C46 C54 C390 C42 C37 C36 C621
4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 1U/6.3V_4 0.1U/10V_4

HSIN
HSIP
Close to Choke L23 RTL8176EH-CG

9
10
11
12
13
14
15
16
SWR mode need stuff C622 & Cz Place Cg & C621 close to each VDD10 pin22
C *RTL8166EH Cg & C621 close pin30 C

LAN_CLKRQ
U9
CLK_PCIE_LANN
CLK_PCIE_LANN <8>
+3V_LAN CLK_PCIE_LANP
1 16 CLK_PCIE_LANP <8>
MDI1+_1 MDI1+ PCIE_TXN4_LAN
TD+ TX+ PCIE_TXN4_LAN <8>
PCIE_CLKREQ_LAN# R10 *0_4/S PCIE_TXP4_LAN
<8> PCIE_CLKREQ_LAN# PCIE_TXP4_LAN <8>
MDI1-_1 3 15 TRA_V_DAC
TD- CMT SI modify to short pad
R22 75/F_4 LAN_MCTG1 2 14 MDI1-
CT TX-
MDI0+_1 6 9 MDI0-
RD+ RX-
MDI0-_1 8 10 TRA_V_DAC

R30 75/F_4 LAN_MCTG0 7

RD-

CT
CT

RX+
11 MDI0+ LAN conn
C366 NS681684 C52
TWD Type
10P/3KV_1808 0.01U/25V_4

Kd͗d^dϭϮϴϰZ>&Ϭ>ϱ>EϬϬ RJ45
(White) CN13
LAN_WLED 9
LAN_WLED# 10 LED_AMB_P A1
LED_AMB_N A2

B
Stuff Ca and Cb only, close to each VDD33 pin-- 11, 32 8 R234 B
7 RX1-
+3V_LAN MDI1-_1 6 RX1+
5 RX0- *0_6/S
4 TX1-
MDI1+_1 3 TX1+
+3VLANVCC RX0+
MDI0-_1 2 14
MDI0+_1 1 TX0- GND1
C34 C45 TX0+ 13
GND
0.1U/10V_4 0.1U/10V_4
Ă ď LAN_AMBLED 11
LAN_AMBLED# 12 LED_GRE_P B1
R266
LED_GRE_N B2
(Amber)
*0_6/S
C40 RJ45_CONN
68P/50V_4

Place Cc and Cd close to each VDD33 pin-- 23

C380 C53 +3VLANVCC C398 1000P/50V_4

4.7U/6.3V_6 0.1U/10V_4 R277 330_4

LAN_AMBLED
Đ Ě

A A
Remove For Not Using SWR mode
LAN_WLED
352-(&78
+3VLANVCC
R279 330_4

C399 1000P/50V_4
4XDQWD&RPSXWHU,QF
<6,7,8,9,10,11,12,13,14,15,16,17,19,20,21,23,24,25,26,27,32,33,34> +3V
Size Document Number Rev
<26,33> +3VLANVCC Custom
LAN RTL8176EH/RJ45 1A

Date: Friday, April 26, 2013 Sheet 22 of 40

5 4 3 2 1
 5 4 3 2 1

<8> PCIE_CLKREQ_CR#
PCIE_CLKREQ_CR# R301 *0_4/S PCIE_CLKREQ_CR#_R
R303 10K_4
Reserve for EMI

SD_D0
SD_D1
SD_D2
SD_D3
EC31
EC32
EC29
EC30
*5.6P/16V_4
*5.6P/16V_4
*5.6P/16V_4
*5.6P/16V_4
SP1
SP2
SP3
SP4
SP5
SP6
SD_D1
SD_D0
SD_CLK
SD_CMD
SD_D3
SD_D2
MS_D1
MS_D0
MS_D2
MS_D3
MS_CLK
23
+3V
SI modify to short pad
SP7 SD_WP MS_BS

RTS5237_3Vaux
R299 *0_6/S

RTS5237_GPIO
+3V

Share Pin
SI modify to short pad

SD_CD#
SD_WP
D C428 0.1U/10V_4 D

<6,22,26,27> PCIE_WAKE# R300 *0_4/S

C424
4.7U/6.3V_6
SD / MMC

32
31
30
29
28
27
26
25
U11

GPIO
3V3aux
WAKE#
MS_INS#
SD_CD#
SP7

NC
NC
PLTRST# 1 24
<6,11,14,22,24,26,27> PLTRST# PERST# NC
PCIE_CLKREQ_CR#_R 2 23
<8> PCIE_TXP2_CARD
PCIE_TXP2_CARD 3 CLKREQ#
HSIP
NC
NC
22 Close to chip pin
Zdiff = 100 ohm PCIE_TXN2_CARD 4 21 SD_D2_R R309 0_4 SD_D2
<8> PCIE_TXN2_CARD CLK_PCIE_CRP 5 HSIN SP6 20 SD_D3_R
RTS5237 R312 0_4 SD_D3
<8> CLK_PCIE_CRP 6 REFCLKP SP5 19
CLK_PCIE_CRN SD_CMD_R R313 0_4 SD_CMD
<8> CLK_PCIE_CRN 7 REFCLKN SP4 18
C443 0.1U/10V_4 PCIE_RXP2_CARD_C DV33_18 1U/10V_4 C441
<8> PCIE_RXP2_CARD 8 HSOP DV33_18 17
C446 0.1U/10V_4 PCIE_RXN2_CARD_C SD_CLK_R R317 33_4 SD_CLK C442 5.6P/16V_4
<8> PCIE_RXN2_CARD HSON SP3

CARD_3V3
WůĞĂƐĞĂĚĚϵ'Es/Ɛ SI modify

3V3_IN

DV12S
RREF
ĐŽŶŶĞĐƚŝŽŶǁŝƚŚƚŚĞƌŵĂůW

AV12

SP1
SP2
33

NC
GND
RTS5237 CARD READER

9
10
11
12
13
14
15
16
CN15

RTS5237_DV12S
C SD_D0_R R318 0_4 SD_D0 SD_D2 1 C
SD_D1_R R321 0_4 SD_D1 +3VCARD SD_D3 2 DAT2
SD_CMD 3 DAT3
SD_CD# 4 CMD
ZϳϬϬϵŶĞĞĚĐŽůƐĞƚŽŚŝƉ Close to chip pin CLOSE CONN 5 C/D
VSS1

C450

C457
6
+3VCARD VDD
R322 6.2K/F_4 RTS5237_RREF SD_CLK 7

RTS5237_AV12
1 2 8 CLK
C451 *100P/50V_4 C459 SD_D0 9 VSS2
SD_D1 10 DAT0

0.1U/10V_4

*0.1U/10V_4
10U/6.3V_8 SD_WP 11 DAT1
12 W /P
SI modify to short pad 0.1U/10V_4 C453 C449 C458 13 GND
14 GND
RTS5237_AV12 R330 *0_4/S RTS5237_DV12S 4.7U/6.3V_6 C454 0.1U/10V_4 4.7U/6.3V_6 15 GND
GND
+3V CARDREADER CONN

R5106 0_8

C460 C452 SI modify R3X Type

10U/6.3V_8 0.1U/10V_4 +3VCARD

SATA ODD
B
CONNECTOR +5V
B

+12VALW

C914
15'' SATA ODD

2
0.1U/10V_4
14'' SATA ODD Bypass CAP close conn R821
330K_6

3
Q44
New Type

1
CN26 AO3404 +5V_ODD
S1 2 SATA_TXP14_C C766 0.01U/25V_4 +3V
TXP 3 SATA_TXN14_C C764 0.01U/25V_4 SATA_TXP2 <7> 2
14 TXN SATA_TXN2 <7> CN24
14

1
5 SATA_RXN14_C C765 0.01U/25V_4
RXN 18

3
16 6 SATA_RXP14_C C767 0.01U/25V_4 SATA_RXN2 <7> R824
16 RXP 8 ZERO_ODD_DP# R822 1 2 1K_4 SATA_RXP2 <7> 10K_4 20 17 ZERO_ODD_DA# SI modify to short pad R823

1
DP 9 19 20 16 22_8
+5V ZERO_ODD_DP# <9> 19 15
S7 10 R574 *0_4/S 2
+5V_ODD <27> ZERO_PWR_ODD

2
+5V 14

1
P1 11 ZERO_ODD_DA# *0_4/S R40
MD ODD_EJECT# <27> 13
17 1 C913
17 GND1 4 SI modify to short pad 12 Q43 0.027U/25V_6
High : ODD power down

2
GND2 11

3
15 7 2N7002

1
15 GND3 10
GND
12
+5V_ODD +5V 9 +5V_ODD Low : ODD power on
13 ZERO_ODD_DP#
P6 GND 8 2
14 SATA ODD 7 SATA_RXP15_C C912 *0.01U/25V_4 SATA_RXP2
R564 *0_8 6 SATA_RXN15_C C910 *0.01U/25V_4 SATA_RXN2 Q47
5 2N7002
4 SATA_TXN15_C SATA_TXN2
SI change footprint C909 *0.01U/25V_4

1
A 3 SATA_TXP15_C C911 *0.01U/25V_4 SATA_TXP2 A
2
1
120 mils
+5V_ODD
*15 SATA ODD

C903
10U/6.3V_8
C905
0.1U/10V_4
C901
0.1U/10V_4
C902
0.1U/10V_4
C904
0.1U/10V_4
352-(&78
SI change pin define/PN 4XDQWD&RPSXWHU,QF
& footprint
Size Document Number Rev
Custom CR RTS5237 & CR SOCKET 1A

Date: Friday, May 03, 2013 Sheet 23 of 40

5 4 3 2 1
 Ϯϰ
A B C D E

WŽǁĞƌŽƚƚŽŶŽŶŶĞĐƚŽƌ dŽƵĐŚWĂĚŽŶŶĞĐƚŽƌ
WŝŶϭ͗нϯsWh;>/^t/d,WtZͿ
WŝŶϮ͗WKtZ> +3VPCU
WŝŶϯ͗>/^t/d,
WŝŶϰ͗'E Q1A 2N7002KDW +3VSUS R169 4.7K_4 TPCLK
WŝŶϱ͗'E R356 R165 4.7K_4 TPDATA 88513-0601-6p-l-smt
WŝŶϲ͗WKtZKEη 10K/F_4 <8,11,12,13,19> SMB_RUN_CLK
4 3 TP_SMB_CLK DFFC06FR062
C43 0.1U/10V_4
CN4
ƵĂů R107 4.7K_4
C257 10P/50V_4
<27> TPCLK 6
+3VPCU DEEP_PWRLED# L7 BLM18BA470SN1D TPCLK-1
<21> DEEP_PWRLED#

5
L6 BLM18BA470SN1D TPDATA-1 5
1 +3V +3VSUS 4

3
DEEP_PWRLED# C256 10P/50V_4
2 <27> TPDATA 3

2
4 R108 4.7K_4 TP_SMB_DATA 4
<27> LID_EC# 3 2
2 PWR_LED# TP_SMB_CLK
4 PWR_LED# <27> 1 6 1
TP_SMB_DATA
5 <8,11,12,13,19> SMB_RUN_DAT
CN7
<27> NBSWON1# 6 Q29 C474 C194 *10P/50V_4

1
DDTC144EUA-7-F 0.1U/10V_4 Q1B 2N7002KDW
POWER BTN CONN 25 mils C195 *10P/50V_4
C391 C51 DFFC06FR062
*220P/50V_4 C57 88513-0601-6p-l-smt +3VSUS C219 0.1U/10V_4

*220P/50V_4 *220P/50V_4

^d,ŽŶŶĞĐƚŽƌ;ĂďůĞƚLJƉĞͿ &E Mini PCI-E Card 2- Full size

CN25
Bypass CAP close conn
+5V
mSATA
C274 10U/6.3VS_6
1 R559 *0_4
<9> DEVSLP1
2
1
SATA_TXP0_C C253 0.01U/16V_4 C278 0.1U/10V_4
3 SATA_TXN0_C C254 SATA_TXP0 <7>
0.01U/16V_4
SATA_TXN0 <7> +3V
4 FAN1
5 SATA_RXN0_C C251 0.01U/16V_4 SATA_RXN0 <7>
6 SATA_RXP0_C C252 0.01U/16V_4 SATA_RXP0 <7> 5
7 15
3 8 <27> FAN1_PWM 2 3
9 3 6 +1.5V
+3V <27> FAN1SIG 46
Main HDD

,сϰ͘Ϭ
10
11 R186 4.7K_4 FAN Connect CN21
+3V
12 51 52
+5V Reserved +3.3V
13 49 50
14 +5V 月役EC 47 Reserved GND 48
15 C536 *10U/6.3V_8 45 Reserved +1.5V 46
16 43 Reserved LED_W PAN# 44
17 C539 *10U/6.3VS_6 41 Reserved LED_W LAN# 42
Reserved LED_W W AN#
18
19 C542 4.7U/6.3V_6 FAN1_PWM C277 *220P/50V_4
WůĂĐĞĂƉĐůŽƐĞƚŽ 39
37 Reserved GND
40
38
19 ĐŽŶŶǁŝƚŚŝŶϭϬϬŵŝůƐ 35 Reserved USB_D+ 36
C543 0.1U/10V_4 FAN1SIG C276 *220P/50V_4 C270 0.01U/16V_4 SATA_TXP1_C 33 GND USB_D- 34
<7> SATA_TXP1 31 PETp0 GND 32
C269 0.01U/16V_4 SATA_TXN1_C
<7> SATA_TXN1 29 PETn0 SMB_DATA 30
+5V: 2 A(4 Pin) GND SMB_CLK
SATA HDD(1ST) 27 28
DFHS13FS019 +3V: 2 A(4 Pin) C273 0.01U/16V_4 SATA_RXN1_C 25 GND +1.5V 26
<7> SATA_RXN1 PERp0 GND
sata-ah534-00-13p-r C275 0.01U/16V_4 SATA_RXP1_C 23 24
<7> SATA_RXP1 PERn0 +3.3Vaux
Gnd : (5 Pin) 21 22
19 GND PERST# 20
+3V 17 Reserved W _DISABLE# 18
Reserved GND
C265 4.7U/6.3V_6 15 16
13 GND Reserved 14
REFCLK+ Reserved

dWD;ϭ͘ϮͿ
C573 0.1U/10V_4 11 12
9 REFCLK- Reserved 10
C575 0.1U/10V_4 7 GND Reserved 8
TPM_XIN 5 CLKREQ# Reserved 6
BT_CHCLK +1.5V
TPM_XOUT
,сϮ͘ϱϰŵŵ C576 0.1U/10V_4 3 4

GND

GND
2 CLK_PCI_TPM 1 BT_DATA GND 2 2
C266 *4.7U/6.3V_6 W AKE# +3.3V
R581 *10M_4 MINI PCIE H4

54

53
C570 4.7U/6.3V_6
R582 DFHS52FR108
*33_4
Y6
1 4 C361 *0.1U/25V_4
+VIN
$GGUHVV 2 3
C828
+VIN
+VIN
C264
C610
*0.1U/25V_4
*0.1U/25V_4
C827 C826 *10P/50V_4 +VIN C611 *0.1U/25V_4
*32.768KHZ
%$'' *12p *12p +VIN C612
C613
*0.1U/25V_4
*0.1U/25V_4
BATT+ C17
C15
*0.1U/25V_4
*0.1U/25V_4 +1.5V
+3VS5 +VIN BATT+
+,*+ (+) GHIDXOW +VIN C615
C614
*0.1U/25V_4
*0.1U/25V_4
BATT+ C18
C16
*150P/50V_4
*150P/50V_4
+VIN BATT+
)25(0, +VIN
+VIN
C616
C618
*0.1U/25V_4
*0.1U/25V_4
+VIN C617 *0.1U/25V_4 C571 C574 C572
C822 +3V C619 *0.1U/25V_4 0.01U/16V_4 *0.1U/10V_4 *4.7U/6.3V_6
+VIN
*0.1U/10V_4
+1.35VSUS C625 *0.1U/25V_4
U41 C624 *0.1U/25V_4
LAD0 R584 *0_4 LAD0_T 26 10 C29 0.1U/25V_4 C626 *0.1U/25V_4
<7,26,27> LAD0 LAD0 VDD +VIN
LAD1 R585 *0_4 LAD1_T 23 19 C69 0.1U/25V_4
<7,26,27> LAD1 LAD1 VDD +3V +VIN
LAD2 R586 *0_4 LAD2_T 20 24 C196 0.1U/25V_4
<7,26,27> LAD2 LAD2 VDD +3V +VIN
LAD3 R587 *0_4 LAD3_T 17 5 C823 C824 C825 C240 0.1U/25V_4 C409 *0.1U/25V_4
<7,26,27> LAD3 LAD3 VSB +VIN +PRWSRC
CLK_PCI_TPM 21 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 C259 0.1U/25V_4 C632 *0.1U/25V_4 C408 *0.1U/25V_4
<8> CLK_PCI_TPM LCLK +VIN +5VS5 +PRWSRC
4 C5 0.1U/25V_4 C633 *0.1U/25V_4
GND +VIN
LFRAME# R588 *0_4 LFRAME#_T 22 11 R579 C11 0.1U/25V_4
<7,26,27> LFRAME# LFRAME# GND +VIN
PLTRST# 16 18 *4.7K/F_4 C39 0.1U/25V_4
<6,11,14,22,23,26,27> PLTRST# LRESET# GND +VIN <6,7,8,9,10,11,12,13,14,15,16,17,19,20,21,22,23,25,26,27,32,33,34> +3V
1 LPCPD#_TPM 28 25 R578 C371 0.1U/25V_4 1
LPCPD# GND +VIN <6,20,21,23,25,26,33> +5V
SERIRQ 27 *4.7K/F_4 C370 0.1U/25V_4
<9,27> SERIRQ SERIRQ +VIN <4,7,21,25,26,27,28,29> +3VPCU
6 C447 0.1U/25V_4
GPIO +VIN <28> BATT+
R577 *4.7K/F_4 9 2 TPM_PP C395 0.1U/25V_4
+3V TEST/BADD GPIO2 +VIN <23,28,33,35> +12VALW
LPCPD#_TPM C261 0.1U/25V_4
+VIN
CLKRUN# 15 7 TPM_PP C268 0.1U/25V_4
352-(&78
<6,27> CLKRUN# CLKRUN# PP +VIN
8
1 TESTI R580
3
12
NC
NC XTALI/32K IN
13
14
TPM_XIN
TPM_XOUT
*0_4
C19 0.1U/25V_4
4XDQWD&RPSXWHU,QF
NC XTALO +PRWSRC
+PRWSRC C12 0.1U/25V_4
*SLB9635TT1.2-FW3.17 +PRWSRC C44 0.1U/25V_4 Size Document Number Rev
+PRWSRC C110 0.1U/25V_4 Custom
,ͬŵ^dͬ&Eͬ> 1A

Date: Friday, April 26, 2013 Sheet 24of 40

A B C D E
 5 4 3 2 1

Ϯϱ
KEYBOARD Con. MY5
MY6
C83
C124
*220P/50V_4
*220P/50V_4
MY3 C128 *220P/50V_4
MY[0..17] KB CONN MY7 C106 *220P/50V_4 +5V +5V
<27> MY[0..17]
MX[0..7] MX1 32 MY8 C114 *220P/50V_4
<27> MX[0..7] 31 32
MX7 MY9 C63 *220P/50V_4 R350 R359
MX6 30 31 MY10 C137 *220P/50V_4
30 1K/F_4 1K/F_4
MUTE_LED_CNTL_R1 MY9 29 MY11 C136 *220P/50V_4
29

3
MX4 28
MX5 27 28
27
.(<%2$5'38//83
MY0 26 R355 2 1 *200/F_6 R364 2 1 *200/F_6
2 MX2 25 26 MY1 C89 *220P/50V_4
<21> MUTE_LED_CNTL_M 24 25
Q21 MX3 MY2 C100 *220P/50V_4 WIRELESS_ON_R WIRELESS_OFF_R
D SI modify 2N7002K MY5 23 24 MY4 C102 *220P/50V_4 Q24 Q26 D
23

3
MY1 22 MY0 C71 *220P/50V_4 DDTC144EUA-7-F DDTC144EUA-7-F
R348 1 MX0 21 22
10K/F_4 MY2 20 21 MX4 C64 *220P/50V_4 2 2
RP3 <27> WIRELESS_ON <27> WIRELESS_OFF
MY4 19 20 10 1 MY14 MX6 C62 *220P/50V_4
19 +3VPCU
MY7 18 MY13 9 2 MY11 MX3 C80 *220P/50V_4
MY8 17 18 MY12 8 3 MY10 MX2 C73 *220P/50V_4

1
MY6 16 17 MY3 7 4 MY15
MY3 15 16 MY6 6 5
MY12 14 15 MX7 C61 *220P/50V_4
MY13 13 14 MX0 C93 *220P/50V_4
+3VPCU *10P8R-8.2K
MY14 12 13 MX5 C68 *220P/50V_4
MY11 11 12 MX1 C60 *220P/50V_4
RP2
MY10 10 11 10 1 MY2
MY15 9 10 MY1 9 2 MY4 MY12 C132 *220P/50V_4
MY16 8 9 MY5 8 3 MY7 MY13 C133 *220P/50V_4
MY17 7 8 MY0 7 4 MY8 MY14 C134 *220P/50V_4
6 7 MY9 6 5 MY15 C139 *220P/50V_4
R64 2 1 200/F_6 CAPSLED#_R 5 6 MY16 C141 *220P/50V_4
<27> CAPSLED# 5
MUTE_LED_CNTL_R1 R67 2 1MUTE_LED_CNTL_R 4 *10P8R-8.2K MY17 C143 *220P/50V_4
4 +3VPCU
200/F_6 WIRELESS_ON_R 3
WIRELESS_OFF_R 2 3 R77 *8.2K_4 MY16
LED_PW 1 2 R79 *8.2K_4 MY17
+3V 1

CN5
50698-03201-001-32p-l
DFFC32FR039

C
R6X Type C

Hole
C533 0.1U/10V_4
USB 2.0/3.0 Combo C537 470P/50V_4 USB 3.0 H36
H37
*spad-re197x394np H30
VC4 *AVLC5S_4 H39 *h-tc197bc102d102pt *INTEL-BKT-SHARK-ULT FAN nut
C529 1000P/50V_4 CN20 *h-tsbc102d102pt H38
USB3.0 CONN *spad-re197x394np H27 H29
L33 DLP11SN900HL2L +5V_USBP0 1A 1
VBUS
h-tc256bc236d145p2 h-tc256bc236d145p2
4 3 USBP0-_C 2 1
<8> USBP0- D-

1
1 2 USBP0+_C 3 2
<8> USBP0+

1
2
3
4
USBP0-_C C549 *Clamp-Diode L32 *DLP11SN900HL2L 4 3 D+

1
1 2 1 2 USB30_RX1-_C 5 4 GND

1
<8> USB30_RX1- 4 3 6 5 SSRX-
USB30_RX1+_C SI modify
<8> USB30_RX1+

1
7 6 SSRX+
7 GND
SI add
USB30_TX1-_C C555 *Clamp-Diode C557 0.1U/10V_4 USB3_1- 1 2 USB30_TX1-_C 8
1 2 <8> USB30_TX1- 8 SSTX-
C567 0.1U/10V_4 USB3_1+ 4 3 USB30_TX1+_C 9 H33 H34 H10
<8> USB30_TX1+ 9 SSTX+
USBP0+_C C546 *Clamp-Diode *H-TC279BC216D141P2 *H-TC279BC216D141P2 *H-TC279BC216D141P2

13
12
11
10
1 2 L34 *DLP11SN900HL2L
Nut PN:MBFF4001010

13
12
11
10
SI del 0ohm
USB30_TX1+_C C568 *Clamp-Diode USB3_1- R529 0_4 USB30_TX1-_C
1 2 USB3_1+ R537 0_4 USB30_TX1+_C

1
USB30_RX1-_C C541 *Clamp-Diode
1 2 USB3_2- R457 0_4 USB30_TX2-_C
USB3_2+ R467 0_4 USB30_TX2+_C DFHS09FR122
B usb-2ub4029-200201f-9p B
USB30_RX1- R507 0_4 USB30_RX1-_C H13 H20 H14 H25 H16
USB30_RX1+ R508 0_4 USB30_RX1+_C *H-C394D118P2 *H-C394D118P2 *H-TC157BC236D118P2 *H-TC236BC314D102P2 *O-U83M-1
USB30_RX1+_C C544 *Clamp-Diode C532 0.1U/10V_4
1 2 USB30_RX2- R404
USB30_RX2+ R409
0_4
0_4
USB30_RX2-_C
USB30_RX2+_C
C535 470P/50V_4 USB 3.0
VC1 *AVLC5S_4
C262 1000P/50V_4 CN17

1
2
USB3.0 CONN
L30 DLP11SN900HL2L +5V_USBP0 1A 1
1 VBUS
USBP5-_C C519 *Clamp-Diode 4 3 USBP5-_C 2 SI modify
1 2 <8> USBP5- 2 D-
1 2 USBP5+_C 3
<8> USBP5+ 4 3 D+
*DLP11SN900HL2L
L29 1 2 USB30_RX2-_C 5 4 GND
USB30_TX2-_C C523
1 2
*Clamp-Diode
<8>
<8>
USB30_RX2-
USB30_RX2+
4 3 USB30_RX2+_C 6 5
6
SSRX- H17 H18 H15 Mini-PCIe & mSATA nut
7 SSRX+ *h-tsbc394d118p2 *H-C394D118P2 *H-C394D118P2
USBP5+_C C515 *Clamp-Diode C226 0.1U/10V_4 USB3_2- 1 2 USB30_TX2-_C 8 7 GND
1 2 <8> USB30_TX2- 8 SSTX-
C230 0.1U/10V_4 USB3_2+ 4 3 USB30_TX2+_C 9 H28
<8> USB30_TX2+ 9 SSTX+ *h-c236d102p2
13
12
11
10
L31 *DLP11SN900HL2L
USB30_TX2+_C C527 *Clamp-Diode
13
12
11
10

1
1 2
USB30_RX2-_C C510 *Clamp-Diode SI modify
1 2
SI delete

1
DFHS09FR122 H19 H24 H22 SI modify
usb-2ub4029-200201f-9p *H-C394D118P2 *H-C393D354P2 *O-U6X-2
USB30_RX2+_C C512 *Clamp-Diode
150 mils (Iout=3.7A)
1 2 +5VS5 +5V_USBP0
A U20 C525 220U/6.3V_6X4.5 Nut PN:MBZR7001010 A
2 8 +5V_USBP0 1 2
3 VIN1 OUT3 7
+

1
4 VIN2 OUT2 6
<21,27> USBPW_ON# EN OUT1
1 5
GND OC
VC5 C538
1U/6.3V_4
UP7534BRA8-20
Active Low
352-(&78
*AVLC5S_4 SI modify 4XDQWD&RPSXWHU,QF
<13,21,24,29,31,32,33,34,36> +5VS5
<4,7,21,24,26,27,28,29> +3VPCU
Size Document Number Rev
Custom
h^ϯ͘Ϭͬ< 1A

Date: Monday, May 06, 2013 Sheet 25of 40

5 4 3 2 1
 A B C D E

Ϯϲ
+1.5V +3V_WLAN_P
+3V_WLAN_P
+3VPCU +3VS5
+3V_WLAN_P
<9> BT_OFF
R292 C419 C416 C420 C418 C417 C438 C415
10K_4 0.01U/16V_4 0.1U/10V_4 10U/6.3VS_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 10U/6.3VS_6

2
+1.5V +3V_WLAN_P R324 C444

,сϰ͘Ϭ ƉŚ 10K_4

1
1 3 CN14 *0.022U/25V_4
Q39 6 52 Q18
28 +1.5V +3.3V 2 ME2303T1
2N7002E 48 +1.5V +3.3V 24 R560 200K_4 2
+1.5V +3.3Vaux
DŝŶŝĂƌĚ
R297 *0_6 INT_BT_OFF# 51 41 R293 4.7K_4 +3V_WLAN_P
4 +5V 49 Reserved Reserved 39 4
R316 *0_8 +3V
Reserved Reserved

3
t>Eͬd;KƉƚŝŽŶͿ
47 44 WLAN_LED# R294 *0_4/S 24mil
Reserved LED_W LAN# RF_LINK# <27>
R295 *0_4 45 46 Q20
<27> EC_DEBUG

3
19 Reserved LED_W PAN# 42 SI modify to short pad C8538 +3V_AOCS
<8> CLK_24M_DEBUG Reserved LED_W W AN#
PLTRST# 17 38 2
Reserved USB_D+ USBP6+ <8> <27> EC_AOCS#
33 36 *0.022U/25V_4 C439
<8> PCIE_TXP3_WLAN PETp0 USB_D- USBP6- <8>
31 32
<8> PCIE_TXN3_WLAN PETn0 SMB_DATA PLTRST# <6,11,14,22,23,24,27>
25 30 2N7002E SI modify *0.1U/10V_4
<8> PCIE_RXP3_WLAN PERp0 SMB_CLK
23 22 PLTRST#
<8> PCIE_RXN3_WLAN

1
13 PERn0 PERST# 20 INT_RF_OFF# R296 10K_4
<8> CLK_PCIE_WLANP REFCLK+ W _DISABLE# +3V_WLAN_P
11 16 LAD0
<8> CLK_PCIE_WLANN REFCLK- Reserved LAD0 <7,24,27>
R284 *0_4/S REQ_WLAN# 7 14 LAD1
<8> PCIE_CLKREQ_WLAN# CLKREQ# Reserved LAD1 <7,24,27>
R283 *0_4 5 12 LAD2
<9> BT_COMBO_EN# BT_CHCLK Reserved LAD2 <7,24,27> Q40
3 10 LAD3
SI modify to short pad BT_DATA Reserved LAD3 <7,24,27> 2N7002E
MINICAR_PME# 1 8 LFRAME#
W AKE# Reserved LFRAME# <7,24,27>
43 50
Reserved GND
37
35 Reserved GND
40
34
3 1
&ŽƌD/^ƵŐŐĞƐƚŝŽŶ
29 GND GND 26 CLK_24M_DEBUG EC3 *33P/50V_4
27 GND GND 18 R63 *0_4

2
GND GND
HOLE
HOLE
21 4

PAD
PAD
15 GND GND 9
GND GND RF_OFF <9>
MINI PCIE H=4.0
56
55
54
53
DFHS52FR108
D/E/ZͲϭϭϬϬϮϭͲϱϮϭϯϭͲϱϮWͲZhs
+3V_WLAN_P

3 ^ƵƉƉŽƌƚtĂŬĞ&ƵŶĐƚŝŽŶ;ZĞƐĞƌǀĞͿ 3

2
Accelerometer Sensor <6,22,23,27> PCIE_WAKE#
3
Q17
1 MINICAR_PME#
*DDTC144EUA-7-F

SI modify to short pad

+3V_WLAN_P
R46 *0_6/S +3V_WLAN_P
R308 10K/F_4

+G_SEN_PW U2
HP3DC2TR

2
C77 C107 1 2
0.1U/10V_4 0.1U/10V_4 14 Vdd_IO NC 3
VDD NC
3 1 MINICAR_PME#
<27> EC_PCIE_WAKE#
Q19 DDTC144EUA-7-F

10
ACCEL_INTA# 2 1 ACCEL_INTA#_R 11 RESERVED 13
<9> ACCEL_INTA# INT1 RESERVED
D5 RB500V-40 9 15
TP6 INT2 RESERVED

'ƌĞĞŶ><ŝƌĐƵŝƚƌLJ
16
ACCEL_INTA# R69 *0_4/S 7 RESERVED
MBDATA3 6 SDO
<27> MBDATA3 4 SDA 5
MBCLK3
<27> MBCLK3 SCL GND
2
C55 +G_SEN_PW 8 GND
12
ϮϬŵŝůƐǁŝĚƚŚ;ŵŝŶͿ 2

+G_SEN_PW CS +3VPCU
*22P/50V_4
MBDATA3 C98 *33P/50V_4
нϯsͺZdͺϬ͕нϯsͺZdͺZ͕нϯsͺZd͘͘
+3VLANVCC +3V_RTC_0
MBCLK3 C111 *33P/50V_4 AL003DC2A00
U21
R534 33_4 LAN_XTAL25_IN_R 6 15 C547 0.1U/10V_4
<22> LAN_XTAL25_IN 5 25M +V3.3A 2
R73 4.7K_4 MBDATA3 R518 33_4 PCH_XTAL24_IN_R
+G_SEN_PW <8> PCH_XTAL24_IN 24M VDD
R72 4.7K_4 MBCLK3 9 10 +3V_RTC_R R540 360/F_4
<7> CLKGEN_RTC_X1 32Khz VBAT
R536 22_4 CLK_27M_XTAL_IN_R12
<16> CLK_27M_XTAL_IN 27Mhz/NC C267 22U/6.3VS_8
C569 0.1U/10V_4 14
VDD_RTC_OUT +3V_RTC
8
+3VLANVCC VDDIO_25M
USBP7+ R561 0_4 USBP7+_C 3 7
Touch screen USBP7- R562 0_4 USBP7-_C
+1.05V

+3V_GFX
C548 0.1U/10V_4

GEN_XTAL25_OUT 16
11 VDDIO_24M
VDDIO_27/NC
GND
GND
GND
13
4
17
C558
SI modify to short pad C434 0.1U/10V_4 2.2U/6.3V_6
R816 *0_6/S GEN_XTAL25_IN 1 XTAL_OUT GND
+3V XTAL_IN
SLG3NB3354VTR
R817 *0_6 +5V
+VCC_TS
C545 12P/50V_4 C260 0.1U/10V_4 +3VLANVCC
P/N R536 C434
GEN_XTAL25_IN
R236 0_6 C58 *10P/50V_4 LAN_XTAL25_IN
UMA AL003355000 N/A N/A
2
1

U5 Y5
1 C358 C363 C487 *10P/50V_4 PCH_XTAL24_IN 1
*1U/10V_4 5 1 *1U/10V_4
+VCC_TS
CN22 25MHZ +-10PPM
DIS AL003354001 Install Install
IN OUT L42
4
3

4 2 *MCM2012B900GBE GEN_XTAL25_OUT C263 *10P/50V_4 CLK_27M_XTAL_IN

IN GND 2 1 USBP7-_C 1
<8> USBP7- 2
TS_ON 3 3 4 USBP7+_C C540 15P/50V_4
352-(&78
27> TS_ON ON/OFF <8> USBP7+ 3
TS_INTB#
4
R244
*100K/F_4
*IC(5P) G5243AT11U
Close to CN22 EC41 C623
5
6 <24,28> +PRWSRC 4XDQWD&RPSXWHU,QF
<6,7,8,9,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,27,32,33,34> +3V
SI modify to short pad *100P/50V_4 0.1U/10V_4 <6,20,21,23,24,25,33> +5V
Touch screen <4,7,21,24,25,27,28,29> +3VPCU Size Document Number Rev

R558 *0_4/S
Custom
t>Eͬ'Ͳ^ĞŶƐŽƌͬ'Ͳ><ͬd^ 1A

Date: Friday, May 03, 2013 Sheet 26of 40

A B C D E
 1 2 3 4 5 6 7 8

Ϯϳ
3920_RST#
+3VPCU

+3VPCU_EC +3VPCU Q28

500mA R377 4.7K_4 +3V
adapter Type check

3
C431 0.1U/10V_4 METR3904-G
C414 0.1U/10V_4 2 OVT_DETC 2 1 EC_PWROK
U12 C445 0.1U/10V_4 D11 RB500V-40
SERIRQ 3 9 C473 0.1U/10V_4
<9,24> SERIRQ

1
LFRAME# 4 SERIRQ VCC1 22 C411 0.1U/10V_4 L24
<7,24,26> LFRAME# 10 LFRAME VCC2 33 +3VPCU
LAD0 C448 0.1U/10V_4 BLM18BA470SN1D R353 10K/F_4 +3VPCU
<7,24,26> LAD0 8 LAD0 VCC3 96
LAD1 C472 0.1U/10V_4
<7,24,26> LAD1 7 LAD1 VCC4 111
LAD2 C422 0.1U/10V_4 THRM_ALERT_HW#1 Change to 1SS355 as Current loss
<7,24,26> LAD2 LAD2 VCC5

1
LAD3 5 125 C423 0.1U/10V_4
<7,24,26> LAD3 12 LAD3 VCC6 67
<8> CLK_24M_KBC +3VPCU_EC D10
A 13 PCICLK AVCC C421 A
<6,11,14,22,23,24,26> PLTRST# PCIRST/GPIO5 1SS355
CLKRUN# 38 C482 0.1U/10V_4 Open Drain need pu high
<6,24> CLKRUN# CLKRUN 4.7U/6.3V_6

2
SIO_EXT_SCI# 20 AD_TYPE R327 10K_4 R325 100/F_4
<9> SIO_EXT_SCI# SCI/GPIOE AD_ID <28>
R287 *0_4 SLP_S0#_EC 1 63 TEMP_MBAT
<6,11> PCH_SLP_S0_N GA20/GPIO0 AD0/GPI38 TEMP_MBAT <28>
RCIN# 2 64 AD_TYPE
<9> EC_RCIN# KBRST/GPIO1 AD1/GPI39
3920_RST# 37 65 AD_AIR 3 1
ECRST AD2/GPI3A 66 AD_AIR <28> DGPU_OVT# <17>
SYS_I C456 R342
55 AD3/GPI3B SYS_I <27,28>
MX0 Q25 12.1K/F_4 C455
<25> MX0 KSI0/GPIO30
MX1 56 68 *2N7002 0.1U/10V_4 100P/50V_4
<25> MX1 LAN_POWER <33>

2
MX2 57 KSI1/GPIO31 DA0/GPO3C 70
<25> MX2 58 KSI2/GPIO32 DA1/GPO3D 71 DGPU_PROCHOT_EC# <17,34> DGPU_PWROK <9,16,36>
MX3 BATSHIP
<25> MX3 MX4 59 KSI3/GPIO33 DA2/GPO3E 72 PCH_PCIE_WAKE# BATSHIP <28>
PCIE_WAKE# <6,22,23,26> R382 4.7K_4 +1.05V
<25> MX4 60 KSI4/GPIO34 DA3/GPO3F
MX5
<25> MX5 61 KSI5/GPIO35 21
MX6 R567 *0_4
<25> MX6 KSI6/GPIO36 PW M1/GPIOF FB_CLAMP <15,17> IMVP_PWRGD_R <4>
MX7 62 23 ZERO_PWR_ODD
<25> MX7 KSI7/GPIO37 PW M2/GPIO10 ZERO_PWR_ODD <23>
MY0 39 26 FAN1_PWM C497 220P/50V_4
<25> MY0 KSO0/GPIO20 FANPW M1/GPIO12 FAN1_PWM <24>

2
MY1 40 27 Q27
<25> MY1 KSO1/GPIO21 FANPW M2/GPIO13 FB_CLAMP_TGL_REQ#_EC <17>
MY2 41 28 FAN1SIG
<25> MY2 42 KSO2/GPIO22 FANFB1/GPIO14 29 FAN1SIG <24> 3 1
MY3 TS_ON <26>
<25> MY3 KSO3/GPIO23 FANFB2/GPIO15 PM_THRMTRIP# <9>
MY4 43
<25> MY4 44 KSO4/GPIO24 77
MY5 MBCLK METR3904-G
<25> MY5 45 KSO5/GPIO25 SCL1/GPIO44 78 MBCLK <28>
MY6 MBDATA
<25> MY6
MY7 46 KSO6/GPIO26 SDA1/GPIO45 79 MBCLK2
MBDATA <28> for Battery charge/charge
<25> MY7 MY8 47 KSO7/GPIO27 SCL2/GPIO46 80 MBDATA2 MBCLK2 <8,13,19>
<25> MY8
MY9 48 KSO8/GPIO28 SDA2/GPIO47 MBDATA2 <8,13,19> for DDR Thermal IC
<25> MY9 49 KSO9/GPIO29
<25> MY10 MY10
MY11 50 KSO10/GPIO2A H_PROCHOT#
<25> MY11 KSO11/GPIO2B H_PROCHOT# <2,32>
MY12 51
<25> MY12 KSO12/GPIO2C

3
B MY13 52 B
<25> MY13 KSO13/GPIO2D
MY14 53 6 SUSB#
<25> MY14 KSO14/GPIO2E GPIO4 SUSB# <6,11>
MY15 54
<25> MY15 KSO15/GPIO2F
MY16 81 14 HWPG H_PROCHOT#_EC 2 C405
<25> MY16 KSO16/GPIO48 GPIO7 HWPG <4,11,29,30,31>
MY17 82 15 H_PROCHOT#_EC Q13 *47P/50V_4
<25> MY17 KSO17/GPIO49 GPIO8 R289 2N7002K
GPUT_CLK 83 16 SUSC#
<17> GPUT_CLK 84 PSCLK1/GPIO4A GPIOA 17 SUSC# <6,11>
For GPU thermal GPUT_DATA SUSACK#_EC <6> *10K/F_4
<17> GPUT_DATA

1
85 PSDAT1/GPIO4B GPIOB 18
<26> MBCLK3 PSCLK2/GPIO4C GPIOC EC_AOCS# <26>
For Gsensor 86 19 NBSWON1#
<26> MBDATA3 87 PSDAT2/GPIO4D GPIOD 25 NBSWON1# <24>
TPCLK
<24> TPCLK PSCLK3/GPIO4E GPIO11 EMU_LID <20>
For Touch-Pad TPDATA 88 30 R291 *0_4/S
<24> TPDATA PSDAT3/GPIO4F GPIO16 EC_DEBUG <26>
31
119 GPIO17 32 FB_CLAMP1 <15>
BIOS_RD# SIO_EXT_SMI#
RD/GPIO5B GPIO18 SIO_EXT_SMI# <7>
BIOS_WR# 120
BIOS_CS# 128 W R/GPIO5C 34 VRON
SPICS/GPIO5A GPIO19 VRON <32>
89 36 DGPU_PROCHOT# R290 10K/F_4 NBSWON1#
SELIO/GPIO50 GPIO1A DGPU_PROCHOT# <34> +3VPCU
ACIN 76 R371 4.7K_4 MBCLK
<28,33> ACIN AD5/GPIO43
SI Modify <7> 109 TP116 SI Add Pin36 to DGPU_PROCHOT# for DB error R370 4.7K_4 MBDATA
PCI_SERR# D0/GPXD0
EC_GPXD1 110 R361 10K/F_4 EC_PCIE_WAKE# Reserve for ENE Hold time issue
112 D1/GPXD1 R285 47K/F_4 LID_EC#
<6> SUSWARN#_EC 114 D2/GPXD2 73 EC_PCIE_WAKE# MBCLK2 C479 *10P/50V_4
<26> RF_LINK# 115 D3/GPXD3 AD6/CIR_RX/GPIO40 74 EC_PCIE_WAKE# <26>
THRM_CPU
<6> SLP_SUS#_EC D4/GPXD4 AD7/GPIO41 THRM_MOINTOR <4>
D8 RB500V-40 116 75 GPIO42_EC MBDATA2 C478 *10P/50V_4
<7> GPIO33_EC 117 D5/GPXD5 AD4/GPIO42 90 DNBSWON#
<6> DPWROK_EC D6/GPXD6 GPIO52 DNBSWON# <6,11>
EC_PECI_R 118 91 CAPSLED# MBCLK C481 *10P/50V_4
D7/GPXD7 GPIO53 92 CAPSLED# <25>
PWR_LED# R319 *10K_4 GPIO33_EC
GPIO54 PWR_LED# <24> +3V
USBPW_ON# 97 93 EC_PWROK R366 4.7K_4 GPUT_CLK MBDATA C480 *10P/50V_4
<21,25> USBPW_ON# A0/GPXA0 GPIO55 EC_PWROK <6>
SUSON 98 95 RSMRST# R365 4.7K_4 GPUT_DATA
<31,33> SUSON A1/GPXA1 GPIO56 RSMRST# <6>
MAINON 99 121 VOLMUTE# GPUT_CLK C477 *10P/50V_4
<30,31,33> MAINON A2/GPXA2 GPIO57 VOLMUTE# <21>
C 100 126 BIOS_SPI_CLK R373 4.7K_4 DGPU_PROCHOT_EC# C
<10> SLP_SUS_ON A3/GPXA3 GPIO58
101 127 LID_EC# R368 4.7K_4 MBCLK2 GPUT_DATA C476 *10P/50V_4
SI modify <29> S5_ON A4/GPXA4 GPIO59 LID_EC# <24>
*0_4/S R326 102 R367 4.7K_4 MBDATA2
<4> THRM_MOINTOR1 103 A5/GPXA5
<27,28> SYS_I *0_4 R323
104 A6/GPXA6 123 CRY2 C432 *22P/50V_4
THRM_ALERT_HW#1 105 A7/GPXA7 GPIO5E
106 A8/GPXA8
<23> ODD_EJECT# 107 A9/GPXA9 122 CRY1 HWPG Close to BIOS
R307 *0_4/S AC_PRESENT_EC <6> C413 0.1U/10V_4
108 A10/GPXA10 GPIO5D BIOS_CS# R286 15/F_4
<28> MBATLED0# A11/GPXA11 PCH_SPI_CS0#_R <7>
SI modify to short pad BIOS_SPI_CLK R298 15/F_4
<28> AC_LED_ON# PCH_SPI1_CLK_R <7>
11 BIOS_WR# R310 15/F_4
<25> WIRELESS_ON GND1 PCH_SPI1_SI_R <7>
24 3920_RST# BIOS_RD# R314 15/F_4
<25> WIRELESS_OFF GND2 PCH_SPI1_SO_R <7>
35
124 GND3 94 R306 47K/F_4 C433 0.1U/10V_4
V18R GND4 +3VPCU
113
GND5
2

69 R818 *0_6/S
C429 C412 AGND
0.1U/10V_4 4.7U/6.3V_6 C410 *10P/50V_4 R288 *10_4 CLK_24M_KBC DGPU Thermal protect
1

KB9010QF C4 SI modify to short pad

Need Change New PN

CRY2 R281 *0_4
THRM_MOINTOR
PCH_SUSCLK <6> Adapter select for EC
2

THRM_MOINTOR1 R372 10K_4 GPIO42_EC R360 *10K_4

+3VPCU
R282
2

*100K_4 DIS Hi ==> ( 90W )

C631 C630
0.1U/10V_4 0.1U/10V_4 UMA Low ==>( 65W)
1

D DEL Temp Fail 0314 D

R315 43_4 EC_PECI_R

<2> EC_PECI
FOR SG/DIS H_PECI (50ohm)
Route on microstrip only
DGPU_PWROK R320 *0_4/S EC_GPXD1
Spacing >18 mils 352-(&78
Trace Length: 0.4~6.125 iches
4XDQWD&RPSXWHU,QF
<4,7,10,11,26,30,33,35> +1.05V
Size Document Number Rev
<6,7,8,9,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,32,33,34> +3V
<4,7,21,24,25,26,28,29> +3VPCU
Custom
;<ϵϬϭϬY&ϰͿ 1A

Date: Friday, April 26, 2013 Sheet 27 of 40

1 2 3 4 5 6 7 8
 5 4 3 2 1

Ϯϴ
CN10
*PMPCRF-08MLBK2ZZ4H0
BATT+ 1
2 1
SMD 3 2
EC2 +PRWSRC SMC 4 3
1000P/50V_4 4
Do Not add test pad on BATDIS_G signal 5
B_TEMP_MBAT 6 5
DC_JACK +BATCHG 6
AD_ID <27> Place this ZVS close to 7 10
90W EC21 EC24 EC22 EC23 PQ2 8 7 10 9
PL2
+VA_AC +VA Diode away +VIN TPCA8064-H
15" 8 9
5

CN12 PQ19 80/5A CN11

*1U/25V_4

*1U/25V_4

*1U/25V_4

*1U/25V_4
PL5 PD8
1 EMB20P03V 3 PMPCRA-08MLBK2ZZ4H4

S
PL1
AD_ID

D VDD 2 80/5A 5 1 1 2 +VAD PQ27 5 2 BATT+ 1 D

VDD 6 2 QM3016D 1 80/5A 2 1
PL6
7 3 P4SMAJ20A 4 3 SMD 3 2
4 3

G
6 80/5A 8 PC3 PC1 SMC
GND 4

0.1U/25V_4

0.1U/25V_4
PR39

4
PC15 5

1
8 3 PC16 PC97 PC102 BQBATDRV BATDIS_ID_DOD B_TEMP_MBAT 6 5
0.1U/25V_4

LED2 GND 4 PC99 PC48 +3VPCU 7 6 10

0.1U/25V_4

0.1U/25V_4

0.022U/50V_6
7 GND *2200P/50V_4 2200P/50V_4 8 7 10 9
LED1 PR47 2K/F_4 +VIN 8 9
RC1206-R010 PR1 PR2
DC-IN CONN BATDIS_G 1 2 330_4 330_4
AC_LED_ON# Place this ZVS close to
Far-Far away +VIN 14"
2

To PWR LED <27> MBDATA PR3

PQ21 200K_4

1
DRC5144

IDEA_G
+VAD <27> MBCLK
PR16 PD9
PR18 3 1 PQ22 1M_4 PR4
+12VALW PR15 P4SMAJ20A TEMP_MBAT <27>
4

Q2
1M_4 PQ18 3 PD3 PD4 1K/F_4
2

1
PDZ5.6B

PDZ5.6B
2N7002K 1M_4 PR46 PR48
PR19

2
5 6 PR55 PR56 *0_2/S *0_2/S PC2 PC123
1 3 PR13
2K/F_4 4.02K/F4

0.01U/25V_4

0.01U/25V_4
+5VPCU 220K_4 PR12
2 1

CSIP

CSIN
2.43K/F_6 +VA
3

Q1
PR20 1K_6

2
220K_4 MMDT2907A PC64 PC9 PC8 PC10
2

2200P/50V_4

1000P/50V_4
PC13

4.7U/25V_8

0.1U/25V_4
AC_LED_ON# <27>
PC4 PC5
*0.1U/25V_4

MBATLED0#

*100P/50V_4

*100P/50V_4
REGN6V
Place this cap
PQ16
close to EC
1

C DRC5144 C

BQACN
BQACP
PQ23 PC52 PC38
DRC5144 PC51 PC54

0.1U/25V_4

8
7
6
5
PR17
3 1 1U/16V_4 PQ12

16
+12VALW

1
1M_4 0.1U/25V_4 0.1U/25V_4 NTTFS4C25N EC28 EC27 EC25 EC26
2

2N7002K

*10U/25V_8

*10U/25V_8

*10U/25V_8

*10U/25V_8
ACP

ACN

REGN
18 BQHIDRV 4
PR14 HIDRV
PQ17 1 3
+5VPCU
BQCMSRC 3
CMSRC 1 2
2.43K/F_6 REGN6V
3

3
2
1
PD2 RB501V-40 PR50 +BATCHG
PR42
PC14 2 MBATLED0# <27> BQACDRV 4 17
BQB_2 BQB_1 RC1206-R020
ACDRV BTST F3_2X1_65-2_8
*0.1U/25V_4

0_6
PC39 PL4
PR58 19 1 2
PQ15 REGN6V BQPHASE 0.047U/25V_4 BQLR
1

DRC5144 PHASE 4.7uH/5.5A(EM-47AM05V08)

100K/F_4
ACIN 5 PU2
<27,33> ACIN ACPRES

8
7
6
5
15 BQLODRV
PR57 LODRV
BQ24738 PQ8 PR5 PC53 PC47 PC6 PC7

10U/25V_8

10U/25V_8
+VAD NTTFS4C25N *2.2_6

0.1U/25V_4

0.1U/25V_4
+VA_AIR +VA 100K/F_4
14 PR51 PR49
PD6 GND 21 4 *0_2/S *0_2/S
PR45 GND
1 2 BQVCC 20 22
VCC GND 23 PC37 PC11
22_8 GND
1N4448WS-7-F 24 *2200P/50V_4 PD7

3
2
1
PC50 GND 25 SX34
PR66 0.47U/25V_6 GND 0.1U/25V_4
75K/F_4 PR43 8 13 BQSRP
MBDATA BQDATA PR40 0_4/P
SDA SRP CSOP
*0_4/S
B 12 BQSRN PR36 0_4/P PC36 CSON B
<27> AD_AIR PR41 9 SRN
MBCLK BQCLK

0.1U/25V_4
ACDET
SCL 11 BQBATDRV

IOUT
*0_4/S BATDRV

ILIM
PC134 PC35
0.1U/10V_4
PR60 6

10

7
12.4K/F_4 0.1U/25V_4

BQIOUT
Place this cap PR52
close to EC +VAD
PR38 PR37 PR44
430K/F_4 SYS_I <27> +BATCHG

100K/F_4
*100K/F_4

10/F_4
ACDET=13V PR54 PR53 PC49
69.8K/F_4 88.7K/F_4 PC40 PC138
*0.1U/50V_6

100P/50V_4

0.01U/50V_4
PR69
+3VPCU 470_8
3

MIN. BATV=7.2V

3
PR73 Place this cap
2
+PRWSRC close to EC
1M_4
2
<27> BATSHIP
PR72 PQ7
+3VPCU <4,7,21,24,25,26,27,29>
1M_4 2N7002K
1

+5VPCU <13,29>
PQ13
BATT+ <24>
2N7002K
+PRWSRC <24>

1
A A
3

PQ9
+VA_AIR PR59 2 METR3904-G
1M_4

352-(&78
1

PR311
1M_4 4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom
ŚĂƌŐĞƌ;YϮϰϳϯϴͿ 1A

Date: Friday, April 26, 2013 Sheet 28 of 40

5 4 3 2 1
 5 4 3 2 1

DC/DC +3VS5/+5VS5
29
D D

+VIN Place these CAPs +VIN_5VS5

PL20 close to FETs
*0_8/S
Place these CAPs +VIN_3VS5 +VIN
close to FETs PL19
PC213
PC204 PC207 PC208 PC211 *0_8/S

0.1U/25V_4

2200P/50V_4
4.7U/25V_8

4.7U/25V_8

0.1U/25V_4
PC218 PC215 PC216 PC210 PC214
+VIN

2200P/50V_4
+5VPCU

0.1U/25V_4

4.7U/25V_8

4.7U/25V_8

0.1U/25V_4
PC197
PR173

4.7U/6.3V_6
10_8
+3VPCU
+2VREF +5VPCU
+5 Volt +/- 5%
+3.3 Volt +/- 5%
Countinue current:4A PC209
PC200 Countinue current:4A

4.7U/6.3V_6
Peak current:6A PC217 PR187

0.1U/25V_4
PR181 1U/6.3V_4 *0_2/S Peak current:6A
OCP minimum:7.5A *665K/F_4
OCP minimum:7.5A

16

17
5
6
7
8

8
7
6
5
C C
+5VS5 PQ50 PQ52 +3VS5

VREG3

VREG5

REF
VIN
NTTFS4C25N PR182 8205EN 13 4 NTTFS4C25N
EN0 TONSEL
*330K/F_4
2

2
4 5V_UGATE121 10 3V_UGATE2 4
PJP3 PC205 UGATE1 UGATE2 PC206 PJP4
PR183 22 9 PR184
*POWER_JP/S 5V_BST1 *POWER_JP/S
BOOT1 BOOT2
2.2_6 2.2_6
1

1
2
3

3
2
1

1
PL17 0.1U/25V_4 PU9 0.1U/25V_4 PL18
+5V_ALWP 5V_PHASE120 RT8223P 11 3V_PHASE2 +3.3V_ALWP
2.2uH/8A(EM-22AM05V04) PHASE1 PHASE2 2.2uH/8A(EM-22AM05V04)
PR150 PR180
5
6
7
8

5V_LGATE1 19 12 3V_LGATE2
LGATE1 LGATE2

8
7
6
5
*0_2/S *0_2/S
1

PR170 24 PR166

ENTRIP1

ENTRIP2
VOUT1

SKIPSEL
+ *2.2_6 5V_FB1 2 7 *2.2_6
FB1 OUT2

1
PC183 PC182 PR192 4

GND
GND
ENC
PR186
15.4K/F_4 PR185 0_4/P PGOOD 23 5 3V_FB2 4 +
220U/6.3V_6X4.5

0.1U/10V_4

+3VS5
2

PQ49 PGOOD FB2 PC184 PC203

10K_4
PC202 MDV1595SURH PQ51 PC194

0.1U/10V_4

220U/6.3V_6X4.5
1
2
3

18

14
25
15

2
*2200P/50V_4

*2200P/50V_4
<4,11,27,30,31> HWPG MDV1595SURH

3
2
1
PR191
10K/F_4 PR193 PR179
Rds(on) 14m ohm 80.6K/F_4 *0_2/S Rds(on) 14m ohm
PR190
6.8K/F_4

PR188
B 90.9K/F_4 B

PR189
10K/F_4
PR178 0_4/P S5_ON
S5_ON <27>

PC201
*1000P/50V_4

A A

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom 3/5VPCU(RT8223P) 1A

Date: Friday, April 26, 2013 Sheet 29 of 40

5 4 3 2 1
 5 4 3 2 1

30
D D

+VIN_1.05V +VIN +1.05V Volt +/- 5%

PU5
6 1
PL11 Countinue current:4A
NC VIN *0_8/S
Peak current:7.7A
14 PC114 PC116 PC118 PC115 PC120
AGND OCP minimum:9A

2200P/50V_4
0.1U/25V_4

4.7U/25V_8

4.7U/25V_8

0.1U/25V_4
3 2
NC PGND +1.05V
5
NC

2
PR305
*0_4 PC287 +1.05V_S2 PJP2
PR303
10 NB671BSTPCH NB671BSTPCH_S *POWER_JP/S
4 BST
0_6

1
PGOOD 0.1U/25V_4 PL13
8 NB671SW
SW 9 1uH/11A(EM-10AM05V06)
PR307 SW
HWPG NB671PGPCH 15
<4,11,27,29,31> HWPG SW 16
*0_4/S PR101
SW

1
*2.2_6
+
11 PR122 PC154 PC148 PC149 PC165 PC164 PC166 PC167 PC163
VCC *0_2/S

0.1U/10V_4

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

*22U/6.3V_8

*22U/6.3V_8

*22U/6.3V_8
*330U/2.5V_6X4.5ESR12
2
PC291 PC124
*2200P/50V_4

1U/6.3V_4
C C

7 NB671VOUTPCH
VOUT

MAINON PR306 0_4/P 13

<27,30,31,33> MAINON EN PR304
12 NB671FBPCH
FB
12K/F_4
PC292 PR302
NB671 16.2K/F_4
*0.1U/25V_4

B PR153 +1.5V +/- 5% B

*0_6/S
+3VS5
Countinue current:1.3A
PC181 Peak current:1.5A
4.7U/6.3V_6

OCP current:2A
+1.5V
4

PU8
VIN

PL16
HWPG PR161 0_4/P 5 3 8008LX1.5V
PG LX 2.2uH/1.3A_2520
PR145
MAINON PR159 0_4/P 1 2
<27,30,31,33> MAINON EN GND *0_2/S
PC177 PC178
FB

PC189
10U/6.3V_6

0.1U/10V_4

AWP8824CTI
0.1U/10V_4

R1 +VIN <20,24,28,29,31,32,33,34,35,36>
PR163 +3VS5 <6,9,10,11,24,26,29,33,35>
8008VFB1.5V
+5VS5 <13,21,24,25,29,31,32,33,34,36>
15K/F_4 +5VPCU <13,28,29>
PR164
R2 10K/F_4

VO=(0.6(R1+R2)/R2)
A A

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom +1.05V (NB671)/1.5V 1A

Date: Friday, April 26, 2013 Sheet 30 of 40

5 4 3 2 1
 1 2 3 4 5

31
A A

+1.35VSUS <2,4,12,13,24>

+VIN_DDR +VIN
( VTT/2A ) +1.35VSUS
PL22 +1.35V +/- 5%
+0.675V_DDR_VTT +0.75V_DDR_VTT *0_8/S
PU1 PC225 Countinue current:6A
3 2 PC27 PC26 PC223 PC224 PC25
VTT VLDOIN Peak current:10A

2200P/50V_4
0.1U/25V_4

4.7U/25V_8

4.7U/25V_8

0.1U/25V_4
8
7
6
5
1 *10U/6.3V_6
PC34 VTTSNS OCP minimum:12A
10U/6.3V_6
4 +1.35VSUS
VTTGND 14 51216DRVH 4
DRVH

2
7 PC28 PQ53
GND 15 51216VBST PR28 51216VBST_S NTTFS4C25N PJP5

3
2
1
21 VBST PL21 +1.35VSUS_S
( 3mA ) GND 2.2_6 *POWER_JP/S
PR197 0.1U/25V_4 0.82uH/13A(EM-82BM05V04)

1
B 5 13 51216SW 51216SW B
<12,13> DDR_VTTREF VTTREF SW
*100/F_4

8
7
6
5

1
PC226 PC33 11 51216DRVL PR195
<13> 51216S3 DRVL +
*0.1U/10V_4 0.22U/10V_4 *2.2_6
PR194 PC220 PC219
10 4 *0_2/S

0.1U/10V_4
330U/2.5V_6X4.5ESR12
2
MAINON PR32 0_4/P 51216S3 17 PGND
<27,30,33> MAINON S3 PQ54
9 51216VDDQSNS MDV1595SURH PC221

3
2
1
SUSON PR29 0_4/P 16
51216S5 VDDQSNS *2200P/50V_4
<27,33> SUSON S5 +1.8VREF
<4,11,27,29,30> HWPG HWPG PR35 0_4/P 20
51216PG
PGOOD 6
VREF
PR30 51216TRIP 18
TRIP Rds(on) 14m ohm
120K/F_4 PC32
0.1U/10V_4 PR34
PR33 51216MODE19 10K/F_4
MODE
47K/F_4
8 51216REFIN
12 REFIN
+5VS5 V5IN
APW8819QAI PC31 PR31
PC29 31.6K/F_4
0.01U/25V_4
1U/6.3V_4

C C

D D

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom
Zϯ;WtϴϴϭϵͿ 1A

Date: Friday, April 26, 2013 Sheet 31 of 40

1 2 3 4 5
 5 4 3 2 1


Place close
to inductor

1
PC187

PR157 PR131
*680P/50V_4 75K/F_4 220K_6 NTC TSENSE
PC188

2
PR158
D PR139 D
165K/F_4
1500P/50V_4 0_4/P

PR152
POP Rb and SWN
no POP Ra 64.9K/F_6

15.4K/F_4

1
for nex

22.6K/F_4
version.

1000P/50V_4
Boot Voltage Table PR136 PR119

100K/F_4

8.25K/F_4

TH05-3L104FR
R_boot V_boot

2
PC198 PC196 PC191
PR168

81101IOUT PR162
470P/50V_4

81101ILIMPR165
49.9/F_4 PC170 30.1K 0V

CSREFPC179
330P/50V_4 10P/50V_4 2.2U/6.3V_6

CSCOMP

PR147
PC199 Ra 49.9K 1.65V Place close

CSSUM
PR169 1K/F_4 PR177
to MOSFET
6.04K/F_4 +5VS5
*1500P/50V_4 69.8K 1.7V
PR176
PR167 POP for DIS

20

21

19

18

17

16

15
0_4 Rb 18.7K/F_4 90.9K 1.75V
+VIN_VCC_CORE +VIN

ILIM

CSSUM
IOUT

CSCOMP

CSREF

IMAX

PVCC
PL12
PC193 81101ROSC 22 14 VBOOT PR143 69.8K/F_4 *0_8/S
ROSC VBOOT

1
81101COM 23 13 TSENSE PC169 0.01U/25V_4 + + + +
C *2200P/50V_4 COMP TSENSE PC119 PC122 PC125 PC113 PC117 PC222 PC43 PC42 PC41 PC212 C
24 9

2200P/50V_4

100U/25V

100U/25V
81101FB 81101_HG PR140 1_6 81101_HG_G

*15U/25V

*15U/25V
4.7U/25V_8

4.7U/25V_8

0.1U/25V_4

0.1U/25V_4
*4.7U/25V_8

2
PR175 0_4/P PR172 0_4/P FB HG
81101DIFFOUT 25 PU7 11
DIFFOUT NCP81101MNTXG PGND PC168
<4> VSS_SENSE

2
PC195 81101VSN 26 8 81101_BST
<4> VCC_SENSE VSN BST

G1

D1

D1

D1
1000P/50V_4
PR174 0_4/P 81101VSP 27 10 81101_PH 0.22U/25V_6
VSP SW +VCC_CORE
PR171 81101VCC 28 12 81101_LG PL15

VR_HOT#
+5VS5

S1/D2
VCC LG

VR_RDY
ENABLE

ALERT#
2.2_6 81101_PH

VRMP
9

SCLK
0.36uH

SDIO
PC192 29
PR27 GND
1U/6.3V_4 PC132 PC151

G2

S2

S2

S2
PR116

*22U/6.3V_8

*22U/6.3V_8
*0_4/S

7
*2.2_6

5
PR138 PQ37
81101VRMP RJK03S3DPA

VR_HOT#

ALERT#

VR_RDY
+VIN_VCC_CORE

SCLK
SDIO
1K/F_4
PR160 0_4/P PC140
<27> VRON
PC176 *2200P/50V_4
PR156 *0_4 0.01U/50V_4 PR128 *0_2/S PR26 10/F_4 CSREF
<4> H_VR_ENABLE_MCP

PR127 *0_2/S SWN

PR155 *75/F_4 +VIN_VCC_CORE
+V1.05S_VCCST
+V1.05S_VCCST 81101_HG_G
H_PROCHOT# PR154 0_4/P
<2,27> H_PROCHOT#

<4> VR_SVID_DATA PR151 0_4/P Icc_Max=32A

2
B B
I_TDC=14A

G1

D1

D1

D1
<4> VR_SVID_ALERT# PR149 0_4/P
PR148 I_Dynamic=27A
130/F_4 PR144 PR141 PC190
<4> VR_SVID_CLK
PR146 0_4/P V_Operate=1.6V~1.8V
*75/F_4 54.9/F_4 0.1U/10V_4 DC_LL=2m

S1/D2
<4,6> IMVP_PWRGD IMVP_PWRGD PR142 0_4/P
81101_PH 9 AC_LL=7m
SDIO
+3V PR137 *10K/F_4 AC_LL_VOS=9.4m
ALERT# VBOOT=1.7V

G2

S2

S2

S2
SCLK

5
PQ1
*RJK03S3DPA
81101_LG

+VCC_CORE

PC133 PC135 PC139 PC129 PC152 PC153

*22U/6.3V_8

*22U/6.3V_8

*22U/6.3V_8

*22U/6.3V_8

*22U/6.3V_8

*22U/6.3V_8
A A

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom CPU Core (NCP81101)ULT 1A

Date:Friday, April 26, 2013 Sheet 32 of 40

5 4 3 2 1
 5 4 3 2 1

ϯϯ
+VAD

PR118
22_6
D D

PC144
0.1U/25V_4
PC145 2 1

17 G5934VOUT
0.1U/25V_4 PC143

20 G5934VIN

19 G5934CN

18 G5934CP
PC142

1U/35V_6
ACIN <27,28>

DCAP
0.47U/25V_6

16
PR121
*0_4 +VAD

VOUT
CP

D_CAP
VIN

CN
1 15 G5934PG
<27> LAN_POWER ON1 PG
PR123
*750K/F_4

MAINON 2 14 G5934VSENSE
<27,30,31> MAINON ON2 VSENSE

PU6 +12VALW
G5934RZ1U PR126
PR125 0_4/P 3 13 *100K/F_4
<27,31> SUSON ON3 REG

PC150
1U/16V_4
MAINON 4
ON4
7 G5934DISC3 PR134 0_4/P +3VSUS
C DISC3 C

PR129 0_4/P 5
G5934DISC1 6 G5934DISC2 PR135 0_4/P
+3VS5 +3VLANVCC DISC1 DISC2 +5V
DRIVER4

DRIVER3

DRIVER1

DRIVER2
DISC4
+5VS5

GND
5
6
7
8

PC172 PQ45
12

11

10

21
0.1U/10V_4 NTTFS4C25N

8
7
6
5
PC159
G5934DISC4

4 MAIND3.3V PQ47 0.1U/10V_4

NTTFS4C25N
$ PC162 MAIND 4
1
2
3

+3V
0.022U/25V_4
$
PC156 +5V

3
2
1
for +1.05V_MODPHY timing(64us) 2200P/50V_4

PR133
PC155 PC158 0_4/P
0.1U/10V_4 PC171 PC175
*10U/6.3V_6

0.1U/10V_4

*10U/6.3V_6
+3V
+12VALW +1.05V
+1.05V_MODPHY

B +VIN B
MAIND

8
7
6
5
+3VS5 +3VS5 PR113 PQ42 PC23
PR117 1M_4 LQ3E070BNFU7TB 0.1U/10V_4
*22_8
PR105 1.05VMOD_OND 4
PQ48 1M_4

3
PC174 EMB32N03K PC173 PQ34 PQ41
$
6
5
2
1

1
2
5
6

$ 0.1U/10V_4 *2N7002K 2N7002K PC137

0.1U/10V_4

3
2
1
+1.05V_MODPHY +1.05V

0.01U/25V_4
$
3 SUSD LAN_ON 3 2 2 PL14
+3VSUS
PQ46 *80/5A

3
EMB32N03K PC161 PC180 +3VLANVCC
4

2200P/50V_4 2200P/50V_4 PR106 PC141 PC147 PC24

1
2 1M_4 0.1U/10V_4

0.1U/10V_4
*10U/6.3V_6
<9> MPHY_PWREN
PC157 PC160
PC186 PC185 PQ35
0.1U/10V_4

*10U/6.3V_6

1
0.1U/10V_4 BSS138W 1.05VMOD_ONG
*10U/6.3V_6

for +1.05V_MODPHY timing (64us)

<6,7,8,9,10,11,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,32,34> +3V
<6,20,21,23,24,25,26> +5V
<20,24,28,29,30,31,32,34,35,36> +VIN
<6,9,10,11,24,26,29,30,35> +3VS5
<13,21,24,25,29,31,32,34,36> +5VS5
<23,28,35> +12VALW
A <22,26> +3VLANVCC A
<12,13,31> +0.75V_DDR_VTT

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom
ŝƐͲĐŚĂƌŐĞ/;^>'ϱϱϰϰϴͿ 1A

Date: Friday, April 26, 2013 Sheet 33 of 40

5 4 3 2 1
 5 4 3 2 1

VGA Core ϯϰ
PU3 RT8813A
+VIN_VGACORE +VIN

D D
PL3
PR83 PR67
+5VS5 8813PVCC 21 2 8813UGATE1 8813UGATE1_1 *0_8/S
PVCC UGATE1

1
*0_6/S 1_6
PC55 PC56 PC61 PC46 PC44 PC45 PC58

2200P/50V_4
PC68

4.7U/25V_8

4.7U/25V_8

4.7U/25V_8

0.1U/25V_4

0.1U/25V_4
*4.7U/25V_8

2
5

5
2.2U/10V_6
D D
G G
PC65 4 4
8813UGATE1_1
PR78 S S
PR76 8813TON 9 1 8813BOOT1
+VIN_VGACORE TON BOOT1
1_6 499K/F_4 PQ4 PQ3

1
2
3

1
2
3
PC66 0.22U/25V_6 TPCA8064-H *TPCA8064-H PL8
24 8813PHASE1
PHASE1 0.36uH
1U/25V_6

5
PR75
PR86 *2.2_6
+3V D D
10K/F_4 G G
16 23 8813LGAT1 4 4
<15,35> DGPU_VC_EN PGOOD LGATE1 S S
PD5 PQ20 PQ14

1
2
3

1
2
3
1 2 TPCA8A10-H *TPCA8A10-H PC62
PR77 *2200P/50V_4
RB501V-40 16.2K/F_4
8813EN 3 15 8813ISEN1 PR87 10K_4/P
<8,15,35> DGPU_PWR_EN EN VCC/ISEN1 +5VS5
PR65 47K/F_4
PC79
PC59
*2200P/50V_4 +VIN_VGACORE

13*9
C for VGA sequence 0.22U/10V_4 C

PR85
17 8813UGATE2 8813UGATE2_1
UGATE2
PR61 0_4/P 8813PSI 4
1_6
PC83 PC90 PC84 PC92 PC86 PC87
&RXQWLQXHFXUUHQW$
<17> PSI PSI

5
3HDNFXUUHQW$

2200P/50V_4
4.7U/25V_8

4.7U/25V_8

4.7U/25V_8

0.1U/25V_4
*4.7U/25V_8
D D
<17> GPU_VID
PR62 0_4/P 8813VID 5
VID 4
G
4
8813UGATE2_1
G 2&3PLQLPXP$
PC71 S S
18 8813BOOT2 PQ28 PQ24

1
2
3

1
2
3
BOOT2 TPCA8064-H *TPCA8064-H +VGACORE
8813VREF 0.22U/25V_6 PL10
19 8813PHASE2
8813VREF 8 PHASE2 0.36uH
VREF

1
5

5
PR99 + + + + +
PC60 D D *2.2_6 PC101 PC111 PC91 PC110 PC112

*330u_2V_7343
PR74 0.1U/10V_4

330U/2.5V_6X4.5ESR12

330U/2.5V_6X4.5ESR12

330U/2.5V_6X4.5ESR12

*330U/2.5V_6X4.5ESR12
G G

2
20K/F_4 20 8813LGAT2 4 4
LGATE2 S S
PR63 8813REFADJ 6 PQ26 PQ25

1
2
3

1
2
3
REFADJ TPCA8A10-H *TPCA8A10-H PC104
20K/F_4
PR196 *0_4/P *2200P/50V_4
DGPU_PROCHOT_EC# <17,27>
PC57
2700P/50V_4 PR64 14 8813ISEN2 PR88
TALERT/ISEN2 +3V
2K/F_4 30K/F_4
PR198 0_4/P
DGPU_PROCHOT# <27>
8813REFIN7
REFIN
B 11 8813VOUT1 PR84 B
VSNS +VGACORE
PC63 PC70 100/F_4
PR68 *0.01U/16V_4 *0_6/S PR82
18K/F_4 VGPU_CORE_SENSE <14>
56P/50V_4 PC69 PR81 0_4/P
*100P/50V_4 VSS_GPU_SENSE <14>
10 PR80
8813RGN
PR70 RGND PC67 100/F_4
0_4/P

56P/50V_4

PC72
12 8813SS
SS
56P/50V_4

PR79
22 8813PWM3
GND/PW M3 0_4/P
PR89
8813VREF
PR71 324/F_4
1 2 PR90 8813ISEN3 13 25
0_4/P TSNS/ISEN3 GND
10K/F_4 NTC
PC80
100P/50V_4

A A

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom +VGACORE (RT8813A) 1A

Date: Friday, April 26, 2013 Sheet 34 of 40

5 4 3 2 1
 1 2 3 4 5 6 7 8

ϯϱ
A A

+12VALW
+3V_GFX +VGACORE
+3VS5
+VIN

PR130 PQ61

1
2
5
6
PR299 PR296 1M_4 EMB32N03K
22_8 22_8 PC346
PR295 3VGFX_OND 3 0.1U/10V_4
1M_4

3
PQ59
2N7002K
PQ62
2N7002K
PQ60
2N7002K PC343 $

4
180P/50V_4 +3V_GFX
2 2 2

3
for VGA sequence
PR291 PR290 PC337 PC325

1
2 1M_4 0.1U/10V_4

*10U/6.3V_6
<8,15,34,35> DGPU_PWR_EN
0_4/P

PC293 PQ63

1
*1U/16V_4 LTC044 3VGFX_ONG

B B

+12VALW +1.05V
+1.05V_GFX

PQ38

5
+VIN PR109 MDU1512RH PC136
PR23 1M_4 D 0.1U/10V_4
22_8 G
1.05VGFX_OND 4
S
$

3
PR25

1
2
3
1M_4 PC127 +1.05V_GFX
1000P/50V_4
PR21 2 2
<8,15,34,35> DGPU_PWR_EN
3

110K/F_4 for VGA sequence

PQ32 PQ33 PC22 PC21
C PR22 2 PR24 2N7002K 2N7002K 0.1U/10V_4 C

*10U/6.3V_6
<15,34> DGPU_VC_EN
1

1
*0_4/P 1M_4
2

PC20 PQ31
1

0.047U/25V_4 LTC044
1

D D

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom 1.05V_VGA/3V_VGA
1A
Date:Friday, April 26, 2013 Sheet 35 of 40
1 2 3 4 5 6 7 8
 5 4 3 2 1

36
+VIN_1.5VGA +VIN
D
PR241 PL7
+1.5V Volt +/- 5% D
PR309
+5VS5 Countinue current:6A

RT8238VCC1.1V

RT8238TON1.1V
10_6 360K/F_4 *0_8/S

PC88 PC89 PC81 PC82 PC78 Peak current:8A

2200P/50V_4
PC251

0.1U/25V_4

4.7U/25V_8

4.7U/25V_8

0.1U/25V_4
OCP minimum:12A

8
7
6
5
1U/6.3V_4
PQ65
NTTFS4C25N +1.5V_GFX

11
5
PU12

2
3 RT8238DH1.1V

VCC

TON
PR310 UGATE
10
RT8238ILIM1.1V PC252 PJP1

3
2
1
CS 4 PR229
RT8238BST_1_1.1VRT8238BST1.1V
127K/F_4 BOOST *POWER_JP/S
+1.5VGFX_S2
2_6

1
PR96 0_4/P 9
RT8238HWPG_S2A1.1V RT8228A 0.1U/25V_4 PL9
<9,16,27> DGPU_PWROK PGOOD 2 RT8238LX1.1V
DGPU_FB_EN PR231 8
RT8238EN1.1V PHASE 1uH/11A(EM-10AM05V06)
<15> DGPU_FB_EN EN
30K/F_4 1 RT8238DL1.1V
LGATE

8
7
6
5
MODE
GND

1
PC249 13 PR98

FB
PAD *2.2_6 +
0.47U/6.3V_4

PR100 PC106 PC85 PC74 PC73

12

RT8238FB1.1V 6
4 *0_2/S

0.1U/10V_4

330U/2.5V_6X4.5ESR12

*22U/6.3V_8

*22U/6.3V_8
2
PQ66
Vo=0.5(R1+R2)/R2 MDV1595SURH PC98

3
2
1
*2200P/50V_4
PC250
C PR308 C
+5VS5
0_4/P
*100P/50V_4 RDSon=13m ohm
PR239
20K/F_4
PR240
10K/F_4

+1.5V_GFX
B B

+VIN
PR115
*22_8
3

PR120
*1M_4

2
3

PQ39
RT8238EN1.1V 2 PR114 *2N7002K
1

*1M_4

PC146 PQ40
1
*0.47U/6.3V_4

*DRC5144

A A

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
Custom
нϭ͘ϱsͺs';ZdϴϮϮϴͿ 1A

Date: Friday, April 26, 2013 Sheet 36 of 40

5 4 3 2 1
 1 2 3 4 5 6 7 8

USB3.0 Port Assignment Power control pin SATA Master Port Assignment Power control pin

A A

PORT1 USB2.0/USB3.0 COMBO 1st USBPW_ON#(from EC) SATA0 HDD N/A

USBPW_ON#(from EC) SATA1 mSATA N/A

USB2.0/USB3.0 COMBO 2nd
PORT2
SATA2 NC N/A
PORT3 NC N/A
SATA3/PCIE Card reader N/A

PORT4 NC N/A

PCIE Port Assignment Control pin

USB2.0 Port Assignment Power control pin

B B
USBPW_ON#(from EC) PCIE 5_L0 PEG0
PORT0 USB2.0/USB3.0 COMBO 1st
PCIE 5_L1 PEG1
PORT1 USB2.0/USB3.0 COMBO 2nd USBPW_ON#(from EC)
PCIE 5_L2 PEG2
PORT2 Camera N/A
PCIE 5_L3 PEG3
PORT3 NC N/A
PCIE 1 NC
PORT4 NC N/A
PCIE 2 NC
PORT5 Left side USB daughter B USBPW_ON#(from EC)
PCIE 3 WLAN
PORT6 WLAN N/A
C PCIE 4 LAN C

PORT7 Touch Screen 15" used TS_ON(from EC)

D D

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
1A

Date: Friday, April 26, 2013 Sheet 37 of 40

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+3V_DEEP_SUS +3VSUS +3V +3V

2.2K 2.2K 2.2K 2.2K *4.7K *4.7K 4.7K 4.7K

+3VSUS
AP2 SMB_PCH_CLK TP_SMB_CLK 1
2N7002KDW
AH1 SMB_PCH_DAT TP_SMB_DATA 2 Touch Pad
2N7002KDW
A A
+3VSUS
Haswell +3V
TP_SMB_CLK 53
ULT 2N7002DW
TP_SMB_DATA 51 XDP
+3V_DEEP_SUS
2N7002DW
+3V

2.2K 2.2K DDR3L DIMM

+3V *0ȍ 0ȍ
AU3 SMB_ME1_CLK MBCLK2 CSCL1 9
*2N7002DW
AH3 SMB_ME1_DAT MBDATA2 CSDA1 10 RTD2132R-CG
*2N7002DW
*0ȍ 0ȍ
+3V

B
+3V B

7 CPU heat pipe local thermal sensor (*G781-1P8)

4.7K 4.7K
79 MBCLK2 8

80 MBDATA2 7 DDR thermal sensor (*EMC1412-1-ACZL-TR)

+3VPCU
330
SMC 4

330 SMD 3 Battery

4.7K 4.7K
*short
77 MBCLK BQCLK 9

78 MBDATA BQDATA 8 Charger

+3V *short

C C

EC 4.7K 4.7K
83 GPUT_CLK D9
GPU internal thermal sensor (I2C)
KB9010QF 84 GPUT_DATA D8

+G_SEN_PW

4.7K 4.7K
85 MBCLK3 4

86 MBDATA3 6 G-sensor (AL003DC2A00)

+3VSUS

D 4.7K 4.7K BLM18BA470SN1D D

87 TPCLK TPCLK-1 5

88 TPDATA TPDATA-1 4 Touch Pad

BLM18BA470SN1D
352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
1A
SMBUS
Friday, AprilDate:
26, 2013 Sheet 38 of 40
1 2 3 4 5 6 7 8
 5 4 3 2 1

(+VAD)
Adapter

+PRWSRC
D D

(+VIN)
Battery Discharger IC
MAINON SUSON VRON DGPU_PWR_EN DGPU_FB_EN
SLG55448VTR +12VALW

AOS ANC ONS Richtek AOS LAN_POWER MAINON SUSON MAINON

+3VPCU
AOZ1237 APW8819QAI NCP81101MNTWG RT8813A AOZ1237
Richtek
RT8223P Driver 1 Driver 2 Driver 3 Driver 4
+5VPCU
(+3VS5) (+5VS5) (+3VS5) (+3VS5)
S5_ON
+1.05V +1.35VSUS +VCC_CORE +VGACORE +1.5V_GFX

DGPU_VC_EN

C
+3VLANVCC +5V +3VSUS +3V C

+3VS5 +5VS5 MOS

MDU1512RH

MAINON DGPU_PWR_EN USBPW_ON#

+1.05V_GFX
SGY MOS Power SW
SY8002ABC EMB32N03K G547N2P81U

+1.5V +3V_GFX +5V_USBP0

B B

A A

352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
1A
Power Block Diagram
Date: Friday, April 26, 2013 Sheet 39 of 40
5 4 3 2 1
 5 4 3 2 1

+VIN +PWR_SRC +VIN

+3VS5 +3VLANVCC +3VS5 +3V 17 2 1
16 +3VPCU +3VS5

S5 PWR S5 PWR 3 +5VS5

LAN_POWER 10 MAINON 11 PWR +5VPUC 3V/5V
MOS SW MOS SW BTN VR CHARGER Battery
HWPG
D
+5VS5 +5V
17 +3VS5 +3V_GFX
D

19 23
LATCH
3
S5 PWR S5 PWR 13
(NBSWON1#)
MAINON 11 DGPU_PWR_EN
MOS SW MOS SW
SUS_ON 9
22 4 S5_ON
MAINON 11 5
+3VS5 +3VSUS
15 +1.05V +1.05V_GFX VCCDSW3_3
VRON 12 6 DNBSWON#
PWRBTN#
7 SUSC#
LAN_POWER 10 SLP_S4#
S5 PWR S0 PWR 8 SUSB#
SUS_ON 9 DGPU_VC_EN SLP_S3#
MOS SW MOS SW 13 DGPU_PWR_EN
GPIO54
14 EC DGPU_PWROK
25 GPIO17
PCH
C
25 C

27 PLTRST#
DGPU_PWROK PLTRST#
+VIN 21 D1/GPXD1
+1.5V_GFX EC_PWROK
GPIO55 SYS_PWROK
HWPG 0ȍ
DGPU_VC_EN 14 GPIO7 26 PCH_PWROK
1.5V
VR 23 *TC7SH08FU
DGPU_PWROK APWROK
PG 25 IMVP_PWRGD

+VIN
+1.35VSUS 15 EC_PWROK

SUS_ON 9
1.35V
VR
HWPG
PG
B B
+VIN 17
+1.05V

MAINON 11
1.05V
VR CPU
HWPG
PG

+3VS5 17 +VIN +VIN

+1.5V 20 18
+VGACORE +VCC_CORE
MAINON 11
LDO +3V IMVP
HWPG
PG
VR 14 VR 24
DGPU_VC_EN IMVP_PWRGD
PG PG
EN

EN

A A

DGPU_PWR_EN 13 VRON 12
352-(&78
4XDQWD&RPSXWHU,QF
Size Document Number Rev
1A

Date:
POWER UP Sheet
SEQUENCE of
Friday, April 26, 2013
40 40
5 4 3 2 1
www.s-manuals.com