Embedded Systems by PS CHANDRASHEKAR.

Chpt-3: Introduction to MSP430 Architecture 1.

CHAPTER- 3
INTRODUCTION TO
MSP430 ARCHITECTURE
.

Contents:
3.1: Introduction to MSP430 Architecture
3.2: Features of MSP430
3.3: Different families and naming of MSP430
3.4: Data sheet reading of MSP430
3.5: Central Processing Unit (CPU)
3.6: Registers in the CPU of MSP430
3.7: Memory mapping of MSP430
3.8: Addressing modes
3.9: Constant Generators and Emulated Instructions
3.10: Low Power Modes of MSP430
3.11: Comparison of MSP430 with 8051 Architecture
3.12: Exceptions: interrupts and resets
3.13: Interrupt Processing

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Chpt-3: Introduction to MSP430 Architecture 2.
3.1: Introduction to MSP430 Architecture:
MSP430 is the simplest microcontroller from Texas Instruments which
was introduced in the late 1990’s. It is a 16 bit data processor with RISC
architecture. It has 16 bit address and hence it can address up to 2 16=64-KB
of memory. The MSP430 has 16 registers in its CPU which can be utilized for
storing of address or data.

3.2: Features of MSP430:

The Features that make MSP430 suitable for low power and portable
applications are:

i. CPU is small and efficient with a large number of instructions.

ii. It can be easily used in Low power mode.
iii. There are several low power modes.
iv. There is a choice of clocks. The CPU is clocked by and internal
Digitally Controlled Oscillator (DCO).
v. A wide range of peripherals are available.
vi. MSP430 can directly drive some portable devices like LCDs.
vii. MSP430 is classified as ASSP (Application Specific Standard Product) and
contain Analog hardware for various types of measurement.

3.3: Different families and naming of MSP430:

 MSP stands for Mixed Signal Processor which indicates that it can
process both analog and digital signals.
 The latter after MSP shows the type of memory. ‘F’ Stands for Flash
Memory and ‘C’ stands for ROM memory.
 After that, for ASSPs, the second letter shows the type of
measurement such as ‘E’ stands for Electricity, ‘W’ stands for Water
and ‘G’ stands for Signals.
 Then, the next digit shows the family and final 2 or 3 digits identify the
specific device.

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Chpt-3: Introduction to MSP430 Architecture 3.
1. MSP430x1xx: Provides wide range of general purpose devices from simple
versions to complete systems for processing signals. The peripheral units
include hardware multiplier, which can be used as Digital Signal Processor.
The packages have 20-64 pins.
2. MSP430F2xx: This can run at 16-MHz and consumes very less current.
Packages have 14 pin in Plastic Dual-in-line Package (PDIP).
The pull-up and pull-down resistors are provided. It offers sigma-delta type
of A-D conversion.
3. MSP430x3xx: This includes drivers for LCD. But now, it is no longer
available.
4. MSP430x4xx: This can drive LCD up to 160 segments. Many of them are
ASSPs but general purpose devices as well. The packages have 48 to 113
pins. Among them, most pins are for driving the LCDs.
5. MSP430: This is the original architecture extended to MSP430X in 2006.

3.4: Data sheet reading of MSP430:

i. MSP430 the outside view – Pin out diagram of MSP430:
MSP430F2013 is available in 14 pin Plastic Dual-in-Line (PDIP) with pins
0.1” (0.1 inch) apart. Almost all pins have several functions.

 Vcc and Vss: These pins are Supply voltage and Ground respectively.
 P1.0 – P1.7, P2.6 and P2.7: Grouped into ports P1 and P2.
 TACLK, TA0 and TA1: TACLK can be used as the clock input to the timer.
TA0 and TA1 can be used as either input or output.
 +A0 to +A4 are used as input to the analog to digital convertor. Vref is
the reference voltage to the convertor.
 ACLK and SMCLK are the outputs for the microcontroller’s clock signal.
 SCLK, SDO and SCL are the Serial Interface for the Serial Peripheral
Interface (SPI) or Inter-Integrated Circuit (I2C).
 Xin and Xout are connected to a crystal oscillator.

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Chpt-3: Introduction to MSP430 Architecture 4.
 RST: Reset active low signal.
 NMI: Non Maskable Interrupt.
 TCK, TMS, TCLK, TDI, TDO and test signal are used for JTAG interface.
 SBWTDIO and SBWTCK provide the Spy-bi- wire Interface used as an
alternate to JTAG to save pins.

vcc 1 14 Vss

P1.0/TACLK/ACLJK/A0+ 2 13 XIN/P2.6/TA1

P1.1/TA0/AO-/A4+ 3 12 XOUT/P2.7

OUTSIDE
P1.2/TA1/A1+/A4- 4 VIEW 11 TEST/SBWTCK

P1.3/Vref/A1- 5 10 XRST/NMI/SBWTDF0

P1.4/SMCLK/A2+/TCK 6 9 P1.7/A3-/SDI/SDA/TD0/TDI

P1.5/TA0/A2- 7 8 P1.6/TA1/A3+/SD0/TDI/TCL

ii. MSP430 inside view – Functional block diagram:

 The diagram below shows the inside view of F2013 (2-KB) and
F2003 (1-KB) version of MSP430.
 The block diagram consists of clock generation, emulation, JTAG and
Spy-bi-wire which are used to communicate with a desktop computer
when downloading a program for debugging.
 There are Memory Address Bus (MAB) and Memory Data Bus (MDB).
 There is 1KB of flash memory in MSPF2003 and 2KB of flash
memory in MSPF2013. The RAM is of 128 bytes.
 There are 6 peripheral functional blocks. i.e., ports timer-A Watch
Dog Timer, Universal Serial Interface (USI) SD16-A (Sigma Delta
Analog Digital converter).
 There is only one pair of Address and Data buses as per the
Von-Neumann architecture.

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Chpt-3: Introduction to MSP430 Architecture 5.
Vcc Vss

3.5: Central Processing Unit (CPU):

The CPU executes the instructions stored in memory. A CPU includes:

- Arithmetic Logic Unit(ALU): It performs the computations

- Sixteen registers (R0-R15) to store the data and address internally.
- A logic unit to perform decoding and implementing the instructions.
- The CPU clock frequency can run up to a maximum clock frequency F mclk
of 16-MHz. Each register can hold a word of 16-bits.
- R0-R3 has got the dedicated functions and R4-R15 are the working
registers for general purpose. Either word or byte can be written in the
register.

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Chpt-3: Introduction to MSP430 Architecture 6.
- A set of 16 registers is the characteristic of RISC (Reduced Instruction
Computer).

 The CPU consists of the following registers:

 Program Counter (PC): This consist the address of the next instruction
to be executed. The instructions are composed of 1 to 3words which
must be aligned to even addresses.
 Stack Pointer (SP): this consists of the address of the stack top.
 Status Register (SR): The commonly used flag bits are C, Z, N, V which
reflects the condition of the result after an arithmetic or logical
operation.
 The GIE bits enables the Maskable interrupts CPUOFF, OSCOFF,
SCG0 and SCG1 bits controls the
modes of the operation of MCU.
These bits would put MCU in one of
the low power modes.
 Constant generator: It provides 6
most frequently used constant values
whenever they are required. This uses
both R2 and R3 to provide different
constant values in different
addressing modes.
 General purpose registers: the 12
registers from R4 to R15 are the
general working registers. They may
be used either for storing the data or
address as both of them are 16-bits.

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Chpt-3: Introduction to MSP430 Architecture 7.
3.6: Registers in the CPU of MSP430: There are 4 Special purpose
registers and 12 General purpose registers in MSP430. Those are:

1. Program Counter (PC):

This consist the address of the next instruction to be executed.

The instructions are composed of 1 to 3 words which must start with an even
address. And hence, the LSB of PC is hardwired to 0. In order to execute an
instruction, its address which is available in PC is placed on the address bus
and sent to fetch the instruction from the memory. The value in PC is
automatically increased by 2 to fetch the next instruction. Therefore, the
instructions are executed sequentially unless there is a branch or jump
instruction. Subroutines and interrupts modify the PC but the previous content
of PC is (i.e. return address) is saved on the stack.`

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Program counter bits 15 to 1 0

2. Stack Pointer (SP):

Whenever the subroutine is called, the execution jumps to the

subroutine and returns back to the main routine. Therefore, the return
address of the main routine from where it was branched earlier has to be
saved in the stack. A stack is LIFO (i.e. Last in First Out) data structure.
A stack pointer holds the address of the top of the stack. i.e. the stack pointer
contains the address of the most recently added word.

The stack is mostly initialized to 0x027F which is the highest address of

RAM area. The RAM area is between 0x0200 to 0x027F.

The stack operation is as demonstrated below:

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Chpt-3: Introduction to MSP430 Architecture 8.
a. Initialization: when reset, the stack pointer points to one location ahead,
to stack beginning.
b. After PUSH.W#0x1234 the stack pointer increments by 2 locations to
store a word.
c. Further PUSH.B #0x56
. PUSH.W #0x789A
Here, the Stack Pointer increments twice to store a byte and word.
d. After POP.W R5 the stack pointer decrements by 2 to retrieve a word
from stack to register R5.

15 …... 9 8 7 6 5 4 3 2 1 0

Reserved V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C

3. Status register (SR):

This is a 16-bit register which contains a set of flags which are categorized
into 3 sections. The diagram shows the Status register. N, Z, C & V are
affected by the operation perfumed by ALU.

 C (Carry bit): This indicates the condition of the result of an arithmetic

operation the carry flag bit also involves in rotation and shift operation.
Ex: 0x9706 + 0x8746 =0x1E4C and the carry sets.

 Z (Zero bit): This indicates the all zero condition in the result after
computational operation. The Z-bit is to check whether two values are
equal.

 N (Negative flag): This is made equal to the MSB of the result which
indicates whether they have negative or positive sign of the value.

 V (Overflow flag): The V-bit would be set in the case to show that an
overflow occurs in a signed operation.

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Chpt-3: Introduction to MSP430 Architecture 9.
 Enable Interrupts/ General Interrupt Enable (GIE): This bit is cleared to
disable the maskable interrupts and set to enable the interrupts.

 Control low power modes: CPUOFF, OSCOFF SCG0 and SCG1 bits control
the modes of operation of the MCU. The system is fully operational when
all bits are cleared. Setting combinations of these bits choose different low
power modes.

3.7: Memory mapping of MSP430:

The memory mapping of MSP430 is as shown in the figure. It consists
of 64-KB of memory from 0x0000 to 0XFFFF (216 = 64-KB).
The memory space of 64-KB is partitioned into following regions:

i. Special Functional Registers: These registers do the enabling of

modules and signaling for interrupts from peripherals.
ii. Peripheral Registers of Byte access and Peripheral Registers of Word
access: These registers support
connection between CPU and
Peripherals.
iii. RAM: Used to store the variables. It’s size
is 128 Bytes.
iv. Bootstrap loader: contains programs to
communicate using a standard protocol
with com port of PC.
v. Information memory: A 256 bytes of
flash memory for the storage of non
volatile data such as several settings
information.
vi. Code memory: Holds the program which
is executable code and only constant
data. The size of data for F203 is 1-KB
and for F2013 is 2-KB.
vii. Interrupt and Reset vectors: This is a table of memory which stores
the vectors for the interrupts and exceptions.

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Chpt-3: Introduction to MSP430 Architecture 10.
Memory mapped Input and Output:
In MSP430, memory mapped input and output method is used. This
means that the ports are treated like memory registers called peripheral
register.

Each port is a byte access. These registers can be read, written and
modified just like a ram location. Even arithmetic operations are possible on
them.

For example, P1In can be read as a register to receive input through

port 1. Likewise, P1OUT can be used to write the value to the output port.

Clock generator:

All microcontrollers use a clock circuit to drive CPU and Peripherals. The
MSP430 provides a clock system for different clock sources. Different clock
signals are Master Clock (MCLK), Sub-system Main Clock (SMCLK) and
Auxilary Clock (ACLK).

1. Master Clock (MCLK): It is used by the CPU. It is generated by the

Digitally Controlled Oscillator (DCO).
2. Sub-system Main Clock (SMCLK): it is used as a clock source for high
speed peripherals. The Frequency will be in MHz.
3. Auxilary Clock (ACLK): It is used for the slow peripherals and also for
the Real Time Clock with self wake up function for low power modes
(37.768 MHz). This will always be fed by crystal oscillator. These are
four sources available for the clock.

 Low frequency crystal oscillator (LFXT1): It is usually used with

32.768 KHz.
 High frequency crystal oscillator (XT2): Some families of
MSP430 has a second crystal oscillator which provides the
frequency of 450KHz to 16MHz.

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Chpt-3: Introduction to MSP430 Architecture 11.
 Internal low frequency oscillator (Very Low frequency Oscillator-VLO):
It provides alternative to LFXT1 if the crystal oscillator accuracy
is not required.

Digitally Controlled Oscillator (DCO):

It is an Integrated RC oscillator which provides a controlled frequency.

VLO
Divide by
MUX 1/2/4/8 ACLK (slower peripherals)
IFxT1

XT2 MUX Divide by SMCLK (fast peripherals)

(if present) 1/2/4/8

DCO MUX Divide by MCLK ( To CPU)

1/2/4/8

3.8: Addressing modes:

The addressing modes are the ways in which the operands can be
specified. The MSP430 has 4 basic modes for the source only and only two for
the destination for the instructions with 2 operands.

There are 3 formats of instructions:

Format-1: Arithmetic and logical operations with 2 operands belong to this

groups of instructions.

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Chpt-3: Introduction to MSP430 Architecture 12.
Ex: ADD.W SRC,DST

Format-2: To control or to manipulate single operand instructions.

Jumps: This group of instructions allows the execution to jump to the

destination by adding the offset to the Program Counter (PC).

There are different addressing modes. They are:

1. Register mode: This addressing mode involves registers for both source
and destination.
Ex: MOV.W R5,R6
This copies a word from r5 to r6.
- The PC increments by 2 while this instruction is fetched.
- The constant generator CG2 reads a ‘0’ as a source.
- For the byte operations, the lower byte of the register takes the byte
and the higher byte is cleared.

2. Indexed mode: In this mode, the address is formed by adding a constant

base address value to the content of a CPU register. But the content of the
register is not changed. Indexed addressing is used for both the source and
destination.

Ex: MOV.W 3(R5),R6

Before: After:
R5=0x0210 R5=0x0210

R6=0x1111 R6=0x5555
LOC: 0x0213 0x5555 LOC: 0x0213 0x5555

0X0214 0x0214

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Chpt-3: Introduction to MSP430 Architecture 13.

The data is loaded from 3+(R5) memory location to register R6.

3. Symbolic mode (PC relative mode):

In this case, the offset constant is added to the base address from PC.
Normally, a symbolic label is used to represent a memory location and hence,
it is called as Symbolic mode.

Ex: MOV.W loopctr,R6

Here, a word is loaded from a location called loopctr to the register R6.
The above instruction is replaced by the assembler as: MOV.W X(PC),R6

4. Absolute mode:

In this addressing mode, the constant in the form of indexed addressing is

the absolute address of the data. Absolute addressing will have the prefix of
‘&’.

Absolute addressing is used for special function and peripheral registers

shown in the memory map. Ex: MOV.B &P1In, R6

In this instruction, Loads a byte from P1In into R6. The assembler treats this
like MOV.B P1In(SR),R6 Where SR=0, acts as a ‘0’ constant provider to serve
as constant generator CG1.

5. SP- relative mode:

In this addressing mode, the stack pointer is used as register as in indexed

mode. Ex: MOV.W 2(SP),R6

Copies a word from Stack to register R6.

Before: After:

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Chpt-3: Introduction to MSP430 Architecture 14.
SP= 0x0262 SP= 0x0262

Loc: 0x0264  0x4444 Loc: 0x0264  0x4444

R6=0x1111 R6=0x4444

6. Indirect Register mode:

This addressing mode is available for the source and the symbol ‘@’ is
used in front of a register.

Ex: MOV.W @R5,R6

Here, the register R5 holds the address and not the data. Therefore, R5
acts as a pointer. The above instruction loads the word from the location
pointed by R5 to the register R6.

Before: After:

R5= 0x0230 R5= 0x0230

Loc: 0x0230=0x4444 Loc: 0x0230=0x4444

R6=0x1111 R6=0x4444

7. Indirect auto increment register mode:

This addressing mode is available only for the source and it is represented
by ‘@’ in the front of a register and ‘+’ sign after that register. Here, the
register acts as a pointer which increments by 1 if it is a byte transfer. Or
increments by 2 if it is a word transfer.

Ex: MOV.W @R5+,R6

Before: After:

R5= 0x0260 R5= 0x0262

Loc: 0x0260=0x4444 Loc: 0x0260=0x4444

R6=0x1111 R6=0x444

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Chpt-3: Introduction to MSP430 Architecture 15.

8. Immediate mode:

This addressing mode is like an auto increment mode while PC is the

register which holds the address of the data. i.e, the PC acts as a pointer to
the data.

Ex: MOV.W @PC+, R6

MOV.W #100, R6
This instruction loads the word of data into R6 and the pc is automatically
gets incremented.

3.9: Constant Generators and Emulated Instructions:

Six commonly used constraints are generated by the register R2
and R3. The constraints are selected with the source register
addressing modes.
 By using R2:

i. In Absolute addressing mode, a constant ‘0’ is provided.

Ex: MOV.B P1In (SR),R6
ii. In register indirect addressing mode, ‘+4’ is provided.
Ex: MOV.B @SR,R6
iii. In register Indirect auto increment mode, ‘+8’ is provided.
Ex: MOV.B @ SR+,R6
 By using R3:

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Chpt-3: Introduction to MSP430 Architecture 16.
i. In Register addressing mode, a constant ‘0’ is provided.
Ex: MOV.W R3,R6
ii. In Indexed addressing mode, a constant ‘+1’ is provided.
Ex: MOV.W Cntr(R3),R6
iii. In Register indirect addressing mode, a constant ‘+2’ is
generated.
Ex: MOV.W@(R3),R6
iv. In Register auto increment mode, a constant ‘-1’ or ‘FFFF’ is
generated. Ex: MOV.W @(R3)+,R6

 Due to the constant generator, 24 emulated instructions are

added to 27 basic instructions of MSP430.
Ex: CLR DST instruction is emulated as MOV R3,DST
. Increment DST is emulated as ADD 0(R3),DST

3.10: Low Power Modes of MSP430.

MSP430 offers about 5 low-power operating modes out of which
2 low power modes are not much used.
- Active mode: in this mode, CPU, all clocks and modules are active
with current I ~~ 300uA. The MSP430 always starts with this
mode. An interrupt automatically switches the device to active
mode. The Vcc can be lowered to 1.8 V for FDCO=1MHz, giving
I~~100uA.
Here, CPUOFF=0, OSCOFF=0, SCG0=0, SCG1=0.

- Low Power Mode-0: Here, CPU and MCLK are disabled. ACLK and
SMCLK are active, with I~~85uA. This mode is used when the
CPU is not required but some modules require a fast clock from
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Chpt-3: Introduction to MSP430 Architecture 17.
SMCLK and the DCO.
Here, CPUOFF=1, OSCOFF=0, SCG0=1, SCG1=0.

- LPM-3: CPU, MCLK, SMCLK, and DCO are disabled. Only ACLK is
active with I~~1uA. This is standard low power mode when the
device must wakeup itself at regular intervals and hence, it needs
a slower clock. This is also required to maintain the Real Time
Clock (RTC). The current can be reduced to about 0.5uA by using
VLO instead of an external crystal.
Here, CPUOFF=1, OSCOFF=0, SCG0=1,SCG1=1

- LPM-4: CPU and all the clocks are disabled. I~~0.1uA. This device
can be wakened only by an external signal. This is also called
RAM retention mode.
Here, CPUOFF=1, OSCOFF=1, SCG0=1, SCG1=1.
3.11: Comparison of MSP430 with 8051 Architecture:

Features 8051 MSP430

CPU 8-bit data, 16-bit address. 16-bit data, 16-bit address.
Register sets 8-bit and 16-bit. Only 16-bit.
Addressing modes 5 7
Processor CISC RISC
Clock Fixed Variable MCLK, SMCLK, ACLK.
Instruction set 255 27 basic + 24 emulated
Interfacing General purpose interface. On-chip general purpose
devices.
Timers 2-3 Several.
Watch-dog No. Yes.
Power requirement 5V. 1.8V - 3.6V
Power dissipation 1.5 Watts 4.5mW
On-chip components Not available Available
ADC and DAC Externally interfaced ADC is available
On-chip wireless Not available Available
features
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Chpt-3: Introduction to MSP430 Architecture 18.
DMA Not available Available
Low power modes 2-modes 5-modes
Programming interface RS232 4-wire JTAG and Spy-Bi-wire
Cost High Low
3.12: Exceptions: Interrupts and Resets:
There are 3 exceptions:

i. Non-Maskable interrupts (NMI)

ii. Maskable interrupts
iii. System reset

1. Non-Maskable interrupts (NMI):

NMI are not masked by the General Interrupt Enable bit (GIE). When
NMI occurs, the program execution begins at the address stored in the NMI
vector 0x0FFFC.

The NMI can be generated by 3 sources.

a. An edge on the RST/NMI pin

b. An oscillator fault occurs.
c. An access violation to the flash memory.

 Reset/NMI pin: on power-up, reset/NMI pin is configured in the reset

mode. If this pin is set to the reset function, it remains in that state as long
as this pin is held low. After this pin is changed to a high state, the cpu
starts the program execution from the reset vector 0x0FFFE
.
 Flash access violation: NMI interrupt can be generated when flash access
violation occurs.

 Oscillator faults: This warns an error condition with the crystal oscillator.
The oscillator fault can be enabled to generate the NMI interrupt. A PUC
(Power up Clear) signal can trigger an oscillator fault. The PUC also
switches off the XT2 oscillator.

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Chpt-3: Introduction to MSP430 Architecture 19.

2. Maskable Interrupts:
Maskable interrupts are caused by the peripherals with interrupt
capability including the watch dog timer overflow in interval timer mode. Each
Maskable interrupt source can be individually disabled by an Interrupt Enable
bit or all Maskable Interrupts can be disabled by the General Interrupt Enable
bit (GIE) present in the status register.

3.13: Interrupt Processing

The interrupt latency is 5-cycles. The interrupt occurs in the following steps:

 Interrupt Acceptance:
1. The current instruction is executed.
2. The Program Counter content is saved.
3. The SR is pushed to stack.
4. Higher priority interrupt is selected and other lower priority
interrupts are kept pending.
5. The interrupt request flag resets while serving an interrupt source.
6. The SR is cleared to avoid low-power mode and GIE=0 to avoid
further interrupts.
7. The vector is loaded to the PC to drive the Program execution to
Interrupt Service Routine.

 Return from the Interrupt:

The Interrupt Service Routine ends with RETI instruction.

1. The SR content is pop back from the stack.

2. The PC pops the return address back from the stack to return to
the location from where it was interrupted.

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Chpt-3: Introduction to MSP430 Architecture 20.

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