AN1775

APPLICATION NOTE
STR71x Hardware Development
Getting Started

Introduction
This application note is intended for system designers who require a hardware implementation overview
of the development board features such as the power supply, the clock management, the reset control,
the boot mode settings and the debug management. It shows how to use the STR71x product family and
describes the minimum hardware resources required to develop an STR71x application.
Detailed reference design schematics are also contained in this document with descriptions of the main
components, interfaces and modes.

Rev 3
October 2005 1/27
www.st.com 27
 AN1775

Contents

1 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Power management block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Clock control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 USB clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.1 Hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Boot management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 ICE debug tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 JTAG / ICE connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.4 Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3 USB full speed interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4 CAN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.5 RS232 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.6 Serial ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.6.1 SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.6.2 I2C EEPROM: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.8 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2/27
AN1775

6.9 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.10 LCD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.11 Conclusions and recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3/27
1 Power management AN1775

1 Power management

1.1 Overview
The chip is powered by an external 3V3 supply(V33: 2.7 to 3.6 V, AVDD: 3.0 to 3.6 V).
All I/Os are 3V3-capable. An internal Voltage Regulator generates the supply voltage for core
logic (~=1.8V). The two V18 pins must be connected to external stabilization capacitors. The
following figure indicates the recommended configuration for the power supply pins:

Figure 1. STR71x power supply pins

3V3 STR71x
V33
V33IO-PLL

V18 VSSIO-PLL
33nF 10µF
VSS
VSSBKP
GND
GND

V18BKP
1µF

GND

1.2 Power management block

The following figure describes the power management block implemented on the STR71x
devices.

Figure 2. Power Management Block

3V3
3.3 V
I/O circuitry
V33
Main Voltage Low Power Voltage
Regulator (MVR) Regulator (LPVR)

V18 1.8 V
CORE
33nF 10µF

GND switch
V18BKP see note 1
1µF
Backup block

GND

The STR71x power management block has two regulators:

● The Main Voltage Regulator MVR.
● The Low Power Voltage Regulator LPVR.
Note the following remarks about the two regulators:
● Both regulators can be switched-off by software

4/27
AN1775 1 Power management

● V18 can be used to supply an externally regulated 1.8V, but V33 must supply the IOs
● V18BKP pin can be used to externally supply the backup logic, but V33 must supply the
IOs
● The switch in Figure 2, opened only during STANDBY mode, disconnects the V18 domain
from the V18BKP domain
It is possible to switch-off the MVR and keep LPVR on when the device is in low-power mode
(SLOW, WFI, LPWFI, STOP or STANDBY). The LPVR has a different design from the main VR
and generates a non-stabilized and non-thermally-compensated voltage of approximately 1.6V.
In STANDBY mode the Low Power VR can be switched off when an external regulator provides
a 1.8V supply to the chip through the V18BKP pin for use by RTC and Wake-Up block.
In this case we must to keep the 3.3V on pin V33 even if the two regulators are switch off to
keep stable state on the I/Os.
Remark:The PLL is automatically disabled (PLL off) when the MVR is switched off and the
maximum allowed operating frequency is 1 MHz. This is due to the limitation imposed by the
LPVR which is not able to generate sufficient current to operate in run mode.
The MAIN DEVICE CORE is powered from an external 3V3 power supply pin (V33) through the
main regulator.
For more details on the power regulators, refer to the STR71x Reference Manual.

5/27
2 Clock management AN1775

2 Clock management

The STR71x offers a flexible way for selecting core and peripherals clocks, the devices have up
to 3 external clock sources:
● The PRCCU generates the internal clocks for the CPU and for the on-chip peripherals.
The PRCCU may be driven by an external pulse generator, connected to the CK pin.
● The Real time Clock 32kHz oscillator is connected to the internal CK_AF signal (if present
on the application), and this clock source may be selected when low power operation is
required.
● USB clock source available only with devices with USB feature.

2.1 Clock control unit

The STR71x clock control unit must be driven by an external oscillator, connected to the CK
pin, at a frequency of up to 16 MHz. It generates the clocks for the CPU and for the on-chip
peripherals. A range of available multiplication and division factors allows for a large number of
operating clock frequencies to be driven from the input frequency. However, great care must be
taken to respect the recommendations for allowed frequency limits. For more details on allowed
operating frequencies for each clock, refer to the Reference Manual.
The following diagram shows the basic implementation of the main external clock.

Figure 3. Main clock oscillator

OSCILLATOR
STR71x

33
CK

10K
VSS
3V3 GND GND

The following table gives frequency range examples of the Main clock for some input clock
values:
Input Clock MCLK (Main Clock) Range

4 MHz [15625 Hz, 50 MHz]

8 MHz [31250 Hz, 50 MHz]
16 MHz [62500 Hz, 50MHz]

2.2 Real Time Clock

The Real Time Clock operates at a speed of 32 kHz. This clock must be provided by an
external resonator circuitry.
The RTC is used to generate a time base, and can be selected when low power operation is
needed. Refer to the Reference Manual for more details.

6/27
AN1775 2 Clock management

Figure 4. RTC oscillator

STR71x
32kHz CRYSTAL
RTCXTI
RTCXTO
15pF*
15pF*

VSS
GND GND
* these values are given only as examples, refer to the crystal manufacturer for more details

2.3 USB clock

STR710 and STR711 series microcontrollers contain a USB 2.0 Full Speed device module
interface that operates at a precise frequency of 48 MHz. This clock is usually provided by an
external oscillator connected to the USB clock pin USBCLK. However, to save the board’s
space and cost, the 48MHz USB clock can also be generated by the internal PLL2 using one
single external oscillator for both system and USB module.
This part of the application note describes the hardware and software reference
implementation. USB Full Speed signal quality and jitter results can be measured using a
single external oscillator to generate not only the System PLL clock and Peripheral’s clocks, but
also the 48MHz USB clock.

2.3.1 Hardware implementation

The hardware implementation guidelines are described in the figure below.

7/27
2 Clock management AN1775

Figure 5. USB clock and pins implementation

V33

47K

USB Indicate

56K
BC547E

56K GND
STR710/STR711

GND
GPIO
1K5 GND
Vbus
GPIO 0 Ohm
15pF
DP D+
USB connector

DM D-
15pF
0 Ohm VSS
GND
GND
V33
56K

USB CLK 48MHz Oscillator

GND

USB full speed interface device supported via type B connector. The USB clock uses a
separate 48 MHz oscillator.
Transistor circuit used to indicate the cable status (Cable connected USB/IND pin = 0 logic,
Cable deconnected = USB/IND pin = 1 logic).

8/27
AN1775 3 Reset management

3 Reset management

Both the Main Voltage Regulator and the Low Power Voltage Regulator contain an LVD.
They keep the device under reset when the corresponding controlled voltage value (V18 or
V18BKP falls below 1.35V±10%).
The LVDs do not monitor V33 which supplies the I/O and analog parts of the device.
Note: During power-on, a reset must be provided externally.
At power on, the nRSTIN pin must be held low by an external reset circuit until V33.
Figure 6 gives an example of the hardware implementation of the RESET circuit for STR71x
devices.
● The STM1001 low-power CMOS microprocessor supervisory circuit is used to assert a
reset signal whenever the V33 voltage falls below a preset threshold or a manual reset is
asserted.

Figure 6. Hardware reset implementation

+3V3 +3V3
STR71x
V33 +3V08 +3V3
STM1001T
2K2
1 not Reset VCC 2
nRSTIN
3
Reset_PB

GND
1nF

VSS GND

GND GND

* these values are given only as typical example

9/27
4 Boot management AN1775

4 Boot management

Three different boot modes are available and can be enabled by means of three input pins:
BOOTEN, BOOT0 and BOOT1.
The following table describes the different boot mode configurations.
BOOTEN BOOT0 BOOT1 BOOT Mode

0 x
1 0
1 1
1 0
1 1
x
USER: boot from internal FLASH memory
0
0 Reserved
1 RAM: boot from internal RAM memory
EXTMEM: boot from external memory mapped on the EMI interface
1
at 0000 0000h address.

The following figure gives an implementation example of boot management for STR71x
devices. BOOT0 and BOOT1 are alternate function pins used for boot configuration during the
RESET phase (floating-input configuration), so they can be used afterwards in the application
as standard I/Os. For more details concerning boot configuration, refer to the device reference
manual.

Figure 7. Boot mode selection implementation example

3V3 STR71x 3V3

10K*
BOOTEN 10K*
3V3
10K* nSTDBY
GND
BOOT0
3V3
GND 10K*
BOOT1 TEST
GND GND
* these values are given only as typical example

Note: 1 As the nSTDBY pin has a floating input configuration, an external pull-up has to be provided to
avoid remaining in stand-by mode.
2 The TEST pin of the STR71x must always be forced to ground (ST reserved test pin)

10/27
AN1775 5 Debug management

5 Debug management

The Host/Target interface is the hardware equipment that connects the Host to the application
board. This interface is made of three components: a hardware debug tool, such as Micro-ICE
from ARM, a JTAG connector and a cable connecting the host to the debug tool.
Figure 8 shows the connection of the host to the STR71x board.

Figure 8. Host to board connection

ICE Debug tool

ICE connector

HOST PC
Power
STR71x BOARD Supply

5.1 ICE debug tool

ICE Debug tool is a host interface that connects a PC to an STR71x development board
featuring a debug interface as shown in Figure 8. The Embedded ICE is an intelligent host
interface that provides fast access to host services, access to on-chip emulation and debug
facilities. When you are using the ST7R71x board as stand-alone system, the ICE Debug tool
can be used to download programs.
The STR71x development kit supports the ARM RealView ICE Micro Edition. The Micro-ICE is
plugged in to the host via a USB cable.

5.2 JTAG / ICE connector

The ICE connector enables JTAG hardware debugging equipment, such as RealView-ICE, to
be connected to the ST7R71x board. It is possible to both drive and sense the system-reset
line, and to drive JTAG reset to the core from the ICE connector. The Figure 9 shows the ARM
ICE connector pin-out.
The STR71x has a user debug interface. This interface contains a five-pin serial interface
conforming to JTAG, IEEE standard 1149.1-1993, “Standard Test Access Port-Scan Boundary
Architecture”. JTAG allows the ICE device to be plugged to the board and used to debug the
software running on the STR71x.
JTAG emulation allows the core to be started and stopped under control of the connected
debugger software. The user can then display and modify registers and memory contents, and
set break and watch points.

11/27
5 Debug management AN1775

Figure 9. Ice connector implementation

3V3 3V3 JTAG Connector CN9 3V3

CONN_2*10 RA_IDC
STR71x
(1) VTref (2)
nJTRST (3) nTRST (4)
JTDI (5) TDI (6)
JTMS (7) TMS (8)
JTCK (9) TCK (10)
(11) RTCK (12)
JTDO (13) TDO (14)
nRSTIN (15) nSRST (16)
DBGRQS (17) DBGRQ (18)
10K* 10K*
(19) DBGACK** (20)
See J4
GND GND 3V3 Note 1 J4
10K*
GND
GND
22K GND

TR1
BC846 50v
10K 10nF
TR2
BC846
47K

GND GND GND

* these values are given only as typical example

** The Debug acknowledge to JTAG equipment (DBGACK pin) is not used.

Note: 1 In order for JTAG and Chip Reset to be synchronized the J4 jumper must be fitted.
2 STR71x has a Debug Request (DBGRQS) pin, on 144-pin packages only. This active high
signal can be used to force the core to enter Debug Mode, giving the Emulation system access
to internal resources (code, registers, memory, etc). This pin must be kept LOW when
emulation is not being used.
The following table describes the JTAG connector pins:
Std Name STR71x Description Function

Test Reset This active LOW open-collector is used to reset the JTAG port
nTRST JTRST (from JTAG and the associated debug circuitry. It is asserted at power-up
equipment) by each module, and can be driven by the JTAG equipment.
Test data in TDI goes down the stack of modules to the motherboard and
TDI JTDI (from JTAG then back up the stack, labelled TDO, connecting to each
equipment) component in the scan chain.
Test mode
TMS controls transitions in the tap controller state machine.
select (from
TMS JTMS TMS connects to all JTAG components in the scan chain as
JTAG
the signal flows down the module stack.
equipment)
TCK synchronizes all JTAG transactions. TCK connects to all
JTAG components in the scan chain. Series termination
resistors are used to reduce reflections and maintain good
Test clock (from
signal integrity. TCK flows down the stack of modules and
TCK JTCK JTAG
connects to each JTAG component. However, if there is a
equipment)
device in the scan chain that synchronizes TCK to some other
clock, then all down-stream devices are connected to the
RTCK signal on that component.

12/27
AN1775 5 Debug management

Std Name STR71x Description Function

Some devices sample TCK (for example a synthesizable core

with only one clock), and this has the effect of delaying the
time that a component actually captures data. Using a
Return TCK (to
GND mechanism called adaptive clocking, the RTCK signal is
RTCK JTAG
(not used) equipment) returned by the core to the JTAG equipment, and the clock is
not advanced until the core had captured the data. In adaptive
clocking mode, the debugging equipment waits for an edge on
RTCK before changing TCK.
Test data out (to
TDO JTDO JTAG TDO is the return path of the data input signal TDI.
equipment)
nSRST is an active LOW open-collector signal that can be
driven by the JTAG equipment to reset the target board. Some
JTAG equipment senses this line to determine when a board
System reset
nSRST nRSTIN has been reset by the user.
(bidirectional)
When the signal is driven LOW by the reset controller on the
core module, the motherboard resets the whole system by
driving nSYSRST low.
DBGRQS Debug request
DBGRQ is a request for the processor core to enter debug
DBGRQ (not used (from JTAG
state.
w/ 64pin) equipment)
Debug
GND acknowledge DBGACK indicates to the debugger that the processor core
DBGACK
(not used) (to JTAG has entered debug mode.
equipment)

For more details on the JTAG port refer to the IEEE standard 1149.1-1993, “Standard Test
Access Port-Scan Boundary Architecture” specification.

13/27
6 Reference Design AN1775

6 Reference Design

6.1 Main
This reference design is based on the STR710FZ2T6, a highly integrated microcontroller,
running at 48 MHz that combines the popular ARM7TDMITM 32-bit RISC CPU with 256 Kbytes
of embedded flash, 64 Kbytes of high speed SRAM, and numerous on-chip peripherals.

6.1.1 Clock
● +3.3 V surface mounted 16 MHz oscillator provides the main clock source: S113, please
refer to Section 2.1 on page 6 for more details.
● RTC real-time clock for wakeup from standby mode with 32 KHz crystal: Y101, please
refer to Section 2.2 on page 6 for more details.

6.1.2 Reset
One push button S112 is used to generate a hardware reset, please refer to Section 3 on page
9 for more details.

6.1.3 Boot mode

Three switches S108, S109 and S110 are used to select the boot Mode, please refer to
Section 4 on page 10 for more details.

6.1.4 Wake-Up
S111 push button is used to exit from STANDBY mode (power supply voltage removed except
Real time Clock).
For more details, please refer to the STR71x reference manual.

6.2 Power supplies

Power to the board is supplied using a power supply providing 5 V DC to the board. All other
required voltages are provided by the on-board voltage regulator 3V3 LD1085V33 and Zener
Diode LM4040 for ADC input voltage.
For more details, refer to LD1085V33, LM4040 datasheets and Section 1 on page 4.

6.3 USB full speed interface

USB full speed interface device supported via type B connector. The USB clock uses a
separate 48 MHz oscillator.
A transistor circuit is used to indicate the cable status (Cable connected USB/IND pin = 0 logic,
Cable deconnected = USB/IND pin = 1 logic).

14/27
AN1775 6 Reference Design

6.4 CAN interface

A general purpose, asynchronous serial I/O data port connected through a 9-pin D-type male
connector with micro switches selectable between High or Low bus output S702, and between
Standby or Slope control S700.
For more details, refer to CAN transceiver SN65HVD230D datasheet.

6.5 RS232 serial interface

A general purpose, asynchronous serial I/O data ports is connected through 9-pin D-type male
connectors.
RS232 connects directly to UART0, transmit and receive only (null modem).
RTS is shorted to CTS and DTR is shorted to DSR at the connector.
For more details, refer to RS232 transceiver ST3232 datasheet.

6.6 Serial ROM

6.6.1 SPI Flash

1-Mbit SPI serial flash connected to the buffered serial peripheral interface (BSPI). Switch S603
is used to enable or disable write protect (pull down = Write protect, pull up = Write enabled).
For more details, refer to SPI Flash M25P10-A datasheet.

6.6.2 I2C EEPROM:

8-kbit EEPROM connected to the I2C0 interface, Switch S600 is used to enable or disable write
protect (pull down = Write protect, pull up = Write enabled).
For more details, refer to I2C Eeprom M24C08 datasheet.
The values R614 and R616 are dependent on the I2C communication speed.
For more details on theses values, please refer to the STR71x reference manual.

6.7 JTAG interface

Refer to the section Section 5 on page 11.

6.8 SRAM
Two SRAM 2M byte are connected to External Interface Memoy EMI and mapped from 0x6200
0000 to 0x623F FFFF.
For more details, refer to the SRAM memory TC55V8200FT-12 datasheet.

15/27
6 Reference Design AN1775

6.9 Flash
One Flash 2M word is connect to External Interface Memoy EMI and mapped from 0x6000
0000 to 0x603F FFFF (boot bank).
For more details, refer toFlash memory M28W320ECB datasheet.

6.10 LCD interface

LCd 2 * 16 is connected to external interface memory EMI.
Address 2 A2 is used as the LCD register address signal.
Region space available from 0x6400 0000 to 0x65FF FFFF

6.11 Conclusions and recommendations

● System clock jitter values decrease when the system clock is delivered by STR71x internal
PLL1 (comparing to the jitter values on the external oscillator inputs), because the noise
injected in the CLK pin input was filtered by the internal PLL.
● It is possible to use one single external 4MHz oscillator to generate both core, peripheral’s
clocks and 48MHz USB clock to minimize and save board cost and space.
● With this single external oscillator generating both the system clock using PLL1 and the
48Mhz USB clock using PLL2, the STR710/STR711 has all the characteristics to pass the
requirements for USB revision 2.0 full speed device test and get the USB certification.
Particular care must be taken to decrease external oscillator noise while routing its clock on
board.

16/27
 7
AN1775

1 2 3 4 5 6
+3V3 C102
+3V3
+3V3 +3V3
10uF 33nF
S111 R129 C101 C103 R130
BOOT_EN R100 10K +3V3 2K2
10K SW SPDT SW-PB D105
S108 C100 +3V3AN 1.0uF STM1001T (3.08V)
BOOT.0 R101 R127
SW SPDT 1K not RESET 1 2
10K

47
51
6
22
40
83
104
113
138
66
58
59
129
128
55
54
S109 not RESET VCC
D 10nF R128 D
BOOT.1 R102 STR710
SW SPDT S112

VSS
10K
S110 SW-PB C104
JTAG.Sch 1nF

V33_1
V33_2
V33_3
V33_4
V33_5
V33_6
V33_7
V18_1
V18_2

AVDD
V18BKP
VSSBKP
3

VSS18_1
VSS18_2

not STDBY
30 +3V3
JTDI JTDI
33
JTDO JTDO

P0.15_WAKEUP
32
JTCK JTCK
R122 7 31
22 P2.0_not CS.0 JTMS JTMS
R103 8 34 R131
22 P2.1_not CS.1 not JTRST not JTRST
R104 11 52 not RESET S113 10K
22 P2.2_not CS.2 not RSTIN not Reset
Schematics

12 16MHz OSC
P2.3_not CS.3
46 CK
CK R132
ADD0 98 45 CKOUT DBGRQS CK 3 1
A.0 CKOUT DBGRQS OUT EN
ADD1 99 33
A.1
ADD2 100 50 RTCXTO page 8
A.2 RTCXTO
SRAM.Sch FLASH.Sch ADD4 101 49 RTCXTI CAN.Sch VCC +3V3
A.3 RTCXTI
ADD5 102
A.4
ADD6 114 16 BOOT_EN
ADD (23:0) ADD (23:0) A.5 BOOT_EN CAN_RX
ADD7 115 144 BOOT.0 RTCXTI
A.6 P0.9_U0.TX_BOOT.0 CAN_TX
ADD8 116 3 BOOT.1
DATA (15:0) DATA (15:0) A.7 P0.11_U1.TX_BOOT.1
ADD9 117 page 7 Y101
A.8
ADD10 118 88 RTCXTO
C A.9 P1.11_CANRX C
ADD11 119 89
not CS_SRAM not CS_FLASH A.10 P1.12_CANTX
ADD12 120 USB.Sch 32KHz
not OE not OE A.11 C106 C113
ADD13 121 90
not WR0 not WR A.12 USBDP USBDP 15pF 50V 15pF 50V
ADD14 122 91
not WR1 vpp A.13 USBDN USBDN
ADD15 130 106
not RESET A.14 P1.10_USBCLK USBCLK
page 4 ADD16 131 25
A.15 P2.11 USBV_IND
page 3 ADD17 132 26
A.16 P2.12 USB_PULL_UP
ADD18 133 Serial_ROM.Sch
A.17
ADD19 134 108 page 9
A.18 P1.14_HRXD_I0.SDA SDA
ADD20 135 107

not Reset
A.19 P1.13_HCLK_I0.SCL SCL
ADD21 13 127 *Switch used for ADC calibration +2V5AN
P2.4_A.20 P0.4_S1.MISO MISO
ADD22 14 140
P2.5_A.21 P0.5_S1.MOSI MOSI S115
ADD23 15 141
P2.6_A.22 P0.6_S1.SCLK SCLK
LCD.Sch ADD24 17 142
P2.7_A.23 P0.7_S1.SSN SSN
86
P1.8 not S
DATA (7:0) SW SPDT
DATA0 61 9 RX page 6 S114 R139
D.0 P0.13_U2.RX_T2.OCMPA 4K7
DATA1 62 10 TX ADCIN
notE D.1 P0.14_U2.TX_T2.ICAPA
DATA2 63 RS232.Sch
D.2
DATA3 64 71 ADCIN RX
U101A D.3 P1.0_T3.OCMPB_AIN.0 RX
ADD2 DATA4 65 TX
RS D.4 TX
DATA5 78 123 LED_P0.0
D.5 P0.0_S0.MISO_U3.TX
2 1 DATA6 79 124 LED_P0.1 page 5
R/W D.6 P0.1_S0.MOSI_U3.RX
B DATA7 80 125 LED_P0.2 B
D.7 P0.2_S0.SCLK_I1.SCL
DATA8 81 126 LED_P0.3
D.8 P0.3_S0.SSN_I1.SDA
74LCX14 DATA9 82
Figure 10. Reference design top level schematics

D.9
VCC +3V3 DATA10 92 23 Button_1
D.10 P2.9
page 2 DATA11 93 24 Button_2
D.11 P2.10
DATA12 94
D.12
DATA13 95 73 +3V3 +3V3
D.13 P1.2_T3.OCMPA_AIN.2
DATA14 96 72
D.14 P1.1_T3.ICAPA_AIN.1
DATA15 97 74 D106
D.15 P1.3_T3.ICAPB_AIN.3 R135 LED
75 LED_P0.0
P1.4_T1.ICAPA R137 R138
R133 2 76
22 not RD P1.5_T1.ICAPB 560
R134 137 77 D107 10K 10K
22 not WE.0 P1.6_T1.OCMPB R136
R140 136 85 LED_P0.1 LED
22 not WE.1 P1.7_T1.OCMPA
105 560
P1.9
18 111 D108 Button_1 Button_2
P2.8 P1.15_HTXD R141 LED
143 LED_P0.2
P0.8_U0.RX_U0.TX
1 560
P0.10_U1.RX_U1.TX_SCDATA
4 D109 S116 S117
P0.12_SCCLK R142 LED C114 C115
38 27 LED_P0.3 SW-PB SW-PB
TEST P2.13 0.1uF 0.1uF
36 28 560
TEST P2.14
35 29
NU P2.15
DBGRQS 44
DBGRQS

A A

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
AVSS

Title
STR710 MCU
5

42
84
21
67

103
112
139

Size Number Revision

1 1.0
* For not used pins set to logic level by software B
Date: 22-Jun-2005 Sheet 1 of 10
File: Drawn By:
1 2 3 4 5 6

17/27
7 Schematics
18/27
1 2 3 4 5 6
7 Schematics

D D

+5

R200
4K7
Figure 11. LCD interface

R201 R202
DATA (7:0)
DATA0 18 2 7
B1 A1 DB0
DATA1 17 3 8 15
B2 A2 DB1 A
DATA2 16 4 9
B3 A3 DB2
DATA3 15 5 10
C B4 A4 DB3 C
DATA4 14 6 11 16
B5 A5 DB4 K
DATA5 13 7 12
B6 A6 DB5
DATA6 12 8 13
B7 A7 DB6
DATA7 11 9 14
B8 A8 DB7
+5
2
VCC5V
1 5
DIR R/W
19 6 1
G E GND C203
4
RS C204
3
VO 10uF 16V 0.1uF
74LCX245
VCC +3V3
LCD LWM 1602 B-BG/SYN
RnotW R203
U200A 10K

1 2
notE

74LCX14
VCC +3V3
R209
B RS B
1K
C205
100pF

A A

Title
LCD
Size Number Revision 1.0
2
B
Date: 22-Jun-2005 Sheet 2 of 10
File: Drawn By:
1 2 3 4 5 6
AN1775
 AN1775

1 2 3 4 5 6

D D
Figure 12. EMI Flash

DATA (15:0)

ADD (23:0)
R305

ADD1 25 A0
ADD2 24 29 DATA0
C A1 DQ0 C
ADD3 23 31 DATA1
A2 DQ1
ADD4 22 33 DATA2
A3 DQ2
ADD5 21 35 DATA3
A4 DQ3
ADD6 20 38 DATA4
A5 DQ4
ADD7 19 40 DATA5
A6 DQ5
ADD8 18 42 DATA6
A7 DQ6
ADD9 8 44 DATA7
A8 DQ7
ADD10 7 30 DATA8
A9 DQ8
ADD11 6 32 DATA9
A10 DQ9
ADD12 5 34 DATA10
A11 DQ10
+3V3 +3V3 ADD13 4 36 DATA11
A12 DQ11
ADD14 3 39 DATA12
A13 DQ12
ADD15 2 41 DATA13 +3V3
A14 DQ13
ADD16 1 43 DATA14
R306 R307 A15 DQ14
ADD17 48 45 DATA15
10K 10K A16 DQ15
ADD18 17
A17 R308
ADD19 16
A18 10K
ADD20 15
A19
ADD21 10
A20
26
not CS_FLASH not CE
11 13
not WR not WE VPP vpp
28
not OE not OE
B B
14
not WP
12
not RESET not RP

FLASH M28W320ECB
VCC +3V3

A A

Title
FLASH
Size Number 3 Revision Text
B
Date: 22-Jun-2005 Sheet 3 of 10
File: Drawn By:
1 2 3 4 5 6

19/27
7 Schematics
20/27
1 2 3 4 5 6
7 Schematics

D D
Figure 13. EMI SRAM

DATA (15:0)

ADD (23:0)

R401 R402

ADD1 11 A0 ADD1 11 A0
ADD2 10 22 DATA0 ADD2 10 22 DATA8
A1 IO_1 A1 IO_1
ADD3 9 24 DATA1 ADD3 9 24 DATA9
C A2 IO_2 A2 IO_2 C
ADD4 8 31 DATA2 ADD4 8 31 DATA10
ADD5 7 A3 IO_3 33 DATA3 ADD5 7 A3 IO_3 33 DATA11
A4 IO_4 A4 IO_4
ADD6 48 49 DATA4 ADD6 48 49 DATA12
A5 IO_5 A5 IO_5
ADD7 47 51 DATA5 ADD7 47 51 DATA13
A6 IO_6 A6 IO_6
ADD8 46 4 DATA6 ADD8 46 4 DATA14
A7 IO_7 A7 IO_7
ADD9 45 6 DATA7 ADD9 45 6 DATA15
A8 IO_8 A8 IO_8
ADD10 44 ADD10 44
ADD11 38 A9 ADD11 38 A9
A10 A10
ADD12 37 ADD12 37
A11 A11
ADD13 36 ADD13 36
A12 A12
+3V3 +3V3 ADD14 35 A13 ADD14 35 A13
ADD15 34 +3V3 ADD15 34
A14 A14
ADD16 21 ADD16 21
A15 A15
ADD17 20
A16
ADD17 20 A16
R403 R404 ADD18 19 ADD18 19
10K 10K A17 R405 A17
ADD19 18 ADD19 18
A18 10K A18
ADD20 17 A19 ADD20 17 A19
ADD21 39 ADD21 39
A20 A20
15 15
not WR0 13 not WE not WR1 13 not WE
not CS_SRAM not CE not CE
16 16
42 N_CE2 42 N_CE2
not OE not OE not OE
B B
SRAM TC55V8200FT-12 SRAM TC55V8200FT-12
VCC +3V3 VCC +3V3

A A

Title
SRAM
Size Number 4 Revision 1.0
B
Date: 22-Jun-2005
10 Sheet 4 of 10
File: Drawn By:
1 2 3 4 5 6
AN1775
 AN1775

1 2 3 4 5 6

D D

+3V3
Figure 14. RS232 interface

C501 C502
0.1uF 25V 0.1uF 25V

6
2
C C

V-
V+
1 4
C1+ C2+
C500 C503 J500
0.1uF 25V 0.1uF 25V 1
3 5 6
C1- C2- 2
7
11 14 3
TX T1IN T1OUT
10 T2IN T2OUT 7 8
12 13 4
RX R1OUT R1IN
9 8 9
R2OUT R2IN
5

R510 DB9 male

ST3232
VCC +3V3

B B

A A

Title
RS232
Size Number 5 Revision 1.0
B
Date: 22-Jun-2005 Sheet 5 of 10
File: Drawn By:
1 2 3 4 5 6

21/27
7 Schematics
22/27
1 2 3 4 5 6
7 Schematics

D D

+3V3 +3V3 +3V3

+3V3
+3V3 R600 R601 R602
+3V3 10K 10K 10K

R603 R614
R616 4K7
R615 4K7 1
10K 2 E1
E2
3 E3
SDA 5
6 SDA
S600 SCL SCL
7 not WC
SW SPDT
I2C_EEP
ROM M24C08
C * connect to pull-up by default VCC +3V3 C
Figure 15. Serial ROM interface

+3V3
+3V3

R617 R619
10K R618
10K 5 2
MOSI D Q MISO

SCLK 6 C
S603 1
B not S not S B
3
7 not W
SW SPDT not HOLD

* connect to pull-up by default SPI_FLAS

H M25P10-A
VCC +3V3

+3V3

R620
10K

SSN

A A
Title
SERIAL MEMORY
Size Number 6 Revision 1.0
B
Date: 22-Jun-2005 Sheet 6 of 10
File: Drawn By:
1 2 3 4 5 6
AN1775
 AN1775

1 2 3 4 5 6

D D

+3V3
Figure 16. CAN interface

+3V3
R701
10K
SW SPDT
R703
+3V3 S700 10K
C C

J701
R700 1
6
CAN_TX 1 D RS 8 2
2 GND CANH 7 7
3 VCC CANL 6 3
CAN_RX 4 R Vref 5 8
4
9
SN65HVD230D R702 5
VCC +3V3 10K
R704 DB9
120

S702
SW-SPST
B B

A A
Title
CAN
Size Number 7 Revision 1.0
B
Date: 22-Jun-2005 Sheet 7 of 10
File: Drawn By:
1 2 3 4 5 6

23/27
7 Schematics
24/27
1 2 3 4 5 6
7 Schematics

D D

+3V3

+3V3
R800 R801 R802
10K 10K 10K

JP801
1 2
Figure 17. JTAG interface

not JTRst 3 4
JTDI 5 6
JTMS 7 8
JTCK 9 10
11 12
JTDO 13 14
C 15 16 C
DBGRQS 17 18
19 20
R804 HEADER 10X2
10K R803
10K R805
10K

*Switch closed by default

not Reset
+3V3 S801
SW SPST

R817
22K
B B

R818 C800
0.01uF
R807 10K
Q803
Q800 BC846
47K
BC846

A A

Title
JTAG
Size Number 8 Revision 1.0
B
Date: 13-Sep-2005 Sheet 8 of 10
File: Drawn By:
1 2 3 4 5 6
AN1775
 AN1775

1 2 3 4 5 6

D D

+3V3

R900
47K

USBV_IND

R905 Q900
BC547E
Figure 18. USB interface

56K
R904
56K

USB_PULL_UP
C C
R901
1K5

R906
USB_CON
1 VBUS
USBDN R902 0 2 DN
USBDP R903 0 3 DP
4 GND
C900 C901
15pF 15pF

+3V3
B B
R907
10K
J900
OS
48MHz C

USBCLK 3 OUT EN 1
VCC +3V3

A A
Title
USB
Size Number9 1.0
Revision
B
Date: 22-Jun-2005 Sheet 9 of 10
File: Drawn By:
1 2 3 4 5 6

25/27
7 Schematics
26/27
1 2 3 4 5 6
7 Schematics

+5V +3V3AN +2V5AN

D R1000 +3V3 D
J1000
2 +5V 1 SV CV 3
L1001 R1001
1
C1000 C1001 C1002 C1003 C1004 FBEAD 1K
JACK +5V CG1 4
5 47uF 16V 100nF 25V 100nF 25V 100nF 25V 100nF 25V
2 CG2 6 C1045 D1002
SG CG3 C1046 C1047 LM4040
10uF 16V 0.1uF 25V 10nF 50v
BNX002

+5V +3V3
U1001
VOLT_REG_3V3
1 Vin Vout 3

GND
Figure 19. Power schematics

C1011 C1014 C1018 C1020

10uF 10V 10nF 50V 10uF 10V 10nF 50V
C C

2
+3V3
+5V +3V3

C1012 C1013 C1015 C1016 C1017 C1019 C1021 C1022 C1023

10uF 10V 10uF 10V 100uF 10V 100uF 10V 10nF 50V 10nF 50V 100nF 25v 100nF 25V 100nF 25v
R1002 R1003
1K 560

+3V3
D1000 D1001
LED LED

B C1024 C1026 C1028 C1030 C1032 C1034 C1036 C1038 C1040 C1042 C1044 B
100nF 25V 100nF 25V 100nF 25V 100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V 100nF 25V

+3V3

C1025 C1027 C1029 C1031 C1033 C1035 C1037 C1039 C1041 C1043
100nF 25V 100nF 25V 100nF 25V 100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V

A A
Title
POWER
Size Number 10 Revision 1.0
B
Date: 22-Jun-2005 Sheet 10 of 10
File: Drawn By:
1 2 3 4 5 6
AN1775
AN1775 7 Schematics

“THE PRESENT NOTE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A
RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
SUCH A NOTE AND/OR THE USE MADE BY CUSTOMERS OF THE INFORMATION CONTAINED
HEREIN IN CONNECTION WITH THEIR PRODUCTS.”

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

© 2005 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com

27/27