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BSNL Tta (Je) Microprocessors 200 MCQ
BSNL Tta (Je) Microprocessors 200 MCQ
4) The 8085 microprocessor will enter into INA cycle after recognition of
A [ ]) any interrupt
B [ ]) TRAP only
C [v]) INTR only
D [ ]) RST 7.5,RST 6.5 & RST 5.5 only
7) In order to reset the carry without affecting the accumulator content one has to use,
A [ ]) SUB A
B [ ]) XRA A
C [v]) ORA A
D [ ]) CMC
10) The 8085 microprocessor enters into bus idle machine cycle whenever
A [ ]) INTR interrupt is recognized
B [v]) RST 7.5 is recognized
C [ ]) DAD RP instruction is executed
D [ ]) none of the above
14) The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port
address” instruction are
A [v]) same as the content of A7-A0
B [ ]) irrelevant
C [ ]) all bits reset (i.e. 00H)
D [ ]) all bits set (i.e. FFH)
15) Which one of the following ICs is used to interface keyboard and display?
A [ ]) 8251
B [v]) 8279
C [ ]) 8259
D [ ]) 8253
17) Which one of the following instruction may be used to clear the accumulator content
irrespective of its initial value?
A [ ]) CLR A
B [ ]) ORA A
C [v]) SUB A
D [ ]) MOV A, 00H
23) A single instruction to clear the lower nibble of accumulator in 8085 language
assembly is
A [ ]) XRI 0FH
B [v]) ANI F0H
C [ ]) XRI FOH
D [ ]) ANI OFH
25) A sequence of two registers that multiplies the content of DE register pair by two and
stores the result in HL register pair (in 8085 assembly language) is
A [ ]) XCHG & DAD B
B [ ]) XTHL & DAD H
C [ ]) PCHL & DAD D
D [v]) XCHG & DAD H
30) The maximum number of seven segment displays that can be connected to 8279 is
A [ ]) 12
B [ ]) 16
C [v]) 18
D [ ]) 8
31) Using one 8259 IC is equivalent to providing BBBB. INTR pins on 8085
A [ ]) 16
B [ ]) 12
C [v]) 8
D [ ]) 18
35) The frequency of the driving network connected between pins 1 and 2 of 8085
microprocessor is
A [v]) twice the desired frequency
B [ ]) equal to the desired frequency
C [ ]) four times the desired frequency
D [ ]) none of the above
37) READY signal in 8085 is useful when the CPU communicates with
46) How many T-states are required for execution of OUT 80H instruction?
A [v]) 10
B [ ]) 13
C [ ]) 16
D [ ]) 7
47) How many machine cycles are required for execution of IN 30H instruction
A [v]) 3
B [ ]) 4
51) Which instruction is required to rotate the content of accumulator one bit right along
with carry?
A [ ]) RLC
B [ ]) RAL
C [ ]) RRC
D [v]) RAR
54) The ________ ensures that only one IC is active at a time to avoid a bus conflict caused
by two ICs writing different data to the same bus.
A [ ]) control bus
B [ ]) control instructions
C [v]) address decoder
D [ ]) CPU
56) The technique of assigning a memory address to each I/O device in the computer
system is called
A [v]) memory-mapped I/O
B [ ]) ported I/O
C [ ]) dedicated I/O
D [ ]) wired I/O
57) What type of circuit is used at the interface point of an output port?
A [ ]) decoder
B [v]) latch
C [ ]) tristate buffer
D [ ]) none of the above
59) What type of circuit is used at the interface point of an input port?
A [ ]) decoder
B [ ]) latch
C [v]) tristate buffer
D [ ]) none of the above
61) Because microprocessor CPUs do not understand mnemonics as they are, they have to
be converted to _______
A [ ]) hexadecimal machine code
B [v]) binary machine code
C [ ]) assembly language
D [ ]) all of the above
62) A register in the microprocessor that keeps track of the answer or results of any
arithmetic or logic operation is the
A [ ]) stack pointer
B [ ]) program counter
C [ ]) instruction pointer
D [v]) accumulator
63) What is the difference between a mnemonic code and machine code?
64) Which of the following buses is primarily used to carry signals that direct other ICs to
find out what type of operation is being performed?
A [ ]) data bus
B [v]) control bus
C [ ]) address bus
D [ ]) address decoder bus
65) What kind of computer program is used to convert mnemonic code to machine code?
A [ ]) debug
B [v]) assembler
C [ ]) C++
D [ ]) Fortran
66) Which of the following are the three basic sections of a microprocessor unit?
A [ ]) operand, register, and arithmetic/logic unit (ALU)
B [v]) control and timing, register, and arithmetic/logic unit (ALU)
C [ ]) control and timing, register, and memory
D [ ]) arithmetic/logic unit (ALU), memory, and input/output
73) Assertion (A): Microprocessor 8085 can address 65536 memory locations.
Reason (R): Microprocessor 8085 has 16 address lines.
A [v]) Both A and R are correct and R is correct explanation of A
B [ ]) Both A and R are correct but R is not correct explanation of A
C [ ]) A is correct R is wrong
D [ ]) A is wrong R is correct
78) Which of the following is not treated as hexadecimal constant by assembler in 8085?
A [ ]) 64 H
B [ ]) 5 AFH
C [v]) AFH
D [ ]) OCFH
79) In 8085, which instructions are useful for writing and using subroutines?
82) Which of the following instruction modes does not exist in microprocessor 8085?
A [v]) instrict
B [ ]) Register
C [ ]) Immediate
D [ ]) Implied/implicit/Inherent
83) Read the following statements as regards register pairs in microprocessor 8085
1.B represents B, C pair with B as high order register and C as low order register.
2.D represents D, E pair with D as high order register and E as low order register.
3. H represents H, L pair with H as high order register and L as low order register.
Which of the above statements are correct?
A [v]) All
B [ ]) 1 and 3
C [ ]) 1 and 2
D [ ]) 2 and 3 only
88) System bus is the communication channel between microprocessor and peripherals.
A (V) TRUE
B ( ) FALSE
89) Assertion (A): In 8085 WR and RD signals are active high.
Reason (R): LOW WR means write operation and low RD means read operation.
A [ ]) Both A and R are correct and R is correct explanation of A
B [ ]) Both A and R are correct but R is not correct explanation of A
C [v]) A is wrong R is correct
92) In 8085
A [v]) the upper 8 address bits appear on address bus and lower 8 bits on address data bus
B [ ]) the lower 8 address bits appear on address bus and the upper 8 address bits appear on
address data bus
C [ ]) either upper or lower 8 address bits may appear at address bus
93) Which of the following methods does not cause any reduction in instruction length?
A [ ]) Using program counter
B [ ]) Common source and destination address
C [ ]) Implicit source and destination address
D [v]) Machine language programming
96) In a microprocessor
A [ ]) one machine cycle is equal to one clock cycle
B [ ]) one clock cycle consists of several machine cycles
C [v]) one machine cycle consists of several clock cycles
D [ ]) one machine cycle is always less than one clock cycle
97) Which addressing mode is suitable only for these instructions in which there is only
one operand?
A [v]) Implicit
B [ ]) Register
C [ ]) Direct
D [ ]) Immediate
98) In 8085 microprocessor with memory mapped I/O which of the following is true?
A [v]) I/O devices have 16 bit addresses
B [ ]) I/O devices are accessed during IN and OUT instructions
C [ ]) There can be a maximum of 256 input and 256 output devices
D [ ]) Logic operations can not be performed
107) When a peripheral device is not ready for data transfer it will send to the
microprocessor a
A [v]) low READY bit
B [ ]) high READY bit
C [ ]) low or high READY bit depending on whether input or output is activated
D [ ]) none of the above
118) In 8086 the number of lines on which data and address is multiplexed is
A [ ]) 8
B [ ]) 16
C [v]) 20
D [ ]) 32