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LOGIC
GATE
Juan Carlos Martinez Santos
Chapter
3
Basic
Logic
Gates
Input Output
A X
0 1
1 0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
A X
The Inverter
Example waveforms:
A
X
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A A
X & X
The AND Gate B
B
The AND gate produces a HIGH output when all inputs are
HIGH; otherwise, the output is LOW. For a 2-input gate,
the truth table is Inputs Output
A B X
0 0 0
0 1 0
1 0 0
1 1 1
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A A
X & X
The AND Gate B
B
Example waveforms:
A
B
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The AND Gate
A Multisim circuit is shown. XWG1 is a word generator set in
the count down mode. XLA1 is a logic analyzer with the
output of the AND gate connected to first (upper) line of the
analyzer. What signal do you expect to on this line?
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
A X A ≥1 X
The OR Gate
B B
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
A X A ≥1 X
The OR Gate
B B
Example waveforms:
A
B
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The OR Gate
A Multisim circuit is shown. XWG1 is a word generator set
to count down. XLA1 is a logic analyzer with the output
connected to first (top) line of the analyzer. The three 2-input OR gates act
as a single 4-input gate. What signal do you expect on the output line?
The output (line 1) will be
HIGH if any input is HIGH;
otherwise it will be LOW.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
A X A & X
The NAND Gate
B B
The NAND gate produces a LOW output when all inputs
are HIGH; otherwise, the output is HIGH. For a 2-input
gate, the truth table is Inputs Output
A B X
0 0 1
0 1 1
1 0 1
1 1 0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
A X A & X
The NAND Gate
B B
Example waveforms:
A
B
X
The NAND gate is particularly useful because it is a
“universal” gate – all other basic gates can be constructed
from NAND gates.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The NAND Gate
A Multisim circuit is shown. XWG1 is a word generator set in
the count up mode. A four-channel oscilloscope monitors the
inputs and output. What output signal do you expect to see?
Inputs
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
A X A ≥1 X
The NOR Gate
B B
Example waveforms:
A
B
X
The NOR operation will produce a LOW if any input is HIGH.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Enable/Disable Using AND Gate
14
Enable/Disable Using OR Gate
15
Integrated Circuits
Pins
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Integrated Circuits
Pin 1
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Integrated Circuits
Chip Densities:
• Small scale integration (SSI): <=10 gates per chip.
• Medium-scale integration (MSI): 10 to 100 gates per
chip.
• Large-scale integration (LSI): 100 to 10,000 gates per
chip.
• Very large-scale integration (VLSI): 10,000 to 100,000
gates per chip.
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Programmable Logic
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Figure 3.50 Pin configuration diagrams for
some common gate configurations.
Website
for
Datasheets
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Multisim Troubleshooting
• Multisim lets you insert the following kinds of faults into
digital components:
• An open pin