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In this presenta-on, you will learn the fundamentals of -ming analysis including the
calcula-ons and terminology used by the TimeQuest Timing Analyzer.

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Here’s what we will cover in this video:
1. Fundamentals of Timing Analysis
2. Timing Hazards and how to avoid them
3. Timing Analysis Terminology and Calcula-ons
4. Using TimeQuest to do -ming Analysis

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Clocks are fundamental to modern digital electronics. They provide synchroniza-on
which is necessary for error-free data transfer.
As data on a digital line transi-ons from one value to another, during the transi-on
-me the data value will be incorrect. We need to wait un-l the data is stable before
using it. The synchronizing signal is the clock.

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Data must be stable before and aMer the clock edge to be reliably transferred. If not
properly synchronized, there will be a host of design issues like:

§  Hazards – which are unexpected or undesired signals; like in golf, you just don’t
want to go there.
§  Metastability – a condi-on caused by -ming viola-ons in flip-flop outputs leading to
erroneous data.
§  Race Condi-ons – which lead to viola-ons that occur depending on opera-ng
condi-ons, bugs that come and go, a primary cause of gray hair in engineers.
§  Clock Skew – another unexpected source of viola-ons

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 Sta-c Hazards occur as the consequence of unequal delays in logic. This diagram
shows the use of a Karnaugh Map or K-map to minimize the logic for a par-cular logic
func-on. Can you tell where there might be a problem with this circuit because of
path delays?

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 Analysis of the circuit using a -ming diagram reveals the genera-on of a runt pulse,
during which -me the output of the logic circuit does not match what is expected
from the logic equa-on. If B and C are always a one, we would expect F to always be
a one. It’s not because of the delays present.

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 One way to remove the hazard is through addi-onal logic as shown here, with the
addi-on of another AND gate. However, a be_er method is the use of flip-flops and
synchronous design, which allows data transfer only on a clock edge when the data is
correct and stable.

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 Here is the fundamental synchronous circuit that sta-c -ming analyzers can analyze.
ClockA and ClockB may have a common source, but the path delays may be different,
par-cularly in FPGAs where rou-ng can be changed.

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 We need to have some common terminology when we talk about -ming analysis. A
Launch Edge is the clock that ac-vates the source register in a register-to-register
path. A Latch Edge is the clock edge that ac-vates the des-na-on register and
captures the data.

TimeQuest measures performance by analyzing delays between -ming path launch
and latch edges.

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 Setup Time = The minimum -me the data signal must be stable BEFORE the clock
edge
Hold Time = The minimum -me the data signal must be stable aMer the clock edge
If these minimum -mes are not met, we have a setup or hold viola-on, which will
lead to possible data errors or metastability of the flip-flop register.
Together, the setup -me and the hold -me form a Data Required Window, the -me
around a clock edge in which data must be stable.

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 Data Arrival Time = the -me for data to arrive at a des-na-on register’s D input from
the common clock edge.
Data Arrival Time = Launch edge + TclkA + Tco + Tdata
The general concept is to compare the -me when the data arrives with the -me the
clock arrives, to see if there is a setup or hold viola-on.

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 Clock Arrival Time = the -me for data to arrive at a des-na-on register’s clock input
from the common clock edge.
Clock Arrival Time = Latch edge + TclkB
Do you think the delay in the clock path helps or hurts – can it cause a viola-on of
-ming requirements?

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 Data Required Time (Setup) = the minimum -me required for the data to get latched
into the des-na-on register.
Data Required Time (Setup) = Clock Arrival Time – Tsu
The setup -me T of su is a fundamental requirement of all flip-flop devices, and is
specified in FPGA datasheets. This value will vary from one FGPA family to another.

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 Data Required Time (Hold) = the minimum -me required for the data to get latched
into the des-na-on register.
Data Required Time (Hold) = Clock Arrival Time + Th
Typical hold -mes for FPGA flip flops are oMen 0 or 1 ns.

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 Setup Slack = The margin by which the setup -ming requirement is met.
Setup Slack = Data Required Time – Data Arrival Time
Setup Slack = Clock Period + TclkB – Tsu - TclkA - Tco – Tdata
Note that the delay in the clock B path actually makes the setup margin larger – so
some-mes delay can be a good thing. However, the delay in the clock A path hurts
us, as does the logic and flip-flop clock to out delays.

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 Hold Slack = The margin by which the setup -ming requirement is met.
Hold Slack = Data Arrival Time – Data Required Time – just the opposite of the setup
slack calcula-on
Hold Slack = TclkA + Tco + Tdata - TclkB – Th
Here the delay in clock B hurts us, but the delay in clock A helps us. Given
requirements in the form of clock and delay constraints entered by the designer,
Timequest can generate informa-on used by the fi_er to adjust the rou-ng delays to
meet all the requirements. When all -ming requirements are met, this status is
known as -ming closure. Achieving -ming closure can be one of the most difficult
challenges in FPGA design, which is why so much -me and effort are spent on -ming
analysis.

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 I/O -ming analysis uses the same slack equa-ons as there is s-ll data transfer
between 2 registers, with setup and hold requirements. This shows the input delay
case. The net -me of arrival for inputs of the data rela-ve to the clock is known as
input delay, net delay -me for outputs is known as output delay.

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 Why Know these terms and calcula-ons?

Understanding the calcula-ons is important when -ming viola-ons occur, as you
need to know the cause of the viola-on before you can fix it.

Viola-ons can be caused by rou-ng paths that are too long, insufficient constraint
defini-ons, clock skew, and a number of other causes. Timing analysis helps us find
the root cause of these viola-ons.

TimeQuest analyzer uses these equa-ons to calculate slack, and also to determine
Fmax, an important metric in FPGA performance.

The terminology we have learned is used in the -ming reports, so it is important to
have the terms in your mind before reading the reports.

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 Here’s an example -ming report. In it, note the use of the Data Arrival Time, Data
Required Time, and calcula-on of the slack, which is nega-ve in this case, indica-ng a
setup viola-on.

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 Here are some guidelines for using -ming contraints:

Generally, the user MUST enter constraints for all paths to fully
analyze the design. This is because
•  The Timing analyzer only performs slack analysis on constrained
design paths
•  Constraints guide the fi_er to place & route design in order to
meet -ming requirements
•  My Recommenda-on: Constrain all paths (at least clocks & I/O)
This is not as difficult a task as it may sound
•  Wildcards can help to find signals and group them
•  A Single, generalized constraints cover many paths, even all paths in an
en-re clock domain

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In this video, you have learned:

•  Fundamentals of Timing Analysis
•  How Timing Hazards are caused and how to avoid them
•  Timing Analysis Terminology and Calcula-ons
•  Guidelines for Using TimeQuest to do -ming Analysis

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