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In this presenta1on, you will learn how to use the Mentor Graphics ModelSim
Simulator to simulate the logic in your FPGA design. ModelSim is a very powerful
tool, this is only an introduc1on to what it can do for you to help verify the
correctness of your design.

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Here’s what we will cover in this Video.
Convert a Schema1c bdf file into a VHDL file for simula1on
Start ModelSim from Quartus Prime
Add Signals to the Waveform Window
Create S1mulus to drive inputs in the simula1on
Verify logic design by thoughNul design of test cases applied in the
simula1on.

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Gradually we added signals un1l we could verify that the logic was working at least
for some test cases.

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Finally, we added several more test cases, learned how to add cursors and make
1ming measurements and how the choice of radix impacts the presenta1on of the
data.

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In this video, you have learned:
How to Convert a Schema1c bdf file into a VHDL file for simula1on
How to start and configure ModelSim
How to Add Signals to the Waveform Window
How to Create S1mulus to drive inputs in the simula1on
How to Verify logic design by thoughNul design of test cases applied in simula1on.