AC Mat EDC AE Comm - Sol. - 2522

Detailed Solutions
ESE-2018 E & T Engineering

Mains Test Series Test No : 5
Section A : Analog Circuits + Materials Science

Q.1 (a) Solution:
(i) Case-I, when both the diodes are in OFF state:
In this case both the diodes act as open circuits and the equivalent circuit can be
given by,
vo = vb = 25 V
va = vi
100 kΩ a D2 b
+ A K +
A
D1 200 kΩ
vi K vo
100 V 25 V
– –
From the above diagram, it is clear that the diode D2 conducts for vi > 25 V and the
diode D1 conducts for vi much greater than 25 V. So, both the diodes are in OFF state
for vi < 25 V.
Hence, vo = 25 V ; for vi ≤ 25 V ...(i)
Case-II, when D2 is in ON state and D1 is in OFF state:
From case-I, it is clear that D1 will be in ON state for vi > 25 V and the equivalent
circuit for this case can be given by,
2 | ESE 2018 : MAINS TEST SERIES
vo = va = vb
vi − 25 V
= × 200 + 25 V
100 + 200
2 25
= vi + V
3 3
This case will sustain until D1 starts conducting.
D1 conducts for, va > 100 V
2 25
vi + V > 100 V
3 3
vi > 137.5 V
2 25
So, vo = vi + V ; for 25 V < vi ≤ 137.5 V ...(ii)
3 3
Case-III, when both the diodes are in ON state:
From case-II, it is clear that for vi > 137.5 V both the diodes will be in ON state and
the equivalent circuit for this case can be given by,
100 kΩ a D2 b
+ A K +
A
D1 200 kΩ
vi K vo
100 V 25 V
– –
vo = 100 V ; for vi > 137.5 V ...(iii)

By summarizing all the three cases, the voltage transfer characteristic of the circuit
can be plotted as shown below.
⎧25 V ; vi ≤ 25 V
⎪⎪ 2 25
vo = ⎨ vi + V ; 25 V < vi ≤ 137.5 V
⎪3 3
⎪⎩100 V ; vi > 137.5 V
vo
100 V
25 V
D1 OFF, D2 OFF D1 OFF, D2 ON D1 ON, D2 ON

0 25 V 137.5 V vi
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Test No : 5 E & T ENGINEERING | 3
Q.1 (b) Solution:
The current flowing through the gate terminal of the MOSFET is zero. Hence, the
voltage across the resistor R1 can be given by,
8 16
V1 = × 20 V = V
22 + 8 3
VSG = V1 – RS ID
+10 V
ID
+
RS = 0.5 kΩ
R1 = 8 kΩ V1
–
R2 = 22 kΩ
RD = 2 kΩ
–10 V
For simplifying the calculations, let us take the numerical value of ID in mA units.
16
So, VSG = − 0.5I D
3
Assuming that the MOSFET is in saturation, then
2
16
ID = K p (VSG + Vtp )2 = 1 ⎛⎜ − 0.5 ID − 1⎞⎟
⎝ 3 ⎠
36ID = (26 – 3ID)2
2
9ID − 192 I D + 676 = 0
By solving the above quadratic equation, we get,
ID = 16.885 mA, 4.45 mA
For ID = 16.885 mA, VSG = V1 – RS ID = −3.11 V < Vtp
For ID = 4.45 mA, VSG = V1 – RS ID = 3.11 V > Vtp

Hence, the valid value of ID is 4.45 mA.
VSG = 3.11 V
VSD(sat) = VSG − Vtp = 2.11 V
VSD = 20 V – ID(RD + RS) = 8.875 V

VSD > VSD(sat) ⇒ The initial assumption is correct.
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So, the MOSFET in the given circuit is in saturation region and the required values are,
ID = 4.45 mA
VSG = 3.11 V
VSD = 8.875 V
Q.1 (c) Solution:
(i)
If we consider the electron energy band schemes for metals while photon absorption and
photon emission, in both cases a high-energy band is only partially filled with electrons.
Metals are opaque because the incident radiation having frequencies within the visible
range excites electrons into unoccupied energy states above the Fermi energy, as a
consequence, the incident radiation is absorbed. Total absorption is within a very thin
outer layer, usually less than 0.1 μm, thus only metallic films thinner than 0.1 μm are
capable of transmitting visible light. All frequencies of visible light are absorbed by
metals because of the continuously available empty electron states, which permit electron
transitions.
In fact, metals are opaque to all electromagnetic radiation on the low end of the frequency
spectrum, from radio waves, through infrared, the visible, and into about the middle of the
ultraviolet radiation. Metals are transparent to high-frequency (X-ray and γ-ray) radiation.
Most of the absorbed radiation is re-emitted from the surface in the form of visible light
of the same wavelength, which appears as reflected light. The reflectivity for most metals
is between 0.90 and 0.95; some small fraction of the energy from electron decay processes
is dissipated as heat.
Since metals are opaque and highly reflective, the perceived color is determined by the
wavelength distribution of the radiation that is reflected and not absorbed. A bright silvery
appearance when exposed to white light indicates that the metal is highly reflective over
the entire range of the visible spectrum. In other words, for the reflected beam, the
composition of these re-emitted photons, in terms of frequency and number, is
approximately the same as for the incident beam. Aluminium and silver are two metals
that exhibit this reflective behavior. Copper and gold appear red-orange and yellow
respectively, because some of the energy associated with light photons having short
wavelengths is not re-emitted as visible light.
(ii)
The relation between incident and transmitted components of a non-reflective radiation
can be given by,
IT = I0e–βx
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Where, I0 = Incident radiation
IT = Transmitted radiation
β = Absorption coefficient
x = Distance
I
Given that, for x = 200 mm, T = 0.98.
I0
IT
So, e–β(200 mm) = = 0.98
I0
1
Absorption coefficient, β = − ln(0.98)mm −1 = 1.01 × 10–4 mm–1
200
Q.1 (d) Solution:
According to Weiss, a specimen of ferromagnetic material consists of a large number of
regions or domains which are permanently magnetized. The atomic moments in the
individual domains are all aligned parallel to one another at temperatures far below the
Curie point. Each domain is magnetically saturated and has a net magnetic moment.
However, the direction of the permanent magnetization varies from domain to domain,
and consequently the resultant magnetization may be zero, or nearly zero. Above the
Curie temperature, the domains may disrupt and the material may loose its ferromagnetic
properties.
The domains exist in single crystals as well as in polycrystals line samples. The domains
are separated by domain walls in which the spin direction gradually changes from the
preferred direction of one domain to the preferred direction of the neighbouring domain.
A schematic arrangement of domains with zero resultant magnetic moment is shown in
Fig. (a) for a single crystal. The size of each domain may be of the order of 0.01 mm.
Consequently even a small sample of ferromagnetic material can be divided into domains.
The actual size of the domain depends to a large extent on the shape and size of the
crystal which in turn depends on previous history of the specimen.
H H
Fig. (a) Fig. (b) Fig. (c) Fig. (d)
Unmagnetised Magnetised by Magnetised by Variation of spin orientation
crystal domain growth domain rotation in a domain wall
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If an external field is applied as shown in Fig. (b) the domains with the proper direction
of permanent magnetization grow at the expense of those that are magnetized in the
other directions by virtue of the motion of domain walls. Ultimately as the field is increased
the whole specimen may become one single domain, and saturation has been achieved.
Thus the hysteresis curve is associated with the movement of domain walls and to some
extent by domain rotation which brings the magnetization parallel to the applied magnetic
field.
Q.1 (e) Solution:

Josephson effect is the phenomenon of super-current, i.e. a current that flows indefinitely
long without any voltage applied across a device known as Josephson junction.
The Josephson junction is a junction between two superconductors that are separated by
a thin insulator (a few nanometers thick) as depicted in Fig. (a). If the insulating barrier is
sufficiently thin, then there is a probability that the Cooper pairs can tunnel across the
junction. The wave function ψ of the Cooper pair, however, changes phase by θ when it
tunnels through the junction, not unexpected as the pair goes through a potential barrier.
The maximum superconducting current Ic that can flow through this weak link depends
on not only the thickness and area (size) of the insulator but also on the superconductor
materials and the temperature. The current I, or the supercurrent, through the junction
due to Cooper pair tunneling is determined by the phase angle θ,
I = Ic sin θ
Where Ic is the maximum current or the critical current.
I
D Normal
current
Insulating barrier C
Ic B
Superconductor Superconductor
I Super-
I
I current
A
V
V O Va
Fig. (a) Fig. (b)
If the current through the junction is controlled by an external circuit, then the tunneling
Cooper pairs on either side of the junction (in the superconductors) adjust their respective
phases to maintain the phase change to satisfy equation. If we plot the I - V characteristics
of this junction as in Fig. (b), we would find that for I < Ic , the behavior follows the vertical
OC line with no voltage across the junction.
If the current through the junction exceeds Ic , then the Cooper pairs cannot tunnel through
the insulator because equation cannot be satisfied. There is still a current through the
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junction, but it is due to the tunneling of normal, that is, single electrons as represented
by the curve OABD in Fig. (b). Thus, the current switches from point C to point B and
then follows the normal tunneling curve B to D. At point B, a voltage develops across the
junction and increases with the current. The normal tunneling current in the range OA is
negligible and rises suddenly when the voltage exceeds Va. The reason is that a certain
amount of voltage (corresponding to a potential energy eVa) is needed to provide the
necessary energy to disassociate the tunneling single electron from its Cooper pair. It is
apparent that the thin insulation acts as a weak superconductors or as a weak link in the
superconductor; weak with regard to the currents that can flow in the superconductor
itself. The I-V characteristic in Fig. (b) is symmetric about O, and is called the DC
characteristic of the Josephson junction. In addition, the I-V behaviour exhibits hysteresis;
that is, if we were to decrease the current, the behaviour does not follow DBC down to O,
but follows the DBA curve. When the current is decreased nearly to zero, the normal
tunneling current switches to the supercurrent. The Josephson junction is bistable; that
is, it has two states corresponding to the superconducting state OC and normal state
ABD. Thus, the device behaves as an electronic switch whose switching time, in theory,
is determined by tunneling times, in the picoseconds range. In practice the switching
time (~10 ps) is limited by the junction capacitance.
If, on the other hand, a DC voltage is applied across the Josephson junction, then the
phase change θ is modulated by the applied voltage. The most interesting and surprising
aspect is that the voltage modulates the rate of change of the phase through the barrier,
that is,
dθ 2eV
=
dt
When we integrate this, we find that θ is time and voltage dependent, so, according to
equation, the current is a sinusoidal function of time and voltage, that is,
⎛ 2 π(2 eV )t ⎞
I = Ic sin ⎜⎝ θ0 − ⎟⎠
h
or, I = I0 sin(2πft)
Where I0 is a new constant incorporating θ0 and the frequency of the oscillations of the
current is given by,
2eV
f =
h
The Josephson junction therefore generates an oscillating current of frequency f when
there is a DC voltage V across it. This is called the AC Josephson effect, a remarkable
phenomenon originally predicted by Josephson. According to the AC Josephson effect,
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the junction generates an AC current at a frequency of 2e/h Hz per volt or 483.6 MHz per
microvolt. Furthermore, the frequency of the current has nothing to do with the material
properties of the junction but is only determined by the applied voltage through e and h.
The AC Josephson effect has been adopted to define the voltage standard: One volt is the
voltage that, when applied to a Josephson junction, will generate an AC current and
hence an electromagnetic radiation of frequency 483,597.9 GHz.
Q.2 (a) Solution:

• To simplify the circuit, the portion left side to the base terminal of the transistor Q1
can be replaced with its Thevenin’s equivalent circuit, which can be determined as
follows: +10 V
40
VTh = × 10 V = 2.86 V R1 = 100 kΩ
40 + 100
VTh
R Th = (40 100) kΩ = 28.6 kΩ
R2 = 40 kΩ
• So, the equivalent of the given circuit will be as shown below.
+10 V
RC1 = 3 kΩ IC2
+
I1 IB2
Q2 VCE2
IC1 +
VBE2 –
+ –
RTh IB1 IE2
VTh = 2.86 V Q1 VCE1
+
28.6 kΩ RE2 = 5 kΩ
VBE1 –
– IE1
RE1 = 1 kΩ
–10 V
• By assuming that the transistor Q1 is in forward active mode, we get,

VTh − VBE1 2.16
IB1 = = mA = 14.44 µA
RTh + RE1 (1 + β) 28.6 + 121
IC1 = βIB1 = 1.733 mA

IE1 = (1 + β)IB1 = 1.75 mA
• By assuming that the transistor Q2 is also in forward active mode, we get,
I1 = IC 1 + I B2
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I1 RC1 + IE2 RE2 = 20 – VBE2
RC 1 ( IC 1 + I B2 ) + RE2 (1 + β)IB2 = 19.3
(608 k)IB2 = 19.3 – (3 × 1.733) = 14.1
IB 2 = 23.2 µA
IC2 = βIB2 = 2.784 mA
IE2 = (1 + β)IB2 = 2.81 mA
• Checking for the validity of assumptions:
VCE 1 = 10 – I1 RC1 – IE1 RE1 = 2.98 V
VCE 2 = 20 – IE2 RE2 = 5.95 V
VCE1 > 0 and VCE2 > 0. So, the assumptions made regarding the mode of operation of
Q1 and Q2 are correct and the quiescent values obtained are correct.
Q.2 (b) Solution:

Method-I:
The h-parameter model of the given amplifier with voltage series feedback is,
B1 ib1 C1 B2 ib2 C2
+
hie hfe ib1 10 kΩ RB2 hie hfe ib2 4.7 kΩ
E2
E1
Vs RB1
R2 = 4.7 kΩ
+ +
Vf R1 = 100 Ω
– Vo
– –
Rif R of′
R B 1 = (47 || 150) kΩ = 35.7868 kΩ

R B 2 = (47 || 33) kΩ = 19.3875 kΩ R2
R′L 1 = (RB2 || 10 kΩ || hie ) = 0.9428 kΩ
+ +
To calculate feedback factor β : Vf R1 Vo
Vf R1 1 – –
β = = =
Vo R1 + R2 48
as the feedback is voltage series type of negative feedback,
Av
Avf =
1 + Av β
R′o
′ =
Rif = Ri (1 + Avβ) and Rof
1 + Av β
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To calculate Av , Ri , R′0 (i.e. parameters without feedback):

B1 ib1 C1 B2 ib2 C2
+ +
4.7 k Ω
hie hfe ib1
10 kΩ RB2 hie hfe ib2 4.7 kΩ Vo
E1 100 Ω
E2 –
Vs RB1
R o′
100 Ω 4.7 kΩ
Ri
Vs
Ri = = hie + ⎡⎣(1 + h fe ) (100 || 4700)⎤⎦
ib1
Ri = 6093.75 Ω = 6.09375 kΩ
R′o = (4.7 || 4.8) kΩ
R′o = 2.37474 kΩ
h fe ib 1 ( RL′ 1 )
Vo = –hfe ib2 (4.7 kΩ || 4.8 kΩ) = h fe (4.7 kΩ || 4.8 kΩ)
hie
(4.7 kΩ || 4.8 kΩ ) RL′ 1 Vs ⎛ Vs ⎞

Vo = h 2fe ⎜⎝ ∵ i =
R ⎟⎠
b 1
hie Ri i
Vo
Av = ≈ 835
Vs
1 835
s = 1 + A β ; D = 1 + Av β = 1 + 48 18.4
v
To calculate Avf, Rif , R′of (i.e. Parameters with feedback):

Rif = 6.09375 × 18.4 = 112.125 kΩ
835
Avf = 45.4
18.4
Ro′ 2.37474
R′of = = kΩ = 129.062 Ω
1 + Av β 18.4
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Q.2 (c) Solution:
Given, Y = 80 GPa and ρ = 2.65 g/cm3 = 2650 kg/m3.
So, the velocity of ultrasonic wave will be,
Y 80 × 109 Pa
v = = = 5494 m/s
ρ 2650 kg/m 3
For fundamental mode,n = 1
For f = 1 kHz:
v 5494
λ = f = 1000 m = 5.494 m
The length of quartz crystal at 1 kHz for the fundamental mode (n = 1) is,
⎛1 ⎞ λ
L = n ⎜ λ ⎟ = 2.75 m
⎝2 ⎠ 2
For f ′ = 1 MHz:
v 5494
λ′ = f ′ = m = 5.494 mm
106
⎛1 ⎞ λ
L′ = n ⎜⎝ λ ⎟⎠ = 2.75 mm
2 2
From the values of L and L′, it can be observed that,
• When f is small, a huge crystal is required which is impractical. As f increases, the
crystal dimensions will be reduced to practically possible values.
• Increasing the value of n also increases the size of the quartz crystal.
Q.3 (a) Solution:

By using the concept of virtual short, we can write V+ = V– = Vin for both the op-amps
as shown below.
– +
Vin R1 I5 I4 R2 R3 V2 C4 I1
+ Iin V3 Vin I3 I2 Vin
Vin
R5
– + –
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Vin
Now, I1 =
R5
Vin
Thus, I2 = I 1 =
R5
Vin
⇒ V 2 = Vin +
sC 4 R5
V2 − Vin Vin
⇒ I3 = =
R3 sR5 R3C 4
Vin
Now, I3 = I 4 =
sC 4 R5 R3
Vin R2
V 3 = Vin −
sC 4 R5 R3
V3 − Vin Vin R2
Thus, I5 = =
R1 sC 4 R5 R3 R1
⇒ I5 = Iin
Vin R2
Iin =
sC 4 R5 R3 R1
Vin ( s) ⎡C R R R ⎤
⇒ Zin(s) = = s⎢ 4 5 3 1 ⎥
I in (s ) ⎣ R2 ⎦
Comment:
The above equation is equivalent to
Zin(s) = sLeq
⎡C R R R ⎤
where Leq = ⎢ 4 5 3 1 ⎥
⎣ R2 ⎦
thus the circuit can be used for simulating an inductor. Thus an equivalent model, of
the circuit can be represented as.
iin
+
⎡ C 4 R5 R3 R1 ⎤
vin Leq = ⎢ ⎥
⎣ R2 ⎦
–
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Q.3 (b) Solution:
(i)
• The small signal T-model equivalent parameters of the BJT are,
VT 25 mV
re = = = 25 Ω
I EQ 1 mA
β 100
α = = = 0.99
1 + β 101
VA
ro = =∞
ICQ
• By deactivating the DC sources, shorting the coupling capacitors and replacing the
transistor with its T-model, the small signal equivalent of the given circuit will be,
C
Rin
αie
is 10 kΩ B ie/(1 + β)
ie
vs +
–
10 kΩ re = 25 Ω
vo
E
10 kΩ 2 kΩ
• By applying KCL at node E, we get,

vB − vo vo vo
− + ie =
10 kΩ 10 kΩ 2 kΩ
vB − v0
ie =
25 Ω
vB – vo – vo + 400(vB – vo ) = 5 vo
401
vo = vB ...(i)
407
• By applying KCL at node B, we get,
vs − vB vB − vo i
= + e
10 kΩ 10 kΩ 101
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( vB − vo )
vs – vB = vB − vo +
0.2525
401
From equation (i), vo = vB
407
401 vB 401 vB
So, vs = 2 vB − vB + −
407 0.2525 407 × 0.2525
vs = 1.073 vB
vB = 0.932 vs
vB vB 10 vB
• Input impedance, Rin = = = kΩ = 137 kΩ
is ( vs − vB ) 1.073 vB − vB
10 kΩ
v0 (401/407) vB
• Voltage gain, = = 0.92
vs 1.073 vB
(ii) When CB is open circuited:
• The small signal equivalent circuit for this case can be given by,
C
Rin
αie
is 10 kΩ B ie/(1 + β)
ie
vs +
–
10 kΩ re = 25 Ω
E vo
10 kΩ 2 kΩ
• By applying KCL at node B, we get,

vs − vB vB i
= + e
10 kΩ 20 kΩ 101
vB
ie =
2025 Ω
vB
2 vs – 2 vB = vB +
10.23
v
3 vB + B
vs = 10.23 = 1.55 v
B
2
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vB = 0.645 vs
vB 10
• Input impedance, Rin = = kΩ = 18.2 kΩ
( vs − vB ) 1.55 − 1
10 kΩ
vo (2000 /2025) vB
• Voltage gain, = = 0.64
vs 1.55 vB
Observation:
Without CB ⇒ Rin = 18.2 kΩ, AV = 0.64
With CB ⇒ Rin = 137 kΩ, AV = 0.92
Hence CB acts as bootstrap capacitor. It provides negative feedback and improves
the input impedance.
Q.3 (c) Solution:

• Since molybdenum has BCC crystal structure, there are 2 atoms in the unit cell.
• The density can be given by,
Mass of atoms in unit cell
ρ =
Volume of unit cell
(Number of atoms in unit cell) × (Mass of one atom)
=
Volume of unit cell
⎛M ⎞
2 ⎜ at ⎟
⎝ NA ⎠
=
a3
1/3 1/3
⎛ 2 Mat ⎞ ⎛ 2 × 95.94 ⎞
So, a = ⎜ =⎜ ⎟ cm
⎝ ρN A ⎟⎠ 23
⎝ 10.22 × 6.022 × 10 ⎠
= 3.147 × 10–10 m
• The atomic concentration (nat) is 2 atoms in a cube of volume a3.
2 2
So, n at = 3
= −10 3
m −3
a (3.147 × 10 )
= 6.415 × 1028 m–3
• For a BCC cell, the lattice parameter a and the radius of the atom R are related by,
a 3 (3.147 × 10 −10 ) 3
R = = m = 1.363 × 10–10 m
4 4
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Q.4 (a) Solution:

(i) For DC analysis, the small-signal input voltage can be deactivated and the coupling
capacitor can be open-circuited. So, the equivalent circuit for DC analysis will be as
shown below.
15 V − 0.7 V +15 V
IE =
⎛ 2.5 kΩ⎞
⎜⎝ 1 + β ⎟⎠ + RE RC
VC
14.3 2.5
RE = − kΩ = 28.575 kΩ Rs = 2.5 kΩ
0.5 100
+
VC = 15 V – ICRC ; IC = αIE 0.7 V – IE
15 − 5 10 RE
RC = kΩ = kΩ = 20.2 kΩ
α(0.5) 0.99 × 0.5
(ii) The small signal equivalent of the given circuit will be, –15 V
Rs = 2.5 kΩ
vo
ib
vo
rπ βib ro = 200 kΩ
R′L
vs +
– + vo
ib – R′L = RC || RL
R R′L
ibRE – E vo
R′L RE
–
R′L = RC ⎜⎜ RL = (20.2 ⎜⎜ 10) kΩ = 6.7 kΩ
(1 + β )VT 100 × 25
r π = (1 + β ) re = = Ω = 5 kΩ
IE 0.5
By applying KCL at output node, we get,
RE
v0 − ib RE + vo
v0 RL′
+ + βib = 0
RL′ ro
⎡1 1 RE ⎤
⎢ r + R′ + R′ r ⎥
⎣ o L L o⎦
v0 = −1.78 × 10 −6 v0
ib =
⎡ RE ⎤
⎢ r − β⎥
⎣ o ⎦
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By applying KVL in input loop, we get,
RE
vs = ( Rs + rπ + RE ) ib − v0
RL′
⎡ −3 28.575 ⎤
= ⎢ −(7.5 + 28.575) × 1.78 × 10 − v0
⎣ 6.7 ⎥⎦
vo
Voltage gain, = –0.231
vs
Q.4 (b) Solution:

(i) For DC analysis of the given circuit, all the coupling capacitors can be open circuited
and the resultant equivalent circuit will be as shown below:
+5 V
R1 = 1.2 kΩ
+ IDQ
VSGQ
+
–
VSDQ
–
RD = 1.2 kΩ
–5 V
By assuming that the transistor is in saturation mode and taking the numerical values
of IDQ in mA units, we get,
IDQ = Kp(VSGQ + Vtp)2
VSGQ = 5 – 1.2 IDQ
So, ID = (1) (5 – 1.2 IDQ – 1.5)2 = (3.5 – 1.2 IDQ)2
2
ID = 1.44 I DQ − 8.4 I DQ + 12.25
2
1.44 I DQ − 9.4 I DQ + 12.25 = 0
IDQ = 4.73 mA, 1.8 mA
For IDQ = 4.73 mA, VSGQ = 5 – (1.2 × 4.73) = –0.676 V < Vtp
For IDQ = 1.8 mA, VSGQ = 5 – (1.2 × 1.8) = 2.84 V > Vtp
So, for the assumed case, the valid value of IDQ is 1.8 mA.
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VSDQ = 10 – (2 × 1.2 × IDQ ) = 10 – (2.4 × 1.8) = 5.68 V

VSGQ − Vtp = 2.84 – 1.5 = 1.34 V
VSDQ > VSGQ − Vtp . So, the initial assumption is correct about the mode of operation
of transistor.
The small-signal parameters of the transistor are,
gm = 2Kp (VSGQ + Vtp ) = 2(1) (1.34) = 2.68 mA/V
VA 1
ro = = =∞
I DQ λI DQ
(ii) The small signal equivalent of the given amplifier will be,
CC1 = 4.7 µF gm vgs CC 2 = 1 µF
Rs = 200 Ω S D
vo
–
vs +
– R1 = 1.2 kΩ vgs RD = 1.2 kΩ RL = 50 kΩ
+
G
Calculation of time constant (ττ 1) associated with CC 1 :

τ1 = Req CC 1
1
While calculating Req 1 , CC 2 must be short circuited and the voltage source vs should
be deactivated as shown below.
Vx
+–
Ix Req 1 gm vgs
Rs
–
R1 vgs RD || RL
Ix – gm vgs +
V x = Rs Ix + vgs
vgs = R 1 (Ix – gm vgs)
R1
vgs = Ix
1 + gm R1
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⎛ R1 ⎞
So, V x = ⎜ Rs + Ix
⎝ 1 + gm R1 ⎟⎠
Vx R1
Req 1 = = Rs + = 484.63 Ω
Ix 1 + gm R1
τ 1 = Req1 CC1 = 484.63 × 4.7 µs = 2.28 ms
Calculation of time constant (ττ 2) associated with CC2 :
τ2 = Req CC 2
2
While calculating Req 1 , CC 1 must be short circuited and the voltage source must be
deactivated as shown below.
Vx
+–
gm vgs Ix Req 2
–
(Rs || R1) vgs RD RL
vgs = − gm v gs ( Rs R1 )
So, vgs = 0
V
Req2 = x = RD + RL = 51.2 kΩ
Ix
τ 2 = Req2 CC 2 = 51.2 ms
(iii) The corner frequency associated with CC1 is,

1
fC 1 = = 69.8 Hz
2 πτ 1
The corner frequency associated with CC 2 is,
fC 2 = 1
= 3.12 Hz
2 πτ2
So, the corner frequency due to CC1 dominates that due to CC2. Hence, the lower cut-
off frequency of the amplifier can be given by,
fL = fC 1 = 69.8 Hz
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Q.4 (c) Solution:

(i) σ = neμd
Concentration of conduction electrons,
σ 1
n = =
eμ d ρeμ d
1
= −8 −19
cm -3
(8.37 × 10 × 100)(1.602 × 10 )(6)
n = 1.243 × 1023 cm–3
d N A 7.31 × 6.022 × 1023

Atomic concentration, n at = = cm −3
Mat 114.82
n at = 3.834 × 1022 cm–3

Effective number of conduction electrons donates per In atom (neff) is,
n 1.243 × 10 23
neff = = = 3.24
nat 3.834 × 10 22
(ii) If τ is the mean scattering time, l is the mean free path and u = mean speed of
conduction electrons, then
l = uτ
eτ
Drift mobility, μd = ; me = electron mass
me
μ d me (6 × 10 −4 )(9.1094 × 10 −31 )
So, τ = = s
e (1.602 × 10 −19 )
= 3.412 × 10–15 s
Mean free path, l = uτ = (1.74 × 108) (3.412 × 10–15) cm
= 5.94 nm
(iii) According to Wiedemann – Franz – Lorentz law,
Thermal conductivity, K = σTCWFL
Where, CWFL = Lorentz number (or) Wiedemann – Franz – Lorentz coefficient
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π 2 kB2 π 2 × (1.381 × 10 −23 )2

2 =
CWFL = –8 –2
−19 2 = 2.443 × 10 WΩK
3e 3 × (1.602 × 10 )
300 × 2.443 × 10 −8
So, K = −8
W m −1 K −1
8.37 × 10
= 87.563 W m–1 K–1
\Section B : Electronic Devices and Circuits-1 + Advance Electronics Topics-1 +
Analog and Digital Communication Systems-2
Q.5 (a) Solution:

• The entropy of a discrete memoryless source producing “N” independent symbols
can be given by,
N ⎛ 1⎞
H(X) = ∑ pi log 2 ⎜ p ⎟ bits/symbol
i=1 ⎝ i⎠
• We can use the following property of the natural logarithm to prove the given
inequality:
ln(x) ≤ x – 1 ; for x ≥ 0 ...(i)
The equality holds only at x = 1.
1 y
• By replacing x with in the equation (i), we get, y=x–1
Npi
⎛ 1 ⎞ 1 y = ln(x)
ln ⎜ ⎟ ≤ −1
⎝ Npi ⎠ Npi 0 x
1
⎛ 1 ⎞ 1
pi ln ⎜ ⎟ ≤ − pi –1
⎝ Np i ⎠ N
N N
N ⎛ 1 ⎞ N ⎛1⎞
∑ pi ln ⎜ p ⎟ − ∑ pi ln ( N ) ≤ ∑ ⎜ ⎟ ∑ pi
−
i = 1⎝ N ⎠ i = 1
i=1 ⎝ i ⎠ i=1
N N
⎛1⎞
ln(2) H ( X ) − ln( N ) ∑ pi ≤ N ⎜ ⎟ − ∑ pi
i=1
⎝ N ⎠ i=1
N
• By using the fact ∑ pi = 1 , we get,
i=1
ln(2) H(X) – ln(N) ≤ 0

⎡ ln ( N ) ⎤
H(X) ≤ ⎢ ln (2) = log 2 ( N )⎥
⎣ ⎦
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So, H(X) ≤ log2 (N) bits/symbol

1
The equality holds only at pi = , i.e. when all the symbols of X are equiprobable.
N
5. (b) Solution:
Finding Nyquist sampling rate of x(t):
x(t) = sinc 2(10 4t )
CTFT
sinc(t) ←⎯⎯ → rect( f )
CTFT
sinc(104 t) ←⎯⎯ ⎯
→
1 ⎛ f ⎞
rect ⎜ 4 ⎟
10 4 ⎝ 10 ⎠
CTFT
sinc2 (104 t) ←⎯⎯ ⎯→ ⎡⎢
1 ⎛ f ⎞ 1 ⎛ f ⎞⎤
rect ⎜ ⎟ ∗ rect ⎜⎝ 4 ⎟⎠ ⎥
⎣ 10
4 ⎝ 10 4 ⎠ 10 4 10 ⎦
"∗ denotes convolution"
⎡ 1 ⎛ f ⎞ 1 ⎛ f ⎞⎤
X( f ) = ⎢ 4 rect ⎜ 4 ⎟ ∗ 4 rect ⎜ 4 ⎟ ⎥
⎣ 10 ⎝ 10 ⎠ 10 ⎝ 10 ⎠ ⎦
10–4 rect (f /104) 10–4 rect (f /104) X (f )
10–4
–8
10–4 10–4 Slope = 10
∗ ≡
–5 kHz 0 5 kHz f –5 kHz 0 5 kHz f –10 kHz 0 10 kHz f

From the spectrum of X( f ), it is clear that, fm (max) = 10 kHz.
Nyquist sampling rate, fs = 2fm (max) = 20 kHz.
Finding bit rate of the system:
Given that, the quantizer is an 8-bit uniform quantizer.
So, number of bits per sample, n = 8 bits/sample
Bit rate of the system, Rb = nfs = 160 kbps
Finding the minimum baseband channel bandwidth:
It is given that, the quantized samples are passed through a raised-cosine filter with a
roll-off factor (α) of unity.
For this case, the minimum baseband channel bandwidth required will be,
1 R
(BW)min = (1 + α ) = b (1 + α )
2Tb 2
Given that, α = 1
160
So, (BW)min = (1 + 1) kHz = 160 kHz
2
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Q.5 (c) Solution:
(i) The electron concentration in an n-type semiconductor is approximate equal to the
donor concentration.
So, n(x) = Nd0 e –(x/L) ; 0≤x≤L
The electron diffusion current density can be given by,

J n(diff) = qDn dn( x ) xˆ
dx
kT
Dn = μnVT = μn
q
qDn = μn kT = 6000 × 1.38 × 10 –23 × 300

= 2.484 × 10–17 A-cm2
N
J n(diff) = 2.484 × 10 −17 × d 0 × ( − e − x /L ) xˆ A/cm 2 ; 0 ≤ x ≤ L
L
−17 5 × 1016 −107 x

= 2.484 × 10 × −5
× e ( − xˆ ) A/cm 2 ; 0 ≤ x ≤ L
10
5 −107 x
= 1.242 × 10 × e ( − xˆ ) A/cm 2 ; 0 ≤ x ≤ 0.1 μm

(ii) J n(drift) = n( x )q μ E
n i

Ei = induced electric field

Jn(drift) + Jn(diff) = 0 ∵ Drift current due to Ei compensates diffusion current
5 −107x ˆ
n( x )q μn Ei = − Jn(diff) = 1.242 × 10 × e x A/cm 2 ; 0 ≤ x ≤ L
7
1.242 × 10 5 × e −10 x
Ei = xˆ V/cm ; 0 ≤ x ≤ L
16 −19 −107 x
5 × 10 × 1.6 × 10 × 6000 × e
3
= 2.5875 × 10 xˆ V/cm ; 0 ≤ x ≤ 0.1 μm
Q.5 (d) Solution:

The Shallow Trench Isolation (STI) is the preferred isolation technique for the sub 0.5 μm
technology, because it completely avoids the bird's beak shape characteristic. With its
zero oxide field encroachment, STI is more suitable for the increased density
requirements, because it allows to form smaller isolation regions.
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The starting step in STI process is a shallow trench is etched into the silicon substrate, as
shown in Figure-a.
After under-etching of the oxide pad, also a thermal oxide in the trench is grown, the so-
called liner oxide as shown in Figure-c. But unlike with LOCOS, the thermal oxidation
process is stopped after the formation of a thin oxide layer, and the rest of the trench is
filled with a deposited oxide as shown in Figure-d. Next, the excessive (deposited) oxide
is removed with chemical mechanical planarization. At last the nitride mask is also
removed. The price for saving space with STI is the larger number of different process
steps.
The process flow for the STI technique can be summarized as follows:
1. Stack deposition (oxide + protective nitride)
2. Lithography print
3. Trentch etching
4. Pad oxide under-etching
5. Linear oxidation
6. CVD oxide gap fill
7. Chemical mechinical planarization (CMP)
8. Removal of the protective nitride
Liner
Resist Pad Resist Oxide
Nitride Oxide Nitride
Silicon Silicon
(a) Stack and trench etching (b) Pad oxide underetching (c) Liner oxidation
Isolat. Isolat. Isolat.

Oxide Oxide Oxide
(d) CVD Oxide gap fill (e) CMP (f) Nitride strip
Q.5 (e) Solution:

(i) Diffusion:
Diffusion is the movement of impurity atoms in a semiconductor material at high
temperatures. The driving force of diffusion is the concentration gradient. There is a
wide range of diffusivities for various dopant species, which depend on how easy the
respective dopant impurity can move through the material. Diffusion is applied to anneal
the crystal defects after ion implantation or to introduce dopant atoms into silicon from
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a chemical vapour source. In the lateral case the diffusion time and temperature determine
the depth of dopant penetration. But diffusion can also be an unwanted parasitic effect,
because it takes place during all high temperature process steps.
The biggest limitation of thermal diffusion is that the process is isotropic, i.e. lateral
diffusion cannot be avoided, though diffusion coefficients in different crystallographic
directions might be different. Thus, an oxide window that serves as a mask to protect
certain regions of the wafers can be ineffective due to lateral diffusion. This is especially
important for doping small regions. Doping control is also difficult to achieve due to
presence of concentration gradients. These gradients will change in subsequent annealing
steps. Thus, there is a thermal budget associated with doping.
(ii) Ion implantation:
Ion implantation is a relatively newer doping technique that operates close to room
temperature. It is a physical process of doping, not based on a chemical reaction. It is the
dominant technique to introduce dopant impurities into crystalline silicon. This is
performed with an electric field which accelerates the ionized atoms or molecules so that
these particles penetrate into the target material until they come to rest because of
interactions with the silicon atoms.
Ion implantation is able to control exactly the distribution and dose of the dopants in
silicon, because the penetration depth depends on the kinetic energy of the ions which is
proportional to the electric field. The dopant dose can be controlled by varying the ion
source. Since ion implantation takes place close to room temperature, it is compatible
with conventional lithographic processes, so small regions can be doped. Also, since
temperature is low, lateral diffusion is negligible.
Unfortunately, after ion implantation the crystal structure is damaged which implies
worse electrical properties. Another problem is that the implanted dopants are electrically
inactive, because they are situated on interstitial sites. Therefore after ion implantation a
thermal process step is necessary which repairs the crystal damage and activates the
dopants.
6. (a) Solution:
For binary modulation schemes, using correlator receivers with exact phase
synchronisation and optimum threshold detection, the average symbol error probability
can be given as,
⎡ d2 ⎤
Pe = Q ⎢ min ⎥
⎢⎣ 2 N 0 ⎥⎦
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Where, dmin= Minimum distance between adjacent message points in the constellation diagram
N0
= Two sided power spectral density of white noise = 0.5 × 10–11 W/Hz
2
So, N0 = 10–11 W/Hz
Let us take a reference energy,
A2
E1 = Tb
2
1
Where, A = carrier amplitude and Tb = = bit duration
Rb
(5 × 10 −3 )2 1
So, E1 = × 6 = 12.5 × 10 −12 J
2 10
(i) Average symbol error for BASK scheme:
The constellation diagram of a BASK scheme can be given as shown in the figure
below.
dmin
φ1(t )
0 E1
dmin = E1
⎡ E1 ⎤ ⎡ 12.5 × 10 −12 ⎤
Pe = Q ⎢ ⎥ = Q⎢ −11
⎥
⎣ 2N0 ⎦ ⎢⎣ 2 × 10 ⎥⎦
= Q ⎡⎣ 0.625 ⎤⎦ Q(0.79)
(ii) Average symbol error for BFSK scheme:
The constellation diagram of a BFSK scheme can be given as shown in the figure
below.
φ2(t)
E1
dmin
0 φ1(t)
E1
dmin = E1 + E1 = 2E1
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⎡ 2 E1 ⎤ ⎡ E1 ⎤
Pe = Q ⎢ ⎥ = Q⎢ 2 ⎥ = Q ⎡⎣ 2 × 0.625 ⎤⎦
⎣ 2N0 ⎦ ⎣ 2N0 ⎦
= Q ⎡⎣ 1.25 ⎤⎦ Q(1.12)
(iii) Average symbol error for BPSK scheme:
The constellation diagram of a BPSK scheme can be given as shown in the figure
below.
dmin
0 φ1(t )
– E E1
1
dmin = 2 E1
⎡ 4E1 ⎤ ⎡ E1 ⎤
Pe = Q ⎢ ⎥ = Q ⎢2 ⎥ = Q ⎡⎣ 2 0.625 ⎤⎦ Q(1.58)
⎣ 2 N 0 ⎦ ⎣ 2 N 0 ⎦
Q.6 (b) Solution
Given data:
Junction depth, xj = 1 μm
Doping concentration of substrate, NB = 1017/cm 3
Solid solubility limit of boron, N0 = 2 × 1020/cm3
Final surface concentration of boron, NS = 5 × 1019/cm3
Temperature used for pre-deposition, T1 = 1000 + 273 K = 1273 K
Temperature used for drive-in, T2 = 1100 + 273 K = 1373 K
Diffusion constant for boron, D0 = 10.5 cm2/sec
Activation energy for boron, Ea = 3.69 eV
Useful relations :
The concentration profile of the diffused atoms inside the substrate for pre-deposition
process can be given as,
⎡ x ⎤
N(x, t) = N 0 erfc ⎢ ⎥
⎣ 2 Dt ⎦
Where, erfc(τ) = complementary error function
D = Diffusivity = D0 e − Ea / kT
t = process time used for diffusion
x = depth from the surface of the substrate
The concentration profile of the diffused atoms inside the substrate for drive-in process
can be given as,
Q0 − x 2 /4Dt 2
N(x, t) = e = NS e − x /4Dt
πDt
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Where, Q0 =Amount of solute per unit area present on the surface prior to drive-in
D1t1
Q0 = 2 N 0
π
Here, D1 = Diffusivity used in pre-deposition process
t1 = process time of pre-deposition
After drive-in process, at junction depth (x j ), the concentration of solute (or diffused
atoms) equals to the initial doping concentration of the substrate (or background
concentration).
Q0 − ( x 2j /4D2 t2 )
i.e., e = NB
πD2t2
Here, D2 = Diffusivity used in drive-in process ; t2 = process time of drive-in
Finding the values of D1 and D2:
For pre-deposition process,
⎛ 3.69 ⎞
−⎜ ⎟
−5
D1 = D0 e − Ea / kT1 = (10.5)e ⎝ 8.62×10 ×1273 ⎠ = 2.6 × 10–14 cm2/sec
For drive-in process,
⎛ 3.69 ⎞
−⎜ ⎟
−5
D2 = D0 e − Ea / kT2 = (10.5)e ⎝ 8.62×10 ×1373 ⎠ = 3 × 10 –13 cm2/sec
Finding the process time of drive-in (t 2):
For drive-in process,
Q0 2 2
N(x, t) = e − x /4D2 t2 = NS e −x /4D2 t2
πD2t2
At x = xj, N(x, t) = NB
− x 2j /4D2 t2
So, NS e = NB
x 2j ⎛ NS ⎞
= ln ⎜ N ⎟
4D2t2 ⎝ B⎠
x 2j
t2 = ...(i)
4D2 ln( NS / N B )
By substituting the values of xj, D2, NS and NB in equation (i), we get,
(10−4 )2
t2 = seconds
⎛ 19 ⎞
5 × 10
4 × 3 × 10 −13 × ln ⎜ ⎟
⎜ 1017 ⎟
⎝ ⎠
t2 ≈ 1341 seconds = 22 minutes 21 seconds
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Finding the process time of pre-deposition (t1):
First, by using the values of t2 and NS, we can calculate the value of Q0 as follows,
Q0
NS =
πD2t2
19 −13 2
So, Q0 = N S πD2t2 = (5 × 10 ) π(3 × 10 )(1341) / cm
= 17.775 × 1014 /cm2
The value of Q0 depends on pre-deposition process time, diffusivity, solid solubility
limits as,
D1 t1
Q0 = 2 N 0
π
2
⎛ π ⎞ ⎛ Q0 ⎞
So, t1 = ⎜ ⎟⎜ ⎟ ...(ii)
⎝ D1 ⎠ ⎝ 2 N 0 ⎠
By substituting the values of D1, Q0 and N0 in equation (ii), we get,
2
π ⎛ 17.775 × 1014 ⎞
t1 = ⎜ ⎟ seconds
(2.6 × 10 −14 ) ⎜⎝ 2 × 2 × 10 20 ⎟⎠
≈ 2386 seconds = 39 minutes 46 seconds
So, the process times required for both pre-deposition and drive-in processes are as
follows:
Process time of pre-deposition, t1 = 2386 seconds
Process time of drive-in, t2 = 1341 seconds
Q.6 (c) Solution:
(i) With a γND excess of holes being created at the bar ends, some of the excess carriers
will move into the bar interior via diffusion. Recombination will symmetrically reduce
the excess carriers as it moves into the bar. A distribution of excess minority carriers
symmetrical about the center of the bar is expected because both ends of the bar are
being perturbed in an identical manner. The expected general form of the Δpn(x)
solution is therefore as sketched below.
Δpn(x)
γND
0 L L x
2
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(ii) Low-level injection conditions prevail inside the illuminated bar. Because,
Δpn ( x ) max = γND = 10–3 × 1016 = 1013 cm–3

n 0 ≈ ND = 1016 cm–3
ni2 2.25 × 10 20
p0 = = 16
= 2.25 × 10 4 cm −3
n0 10
13 −3
pn ( x ) max = p0 + Δpn ( x ) max ≈ 10 cm
pn ( x ) max << n0 ⇒ low level injection

(iii) The minority carrier diffusion equation can be given by,
∂Δpn ∂ 2 Δpn Δpn

D
= p − + GL
∂t ∂x 2 τp
∂ΔPn
Under the steady state condition = 0 and illumination does not penetrate into
∂t
the bar. So, GL = 0 inside the bar. Hence,
∂ 2 Δpn Δpn
Dp
2
− = 0
∂x τp
∂ 2 Δpn Δpn
− = 0
∂x 2 Dp τ p
Dp τp = L2p
∂ 2 Δpn 1
So, − Δpn = 0
∂x 2 L2p
1
Auxiliary equation, m2 − 2 = 0
Lp
1 1
m = − ,+
Lp Lp
So, the solution for Δpn(x) can be given by,

x x
− +
Lp Lp
Δpn(x) = Ae + Be
Lp = Dp τ p = 16 × 10 −4 × 10 −6 m = 40 μm
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Using the boundary conditions, Δpn(0) = 1013 cm–3 and Δpn(L) = 1013 cm–3, we get,
A + B = Δpn(0) = 1013 cm–3
Ae –2 + Be 2 = Δpn(L = 80 μm) = 1013 cm–3
By solving the above two equations, we get,
A = 8.81 × 1012 cm–3
B = 1.19 × 1012 cm–3
⎛ x x ⎞
− +
⎜ L L ⎟⎟
So, Δpn(x) = ⎜⎝ 8.81 e p + 1.19 e p 12 −3
⎠ × 10 cm ; 0 ≤ x ≤ L
(iv) The hole diffusion current density can be given by,

dp( x ) dΔpn ( x )
Jp(diff) = − Dp q = − Dp q
dx dx
⎡ x x ⎤
− +
Dp ⎢ L L ⎥ 12
= − q ⎢ − 8.81 e p + 1.19 e p ⎥ × 10
Lp ⎢ ⎥
⎣ ⎦
16 × 1.6 × 10 −19
At x = 0, Jp (diff) = − ( − 8.81 + 1.19) × 1012 A/cm 2
−4
40 × 10
= 4.8768 mA/cm2
Q.7 (a) Solution:

• Each regenerative repeater will have a receiver system with a detector. So, including
(n – 1) repeaters and one terminal receiver, there are “n” detectors in cascade.
• The probability of “i” out of “n” detectors to produce an error can be given by the
binomial distribution as,
⎛n⎞
Pi = ⎜ ⎟ pi (1 − p )n − i
⎝i⎠
• As the channel is used for binary transmission, an error will be posted at the output
of final detector, when the odd number of detectors produces an error. Hence, the
required probability can be given as,
⎛n⎞ i n−i
Pn = Podd = ∑ ⎜ ⎟ p (1 − p)
i
i = odd ⎝ ⎠
• Let Peven be the probability that an even number of detectors produces an error.
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⎛ n⎞ i n−i
Then, Peven = ∑ ⎜ ⎟ p (1 − p)
i
i = even ⎝ ⎠
n
⎛n⎞
Peven + Podd = ∑ ⎜ i ⎟ pi (1 − p)n − i
i = 0⎝ ⎠
⎡ n n
⎛ ⎞ ⎤
⎢
Using the binomial expansion theorem ⎢( a + b )n
= ∑ ⎜ i ⎟ ai bn − i ⎥⎥ ,
⎣ i = 0⎝ ⎠ ⎦
Peven + Podd = [p + (1 – p)] n = 1 ...(i)
⎛n⎞ i n−i ⎛n⎞
Peven – Podd = ∑ ⎜ ⎟ p (1 − p) − ∑ ⎜ ⎟ pi (1 − p)n − i
i
i = even ⎝ ⎠
i
i = odd ⎝ ⎠
⎛n⎞ n−i ⎛n⎞

= ∑ i
⎜ ⎟ ( − p) (1 − p ) + ∑ ⎜ ⎟ ( − p)i (1 − p)n − i
i
i = even ⎝ ⎠
i
i = odd ⎝ ⎠
n
⎛ n⎞
= ∑ ⎜ i ⎟ ( − p)i (1 − p)n − i
i = 0⎝ ⎠
Peven – Podd = [(–p) + (1 – p)]n = (1 – 2p)n ...(ii)
• By subtracting equation (ii) from equation (i), we get,
2Podd = [1 – (1 – 2p)n]
1⎡
Pn = Podd = 1 − (1 − 2 p )n ⎤
2⎣ ⎦
Q.7 (b) Solution:

• The charge density and the electric field variation with x can be plotted as,
ρv(x)
qaxn
–xp +
0 xn x
–
–qaxn
E(x)
–xp xn
x
⎥ Area⎥ = Vbi
–Em
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• The magnitude of space charge on n-side is equal to that of on p-side.
1 1
So, A × × xn × qaxn = A × × x p × ( − qax p )
2 2
2
xn2 = x p
xn = x p
Width of the depletion region,
W = xn + xp
W
So, xn = x p =
2
• The charge density is varying as a function of “x” only and it is given by,
W W
ρv(x) = qax ; − ≤x≤
2 2
• From Poisson’s equation,
ρ
∇ 2V = − v
εs
dV ρv ( x)
E(x) = − dx = ∫ ε dx + C
s
qax qax 2 W W
= ∫ εs dx + C =
2 εs
+C ; −
2
≤x≤
2
⎛ W⎞
Using the boundary condition E ⎜ ± ⎟ = 0 , we get,
⎝ 2 ⎠
qa( W /2)2
+C = 0
2 εs
qaW 2
C = −
8 εs
qa ⎡ 2 W 2 ⎤ W W
So, E(x) = ⎢x − ⎥; − ≤x≤
2 εs ⎣⎢ 4 ⎥⎦ 2 2
qaW 2
Em = E( x = 0) =
8 εs
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• The built-in voltage across the junction can be given by,

W /2 W /2 ⎛
qa W2 ⎞
Vbi = − ∫ E( x ) dx = ∫ ⎜ − x 2 ⎟ dx
εs ⎜ 4 ⎟
− W /2 0 ⎝ ⎠
W /2
qa ⎡ W 2 x3 ⎤ qa ⎡ W 3 W 3 ⎤ qaW 3
= ⎢ x − ⎥ = ⎢ − ⎥=
εs ⎢⎣ 4 3 ⎥⎦ εs ⎢⎣ 8 24 ⎥⎦ 12 εs
0
• So, the width of the depletion region as a function of Vbi can be given by,
1/3
⎛ 12 εs ⎞
W = ⎜ Vbi ⎟
⎝ qa ⎠
Q.7 (c) Solution
Step 1 : Photoresist Application
Laying a film of a photoresist (light sensitive liquid) on the wafer surface which is covered
by the oxide layer. For ideal case, the film should be uniform, highly adherent and free
from dust.
Photoresist film
SiO2 layer
Silicon wafer
Step 2 : Prebake
Here the wafer covered with photoresist is put into an oven to drive off the solvents. It
also hardens the wafer and form semisolid film.
Step 3 : Alignment and Exposure
Then the wafer having photoresist is placed in apparatus called mask aligner (used to
align mask to the pattern) in very close proximity (25 to 125 mm) to a photomask.
Photomask should be correctly lined up with reference masks or a pre-existing pattern
on the wafer as shown in the figure below. Then after alignment, the wafer is brought
near to photomask.After this the UV light is turned on the areas which are not covered
by photomask are exposed to UV light the exposure time is 3 to 10 sec.
UV light
Opaque pattern
on photo emulsion Glass photomask
Photoresist layer
SiO2 layer
Silicon wafer
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Step 4 : Development
The exposed photoresist (positive) becomes soft which can be removed easily by
developer solution and the unexposed photoresist remains hard which is not soluble in
developer solution.
UV light
Glass photomask Photoresist

SiO2
Photoresist layer
SiO2 layer ⇒ Silicon wafer
Silicon wafer
Step 5 : Post Bake

After these steps wafers are post bake in an oven at a temperature of 150°C for 30 to 60
min. It is used to toughen the remaining photoresist material and the wafer become
more adhesive and resistance to hydrofluoric acid (HF) used for etching process.
Photoresist
SiO2
Silicon wafer
Step 6 : Oxide Etching

After post bake the wafer is harden and from there oxide layer can be etched away to
expose areas of semiconductor underneath. For this process the wafers are immersed in
HF acid solution. HF is a diluted solution of H2O and HF i.e., 10 : 1.
Silicon wafer
Step 7 : Photoresist Stripping

Here the removal of photoresist material takes place with the mixture of sulphuric acid
and hydrogen peroxide using abrasion process.
SiO2
Silicon wafer
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Q.8 (a) Solution:

• The quantization boundaries can be mapped in the given PDF as follows:
fX(x )
1
1 1
3 Slope = –
Slope = 9
9
3 4
2 5
1
–3 –2 –1 0 1.50 3 x
• Let us represent the quantized samples as y = {y1, y2, y3, y4, y5} and the probabilities
associated with these quantized samples are,
P(yi) = Area bounded by quantization region-i under fX(x)
1 ⎛ 1⎞ 1
P(y1) = × 1×⎜1× ⎟ =
2 ⎝ 9 ⎠ 18
⎡1 ⎛ 1 ⎞⎤ 1 3 1
P(y2) = ⎢ 2 × 2 × ⎜ 2 × 9 ⎟ ⎥ − 18 = 18 = 6
⎣ ⎝ ⎠⎦
1 1 1 5
P(y3) = − − =
2 6 18 18
1 ⎡1 3 3 1⎤ 3
P(y4) = − × × × =
2 ⎢⎣ 2 2 2 9 ⎥⎦ 8
1 3 3 1 1
P(y5) = × × × =
2 2 2 9 8
yi y1 y2 y3 y4 y5
1 1 5 3 1
P(yi)
18 6 18 8 8
• Huffman code can be developed for the quantized samples by using the following
tree diagram.
yi P(yi)
y4 3 3 3 11.25 0
8 8 8 18
y3 5 5 6.25 0
18 18 3
18 8 1
y2 1 3.25 0
6 18 5
18 1
y5 1 0 3
8 18 1
y1 1
18 1
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• The binary code-words obtained from the above tree diagram can be summarized
as,
yi y1 y2 y3 y4 y5
1 1 5 3 1
P(yi)
18 6 18 8 8
Code-word 0001 001 01 1 0000

Code-word
length (li) 4 3 2 1 4
• The entropy of the samples at the quantizer output is,

5
H(y) = − ∑ P( yi )log 2 P( yi )
i=1
⎡ 1
⎛ ⎞ 1
⎛ ⎞ ⎛ ⎞ 1 ⎛ ⎞ ⎛ ⎞ 1 ⎛ ⎞ ⎛ ⎞ 5 ⎛ ⎞ ⎛ ⎞ 5 ⎛ ⎞ 3 3 1 1 ⎤
= − ⎢⎜ ⎟ log2 ⎜ ⎟ + ⎜ ⎟ log2 ⎜ ⎟ + ⎜ ⎟ log2 ⎜ ⎟ + ⎜ ⎟ log2 ⎜ ⎟ + ⎜ ⎟ log2 ⎜ ⎟⎥ bits/sample
⎣⎝ 18 ⎠ ⎝ 18 ⎠ ⎝ 6 ⎠ ⎝ 6 ⎠ ⎝ 18 ⎠ ⎝ 18 ⎠ ⎝ 8 ⎠ ⎝ 8 ⎠ ⎝ 8 ⎠ ⎝ 8 ⎠⎦
= 2.0815 bits/sample
• The average code-word length of the binary code-words is,
5
⎛ 1 ⎞ ⎛1⎞ ⎛ 5 ⎞ ⎛3⎞ ⎛1⎞
L = E[ L ] = ∑ li P( yi ) = 4 ⎜ ⎟ + 3 ⎜ ⎟ + 2 ⎜ ⎟ + 1 ⎜ ⎟ + 4 ⎜ ⎟ bits/sample
⎝ 18 ⎠ ⎝6⎠ ⎝ 18 ⎠ ⎝8⎠ ⎝8⎠
i=1
= 2.153 bits/sample
• The coding efficiency of the Huffman code is,
H ( y ) 2.0815
η = = = 0.967 (or) 96.7%
L 2.153
Q.8 (b) Solution:

• The device is in equilibrium. So, the charge density variation and the electric field
variation with x can be plotted as,
ρv(x)
qND
xi +
–xp 2
0 xi xn x
– 2
–qNA
E(x)
–Em
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⎛ xi ⎞
⎥ Qp⎥ = qN A ⎜ x p − ⎟ ...(i)
⎝ 2⎠
⎛ xi ⎞
⎥ Qn⎥ = qN D ⎜ xn − ⎟ ...(ii)
⎝ 2⎠
Qp Qn qN A ⎛ xi ⎞ qN D ⎛ xi ⎞
Em = = = ⎜⎝ x p − ⎟⎠ = ⎜⎝ xn − ⎟⎠ ...(iii)
ε si ε si ε si 2 ε si 2
E ⎛ x x ⎞
Vbi = Area under E(x ) = xi Em + m ⎜ x p − i + xn − i ⎟
2 ⎝ 2 2⎠
2Vbi = (2 xi + xp + xn – xi )Em
2Vbi
Em = ...(iv)
xn + x p + xi
⎛N N ⎞ ⎛ 15
A D ⎟ = 0.026 ln 10 × 2 × 10
15 ⎞
Vbi = tV ln ⎜ ⎜ ⎟ V = 0.6 V
⎜ n2 ⎟ ⎜ 2.25 × 1020 ⎟
⎝ i ⎠ ⎝ ⎠
• From equations (i) and (ii), we get,
⎥ Qp⎥ = ⎥ Qn⎥
⎛ x ⎞ ⎛ x ⎞
N A ⎜ x p − i ⎟ = 2 N A ⎜ xn − i ⎟
⎝ 2⎠ ⎝ 2⎠
Given that, xi = 2 μm. For making the calculations simple, let us take units of all
lengths in μm.
So, (xp – 1) = 2(xn – 1)
xp = 2 xn – 1 ...(v)
• From equations (iii), (iv) and (v), we get,
qN D 2Vbi
( xn − 1) =
ε si xn + x p + 2
1.6 × 10 −19 × 2 × 10 15 × (10 4 )−3 1.2

( xn − 1) =
1.06 × 10 −12 × (10 4 )−1 xn + (2 xn − 1) + 2
1.2 × 1.06
(xn – 1) (3xn + 1) = = 0.3975
2 × 1.6
3xn2 − 2 xn − 1 = 0.3975
3xn2 − 2 xn − 1.3975 = 0
xn = 1.093, –0.426
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As the width of depletion region can be only a positive quantity, by neglecting the
negative value, we get,
xn = 1.093 μm
xp = 2xn –1 = 1.186 μm
• By substituting the values of Vbi , xi , xn and xp in equation (iv), we get,
2 × 0.6
Em = V/μm = 0.28 V/μm
1.093 + 1.186 + 2
Q.8 (c) Solution

Step-1: (Selecting starting material)
• The starting material for the fabrication of a CMOS transistor using SOS process is
aluminium oxide (sapphire).
• Sapphire is an insulating material and the SOS technology is one of the possibilities
of the silicon on insulator (SOI) technology.
Step-2: (Formation of silicon film on sapphire)
• After selecting a sapphire substrate, we have to form a lightly doped n-type silicon
film on the substrate through the process epitaxy, as shown in the figure below.
n– Silicon
Sapphire
• Both molecular beam epitaxy (MBE) and vapour phase epitaxy (VPE) can be used to
form silicon on sapphire. But VPE is used most widely.
Step-3: (Formation of islands)
• Now we have to define the active regions on the silicon layer, where the actual PMOS
and NMOS transistors are to be fabricated.
• This can be done by selectively etching silicon, using photolithographic process.
• After this selective etching, the substrate with silicon islands will be as shown in the
figure below.
n– n– Silicon
Sapphire
Step-4: (Formation of p-island)

• Now we have to dope one silicon island with boron impurities to form a p-type
island, where the NMOS transistor is to be fabricated.
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• While doing this p-type doping, the properties of other island should not be changed.
So, we have to form a layer of photoresist on the other island to protect from boron
implant as shown in the figure below.
Boron implant
Photoresist
n– n–
Sapphire
Step-5: (Formation of gate oxide)

• Now we have to form high quality oxide layers on both the islands as shown in the
figure below.
p– n– Thin gate oxide
Sapphire
• Thermal oxidation is used to form high quality gate oxide.

Step-6: (Formation of polysilicon gates)
• The polysilicon gate is a self-aligned structure and is preferred over the older type of
metal gate structure.
• A polysilicon layer, usually arsenic doped (n-type), is deposited and patterned as
shown in the figure below.
Polysilicon Polysilicon gate
p– n– p– n–
Sapphire Sapphire
Step-7: (Formation of source and drain of NMOS)

• Now we have to form source and drain regions on p-type island through the process
of implantation.
• A heavy arsenic implant can be used to form the n+ source and drain regions of the
NMOS transistor. A layer of photoresist can be used to block the regions where PMOS
transistor is to be formed as shown in the figure below.
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Arsenic implant
Photoresist
p– n–
Sapphire
Step-8: (Formation of source and drain of PMOS)

• Now we have to form source and drain regions on n-type island through the process
of implantation.
• A heavy boron implant can be used to form the p+ source and drain regions of the
PMOS transistor. A layer of photoresist can be used to block the regions where PMOS
transistor is formed as shown in the figure below.
Boron implant
Photoresist
n+ p– n+ n–
Sapphire
• After completion of this p+ implantation, we have to form a CVD oxide layer on the
entire surface of the substrate as shown in the figure below.
CVD oxide
– + – +
n+ p n+ p n p Gate oxide
Sapphire
Step-9: (Opening of contact holes)

• Now we have to open the windows on the CVD oxide layer at the required places, to
facilitate the metal contacts.
• This task can be accomplished with the help of photolithography as shown in the
figure below.
Contact hole
CVD oxide
–
n+ p n + p+ n– p+ Gate oxide
Sapphire
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Step-10: (Metallization)
• Now we have to form metal contacts through the contact windows.
• First we have to form a thin layer of aluminium on the entire surface of the wafer,
through the process of evaporation or sputtering, as shown in the figure below.
Aluminium layer
CVD oxide
n+ p– +
n
+
p n– p +
Gate oxide
Sapphire
• Now we have to etch the aluminium from the surface of the wafer, selectively, so that
the aluminium must present only on the places where the contacts are required as
shown in the figure below.
Aluminium metal contact
CVD oxide
n+ p– n+ +
p n– p +
Gate oxide
Sapphire
• Now the CMOS transistor is ready for passivation, packaging and wire bonding which
are final steps in any IC fabrication.

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AC Mat EDC AE Comm - Sol. - 2522

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Detailed Solutions

ESE-2018 E & T Engineering

Section A : Analog Circuits + Materials Science

vo = 100 V ; for vi > 137.5 V ...(iii)

D1 OFF, D2 OFF D1 OFF, D2 ON D1 ON, D2 ON

For ID = 4.45 mA, VSG = V1 – RS ID = 3.11 V > Vtp

VSD = 20 V – ID(RD + RS) = 8.875 V

Q.1 (e) Solution:

Q.2 (a) Solution:

• By assuming that the transistor Q1 is in forward active mode, we get,

IC1 = βIB1 = 1.733 mA

Q.2 (b) Solution:

R B 1 = (47 || 150) kΩ = 35.7868 kΩ

To calculate Av , Ri , R′0 (i.e. parameters without feedback):

(4.7 kΩ || 4.8 kΩ ) RL′ 1 Vs ⎛ Vs ⎞

To calculate Avf, Rif , R′of (i.e. Parameters with feedback):

Q.3 (a) Solution:

• By applying KCL at node E, we get,

• By applying KCL at node B, we get,

Q.3 (c) Solution:

Q.4 (a) Solution:

R′L = RC ⎜⎜ RL = (20.2 ⎜⎜ 10) kΩ = 6.7 kΩ

Q.4 (b) Solution:

VSDQ = 10 – (2 × 1.2 × IDQ ) = 10 – (2.4 × 1.8) = 5.68 V

Calculation of time constant (ττ 1) associated with CC 1 :

(Rs || R1) vgs RD RL

(iii) The corner frequency associated with CC1 is,

Q.4 (c) Solution:

n = 1.243 × 1023 cm–3

d N A 7.31 × 6.022 × 1023

n at = 3.834 × 1022 cm–3

π 2 kB2 π 2 × (1.381 × 10 −23 )2

Q.5 (a) Solution:

ln(2) H(X) – ln(N) ≤ 0

So, H(X) ≤ log2 (N) bits/symbol

–5 kHz 0 5 kHz f –5 kHz 0 5 kHz f –10 kHz 0 10 kHz f

qDn = μn kT = 6000 × 1.38 × 10 –23 × 300

−17 5 × 1016 −107 x

Q.5 (d) Solution:

Isolat. Isolat. Isolat.

Q.5 (e) Solution:

Δpn ( x ) max = γND = 10–3 × 1016 = 1013 cm–3

pn ( x ) max << n0 ⇒ low level injection

∂Δpn ∂ 2 Δpn Δpn

So, the solution for Δpn(x) can be given by,

(iv) The hole diffusion current density can be given by,

Q.7 (a) Solution:

⎛n⎞ n−i ⎛n⎞

Q.7 (b) Solution:

• The built-in voltage across the junction can be given by,

Glass photomask Photoresist

Step 5 : Post Bake

Step 6 : Oxide Etching

Step 7 : Photoresist Stripping

Q.8 (a) Solution:

Code-word 0001 001 01 1 0000

• The entropy of the samples at the quantizer output is,

Q.8 (b) Solution:

1.6 × 10 −19 × 2 × 10 15 × (10 4 )−3 1.2

Q.8 (c) Solution

Step-4: (Formation of p-island)

Step-5: (Formation of gate oxide)

p– n– Thin gate oxide