NPTEL » VLSI Physica! Design ‘About the Course Ask a. Unit 3 - Week 1 —— : Week 1 Assignment 1 faa ‘Thea date forsubmiting thi ssgnment ha ossad Due on 2020-02-12, 23:58 IST, As per ourrecores you have not submatoa hs assent +) whieh of the following represents the behavioral description of a function? ‘point ‘a. Anetlst of gates and their interconnection, —, b. The truth table description of a combinational function. —— (cThe sum-of-produets representation of the function. tac YLSIOHG Ses 4. Allof these, nt) q ftscare Ys 05097 S86 b (ean) iS tect VSP 4 Desgn Atonaton a1) to, newer inca. tac LSP DeeprAssnaton a2) fosied Aner: ~ 2 Which of the following functions can be realized by a single 4-input LUT in a typical FPGA? Tpoimt ace 0 & Feapeec ace he b. FEAR ERC ECD tects te © FHABSCD+AE @ Lecture Note Fat Chie: Wek Asannet 5 ed Fee oer te rover inact Sante woes ecpted Aros Week @ 9 Consider a gate array fabrication facility, where the chips designed by three customers X, Y and woe are being fabricated. X orders 2,000 units, orders 5,000 units and Z orders 3,000 unis of chips. Assume thatthe cast of fabricating the generic masks corresponding to a design is RS. 75 Wook lakhs, and the cost of customization f Rs 5 lakhs for every 500 chips. The total cost of vane fabrication of ll the 10,000 chips will be Rs. lak. to.esooerincae, Wook st a wane penn 1 point “oa Tansee Which ofthe following statements is/are not true for standard cll based design? ‘pont Pownload Videos: @, Cells of arbitrary sizes can be included in @ design. Det seton b. The area ofeach ofthe cells must be the same. ‘6 The eight ofeach ofthe ces must be the same Loe tneractve Session d. Feed-through cells may be required to complete the interconnections, ty,pegooer eer ovpid Anew: * 9) If itis required to design a circuit with the maximum possible performance, which of the 1 following design styles would you prefer? 2. FPGA Gate array © Fulleustom 4. Standard cet evga haar: Which ofthe fllowing statements is/are true in physical ‘pom 2 Hoorplanning precedes partitioning b. Parttoning precedes placement Floorplanning and routing can proceed in parallel 4. Placement precedes routing sevetea Aner: * 7. in which step of physical design are the shapes and pin locations of flexible blocks get defined? pent 4 Floorplanning b. Placement & Routing 4. None ofthese a sett Aner: x 5 Which of the following is/are true with respect to static timing analysis? ‘pom We analyze a given circuit nets to estimate worst-case signal delays \We can estimate the maximum clack frequency with which a cuit can un correct. Allows us to carryout timing optimizations ta improve the circuit speed 4. Allof these sews ener Which ofthe following steps in digital IC design flow correspond to physical design? ‘pom 2 Logie synthesis . Routing © Logic simulation 4. Placement to,ne grower orc. potted Ares "8 For the function F=A.8+ C.D, which ofthe following represent the correct bit patter tobe pom loaded into a 4input LUT to realize the function? (9001 0001 0003 1111, ‘0101 01020202 1111 {0000 0001 0000 0101, 11000 1000 1000 1111 ‘econo Anewor