Samsung NP350V5X QCLA4QCLA5 LA-8862P Schematic

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1 1
QCLA4,5
2
Eureka 14" & 15" 2
LA-8862P REV 0.2 Schematic

3
Intel Processor(Ivy Bridge / Sandy Bridge) 3
PCH(Panther Point)
m
2011-11-24 Rev 0.2
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ts
re
ec
4 4
rs
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/31 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QCLA4,5
Date: Thursday, February 16, 2012 Sheet 1 of 48
A B C D E
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A B C D E
Intel CPU
Ivy Bridge
Sandy Bridge
eDP Conn.
1
rPGA-989 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1
page 13
37.5mm*37.5mm Dual Channel BANK 0, 1, 2, 3 page 11,12
page 5,6,7,8,9,10 1.5V DDRIII 1066/1333/1600 MT/s
CRT FDI X8 DMI X4

page 14
2.7GT/s 5GT/s
USB30 4x USB Right USB Left

5V 5GT/s USB20 port 2,3 USB20 port 0,1
USB30 port 3,4 USB30 port 1,2
USB20 4x page 25 page 30
LVDS Conn.
5V 480MHz
page 13
2
USB20 3x FingerPrinter Int. Camera 2
5V 480MHz USB port 8 USB port 11

EC SMBus page 29 page 13
HDMI-CEC HDMI Conn.
page 15
page 15 Intel PCH USB20 3x PCIeMini Card PCIeMini Card

5V 480MHz
Panther Point PCIe Gen1 1x
WiMax USB port 9 3G/TV#1
TV#2
USB port 12
USB port 10
page 27 page 27
1.5V 5GT/s
RJ45 RTL8105E-VD 10/100M PCIe Gen1 1x PCIeMini Card
SATA Gen3 port 1
page 40 RTL8111F-VB 1G 1.5V 5GT/s
5V 6GHz(600MB/s) WLAN PCIe port 2 mSATA
PCIe port 1 page 31 SATA port 1
FCBGA-989 page 27 page 27 B-CAS SIM
25mm*25mm page 26 page 27
Cardreader PCIe Gen1 1x SATA Gen3 port 0 5V 6GHz(600MB/s)

RTS5229 1.5V 5GT/s
PCIe port4 page 16,17,18,19,20,21,22,23,24
page 29 SATA port 2 SATA ODD SATA HDD
3 5V 3GHz(300MB/s) SATA port 2 SATA port 0 3
page 23 page 23
PCIe Gen2 2x
1.5V 5GT/s
om
LPC BUS HD Audio
3.3V 33 MHz 3.3V 24MHz
USB3.0 Right-side USB3.0 Left-side
HDA Codec UPD720202 UPD720202
PCIe port5 PCIe port6
ALC280 page 31 page 32
SPI ROM Debug Port ENE KB930/KB9012
.c
page 33
page 36 page 35
(4MB + 2MB)
page 16
ts
RTC CKT.
page 16
SPK Conn JPIO
DC/DC Interface CKT.
page 38
Touch Pad
page 37
Int.KBD
page 36
EC ROM CIR
page 35
re
G-Sensor
page 36
page 34
(HP &page
MIC)34
ec
(128KB)
page 36
4 4
Power Circuit DC/DC EC SMBus

irs
page 39,40,41,42,43,
44,45,46,47,48,49 Finger Printer/B
page 26 Security Classification Compal Secret Data Compal Electronics, Inc.
pa
Power On/Off CKT. Power/B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
page 37 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
page 37 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS QCLA4,5 0.2
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5 4 3 2 1
DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 0.1A +5VL
B+
Ipeak=10.63A, Imax=7.44A, Iocp min=12.3A DESIGN CURRENT 11A +5VALW
SUSP#
DESIGN CURRENT 1.8A +1.8VS

SY8033BDBC
SUSP
D D
N-CHANNEL DESIGN CURRENT 6.5A +5VS
SI4800 BCPWON
DESIGN CURRENT 0.1A +5VS_L_BCAS
P-CHANNEL
AO-3413
KB_LED
TPS51125 DESIGN CURRENT 0.4A +5VS_LED
P-CHANNEL
AO-3413
+5VS
DESIGN CURRENT 0.3A +3VS_HDP
LDO
G9191
ODD_EN#
DESIGN CURRENT 1.6A +5VS_ODD
P-CHANNEL
AO-3413
SYSON
Ipeak=6A, Imax=4.2A, Iocp min=8A DESIGN CURRENT 13.5A +1.5V

SY8036 SUSP
N-CHANNEL DESIGN CURRENT 5A +1.5V_CPU

FDS6676AS
SUSP
C C
N-CHANNEL DESIGN CURRENT 1.5A +1.5VS
FDS6676AS
0.75VR_EN#
DESIGN CURRENT 1A +0.75VS

VCCPPWRGD
G2992
Ipeak=6A, Imax=4.A, Iocp min=8 DESIGN CURRENT 6A +VCCSA

SY8037
LNB EN
Imax=0.3A, Iocp min=0.8A DESIGN CURRENT 0.3A +16VS

APW7137
Ipeak=5A, Imax=3.5A, Iocp min=6.2A DESIGN CURRENT 7.5A +3VALW
m
WOL_EN
P-CHANNEL DESIGN CURRENT 0.1A +3V_LAN

SUSP AO-3413
co
N-CHANNEL DESIGN CURRENT 6A +3VS
B B
SI4800 UMA_ENVDD
.
P-CHANNEL DESIGN CURRENT 2A +LCD_VDD
ts
AO-3415
VR_ON
FELICA_PWR
P-CHANNEL
AO-3413
DESIGN CURRENT 0.1A re
+FLICA_VCC
ec
DESIGN CURRENT 94A +CPU_CORE
NCP6132A DESIGN CURRENT 50A +GFX_CORE
rs
SUSP#
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Ipeak=14A, Imax=9.8A, Iocp min=16.92A DESIGN CURRENT 15A +1.05VS_VCCP

TPS51212
ep
pr
A A
o
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Power Tree
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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
QFKAA
5 4 3 2 1
w
w
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A B C D E
( O MEANS ON X MEANS OFF )

Voltage Rails
+5VS
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS
+3VL +3VALW
+1.8VS
+VSB
power +1.5VS
1 plane +1.05VS
1
+0.75VS BTO Option Table

+CPU_CORE
+VGA_CORE Function HDMI Camera & Mic TPM MINI PCI-E SLOT
+GFX_CORE
description HDMI Camera & Mic TPM Half Card
+VTT
State
+VRAM_1.5VS explain HDMI Digital MIC Analog MIC SLB 9635 SLB 9655 WIMAX
+3VS_DGPU
BTO HDMI@ CAM@ AMIC@ TPM9635@ TPM9655@ WIMAX@
+1.05VS_DGPU
Function SPI ROM Green CLK USB 3.0 Sleep & Charge LAN
S0
O O O O O O description SPI ROM Green CLK USB 3.0 Sleep & Charge LAN
S1 explain WIN8 Green CLK NOGCLK Internal 10/100M Giga

O O O O O O
2 BTO WIN8@ GCLK@ NOGCLK@ IUSB30@ 8105ELDO@ 8111FVB@ 2
S3
O O O O O X
S5 S4/AC
O O O O X X
S5 S4/ Battery only
O O O X X X
S5 S4/AC & Battery
don't exist
O X X X X X
PCH SM Bus Address
Power Device HEX Address

+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
3
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b 3
+3VS Clock Generator D2 H 1101 0010 b
+3VS New Card
m
+3VS WLAN/WIMAX
+3VS Clock Generator
+3VS 3G
co
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#
EC SM Bus1 Address EC SM Bus2 Address
.
Full ON HIGH HIGH HIGH
ts
Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH
+3VL
+3VL
Smart Battery
HDMI-CEC
16 H
34 H
0001 0110 b
0011 0100 b
+3VS
+3VS
+3VS
PCH
NVIDIA GPU
G-Sensor
96 H
9A H
40 H
1001 0110 b
1001 1010 b
0100 0000 b
re
S3 (Suspend to RAM)
S4 (Suspend to Disk)
LOW
LOW
HIGH
LOW
HIGH
HIGH
ec
+3VS Light Sensor 52 H 0101 0010 b S5 (Soft OFF) LOW LOW LOW
4 Power Device HEX Address 4
G3 LOW LOW LOW

+3VL Cap. Sensor Virtual I2C
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Notes List
Custom 0.2
QFKAA
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5 4 3 2 1
JCPUB
100 MHz
@
BCLK
A28 CLK_CPU_DMI
CLK_CPU_DMI 17 Stuff RC157 and RC158 if do not support eDP
1000P_0402_50V7K 2 1 CC63 PM_DRAM_PWRGD_R H_SNB_IVB# C26 A27 CLK_CPU_DMI#
MISC
CLOCKS
11,21 H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# 17
@ 120 MHz +1.05VS_VCCP
1000P_0402_50V7K 2 1 CC62 H_PWRGOOD_R T1 PAD TP_SKTOCC# AN34
SKTOCC# A16 CLK_CPU_EDP
DPLL_REF_CLK A15 CLK_CPU_EDP# CLK_CPU_EDP# 1 2
DPLL_REF_CLK# RC157 1K_0402_5%
D CLK_CPU_EDP 1 2 D
T2 PAD H_CATERR# AL33 RC158 1K_0402_5%
CATERR#
THERMAL
+1.05VS_VCCP H_PECI AN33 R8 H_DRAMRST#
31 H_PECI PECI SM_DRAMRST# H_DRAMRST# 7
DDR3
MISC
RC44 2 1 62_0402_5% H_PROCHOT# RC159
31 H_PROCHOT#
1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 RC56 2 1 140_0402_1% DDR3 Compensation Signals
56_0402_5% PROCHOT# SM_RCOMP[0] A5 SM_RCOMP_1 RC59 2 1 25.5_0402_1%
SM_RCOMP[1] Layout Note:Place these
A4 SM_RCOMP_2 RC61 2 1 200_0402_1%
RC45 2 1 10K_0402_5% H_PWRGOOD SM_RCOMP[2] resistors near Processor
H_THERMTRIP# AN32
21 H_THERMTRIP# THERMTRIP# @
H_DRAMRST# 1 2
CC34 180P_0402_50V8J
AP29
PRDY# AP27
PREQ# by ESD requestion and place near CPU
@
1000P_0402_50V7K 2 1 CC70 H_PECI AR26 XDP_TCK_R PAD T4
TCK AR27 XDP_TMS_R PAD T5
TMS
PWR MANAGEMENT
H_PM_SYNC AM34 AP30 XDP_TRST#_R 2 1
JTAG & BPM

@ 18 H_PM_SYNC
1000P_0402_50V7K 2 1 CC71 H_PM_SYNC PM_SYNC TRST# RC55 51_0402_5%
AR28 XDP_TDI_R PAD T6
@ RC187 TDI AP26 XDP_TDO_R PAD T7
1000P_0402_50V7K 2 1 CC66 BUF_CPU_RST# 1 2 H_PWRGOOD_R AP33 TDO
21 H_PWRGOOD UNCOREPWRGOOD
0_0402_5%
Layout request for test point
AL35
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R V8 DBR#
Please place near JCPU RC58 130_0402_5% SM_DRAMPWROK
C AT28 C
BPM#[0] AR29
BPM#[1] AR30
BUF_CPU_RST# AR33 BPM#[2] AT30
RESET# BPM#[3] AP32
BPM#[4] AR31
BPM#[5] AT31
BPM#[6] AR32
+3VALW_PCH BPM#[7]
+3VALW_PCH
2 1 DRAMPWROK +1.5V_CPU
RC11 200_0402_5%
2 1 TYCO_2013620-2_IVY BRIDGE
1
10K_0402_5% 0.1U_0402_10V7K @
+3VS 2 RC13 1 CC33 RC14
UC1 200_0402_5%
5
74AHC1G09GW_TSSOP5
2
1 2 1
P
18,31 PM_PWROK
RC12 @ 0_0402_5% B 4 PM_SYS_PWRGD_BUF
2 O
18 DRAMPWROK A
G
1
3
RC25
39_0402_5%
@
1
RC181 @ 2 0_0402_5%
1 2
D QC2
9,34 SUSP SUSP 2 2N7002_SOT23
G @
S
3
B B
FAN Control Circuit
om
Buffered Reset to CPU
+5VS JFAN @
1A +FAN2 1
2 1
+3VS @ 3 2
2 3
1
C15
C13 4
GND
.c
10U_0805_6.3V6M 1000P_0402_50V7K 5
2
U1 1 GND
1 0.1U_0402_10V7K
CC36 1 8 ACES_85204-0300N
+1.05VS_VCCP 2 EN GND 7
PLT_RST# 20,26,27,28,31,32 VIN GND
+FAN2 3 6 R24 10K_0402_5%
2 4 VOUT GND 5 2 1
s
31 EN_DFAN1 VSET GND +3VS
1
UC2 10mil
1
PLT_RST# 1 RC38 APL5607KI-TRG_SO8 FAN_SPEED1
OE# FAN_SPEED1 31
5 75_0402_5% C17 1
et
VCC 10U_0805_6.3V6M C14
2
2 RC35 0.01U_0402_25V7K
2
IN 43_0402_1% @
4 BUFO_CPU_RST# 1 2 BUF_CPU_RST# 2
3 OUT
GND
1
cr
A 74AHC1G125GW_SOT353-5 RC40 A
0_0402_5%
@
2
e
rs

Sandy Bridge_JTAG/XDP/FAN
i
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS QFKAA
pa
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PEG_ICOMPI and RCOMPO signals should be

+1.05VS_VCCP shorted and routed
with - max length = 500 mils - typical
impedance = 43 m ohm (4 mils)
1
RC1 PEG_ICOMPO signals should be routed with -
24.9_0402_1%
max length = 500 mils
JCPUA - typical impedance = 14.5 m ohm (12 mils)
2
D J22 PEG_COMP D
PEG_ICOMPI J21
DMI_PTX_CRX_N0 B27 PEG_ICOMPO H22
18 DMI_PTX_CRX_N0 B25 DMI_RX#[0] PEG_RCOMPO
DMI_PTX_CRX_N1
18 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 A25 DMI_RX#[1]
18 DMI_PTX_CRX_N2 B24 DMI_RX#[2] K33
DMI_PTX_CRX_N3
18 DMI_PTX_CRX_N3 DMI_RX#[3] PEG_RX#[0] M35
DMI_PTX_CRX_P0 B28 PEG_RX#[1] L34
18 DMI_PTX_CRX_P0 B26 DMI_RX[0] PEG_RX#[2] J35
DMI_PTX_CRX_P1
18 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 A24 DMI_RX[1] PEG_RX#[3] J32
DMI
18 DMI_PTX_CRX_P2 B23 DMI_RX[2] PEG_RX#[4] H34
DMI_PTX_CRX_P3
18 DMI_PTX_CRX_P3 DMI_RX[3] PEG_RX#[5] H31
DMI_CTX_PRX_N0 G21 PEG_RX#[6] G33
18 DMI_CTX_PRX_N0 E22 DMI_TX#[0] PEG_RX#[7] G30
DMI_CTX_PRX_N1
18 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 F21 DMI_TX#[1] PEG_RX#[8] F35
18 DMI_CTX_PRX_N2 D21 DMI_TX#[2] PEG_RX#[9] E34
DMI_CTX_PRX_N3
18 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] E32
DMI_CTX_PRX_P0 G22 PEG_RX#[11] D33
18 DMI_CTX_PRX_P0 D22 DMI_TX[0] PEG_RX#[12] D31
DMI_CTX_PRX_P1
18 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 F20 DMI_TX[1] PEG_RX#[13] B33
PCI EXPRESS* - GRAPHICS

18 DMI_CTX_PRX_P2 C21 DMI_TX[2] PEG_RX#[14] C32
DMI_CTX_PRX_P3
18 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
J33
PEG_RX[0] L35
PEG_RX[1] K34
FDI_CTX_PRX_N0 A21 PEG_RX[2] H35
18 FDI_CTX_PRX_N0 H19 FDI0_TX#[0] PEG_RX[3] H32
FDI_CTX_PRX_N1
18 FDI_CTX_PRX_N1 E19 FDI0_TX#[1] PEG_RX[4] G34
FDI_CTX_PRX_N2
18 FDI_CTX_PRX_N2 F18 FDI0_TX#[2] PEG_RX[5] G31
FDI_CTX_PRX_N3
18 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 B21 FDI0_TX#[3] PEG_RX[6] F33
Intel(R) FDI
C C
18 FDI_CTX_PRX_N4 C20 FDI1_TX#[0] PEG_RX[7] F30
FDI_CTX_PRX_N5
18 FDI_CTX_PRX_N5 D18 FDI1_TX#[1] PEG_RX[8] E35
FDI_CTX_PRX_N6
18 FDI_CTX_PRX_N6 E17 FDI1_TX#[2] PEG_RX[9] E33
FDI_CTX_PRX_N7
18 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32
PEG_RX[11] D34
FDI_CTX_PRX_P0 A22 PEG_RX[12] E31
18 FDI_CTX_PRX_P0 G19 FDI0_TX[0] PEG_RX[13] C33
FDI_CTX_PRX_P1
18 FDI_CTX_PRX_P1 E20 FDI0_TX[1] PEG_RX[14] B32
FDI_CTX_PRX_P2
18 FDI_CTX_PRX_P2 G18 FDI0_TX[2] PEG_RX[15]
FDI_CTX_PRX_P3
18 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 B20 FDI0_TX[3] M29
18 FDI_CTX_PRX_P4 C19 FDI1_TX[0] PEG_TX#[0] M32
FDI_CTX_PRX_P5
18 FDI_CTX_PRX_P5 D19 FDI1_TX[1] PEG_TX#[1] M31
FDI_CTX_PRX_P6
18 FDI_CTX_PRX_P6 F17 FDI1_TX[2] PEG_TX#[2] L32
FDI_CTX_PRX_P7
18 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29
FDI_FSYNC0 J18 PEG_TX#[4] K31
18 FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
FDI_FSYNC1 J17 K28
18 FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] J30
FDI_INT H20 PEG_TX#[7] J28
18 FDI_INT FDI_INT PEG_TX#[8] H29
FDI_LSYNC0 J19 PEG_TX#[9] G27
18 FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
FDI_LSYNC1 H17 E29
18 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
eDP_COMP signals should be F27
PEG_TX#[12] D28
shorted near balls and PEG_TX#[13] F26
PEG_TX#[14] E25
routed with typical PEG_TX#[15]
RC2 1 2 24.9_0402_1% EDP_COMP A18
impedance <25m ohm +1.05VS_VCCP eDP_COMPIO
A17 M28
1 2 H_EDP_HPD# B16 eDP_ICOMPO PEG_TX[0] M33
B +1.05VS_VCCP eDP_HPD# PEG_TX[1] B
RC3 10K_0402_5% M30
PEG_TX[2] L31
C15 PEG_TX[3] L28
Reserve RC3 for HW Review demand eDP_AUX PEG_TX[4]
D15 K30
eDP_AUX# PEG_TX[5] K27
eDP
PEG_TX[6] J29
C17 PEG_TX[7] J27
m
F16 eDP_TX[0] PEG_TX[8] H28
C16 eDP_TX[1] PEG_TX[9] G28
G15 eDP_TX[2] PEG_TX[10] E28
eDP_TX[3] PEG_TX[11] F28
PEG_TX[12]
co
C18 D27
E16 eDP_TX#[0] PEG_TX[13] E26
D16 eDP_TX#[1] PEG_TX[14] D25
F15 eDP_TX#[2] PEG_TX[15]
eDP_TX#[3]
.
TYCO_2013620-2_IVY BRIDGE
ts
@
re
ec
A A
irs

Sandy Bridge_DMI/PEG/FDI
pa
Custom 0.2
QFKAA
5 4 3 2 1
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5 4 3 2 1
JCPUC JCPUD
11 DDR_A_D[0..63]
12 DDR_B_D[0..63]
AB6 DDRA_CLK0 AE2 DDRB_CLK0

SA_CLK[0] DDRA_CLK0 11 SB_CLK[0] DDRB_CLK0 12
AA6 DDRA_CLK0# AD2 DDRB_CLK0#
SA_CLK#[0] DDRA_CLK0# 11 SB_CLK#[0] DDRB_CLK0# 12
DDR_A_D0 C5 V9 DDRA_CKE0 DDR_B_D0 C9 R9 DDRB_CKE0
SA_DQ[0] SA_CKE[0] DDRA_CKE0 11 SB_DQ[0] SB_CKE[0] DDRB_CKE0 12
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDRA_CLK1 DDR_B_D4 A9 SB_DQ[3] AE1 DDRB_CLK1
D SA_DQ[4] SA_CLK[1] DDRA_CLK1 11 SB_DQ[4] SB_CLK[1] DDRB_CLK1 12 D
DDR_A_D5 C6 AB5 DDRA_CLK1# DDR_B_D5 A8 AD1 DDRB_CLK1#
SA_DQ[5] SA_CLK#[1] DDRA_CLK1# 11 SB_DQ[5] SB_CLK#[1] DDRB_CLK1# 12
DDR_A_D6 C2 V10 DDRA_CKE1 DDR_B_D6 D9 R10 DDRB_CKE1
SA_DQ[6] SA_CKE[1] DDRA_CKE1 11 SB_DQ[6] SB_CKE[1] DDRB_CKE1 12
DDR_A_D7 C3 DDR_B_D7 D8
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] RSVD_TP[1] AA4 DDR_B_D11 G1 SB_DQ[10] RSVD_TP[11] AA2
DDR_A_D12 F9 SA_DQ[11] RSVD_TP[2] W9 DDR_B_D12 G5 SB_DQ[11] RSVD_TP[12] T9
DDR_A_D13 F7 SA_DQ[12] RSVD_TP[3] DDR_B_D13 F5 SB_DQ[12] RSVD_TP[13]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] RSVD_TP[4] AA3 DDR_B_D17 J8 SB_DQ[16] RSVD_TP[14] AB1
DDR_A_D18 K1 SA_DQ[17] RSVD_TP[5] W10 DDR_B_D18 K10 SB_DQ[17] RSVD_TP[15] T10
DDR_A_D19 J1 SA_DQ[18] RSVD_TP[6] DDR_B_D19 K9 SB_DQ[18] RSVD_TP[16]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDRA_SCS0# DDR_B_D22 K8 SB_DQ[21] AD3 DDRB_SCS0#
SA_DQ[22] SA_CS#[0] DDRA_SCS0# 11 SB_DQ[22] SB_CS#[0] DDRB_SCS0# 12
DDR_A_D23 K2 AL3 DDRA_SCS1# DDR_B_D23 K7 AE3 DDRB_SCS1#
SA_DQ[23] SA_CS#[1] DDRA_SCS1# 11 SB_DQ[23] SB_CS#[1] DDRB_SCS1# 12
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
DDR_A_D25 N10 SA_DQ[24] RSVD_TP[7] AH1 DDR_B_D25 N4 SB_DQ[24] RSVD_TP[17] AE6
DDR_A_D26 N8 SA_DQ[25] RSVD_TP[8] DDR_B_D26 N2 SB_DQ[25] RSVD_TP[18]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDRA_ODT0 DDR_B_D29 N5 SB_DQ[28] AE4 DDRB_ODT0
SA_DQ[29] SA_ODT[0] DDRA_ODT0 11 SB_DQ[29] SB_ODT[0] DDRB_ODT0 12
DDR_A_D30 N9 AG3 DDRA_ODT1 DDR_B_D30 M2 AD4 DDRB_ODT1
SA_DQ[30] SA_ODT[1] DDRA_ODT1 11 SB_DQ[30] SB_ODT[1] DDRB_ODT1 12
DDR_A_D31 M7 AG2 DDR_B_D31 M1 AD5
DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A
DDR_A_D32 AG6 SA_DQ[31] RSVD_TP[9] AH2 DDR_B_D32 AM5 SB_DQ[31] RSVD_TP[19] AE5
DDR_A_D33 AG5 SA_DQ[32] RSVD_TP[10] DDR_B_D33 AM6 SB_DQ[32] RSVD_TP[20]
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
C SA_DQ[36] DDR_A_DQS#[0..7] 11 SB_DQ[36] DDR_B_DQS#[0..7] 12 C
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D37 AN2 D7 DDR_B_DQS#0
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
SA_DQ[48] DDR_A_DQS[0..7] 11 SB_DQ[48] DDR_B_DQS[0..7] 12
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
SA_DQ[59] DDR_A_MA[0..15] 11 SB_DQ[59]
DDR_A_D60 AL14 DDR_B_D60 AT12
SA_DQ[60] SB_DQ[60] DDR_B_MA[0..15] 12
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
DDR_A_BS0 AE10 SA_MA[6] W6 DDR_A_MA7 DDR_B_BS0 AA9 SB_MA[6] R2 DDR_B_MA7
B 11 DDR_A_BS0 SA_BS[0] SA_MA[7] 12 DDR_B_BS0 SB_BS[0] SB_MA[7] B
DDR_A_BS1 AF10 V1 DDR_A_MA8 DDR_B_BS1 AA7 T5 DDR_B_MA8
11 DDR_A_BS1 SA_BS[1] SA_MA[8] 12 DDR_B_BS1 SB_BS[1] SB_MA[8]
DDR_A_BS2 V6 W5 DDR_A_MA9 DDR_B_BS2 R6 R3 DDR_B_MA9
11 DDR_A_BS2 SA_BS[2] SA_MA[9] 12 DDR_B_BS2 SB_BS[2] SB_MA[9]
AD8 DDR_A_MA10 AB7 DDR_B_MA10
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
DDR_A_CAS# AE8 SA_MA[12] AF8 DDR_A_MA13 DDR_B_CAS# AA10 SB_MA[12] AB10 DDR_B_MA13
11 DDR_A_CAS# SA_CAS# SA_MA[13] 12 DDR_B_CAS# SB_CAS# SB_MA[13]
DDR_A_RAS# AD9 V5 DDR_A_MA14 DDR_B_RAS# AB8 R5 DDR_B_MA14
11 DDR_A_RAS# SA_RAS# SA_MA[14] 12 DDR_B_RAS# SB_RAS# SB_MA[14]
DDR_A_WE# AF9 V7 DDR_A_MA15 DDR_B_WE# AB9 R4 DDR_B_MA15
11 DDR_A_WE# SA_WE# SA_MA[15] 12 DDR_B_WE# SB_WE# SB_MA[15]
m
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE
co
@ @
+1.5V
RC75
1
.
0_0402_5%
1 2 RC76
ts
@ 1K_0402_5%
RC77
2
QC3 1K_0402_5%
S
5 H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2

SM_DRAMRST# 11,12
re
2
BSS138_NL_SOT23-3
RC78
G
2
4.99K_0402_1%
A A
ec
1
11,17 DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL

RC73 0_0402_5%
1 2
31 DRAMRST_CNTRL_EC
RC74 @ 0_0402_5% 1
irs
CC37 2010/09/03 2012/12/31 Title

0.047U_0402_25V6K
Issued Date Deciphered Date
Sandy Bridge_DDR3
2 Size Document Number Rev
Custom 0.2
QFKAA
pa
5 4 3 2 1
re
op
pt
.la
w
w
w
5 4 3 2 1
+CPU_CORE
JCPUF POWER +1.05VS_VCCP
D D
97A
AG35 8.5A
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
AG31 VCC4 VCCIO3 AC10
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF32 VCC13 VCCIO12 H14
AF29 VCC16 VCCIO15 G14
PEG AND DDR
AF26 VCC19 VCCIO18 F14

AD35 VCC20 VCCIO19 F13
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
C AC35 VCC30 VCCIO28 D11 C
AC34 VCC31 VCCIO29 C14
AC30 VCC35 VCCIO33 B14
AC29 VCC36 VCCIO34 B12
AC28 VCC37 VCCIO35 A14
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
CORE SUPPLY
Y34 VCC51 +1.05VS_VCCP +1.05VS_VCCP

Y33 VCC52
Y32 VCC53 0.1U_0402_10V7K 0.1U_0402_10V7K
Y31 VCC54 1 2 1 2
Y30 VCC55 CC50 CC49
VCC56
1
Y29 @ @
Y28 VCC57 RC91 RC89
Y27 VCC58 130_0402_5% 75_0402_5%
Y26 VCC59
V35 VCC60
2
V34 VCC61 AJ29 H_CPU_SVIDALRT# 1 2

SVID
VCC62 VIDALERT# VR_SVID_ALRT# 42

B V33 AJ30 H_CPU_SVIDCLK RC90 1 2 43_0402_1% B
VCC63 VIDSCLK VR_SVID_CLK 42
V32 AJ28 H_CPU_SVIDDAT RC88 1 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT 42
V31 RC92 0_0402_5%
V30 VCC65
VCC66 Pull high resistor on VR side
V29
V28 VCC67
V27 VCC68
V26 VCC69
U35 VCC70
VCC71
om
U34
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77
U27 VCC78 +CPU_CORE
U26 VCC79
VCC80
.c
R35
R34 VCC81
VCC82
2
R33
R32 VCC83 RC93
VCC84 Close to CPU
R31 100_0402_1%
VCC85
ts
R30
R29 VCC86
1
R28 VCC87
SENSE LINES
R27 VCC88 AJ35 VCCSENSE_R RC94 1 2 0_0402_5%

VCC89 VCC_SENSE VCCSENSE 42
R26 AJ34 VSSSENSE_R RC95 1 2 0_0402_5%
VCC90 VSS_SENSE VSSSENSE 42
P35
P34 VCC91
VCC92 re
1
P33
P32 VCC93 B10 VCCIO_SENSE RC97
VCC94 VCCIO_SENSE VCCIO_SENSE 39
A P31 A10 100_0402_1% A
P30 VCC95 VSS_SENSE_VCCIO
ec
VCC96
1
P29
2
P28 VCC97 RC96 RC98

P27 VCC98 10_0402_1% 10_0402_1%
P26 VCC99
VCC100
2

irs
+1.05VS_VCCP
Close to CPU Sandy Bridge_POWER-1
Custom 0.2
TYCO_2013620-2_IVY BRIDGE
QFKAA
pa
5 4 3 2 1
@
re
op
pt
.la
w
w
w
5 4 3 2 1
+GFX_CORE
1
+GFX_CORE
JCPUG
POWER RC105
10_0402_1%
Close to CPU
33A
2
AT24 AK35 VCC_AXG_SENSE
SENSE
LINES
VAXG1 VAXG_SENSE VCC_AXG_SENSE 42
AT23 AK34 VSS_AXG_SENSE
D VAXG2 VSSAXG_SENSE VSS_AXG_SENSE 42
AT21 D
AT20 VAXG3 1 RC106 2
AT18 VAXG4 10_0402_1%
AT17 VAXG5
AR24 VAXG6 +V_SM_VREF should
AR23 VAXG7 have 20 mil trace width +1.5V_CPU
AR21 VAXG8 RC120
AR20 VAXG9 1 1K_0402_0.5%
2
AR18 VAXG10 AL1 +V_SM_VREF
AR17 VAXG11 SM_VREF 1 1K_0402_0.5%
2
AP24 VAXG12 RC109
1
VREF
AP23 VAXG13
AP21 VAXG14 CC65
AP20 VAXG15 B4 0.1U_0402_10V7K
VAXG16 SA_DIMM_VREFDQ +VREF_DQA_M3 2
AP18 D1 +VREF_DQB_M3
AP17 VAXG17 SB_DIMM_VREFDQ
AN24 VAXG18 +1.5V_CPU Decoupling:
VAXG19
AN23
AN21 VAXG20 1X 330U (6m ohm), 6X 10U
AN20 VAXG21 +1.5V_CPU
AN18 VAXG22
VAXG23 5A
DDR3 -1.5V RAILS

AN17
AM24 VAXG24 AF7 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
GRAPHICS
AM23 VAXG25 VDDQ1 AF4
VAXG26 VDDQ2 1 ESR 6mohm
AM21 AF1 1 1 1 1 1 1
AM20 VAXG27 VDDQ3 AC7 CC55 CC56 CC51 CC57 CC52 CC53 + CC54
AM18 VAXG28 VDDQ4 AC4 @
AM17 VAXG29 VDDQ5 AC1 330U_D2_2VM_R6M
AL24 VAXG30 VDDQ6 Y7 2 2 2 2 2 2 2
AL23 VAXG31 VDDQ7 Y4
AL21 VAXG32 VDDQ8 Y1 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
AL20 VAXG33 VDDQ9 U7
C AL18 VAXG34 VDDQ10 U4 C
AL17 VAXG35 VDDQ11 U1
AK24 VAXG36 VDDQ12 P7
AK20 VAXG39 VDDQ15
AK18 VAXG40 +VCCSA Decoupling:
VAXG41
AK17
AJ24 VAXG42 1X 330U (6m ohm), 3X 10U
AJ23 VAXG43
AJ21 VAXG44 +VCCSA
VAXG45 Bottom Socket Cavity Co-lay for Cost Down Plan
AJ20
AJ18 VAXG46 6A VCCSA_VID0 VCCSA_VID1 +VCCSA
AJ17 VAXG47 M27 10U_0805_10V6K 10U_0805_10V6K
AH24 VAXG48 VCCSA1 M26
SA RAIL
AH23 VAXG49 VCCSA2 L26 1 2+VCCSA_SENSE
VAXG50 VCCSA3 0 0 0.90 V For Sandy Bridge
AH21
VAXG51 VCCSA4
J26 1 1 1 1 1 RC189 0_0402_5%
AH20 J25 CC40 CC41 CC42 CC43
AH18 VAXG52 VCCSA5 J24 + CC44
VAXG53 VCCSA6 0 1 0.80 V
AH17 H26 @ @
VAXG54 VCCSA7 H25 2 2 2 2 330U_D2_2VM_R6M
VCCSA8 2
1 0 0.75 V
10U_0805_10V6K 10U_0805_10V6K
VCCPLL Decoupling: Bottom Socket Edge 1 1 0.65 V
1X 330U (6m ohm), 1X 10U, 2x1U
1.8V RAIL
+1.8VS H23
VCCSA_SENSE +VCCSA_SENSE 41
RC119 1.5A 1 RC111 2
2 1 10U_0805_10V6K +1.8VS_VCCPLL B6 0_0402_5% @
0_0805_5% A6 VCCPLL1 C22 H_VCCSA_VID0
MISC
VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 41

1 A2 C24 H_VCCSA_VID1 Please kindly check whether
B VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 41 B
1 1 1 pull down by 10k in PWR-Side
+ CC58 CC59 CC60 CC61
@
1U_0402_6.3V6K A19
2 2 2 2 VCCIO_SEL
330U_B2_2.5VM_R15M 1U_0402_6.3V6K TYCO_2013620-2_IVY BRIDGE

@
+1.5V_CPU +1.5VS C464
om
PJ1 @ 4.7U_0805_10V4Z
2 1 1 2
+1.5V_CPU +1.5V 2 1
JUMP_43X118 C463
Vgs=10V,Id=14.5A,Rds=6mohm +1.5V 1 2
CC46 1 2 0.1U_0402_10V7K QC4
1 8 1U_0402_6.3V6K
CC47 1 2 0.1U_0402_10V7K 2 S D 7 1 2
S D
2
1 3 6 C469
S D
.c
CC48 1 2 0.1U_0402_10V7K RC192 CC68 4 5 4.7U_0805_10V4Z
470_0805_5% 10U_0805_10V6K G D
CC45 1 2 0.1U_0402_10V7K FDS6676AS_SO8 RC193
2 RUN_ON_CPU1.5VS3 1 2 +VSB
3 1
220K_0402_5%
ts
6
QC5B 1
CC69 RC194 QC5A
SUSP 5 0.1U_0402_25V6 820K_0402_5%
2 SUSP
2 SUSP 5,34
re 2N7002DW-T/R7_SOT363-6
2
4
2N7002DW-T/R7_SOT363-6
1
A A
ec
irs
Sandy Bridge_POWER-2
Custom 0.2
QFKAA
pa
5 4 3 2 1
re
op
pt
.la
w
w
w
5 4 3 2 1
CFG Straps for Processor

JCPUH JCPUI JCPUE (CFG[17:0] internal pull high to VCCIO)
AT35 AJ22
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22 AH27 PAD T3
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19 AK28 VCC_DIE_SENSE AH26
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30 AK29 CFG[0] VSS_DIE_SENSE
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27 AL26 CFG[1]
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24 AL27 CFG[2]
AT16 VSS7 VSS87 AJ3 T30 VSS165 VSS238 E21 CFG4 AK26 CFG[3] L7
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18 AL29 CFG[4] RSVD28 AG7
AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15 AL30 CFG[5] RSVD29 AE7
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13 AM31 CFG[6] RSVD30 AK2
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10 AM32 CFG[7] RSVD31
D AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9 AM30 CFG[8] W8 D
CFG
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8 AM28 CFG[9] RSVD32
AR22 VSS14 VSS94 AH29 P6 VSS172 VSS245 E7 AM26 CFG[10]
AR19 VSS15 VSS95 AH28 P5 VSS173 VSS246 E6 AN28 CFG[11] AT26
VSS16 VSS96 VSS174 VSS247 CFG[12] RSVD33
PEG Static Lane Reversal - CFG2 is for the 16x
AR16 AH25 P3 E5 AN31 AM33
AR13 VSS17 VSS98 AH22 P2 VSS175 VSS248 E4 AN26 CFG[13] RSVD34 AJ27
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3 AM27 CFG[14] RSVD35
1: Normal Operation; Lane # definition matches
AR7
AR4
VSS19
VSS20
VSS21
VSS100
VSS101
VSS102
AH16
AH7
N34
N33
VSS177
VSS178
VSS179
VSS250
VSS251
VSS252
E2
E1
AK31
AN29
CFG[15]
CFG[16]
CFG[17] CFG2
* socket pin map definition
AR2 AH4 N32 D35
AP34 VSS22 VSS103 AG9 N31 VSS180 VSS253 D32
VSS23 VSS104 VSS181 VSS254 0:Lane Reversed
AP31 AG8 N30 D29 T8
AP28 VSS24 VSS105 AG4 N29 VSS182 VSS255 D26 RSVD37 J16
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20 AJ31 RSVD38 H16 CFG4
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17 AH31 VAXG_VAL_SENSE RSVD39 G16
VSS27 VSS108 VSS185 VSS258 VSSAXG_VAL_SENSE RSVD40
1
AP19 AF3 N26 C34 AJ33
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31 AH33 VCC_VAL_SENSE RC82
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28 VSS_VAL_SENSE 1K_0402_1%
AP10 VSS30 VSS111 AE34 L30 VSS188 VSS261 C27 @
AP7 VSS31 VSS112 AE33 L27 VSS189 VSS262 C25 AJ26 AR35
2
AP4 VSS32 VSS113 AE32 L9 VSS190 VSS263 C23 RSVD5 RSVD_NCTF1 AT34
RESERVED
AP1 VSS33 VSS114 AE31 L8 VSS191 VSS264 C10 RSVD_NCTF2 AT33
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1 RSVD_NCTF3 AP35
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22 RSVD_NCTF4 AR34
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19 RSVD_NCTF5
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15 F25
RSVD8
Embedded Display Port Presence Strap
AN16 AE9 L1 B13 F24
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11 F23 RSVD9
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9 D24 RSVD10 B34 1 : Disabled; No Physical Display Port
AN7
AN4
VSS42
VSS43
VSS44
VSS123
VSS124
VSS125
AC8
AC6
K29
K26
VSS200
VSS201
VSS202
VSS273
VSS274
VSS275
B8
B7
G25
G24
RSVD11
RSVD12
RSVD13
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
A33
A34 * attached to Embedded Display Port
AM29 AC5 J34 B5 E23 B35 CFG4
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3 D23 RSVD14 RSVD_NCTF9 C35
C VSS46 VSS127 VSS204 VSS277 RSVD15 RSVD_NCTF10 0 : Enabled; An external Display Port device is C
AM22 AC2 H33 B2 C30
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35 A31 RSVD16 connected to the Embedded Display Port
AM16 VSS48 VSS129 AB34 H27 VSS206 VSS279 A32 B30 RSVD17
AM13 VSS49 VSS130 AB33 H24 VSS207 VSS280 A29 B29 RSVD18
AM10 VSS50 VSS131 AB32 H21 VSS208 VSS281 A26 D30 RSVD19 AJ32
AM7 VSS51 VSS132 AB31 H18 VSS209 VSS282 A23 B31 RSVD20 RSVD51 AK32
AM4 VSS52 VSS133 AB30 H15 VSS210 VSS283 A20 A30 RSVD21 RSVD52
AM3 VSS53 VSS134 AB29 H13 VSS211 VSS284 A3 C29 RSVD22
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285 RSVD23
AM1 VSS55 VSS136 AB27 H9 VSS213 AN35
AL34 VSS56 VSS137 AB26 H8 VSS214 J20 BCLK_ITP AM35
AL31 VSS57 VSS138 Y9 H7 VSS215 B18 RSVD24 BCLK_ITP#
AL28 VSS58 VSS139 Y8 H6 VSS216 RSVD25
AL25 VSS59 VSS140 Y6 H5 VSS217
AL22 VSS60 VSS141 Y5 H4 VSS218
AL19 VSS61 VSS142 Y3 H3 VSS219 J15 AT2
AL16 VSS62 VSS143 Y2 H2 VSS220 RSVD27 RSVD_NCTF11 AT1
AL13 VSS63 VSS144 W35 H1 VSS221 RSVD_NCTF12 AR1
AL10 VSS64 VSS145 W34 G35 VSS222 RSVD_NCTF13
AL7 VSS65 VSS146 W33 G32 VSS223
AL4 VSS66 VSS147 W32 G29 VSS224
AL2 VSS67 VSS148 W31 G26 VSS225 B1 PAD T64
AK33 VSS68 VSS149 W30 G23 VSS226 KEY
VSS69 VSS150 VSS227
PCIE Port Bifurcation Straps
AK30 W29 G20
AK27 VSS70 VSS151 W28 G17 VSS228
AK25 VSS71 VSS152 W27 G11 VSS229
11: (Default) x16 - Device 1 functions 1 and 2 disabled
AK22
AK19
VSS72
VSS73
VSS74
VSS153
VSS154
VSS155
W26
U9
F34
F31
VSS230
VSS231
VSS232
TYCO_2013620-2_IVY BRIDGE *10: x8, x8 - Device 1 function 1 enabled ; function 2
AK16 U8 F29 @
AK13 VSS75 VSS156 U6 VSS233
CFG[6:5] disabled
AK10 VSS76 VSS157 U5
VSS77 VSS158 01: Reserved - (Device 1 function 1 disabled ; function
AK7 U3
AK4 VSS78 VSS159 U2 2 enabled)
AJ25 VSS79 VSS160
B VSS80 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled B
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE
@ @
om
PEG DEFER TRAINING
.c
1: (Default) PEG Train immediately following xxRESETB
CFG7 de assertion
s
0: PEG Wait for BIOS for training
A
r et A
ec
irs

Sandy Bridge_GND/RSVD/CFG
Custom 0.2
pa
5 4 3 2 1
re
op
pt
.la
w
w
w
5 4 3 2 1
+1.5V +1.5V
1
JDDR3L
2
DDR3 SO-DIMM A
+VREF_DQA
DDR_A_D0
3
5
VREF_DQ
VSS
VSS
DQ4
4
6
DDR_A_D4
DDR_A_D5
Reverse Type DDR_A_DQS[0..7] 7
DDR_A_D1 7 DQ0 DQ5 8 DDR_A_DQS#[0..7] 7

1 1 DQ1 VSS
CD1 CD2 9 10 DDR_A_DQS#0
VSS DQS0# DDR_A_D[0..63] 7
11 12 DDR_A_DQS0
DM0 DQS0
2.2U_0603_6.3V4Z
0.1U_0402_10V7K
13 14 DDR_A_MA[0..15] 7
2 2 DDR_A_D2 15 VSS VSS 16 DDR_A_D6
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7 +1.5V
19 DQ3 DQ7 20
DDR_A_D8 21 VSS VSS 22 DDR_A_D12
1
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
D
25 DQ9 DQ13 26 RD1
D
DDR_A_DQS#1 27 VSS VSS 28 1K_0402_1%
DDR_A_DQS1 29 DQS1# DM1 30 SM_DRAMRST#
Close to JDDRL.1 31 DQS1 RESET# 32 SM_DRAMRST# 7,12
Intel DDR Vref M3
2
DQ10 DQ14 +VREF_DQA
DDR_A_D11 35 36 DDR_A_D15 2 @ 1
DQ11
1
37 DQ15 38 0_0402_5%
DDR_A_D16 39 VSS VSS 40 DDR_A_D20 RC115 RD2
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21 1K_0402_1%
43 DQ17 DQ21 44 BSS138_NL_SOT23-3
DDR_A_DQS#2 45 VSS VSS 46 QC7
2
DQS2# DM2
D
DDR_A_DQS2 47 48 3 1
DQS2 VSS +VREF_DQA_M3 +VREF_DQA
49 50 DDR_A_D22
DDR_A_D18 51 VSS DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
G
2
55 DQ19 VSS 56 DDR_A_D28
DDR_A_D24 57 VSS DQ28 58 DDR_A_D29 RH100
DDR_A_D25 59 DQ24 DQ29 60 2 1
61 DQ25 VSS 62 DDR_A_DQS#3 DRAMRST_CNTRL_PCH 7,17 +1.5V
63 VSS DQS3# 64 DDR_A_DQS3 10K_0402_5%
2
DM3 DQS3
G
65 66
VSS VSS
1
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31 3 1 RD10
DQ27 DQ31 +VREF_DQB_M3 +VREF_DQB
71 72
D
1K_0402_1%
VSS VSS QC8
BSS138_NL_SOT23-3
2
DDRA_CKE0 73 74 DDRA_CKE1
7 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 7 2
75 76 @ 1 +VREF_DQB
77 VDD VDD 78 DDR_A_MA15 0_0402_5%
C DDR_A_BS2 79 NC A15 80 DDR_A_MA14 RC116 C
7 DDR_A_BS2
1
1
81 BA2 A14 82 D
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11 QC9 2 RD11
A12/BC# A11 H_SNB_IVB# 5,21
DDR_A_MA9 85 86 DDR_A_MA7 BSS138_NL_SOT23-3 G 1K_0402_1%
87 A9 A7 88 S
3
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
2
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
DDRA_CLK0 101 VDD VDD 102 DDRA_CLK1 +1.5V
7 DDRA_CLK0 DDRA_CLK0# 103 CK0 CK1 104 DDRA_CLK1# DDRA_CLK1 7
7 DDRA_CLK0# 105 CK0# CK1# 106 DDRA_CLK1# 7 1 2
DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1 +1.5V CD50 33P_0402_50V8K
DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS# DDR_A_BS1 7
7 DDR_A_BS0 111 BA0 RAS# 112 DDR_A_RAS# 7 1 2
1
DDR_A_WE# 113 VDD VDD 114 DDRA_SCS0# CD51 33P_0402_50V8K
7 DDR_A_WE# DDR_A_CAS# 115 WE# S0# 116 DDRA_ODT0 DDRA_SCS0# 7
RD6
7 DDR_A_CAS# 117 CAS# ODT0 118 DDRA_ODT0 7 1 2
1K_0402_1%
DDR_A_MA13 119 VDD VDD 120 DDRA_ODT1 CD52 33P_0402_50V8K
DDRA_SCS1# 121 A13 ODT1 122 DDRA_ODT1 7
2
7 DDRA_SCS1# 123 S1# NC 124 1 2
125 VDD VDD 126 +VREF_CAA +VREF_CAA_DIMMA CD53 33P_0402_50V8K
127 TEST VREF_CA 128
1
DDR_A_D32 129 VSS VSS 130 DDR_A_D36 1 2
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37 RD7 CD54 33P_0402_50V8K
133 DQ33 DQ37 134 1K_0402_1%
DDR_A_DQS#4 135 VSS VSS 136 1 2
DDR_A_DQS4 137 DQS4# DM4 138 CD55 33P_0402_50V8K
1 1
2
B DQS4 VSS B
139 140 DDR_A_D38 CD15 CD16
DQ34 DQ39
2.2U_0603_6.3V4Z
0.1U_0402_10V7K
DDR_A_D35 143 144

145 DQ35 VSS 146 DDR_A_D44 2 2
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_A_DQS#5
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
153 VSS DQS5# 154 DDR_A_DQS5 Place near JDDRL Command and Control signals of DIMMA Place near JDDRL1.203 and 204
m
155 DM5 DQS5 156
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
close to JDDRL.126 +1.5V
DDR_A_D48 163 VSS VSS 164 DDR_A_D52 +1.5V +0.75VS
co
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53 1 2
167 DQ49 DQ53 168 CD7 + 330U_2.5V_M
DDR_A_DQS#6 169 VSS VSS 170 CD20 1 2 0.1U_0402_10V7K CD56 1 2 10U_0603_6.3V6M
DDR_A_DQS6 171 DQS6# DM6 172 CD8 1 2 10U_0603_6.3V6M
173 DQS6 VSS 174 DDR_A_D54 CD17 1 2 0.1U_0402_10V7K
DDR_A_D50 175 VSS DQ54 176 DDR_A_D55 CD9 1 2 10U_0603_6.3V6M CD24 2 1 1U_0402_6.3V6K
.
DDR_A_D51 177 DQ50 DQ55 178 CD18 1 2 0.1U_0402_10V7K
179 DQ51 VSS 180 DDR_A_D60 CD10 1 2 10U_0603_6.3V6M CD21 2 1 1U_0402_6.3V6K
ts
DDR_A_D56 181 VSS DQ60 182 DDR_A_D61 CD19 1 2 0.1U_0402_10V7K
DDR_A_D57 183 DQ56 DQ61 184 CD11 1 2 10U_0603_6.3V6M CD22 2 1 1U_0402_6.3V6K
185 DQ57 VSS 186 DDR_A_DQS#7
187 VSS DQS7# 188 DDR_A_DQS7 CD12 1 2 10U_0603_6.3V6M CD23 2 1 1U_0402_6.3V6K
DM7 DQS7
A
RD8 1
DDR_A_D58
DDR_A_D59
10K_0402_5%
2
189
191
193
195
197
199
VSS
DQ58
DQ59
VSS
SA0
VSS
DQ62
DQ63
VSS
EVENT#
190
192
194
196
198
200
DDR_A_D62
DDR_A_D63
PM_SMBDATA
CD13 1
re
2 10U_0603_6.3V6M
A
ec
+3VS 201 VDDSPD SDA 202 PM_SMBCLK PM_SMBDATA 12,17,26
0.1U_0402_10V7K
2.2U_0603_6.3V4Z
203 SA1 SCL 204 PM_SMBCLK 12,17,26

1 1 +0.75VS +0.75VS
1
CD26 VTT VTT

CD25 205 206
RD9 207 GND1 GND2 208
2 2 10K_0402_5% BOSS1 BOSS2 Security Classification Compal Secret Data Compal Electronics, Inc.
irs

2
LCN_DAN06-K4406-0103
@
DDRIII-SODIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
QFKAA
pa

5 4 3 2 1
re
op
pt
.la
w
w
w
A B C D E
+1.5V +1.5V
JDDR3H
1 2
+VREF_DQB
DDR_B_D0
3
5
VREF_DQ
VSS
VSS
DQ4
4
6
DDR_B_D4
DDR_B_D5
Reverse Type
DDR_B_D1 7
9
DQ0
DQ1
DQ5
VSS
8
10 DDR_B_DQS#0
DDR3 SO-DIMM B
11 VSS DQS0# 12 DDR_B_DQS0
13 DM0 DQS0 14
1 1 VSS VSS
CD28 CD27 DDR_B_D2 15 16 DDR_B_D6
DQ2 DQ6 DDR_B_DQS#[0..7] 7
DDR_B_D3 17 18 DDR_B_D7
DQ3 DQ7
2.2U_0603_6.3V4Z
0.1U_0402_10V7K
19 20
2 2 DDR_B_D8 21 VSS VSS 22 DDR_B_D12 DDR_B_DQS[0..7] 7
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
1 DQ9 DQ13 DDR_B_D[0..63] 7 1
25 26
DDR_B_DQS#1 27 VSS VSS 28
DQS1# DM1 DDR_B_MA[0..15] 7
DDR_B_DQS1 29 30 SM_DRAMRST#
31 DQS1 RESET# 32 SM_DRAMRST# 7,11
DDR_B_D10 33 VSS VSS 34 DDR_B_D14
Close to JDDRH.1 37 DQ11 DQ15 38
43 DQ17 DQ21 44
DDR_B_DQS2 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_B_D22
DDR_B_D18 51 VSS DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS 56 DDR_B_D28
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS 62 DDR_B_DQS#3
65 DM3 DQS3 66
71 DQ27 DQ31 72
VSS VSS
DDRB_CKE0 73 74 DDRB_CKE1
7 DDRB_CKE0 75 CKE0 CKE1 76 DDRB_CKE1 7
77 VDD VDD 78 DDR_B_MA15
2 DDR_B_BS2 79 NC A15 80 DDR_B_MA14 2
7 DDR_B_BS2 81 BA2 A14 82
DDR_B_MA12 83 VDD VDD 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
DDRB_CLK0 101 VDD VDD 102 DDRB_CLK1
7 DDRB_CLK0 DDRB_CLK0# 103 CK0 CK1 104 DDRB_CLK1# DDRB_CLK1 7
7 DDRB_CLK0# 105 CK0# CK1# 106 DDRB_CLK1# 7
DDR_B_MA10 107 VDD VDD 108 DDR_B_BS1 +1.5V
DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS# DDR_B_BS1 7
7 DDR_B_BS0 111 BA0 RAS# 112 DDR_B_RAS# 7
VDD VDD
1
DDR_B_WE# 113 114 DDRB_SCS0#
7 DDR_B_WE# DDR_B_CAS# 115 WE# S0# 116 DDRB_ODT0 DDRB_SCS0# 7
RD12
7 DDR_B_CAS# 117 CAS# ODT0 118 DDRB_ODT0 7
1K_0402_1%
DDR_B_MA13 119 VDD VDD 120 DDRB_ODT1
DDRB_SCS1# 121 A13 ODT1 122 DDRB_ODT1 7
2
7 DDRB_SCS1# 123 S1# NC 124
125 VDD VDD 126 +VREF_CAB +VREF_CAB_DIMMB
127 TEST VREF_CA 128
1
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37 RD13
133 DQ33 DQ37 134 1K_0402_1%
DQS4# DM4 1 1
DDR_B_DQS4 137 138 CD46 CD47
2
3 DQS4 VSS 3
139 140 DDR_B_D38
VSS DQ38
2.2U_0603_6.3V4Z
0.1U_0402_10V7K
DDR_B_D34 141 142 DDR_B_D39

DDR_B_D35 143 DQ34 DQ39 144 2 2
145 DQ35 VSS 146 DDR_B_D44
DDR_B_D41 149 DQ40 DQ45 150
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
m
155 DM5 DQS5 156 Place near JDDRH Command and Control signals of DIMMB Place near JDDRH.203 and 204
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
Close to JDDRH.126
161 DQ43 DQ47 162 +1.5V
DDR_B_D48 163 VSS VSS 164 DDR_B_D52 @ +1.5V +0.75VS
co
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53 CD31 1 2 330U_B2_2.5VM_R15M
+
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS VSS 170 CD33 1 2 0.1U_0402_10V7K CD57 1 2 10U_0603_6.3V6M
DDR_B_DQS6 171 DQS6# DM6 172 CD41 1 2 10U_0603_6.3V6M
173 DQS6 VSS 174 DDR_B_D54 CD29 1 2 0.1U_0402_10V7K
DDR_B_D50 175 VSS DQ54 176 DDR_B_D55 CD36 1 2 10U_0603_6.3V6M CD45 2 1 1U_0402_6.3V6K
.
DDR_B_D51 177 DQ50 DQ55 178 CD30 1 2 0.1U_0402_10V7K
179 DQ51 VSS 180 DDR_B_D60 CD37 1 2 10U_0603_6.3V6M CD42 2 1 1U_0402_6.3V6K
ts
DDR_B_D56 181 VSS DQ60 182 DDR_B_D61 CD32 1 2 0.1U_0402_10V7K
DDR_B_D57 183 DQ56 DQ61 184 CD38 1 2 10U_0603_6.3V6M CD43 2 1 1U_0402_6.3V6K
187 VSS DQS7# 188 DDR_B_DQS7 CD39 1 2 10U_0603_6.3V6M CD44 2 1 1U_0402_6.3V6K
DM7 DQS7
4
RD14 1
DDR_B_D58
DDR_B_D59
10K_0402_5%
2
189
191
193
195
197
199
VSS
DQ58
DQ59
VSS
SA0
VSS
DQ62
DQ63
VSS
EVENT#
190
192
194
196
198
200
DDR_B_D62
DDR_B_D63
PM_SMBDATA
CD40 1
re
2 10U_0603_6.3V6M
4
ec
+3VS 201 VDDSPD SDA 202 PM_SMBCLK PM_SMBDATA 11,17,26
1 RD15 2 203 SA1 SCL 204 PM_SMBCLK 11,17,26
2.2U_0603_6.3V4Z
1 1 +0.75VS +0.75VS
@ 10K_0402_5% VTT VTT
205 206
CD48 CD49 207 GND1 BOSS1 208
2 2 GND2 BOSS2 Security Classification Compal Secret Data Compal Electronics, Inc.
irs
0.1U_0402_10V7K Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

FOX_AS0A626-UASN-7F_204P
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
QFKAA
a

A B C D E
ep
o pr
pt
.la
w
w
w
A B C D E F G H
19 LCD_TXOUT0+ LCD_TXOUT0+ 19 LCD_TZOUT0+ LCD_TZOUT0+
LCD_TXOUT0- LCD_TZOUT0-
19 LCD_TXOUT0- 19 LCD_TZOUT0-
LCD_TXOUT1+ LCD_TZOUT1+
19 LCD_TXOUT1+ 19 LCD_TZOUT1+
LCD_TXOUT1- LCD_TZOUT1- +LCD_VDD +3VS
19 LCD_TXOUT1- 19 LCD_TZOUT1-
19 LCD_TXOUT2+ LCD_TXOUT2+ 19 LCD_TZOUT2+ LCD_TZOUT2+
1
19 LCD_TXOUT2- LCD_TXOUT2- 19 LCD_TZOUT2- LCD_TZOUT2- R109
150_0603_5% R108
1 LCD_TXCLK+ LCD_TZCLK+ 100K_0402_5% 1
19 LCD_TXCLK+ 19 LCD_TZCLK+
2
LCD_TXCLK- LCD_TZCLK- +3VS
19 LCD_TXCLK- 19 LCD_TZCLK-
2
6
LCD_EDID_CLK
19 LCD_EDID_CLK
2 W=80mils
19 LCD_EDID_DATA LCD_EDID_DATA Q1A C228
2N7002DW-T/R7_SOT363-6 2 0.1U_0402_10V7K
3
S
@ 1 1 2
R110 2 LCDPWR_GATE
G
Q17
For RF
1
C256 47P_0402_50V8J 47K_0402_5% 1 AO3413_SOT23
3
1 2 D
1
C230 +LCD_VDD
W=20mils CAM@ 0.01U_0402_25V7K W=80mils
0.1U_0402_10V7K 5 2
1 CAM@ 2 +3VS_LVDS_CAM 1 2 19 UMA_ENVDD
+3VS Q1B 1
R388 0_0603_5% C225 2N7002DW-T/R7_SOT363-6 C233
4
2
JLVDS 2 0.1U_0402_10V7K
1 1 R112
1 2 USB20_N11_R 3 100K_0402_5% 2
2 3 USB20_P11_R D84 AZ5125-02S.R7G_SOT23-3
3 4 @
1
4 5 INT_MIC_CLK
5 6 INT_MIC_CLK 30
INT_MIC_DATA 2A
6 7 INT_MIC_DATA 30
7 +LCD_VDD
8 1 1
8
1
9
9 10 C226 C227 C258
10 +3VS Reserve for EMI request
11 LCD_EDID_CLK 1 0.1U_0402_10V7K 4.7U_0805_10V4Z 47P_0402_50V8J
2
2 11 12 LCD_EDID_DATA 2 2 2
12 @
13 C248 For RF 1 2
13 14 LCD_TXOUT0- 0.1U_0402_10V7K R78 CAM@ 0_0402_5%
14 15 LCD_TXOUT0+ 2 WCM-2012-900T_0805
15 16 USB20_P11_R 4 3 USB20_P11 20
16 17 LCD_TXOUT1- LED_PWM 1 2 4 3
17 PCH_PWM 19
18 LCD_TXOUT1+ D17 RB751V40_SC76-2
18
1
19 USB20_N11_R 1 2 USB20_N11 20
19 20 LCD_TXOUT2- R131 1 2
20 21 LCD_TXOUT2+ 47K_0402_5% L55 @
21 22
22 23 LCD_TXCLK- 1 2
2
23 24 LCD_TXCLK+ R96 CAM@ 0_0402_5%

31 24 25 LED_PWM
32 GND1 25 26 BKOFF#_R
33 GND2 26 27
34 GND3 27 28
35 GND4 28 29 BKOFF#_R 1 2
GND5 29 1.5A BKOFF# 31
36 30 D15 RB751V40_SC76-2
GND6 30 +LCD_INV
1
1 2 R113
STARC_107K30-000001-G2 @ 10K_0402_5%
C257 47P_0402_50V8J
2
JLVDS1
12
GND 11
GND 10 LCD_TZOUT0-
3 10 9 LCD_TZOUT0+ 3
9 8 LCD_TZOUT1-
8 7 LCD_TZOUT1+
7 6 LCD_TZOUT2-
6 5 LCD_TZOUT2+
5
4
4
3
LCD_TZCLK-
LCD_TZCLK+
LVDS cable JLVDS1.2 need to contact GND
om
3 2
2 1 LVDS_SEL 17
1 B+
ACES_87036-1001-CP 1.5A For EMI

@ +LCD_INV B+
L2
2 1
.c
1 1 1 1
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1 1 FBMA-L11-201209-221LMA30T_0805
C247 C269 C489 C490
C234 C235 @ @ @ @
68P_0402_50V8J 0.1U_0402_25V6 2 2 2 2
ts
2 2
re
ec
4 4
rs

LVDS/eDP
ai
Custom 0.2
QFKAA
A B C D E F G H
r ep
op
pt
.la
w
w
w
A B C D E
CRT CONNECTOR
If=1A
+5VS +CRT_VCC_R +CRT_VCC
D6
2 F1 40 mils
1 1 2
1 3 RB491D_SOT23-3 1 1
0.5A_8V_KMC3S050RY
C237
0.1U_0402_10V7K
1 2 CRT_R_R L3 1 2 NBQ100505T-800Y_0402 CRT_R_L @ 2
19 UMA_CRT_R
R189 0_0402_5%
19 UMA_CRT_G
1 2 CRT_G_R L4 1 2 NBQ100505T-800Y_0402 CRT_G_L
R190 0_0402_5%
19 UMA_CRT_B
1 2 CRT_B_R L5 1 2 NBQ100505T-800Y_0402 CRT_B_L
R191 0_0402_5%
JCRT
6
11
T65 PAD
R138 R139 R140 CRT_R_L 1
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
7
150_0402_1%
150_0402_1%
150_0402_1%
1 1 1 1 1 1 1 1 1 1
1
CRT_DDC_DAT 12
C249 C250 C251 C238 C239 C240 C241 C242 C243 CRT_G_L 2
@ @ @ 8 G 16
2 2 2 2 2 2 2 2 2 HSYNC 13 17
CRT_B_L 3 G
2
2 9
+CRT_VCC
VSYNC 14
CHP3_SERDBG 4
21 CHP3_SERDBG
10
By EMI demand CRT_DDC_CLK 15
5
+CRT_VCC
SUYIN_070546FR015S251ZR
@
2 1 2 2
C244 0.1U_0402_10V7K 2 1
R141 10K_0402_5%
5
1 P
OE#
2 4 D_CRT_HSYNC 1 2 HSYNC
19 UMA_CRT_HSYNC A Y L6 10_0402_5%
G
U6 +CRT_VCC
SN74AHCT1G125GW_SOT353-5
3
D98 @
1 2 CRT_R_L 6 3 CRT_B_L
C252 I/O4 I/O2
0.1U_0402_10V7K
5
1
5 2
P
OE#
+CRT_VCC VDD GND
2 4 D_CRT_VSYNC 1 2 VSYNC
19 UMA_CRT_VSYNC A Y L7 10_0402_5%
10P_0402_50V8J
10P_0402_50V8J
1 1
G
U7
SN74AHCT1G125GW_SOT353-5 C245 C246 CRT_G_L 4 1 CHP3_SERDBG
3
@ @ I/O3 I/O1
2 2 AZC099-04S.R7G_SOT23-6
D97 @
CRT_DDC_CLK 6 3 HSYNC
I/O4 I/O2
5 2
3 +CRT_VCC VDD GND 3
+CRT_VCC CRT_DDC_DAT 4 1 VSYNC

I/O3 I/O1
+3VS AZC099-04S.R7G_SOT23-6
m
2/9: Add for ESD request
2
R153 R159
co
4.7K_0402_5% 4.7K_0402_5%
1
2
Q205A
19 UMA_CRT_CLK 1 6 CRT_DDC_CLK
.
5
2N7002DW-T/R7_SOT363-6
ts
Q205B
19 UMA_CRT_DATA 4 3 CRT_DDC_DAT
1 1
1 1 2N7002DW-T/R7_SOT363-6
C282
33P_0402_50V8K
@ 2
C285
33P_0402_50V8K
2@
re C284
470P_0402_50V8J
@ 2
C283
470P_0402_50V8J
2@
ec
4 4
irs

CRT
pa
0.2
QFKAA
A B C D E
re
op
pt
.la
w
w
w
5 4 3 2 1
D D
+3VS
+HDMI_5V_OUT
+HDMI_5V_OUT HDMI@
R145
HDMI_HPD_U 1 2 HDMI_HPD_C
2 1K_0402_5%
C264 2
2
0.1U_0402_10V7K R186 C265
1
HDMI@ U9 100K_0402_5% 0.1U_0402_10V7K
C 1 C
HDMI@ HDMI@
OE#
1
1
2 4 HDMI_HPD 1
R184 R185 A Y
1
G
CV308 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXC+ 2.2K_0402_5% 2.2K_0402_5% SN74AHCT1G125GW_SOT353-5
19 UMA_HDMI_TXC+
HDMI@ HDMI@ HDMI@
3
2
CV304 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXC-
19 UMA_HDMI_TXC- 19 UMA_HDMI_CLK
2
G
CV306 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXD0+
19 UMA_HDMI_TX0+
3 1 HDMI_SCLK
2
CV302 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXD0-
19 UMA_HDMI_TX0-
D
G
Q18
CV303 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXD1+ BSH111_SOT23-3
19 UMA_HDMI_TX1+ 3 1 HDMI@ HDMI_SDATA HDMI@
19 UMA_HDMI_DATA
CV301 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXD1- 2 1
19 UMA_HDMI_TX1- +3VS
D
R571
CV307 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXD2+ Q19 2.2K_0402_5%
19 UMA_HDMI_TX2+
BSH111_SOT23-3
CV305 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXD2- HDMI@ HDMI_HPD
19 UMA_HDMI_TX2- HDMI_HPD 19
HDMI_R_CK+ 1 HDMI@ 2
UMA_DVI_TXC- 1 @ 2 HDMI_R_CK- R195 680_0402_1%
R157 0_0402_5% HDMI_R_CK- 1 HDMI@ 2
L8 HDMI@ R197 680_0402_1% HDMI@
1 2 HDMI_R_D1- 1 HDMI@ 2 D53 F2
1 2 R198 680_0402_1% 2 1 +HDMI_5V_OUT_F 1 2
+5VS +HDMI_5V_OUT
HDMI_R_D1+ 1 HDMI@ 2 0.5A_8V_KMC3S050RY
1
4 3 R202 680_0402_1% PMEG2010AEH_SOD123 HDMI@ C259
4 3 HDMI_R_D0+ 1 HDMI@ 2 HDMI@
WCM-2012HS-670T_0805 R201 680_0402_1% 0.1U_0402_10V7K
UMA_DVI_TXC+ 1 @ 2 HDMI_R_CK+ D95 @ HDMI_R_D0- 1 HDMI@ 2 2
B B
R173 0_0402_5% HDMI_R_D1- 1 1 10 9 HDMI_R_D1- R203 680_0402_1%
HDMI_R_D2- 1 HDMI@ 2
HDMI_R_D1+2 2 9 8 HDMI_R_D1+ R205 680_0402_1%
UMA_DVI_TXD0- 1 @ 2 HDMI_R_D0- HDMI_R_D2+ 1 HDMI@ 2
R175 0_0402_5% HDMI_R_D2- 4 4 7 7 HDMI_R_D2- R206 680_0402_1%
1
L9 HDMI@ D
3 4 HDMI_R_D2+5 5 6 6 HDMI_R_D2+ +5VS 2 Q24
3 4 G 2N7002_SOT23-3
m
3 3 S HDMI@
3
2 1
2 1 8
WCM-2012HS-670T_0805
UMA_DVI_TXD0+ 1
R180
@ 2
0_0402_5%
HDMI_R_D0+
AZ1045-04F_DFN2510P10E-10-9 HDMI Connector
co
JHDMI
HDMI_HPD_C 19
UMA_DVI_TXD1- 1 @ 2 HDMI_R_D1- 18 HP_DET
+HDMI_5V_OUT +5V
R182 0_0402_5% 17
L10 HDMI@ D94 @ HDMI_SDATA 16 DDC/CEC_GND
1 2 HDMI_R_CK+1 1 SDA
10 9 HDMI_R_CK+ HDMI_SCLK 15
1 2
.
D96 @ 14 SCL
HDMI_R_CK- 2 2 Reserved
9 8 HDMI_R_CK- HDMI_HPD_C 6 3 HDMI_SDATA 13
ts
4 3 I/O4 I/O2 HDMI_R_CK- 12 CEC 20
4 3 HDMI_R_D0+4 4 CK- GND
7 7 HDMI_R_D0+ 11 21
WCM-2012HS-670T_0805 HDMI_R_CK+ 10 CK_shield GND 22
HDMI_R_D0- 5 5 CK+ GND
UMA_DVI_TXD1+ 1 @ 2 HDMI_R_D1+ 6 6 HDMI_R_D0- +5VS 5 2 HDMI_R_D0- 9 23
R183 0_0402_5% VDD GND 8 D0- GND
D0_shield
A
UMA_DVI_TXD2-
3
1
R187
L11
3
@ 2
0_0402_5%
HDMI@
4
4
HDMI_R_D2-
3 3
AZ1045-04F_DFN2510P10E-10-9
+HDMI_5V_OUT re 4
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
1 HDMI_SCLK
HDMI_R_D0+
HDMI_R_D1-
HDMI_R_D1+
HDMI_R_D2-
7
6
5
4
3
2
D0+
D1-
D1_shield
D1+
D2-
D2_shield
A
ec
HDMI_R_D2+ 1
D2+
2 1 2/9: Add for ESD request HONGL_13-13201904CP
2 1
2/9: Add for ESD request @
WCM-2012HS-670T_0805
UMA_DVI_TXD2+ 1 @ 2 HDMI_R_D2+
R188 0_0402_5%
irs

HDMI Conn./CEC
0.2
pa
5 4 3 2 1
re
op
pt
.la
w
w
w
5 4 3 2 1
UH1A
CMOS Setting, near DDR Door 2 1 A20 C38

JCMOS @ PCH_RTCX1 LPC_AD0
RTCX1 FWH0 / LAD0 LPC_AD0 28,31,32
+RTCVCC RH23 1 2 PCH_RTCRST# 1 2 CH2 15P_0402_50V8J A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 28,31,32
LPC
20K_0402_5% NOGCLK@ PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 28,31,32
1
10M_0402_5%
CH4 1 2 C37
NOGCLK@
LPC_AD3
FWH3 / LAD3 LPC_AD3 28,31,32
1U_0402_6.3V6K AZ_BITCLK_HD YH1 PCH_RTCRST# D20
RTCRST# D36
RH2
32.768KHZ_12.5P_1TJF125DP1A000D LPC_FRAME#
FWH4 / LFRAME# LPC_FRAME# 28,31,32
NOGCLK@ PCH_SRTCRST# G22
1
SRTCRST# E36 +3VS
iME Setting.
2
2 1 SM_INTRUDER# K22 LDRQ0# K36
RTC
JME @ 1
RH24 1 2PCH_SRTCRST# 1 2 CH3 15P_0402_50V8J INTRUDER# LDRQ1# / GPIO23
20K_0402_5% @ CH101 NOGCLK@ PCH_INTVRMEN C17 V5 SERIRQ SERIRQ 2 1
INTVRMEN SERIRQ SERIRQ 28,31
CH5 1 2 10P_0402_50V8J RH31 10K_0402_5%
1U_0402_6.3V6K 2
AM3 SATA_PRX_C_DTX_N0
SATA0RXN SATA_PRX_C_DTX_N0 25
D RH27 1 2 33_0402_5% AZ_BITCLK N34 AM1 SATA_PRX_C_DTX_P0 D
30 AZ_BITCLK_HD HDA_BCLK SATA0RXP SATA_PRX_C_DTX_P0 25 +3VS
AP7 SATA_PTX_DRX_N0
SATA 6G
Integrated SUS 1.05V VRM Enable AZ_SYNC L34 SATA0TXN AP5 SATA_PTX_DRX_P0
SATA_PTX_DRX_N0 25 HDD
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 25
High - Enable Internal VRs PCH_SPKR T10 AM10
30 PCH_SPKR SPKR SATA1RXN
PCH_INTVRMEN (must be always pulled high) AM8
RH30 1 2 33_0402_5% AZ_RST# K34 SATA1RXP AP11
30 AZ_RST_HD# HDA_RST# SATA1TXN AP10
SATA1TXP PCH_GPIO21 RH34 2 1 10K_0402_5%
+RTCVCC AZ_SDIN0_HD E34 AD7 SATA_PRX_C_DTX_N2
30 AZ_SDIN0_HD HDA_SDIN0 SATA2RXN SATA_PRX_C_DTX_N2 25
AD5 SATA_PRX_C_DTX_P2
SATA2RXP SATA_PRX_C_DTX_P2 25
RH12 1 2 SM_INTRUDER# G34 AH5 SATA_PTX_DRX_N2 PCH_GPIO19 RH28 1 2 10K_0402_5%
1M_0402_5% HDA_SDIN1 SATA2TXN AH4 SATA_PTX_DRX_P2
SATA_PTX_DRX_N2 25 ODD
SATA2TXP SATA_PTX_DRX_P2 25
RH33 1 2 PCH_INTVRMEN C34
330K_0402_5% HDA_SDIN2 AB8
PCH_SPK
IHDA
+3VS 2 @ 1 A34 SATA3RXN AB10
High = Enabled (No Reboot) +3VALW_PCH HDA_SDIN3 SATA3RXP
@ RH272 1K_0402_5% AF3
SATA3TXN
1 2 PCH_SPKR Low = Disabled (Default) SATA3TXP
AF1
RH36 1K_0402_5% RH32 1 2 33_0402_5% AZ_SDOUT A36
30 AZ_SDOUT_HD HDA_SDO Y7
SATA
SATA4RXN Y5
SATA4RXP +RTCVCC +RTCBATT
RH25 1 2 0_0402_5% C36 AD3
31 PWRME_CTRL HDA_DOCK_EN# / GPIO33 SATA4TXN
0.1U_0402_10V7K
RB751V-40_SOD323-2
AD1
DH1 NOGCLK@
N32 SATA4TXP
HDA_DOCK_RST# / GPIO13 1
Y3
CH8
SATA5RXN
1
1
Y1
HDA_SDO
8/30 Change PWRME_CTRL# to HDA_SDO by PCH EDS SATA5RXP AB3 DH7
PCH_JTAG_TCK J3 SATA5TXN AB1 2 RB751V-40_SOD323-2
JTAG_TCK SATA5TXP
ME debug mode,
PCH_JTAG_TMS H7 Y11
this signal has a weak internal pull down
2
2
JTAG_TMS SATAICOMPO
JTAG
K5 Y10 1 2
*Low = Disable (default)
High = Enable (flash descriptor security overide)
PCH_JTAG_TDI
JTAG_TDI SATAICOMPI
SATAICOMP
RH43 37.4_0402_1%
+1.05VS_VCC_SATA +RTCBATT +3VL
PCH_JTAG_TDO H1
JTAG_TDO AB12
C SATA3RCOMPO C
If use GCLK, please delet DH1
HDA_SYNC 1
RH26 GCLK@
2
SATA3COMPI
AB13 SATA3_COMP 1
RH48
2
49.9_0402_1%
+1.05VS_SATA3
*This signal has a weak internal pull

H=>On Die PLL is supplied by 1.5V
down 26 PCH_RTCX1_R
0_0402_5%
PCH_RTCX1
PCH_SPICLK T3
SPI_CLK SATA3RBIAS
AH1 RBIAS_SATA3 1 2
RH41 750_0402_1%
L=>On Die PLL is supplied by 1.8V PCH_SPICS0# Y14
SPI_CS0#
Placement near to YH1 +5VS
Need to pull high for Huron River platform PCH_SPICS1# T1 SATA_LED# 2 1
SPI_CS1#
SPI
+3VALW_PCH 2 1 AZ_SYNC P3 SATA_LED# 10K_0402_5% RH29
SATALED# SATA_LED# 33
RH55 1K_0402_5% 1 2
PCH_SPIDI V4 V14 PCH_GPIO21 20K_0402_5% RH35
+5VS SPI_MOSI SATA0GP / GPIO21
PCH_SPIDO U3 P1 PCH_GPIO19
PCH_GPIO19 20
2
SPI_MISO SATA1GP / GPIO19

G
QH1 BOOT BIOS Strap Bit 0

1 2 AZ_SYNC_R 3 1 PANTHER-POINT_FCBGA989
30 AZ_SYNC_HD
RH54 33_0402_5% PCHB0@
S
1 2 BSS138_NL_SOT23-3
RH56 1M_0402_5% 1 @ 2
RH274 0_0402_5%
+3VS
SPI ROM for BIOS & ME (4MByte )

1
1
47P_0402_50V8J UH3
CH19 CH6 8 4 4MB ROM P/N:
VCC VSS
@ 0.1U_0402_10V7K
SA00003K800
2
B 2 3 B
W
7
SA00004LI00
HOLD
For RF
PCH_SPICS0# 1
S
PCH_SPICLK 1 2 PCH_SPI0_CLK 6
RH66 33_0402_5% C
PCH_SPIDI 1 2 PCH_SPI0_DI 5 2 PCH_SPI0_DO 1 2 PCH_SPIDO
RH67 33_0402_5% D Q RH68 33_0402_5%
m
MX25L3205DM2I-12G SO8
Socket: SP07000F500/SP07000H900
Please place U13 & U4 close to U2 PCH,
co
please place RH66, RH67, RH68 near UH3
Please place RH267 near RH66, Please place RH271 near RH67,
Please place RH269 near RH68. +3VS 47P_0402_50V8J For RF +3VALW_PCH +3VALW_PCH +3VALW_PCH
1 2
s.
@ CH20
SPI ROM for Win8 (2MByte )
2
1
1
0.1U_0402_10V7K
1 2 RH46 RH45 RH38
UH4 CH100 200_0402_5% 200_0402_5% 200_0402_5%
PCH_SPICS1# 1 8 WIN8@
et
PCH_SPIDO 1 WIN8@ 2 PCH_SPI1_DO 2 CS# VCC 7 RH267 33_0402_5%
1
2
2
RH269 33_0402_5% +3VS 3 SO HOLD# 6 PCH_SPI1_CLK 1 WIN8@ 2 PCH_SPICLK PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI
4 WP# SCLK 5 PCH_SPI1_DI 1 2 PCH_SPIDI
GND SI
2
1
1
RH271 33_0402_5%
MX25L1606EM2I-12G_SO8 WIN8@ RH44 RH39 RH40
WIN8@ 100_0402_1% 100_0402_1% 100_0402_1%
A
2MB ROM P/N:
r A
1
2
2
ec
PCH_SPI0_CLK PCH_SPI1_CLK
for EMI for EMI
SA000041N00
1
RH65 SA00003FO10 RH69 1

RH50
2 PCH_JTAG_TCK
51_0402_1%
10_0402_5% 10_0402_5%
WIN8@
2
rs
CH7
1
CH21
1 Security Classification Compal Secret Data Compal Electronics, Inc.
10P_0402_50V8J 10P_0402_50V8J 2010/09/03 2012/12/31 Title
WIN8@
2 2 PCH_HDA/JTAG/SATA/SPI/LPC
i
Custom 0.2
pa
5 4 3 2 1
re
op
pt
.la
w
w
w
5 4 3 2 1
UH1B 2 RH72 1 2.2K_0402_5%

+3VALW_PCH +3VS
PCIE_PRX_C_LANTX_N1 BG34 2 RH70 1 2.2K_0402_5% RH102 4.7K_0402_5%
27 PCIE_PRX_C_LANTX_N1 PERN1
5
PCIE_PRX_C_LANTX_P1 BJ34 E12 PCH_SMBALERT# QH3B RH103 4.7K_0402_5%
27 PCIE_PRX_C_LANTX_P1 PERP1 SMBALERT# / GPIO11
LAN 27 PCIE_PTX_C_LANRX_N1 CH13 2 1 0.1U_0402_10V7K PCIE_PTX_LANRX_N1 AV32
CH11 2 1 0.1U_0402_10V7K PCIE_PTX_LANRX_P1 AU32 PETN1 H14 PCH_SMBCLK PCH_SMBDATA 3 4
27 PCIE_PTX_C_LANRX_P1 PETP1 SMBCLK PM_SMBDATA 11,12,26
2
PCIE_PRX_WLANTX_N2 BE34 C9 PCH_SMBDATA QH3A 2N7002DW-T/R7_SOT363-6
26 PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
PCIE_PRX_WLANTX_P2 BF34
26 PCIE_PRX_WLANTX_P2 PERP2
WLAN 26 PCIE_PTX_C_WLANRX_N2 CH14 2 1 0.1U_0402_10V7K PCIE_PTX_WLANRX_N2 BB32 PCH_SMBCLK 6 1
PETN2 PM_SMBCLK 11,12,26
26 PCIE_PTX_C_WLANRX_P2 CH17 2 1 0.1U_0402_10V7K PCIE_PTX_WLANRX_P2 AY32
PETP2
SMBUS
A12 DRAMRST_CNTRL_PCH 2N7002DW-T/R7_SOT363-6
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH 7,11
BG36
BJ36 PERN3 C8 PCH_SMLCLK0
AV34 PERP3 SML0CLK
D PETN3 D
AU34 G12 PCH_SMLDATA0 +3VALW_PCH 2 RH78 1 2.2K_0402_5% +3VS
PETP3 SML0DATA
BF36 2 RH74 1 2.2K_0402_5%
PERN4
5
BE36 QH4B
AY34 PERP4 C13 LAN_EN
PETN4 SML1ALERT# / PCHHOT# / GPIO74 LAN_EN 27
BB34 PCH_SMLDATA1 3 4
PETP4 EC_SMB_DA2 31
E14 PCH_SMLCLK1
SML1CLK / GPIO58
2
PCI-E*
BG37 QH4A 2N7002DW-T/R7_SOT363-6
BH37 PERN5 M16 PCH_SMLDATA1
AY36 PERP5 SML1DATA / GPIO75 PCH_SMLCLK1 6 1
PETN5 EC_SMB_CK2 31
BB36
PETP5 2N7002DW-T/R7_SOT363-6
BJ38
BG38 PERN6
AU36 PERP6 M7
Controller
AV36 PETN6 CL_CLK1
PETP6
Control Link only for support Intel IAMT.
Link
BG40 T11
BJ40 PERN7 CL_DATA1
AY40 PERP7 +3VALW_PCH
+3VS BB40 PETN7 P10
PETP7 CL_RST1#
RH99 1 2 10K_0402_5% PCH_GPIO20 BE38 PCH_SMBALERT# RH262 1 2 10K_0402_5%
BC38 PERN8
RH104 1 2 10K_0402_5% CLKREQ_WLAN# AW38 PERP8 DRAMRST_CNTRL_PCH RH76 1 2 1K_0402_5%
AY38 PETN8
RH95 1 210K_0402_5% CLKREQ_LAN# PETP8 LAN_EN RH75 1 2 10K_0402_5%
M10 PCH_GPIO47
CLK_LAN# Y40 PEG_A_CLKRQ# / GPIO47 PCH_SMLCLK0 RH73 2 1 2.2K_0402_5%
Intel Spec: 27 CLK_LAN# CLKOUT_PCIE0N
LAN CLK_LAN Y39
PCIECLK_RQ0# is suspend well, 27 CLK_LAN CLKOUT_PCIE0P AB37 PCH_SMLDATA0 RH77 2 1 2.2K_0402_5%
CLKOUT_PEG_A_N
but we pull high to +3VS CLKREQ_LAN# J2 AB38
CLOCKS
27 CLKREQ_LAN# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P PCH_GPIO47 2 1
C for LAN en/disable function RH89 10K_0402_5%
C
CLK_WLAN# AB49 AV22 CLK_CPU_DMI#

26 CLK_WLAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# 5
WLAN CLK_WLAN AB47 AU22 CLK_CPU_DMI
26 CLK_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5
CLKREQ_WLAN# M1
26 CLKREQ_WLAN# PCIECLKRQ1# / GPIO18 AM12
CLKOUT_DP_N AM13
AA48 CLKOUT_DP_P
AA47 CLKOUT_PCIE2N
CLKOUT_PCIE2P BF18 PCH_CLK_DMI# PCH_CLK_DMI# RH79 1 2 10K_0402_5%
PCH_GPIO20 V10 CLKIN_DMI_N BE18 PCH_CLK_DMI PCH_CLK_DMI RH82 1 2 10K_0402_5%
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
CLKIN_GND1# RH85 1 2 10K_0402_5%
Y37 CLKIN_GND1_N BJ30 CLKIN_GND1# CLKIN_GND1 RH86 1 2 10K_0402_5%
Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 CLKIN_GND1
CLKOUT_PCIE3P CLKIN_GND1_P
CLKIN_GND1_P CLK_DOT# RH80 1 2 10K_0402_5%
PCH_GPIO25 A8 CLK_DOT RH81 1 2 10K_0402_5%
PCIECLKRQ3# / GPIO25 G24 CLK_DOT#
CLKIN_DOT_96N E24 CLK_DOT From Clock Gen. CLK_SATA# RH83 1 2 10K_0402_5%
Y43 CLKIN_DOT_96P CLK_SATA RH84 1 2 10K_0402_5%
Y45 CLKOUT_PCIE4N
CLKOUT_PCIE4P AK7 CLK_SATA# CLK_14M_PCH RH87 1 2 10K_0402_5%
PCH_GPIO26 L12 CLKIN_SATA_N AK5 CLK_SATA
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
For EMI
V45 K45 CLK_14M_PCH
V46 CLKOUT_PCIE5N REFCLK14IN @
CLKOUT_PCIE5P CLK_PCILOOP 2 @ 1 2 1
PCH_GPIO44 L14 H45 CLK_PCILOOP RH124 10_0402_5% CH28 22P_0402_50V8J
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCILOOP 20
+3VALW_PCH
AB42 V47 PCH_X1
AB40 CLKOUT_PEG_B_N XTAL25_IN V49 PCH_X2
B Please place under DDR SODIMM. CLKOUT_PEG_B_P XTAL25_OUT B
RH107 1 210K_0402_5% PCH_GPIO26 10/25
PASSWORD_CLEAR# E6 RH37
RH110 1 210K_0402_5% PCH_GPIO25 PEG_B_CLKRQ# / GPIO56 1 2 PCH_X1
26 PCH_X1_R
1
JPW Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN 0_0402_5%

RH112 1 210K_0402_5% PCH_GPIO44 @ V40 XCLK_RCOMP RH115 90.9_0402_1% GCLK@
V42 CLKOUT_PCIE6N
2
RH119 1 210K_0402_5% CLKOUT_PCIE6P

PANEL_SEL Placement near to YH2
LVDS_SEL T13
13 LVDS_SEL PCIECLKRQ6# / GPIO45
om
RH114 1 210K_0402_5% PASSWORD_CLEAR#
V38 K43 CLK_FLEX0 T72 PAD NOGCLK@
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 RH117 2 1 1M_0402_5%
FLEX CLOCKS
CLKOUT_PCIE7P F47 CLK_FLEX1

CLKOUTFLEX1 / GPIO65 T74 PAD
PANEL_SEL K12 NOGCLK@
PCIECLKRQ7# / GPIO46 H47 CLK_FLEX2 YH2 25MHZ_20PF_7V25000016
CLKOUTFLEX2 / GPIO66 T73 PAD
AK14
+3VALW_PCH AK13 CLKOUT_ITPXDP_N K49 DGPU_PRSNT# PCH_X1 1 3 PCH_X2
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 1 3
GND GND
.c
1 1
1 2 LVDS_SEL PANTHER-POINT_FCBGA989 Compal common design SW request to CH26 CH27
RH116 10K_0402_5% PCHB0@ NOGCLK@ 2 4 NOGCLK@
add DGPU_Present on this GPIO67
27P_0402_50V8J 27P_0402_50V8J
2 2
ts
LVDS_SEL PANEL_SEL DGPU_PRSNT#
LVDS_SEL H L PANEL_SEL H L DGPU_PRSNT# H L
Channel
Single
(Default) Dual Channel LVDS EDP M/B SKU
e
UMA DIS/OPT
DGPU_PRSNT#
RH227
1 2
10K_0402_5%
+3VS
cr
1 @ 2
A RH261 10K_0402_5% A
e
rs

PCH_PCI-E/SMBUS/CLK
ai
Custom 0.2
QFKAA
5 4 3 2 1
p
re
op
pt
.la
w
w
w
5 4 3 2 1
UH1C
6 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 6
6 DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
6 DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
6 DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
+3VALW_PCH DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 6
BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 6
6 DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 6
6 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
D DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 6 D
6 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 6
6 DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20
2 1 PCH_SUSPWRDN#_R DMI3RXP BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 6
RH234 10K_0402_5% DMI_PTX_CRX_N0 AW24 BB14 FDI_CTX_PRX_P1
6 DMI_PTX_CRX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 6
2 1 RI# DMI_PTX_CRX_N1 AW20 BF14 FDI_CTX_PRX_P2
RH157 10K_0402_5% DMI_PTX_CRX_N2 BB18 BG13 FDI_CTX_PRX_P3
2 1 PCH_LOW_BAT# DMI_PTX_CRX_N3 AV18 BE12 FDI_CTX_PRX_P4
DMI
FDI
RH155 10K_0402_5% BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 6
DMI_PTX_CRX_P0 AY24 BJ10 FDI_CTX_PRX_P6
6 DMI_PTX_CRX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 6
DMI_PTX_CRX_P1 AY20 BH9 FDI_CTX_PRX_P7
6 DMI_PTX_CRX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 6
DMI_PTX_CRX_P2 AY18
6 DMI_PTX_CRX_P2 DMI2TXP
DMI_PTX_CRX_P3 AU18
6 DMI_PTX_CRX_P3 DMI3TXP
2 1 PCH_RSMRST# AW16 FDI_INT
FDI_INT FDI_INT 6
RH163 10K_0402_5% PCH_DPWROK 1 2 PCH_RSMRST#
2 1 PM_PWROK +1.05VS_PCH 1 2 DMI_COMP BJ24 AV12 FDI_FSYNC0 RH128 0_0402_5%
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 6
RH278 10K_0402_5% RH126 49.9_0402_1%
2 1 SYS_PWROK BG25 BC10 FDI_FSYNC1 Stuff R222 if do not support DeepSX state
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 6
RH279 10K_0402_5%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 6
RH127 750_0402_1%
BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 6
0_0402_5% Reserve this signal to EC by SW demand A18 DSWVREN +RTCVCC

1 @ RH280 2 DSWVRMEN
2011/10/18a
System Power Management

+3VS 1 @ 2 SUSACK#_R C12 E22 PCH_DPWROK DSWVREN RH150 2 1 330K_0402_5%
31 SUSACK# SUSACK# DPWROK
0.1U_0402_10V7K RH133 0_0402_5%
1 2 RH47 RH151 2 @ 1 330K_0402_5%
CH103 +3VS 2 1 XDP_DBRESET# K3 B9 EC_SWI#
SYS_RESET# WAKE# EC_SWI# 26,27
5
UH5 1K_0402_5%
C 1 C
31,42 VGATE
P
IN1 4 SYS_PWROK P12 N3 PCH_GPIO32

O SYS_PWROK CLKRUN# / GPIO32 DSWVREN must be always pulled high to +RTCVCC
5,31 PM_PWROK PM_PWROK 2
：：
IN2
G
DSWVREN - Internal Deep Sleep 1.05V regulator

SN74AHC1G08DCKR_SC70-5 PM_PWROK 1 2 PM_PWROK_R L22 G8 SUS_STAT# T76 PAD
* H Enable
3
RH131 0_0402_5% PWROK SUS_STAT# / GPIO61

32.768 KHz L Disable
L10 N14
APWROK SUSCLK / GPIO62 CLK_EC 31
DRAMPWROK B13 D10 PM_SLP_S5#

5 DRAMPWROK DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 31
SUSACK#_R 2 @ 1 PCH_SUSPWRDN#_R
RH281 0_0402_5% PCH_RSMRST# C21 H4 PM_SLP_S4#
31 PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# 31
Follow EC check list demand,
Stuff R137 if EC does not want to 1 @ 2 PCH_SUSPWRDN#_R K16 F4 PM_SLP_S3#
31 PCH_SUSPWRDN#
RH132 0_0402_5% SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# 31 but don't implement CLKRUN# this fuction
involve in the handshake mechanism
for the DeepSX state entry and exit 31 PBTN_OUT# PBTN_OUT# E20 G10 PM_SLP_A# T77 PAD
PWRBTN# SLP_A# +3VS
+3VALW_PCH 1 2 PCH_ACIN H20 G16 PM_SLP_SUS# T78 PAD

RH161 330K_0402_5% ACPRESENT / GPIO31 SLP_SUS# PCH_GPIO32 RH256 1 @ 2 8.2K_0402_5%
DH2 PCH_LOW_BAT# E10 AP14 H_PM_SYNC

BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5
1 2 1 2
31,36 ACIN RH160 10K_0402_5%
CH751H-40PT_SOD323-2 RI# A10 K14 PCH_GPIO29
RI# SLP_LAN# / GPIO29
Reserve this signal to EC by SW demand PANTHER-POINT_FCBGA989

B PCHB0@ B
2011/10/18a +3VALW_PCH
EC_SWI# RH159 1 2 10K_0402_5%
PCH_GPIO29 RH162 1 @ 2 10K_0402_5%
om
DH5
PM_PWROK 2 1 PCH_RSMRST#
CH751H-40PT_SOD323-2
DH6
1 2
35,37 POK
.c
CH751H-40PT_SOD323-2
ts
A
re A
ec
rs
PCH_DMI/FDI/PM
Custom 0.2
QFKAA
ai
5 4 3 2 1
ep
o pr
pt
.la
w
w
w
5 4 3 2 1
UH1D
UMA_ENBKL J47 AP43
31 UMA_ENBKL M45 L_BKLTEN SDVO_TVCLKINN +3VS
UMA_ENVDD AP45
13 UMA_ENVDD L_VDD_EN SDVO_TVCLKINP
PCH_PWM P45 AM42
13 PCH_PWM L_BKLTCTL SDVO_STALLN AM40
SDVO_STALLP
1
LCD_EDID_CLK T40
13 LCD_EDID_CLK L_DDC_CLK
13 LCD_EDID_DATA LCD_EDID_DATA K47 AP39 RH140 RH139
L_DDC_DATA SDVO_INTN AP40 2.2K_0402_5% 2.2K_0402_5%
LCTL_CLK T45 SDVO_INTP HDMI@ HDMI@
D D
LCTL_DATA P39 L_CTRL_CLK
2
L_CTRL_DATA
1 2 LVDS_IBG AF37 P38
AF36 LVD_IBG SDVO_CTRLCLK M39 UMA_HDMI_CLK 15
RH143 2.37K_0402_1%
1 2 LVD_VBG SDVO_CTRLDATA UMA_HDMI_DATA 15
UMA_ENBKL T79 PAD
RH125 100K_0402_5% AE48
AE47 LVD_VREFH AT49
LVD_VREFL DDPB_AUXN AT47
DDPB_AUXP AT40 HDMI_HPD HDMI_HPD 2 1
AK39 DDPB_HPD HDMI_HPD 15
LCD_TXCLK- 100K_0402_5%
13 LCD_TXCLK- LVDSA_CLK#
LVDS
LCD_TXCLK+ AK40 AV42 UMA_HDMI_TX2- RH254
13 LCD_TXCLK+ LVDSA_CLK DDPB_0N AV40 UMA_HDMI_TX2- 15
UMA_HDMI_TX2+
+3VS AN48 DDPB_0P AV45 UMA_HDMI_TX2+ 15
LCD_TXOUT0- UMA_HDMI_TX1-
13 LCD_TXOUT0- LCD_TXOUT1- AM47 LVDSA_DATA#0 DDPB_1N AV46 UMA_HDMI_TX1+ UMA_HDMI_TX1- 15
13 LCD_TXOUT1- LVDSA_DATA#1 DDPB_1P UMA_HDMI_TX1+ 15 HDMI
Digital Display Interface

LCD_TXOUT2- AK47 AU48 UMA_HDMI_TX0-
2 1 13 LCD_TXOUT2- AJ48 LVDSA_DATA#2 DDPB_2N AU47 UMA_HDMI_TX0- 15
LCTL_CLK UMA_HDMI_TX0+
LVDSA_DATA#3 DDPB_2P AV47 UMA_HDMI_TX0+ 15
RH145 2.2K_0402_5% UMA_HDMI_TXC-
AN47 DDPB_3N AV49 UMA_HDMI_TXC- 15
LCD_TXOUT0+ UMA_HDMI_TXC+
2 1 LCTL_DATA 13 LCD_TXOUT0+ LCD_TXOUT1+ AM49 LVDSA_DATA0 DDPB_3P UMA_HDMI_TXC+ 15
13 LCD_TXOUT1+ AK49 LVDSA_DATA1
RH146 2.2K_0402_5% LCD_TXOUT2+
13 LCD_TXOUT2+ AJ47 LVDSA_DATA2 P46
2 1 LCD_EDID_CLK LVDSA_DATA3 DDPC_CTRLCLK P42
RH149 2.2K_0402_5% DDPC_CTRLDATA
LCD_TZCLK- AF40
2 1 13 LCD_TZCLK- AF39 LVDSB_CLK# AP47
LCD_EDID_DATA LCD_TZCLK+
13 LCD_TZCLK+ LVDSB_CLK DDPC_AUXN AP49
RH148 2.2K_0402_5%
LCD_TZOUT0- AH45 DDPC_AUXP AT38 RH141 2 1 100K_0402_5%
2 1 13 LCD_TZOUT0- AH47 LVDSB_DATA#0 DDPC_HPD
UMA_CRT_CLK LCD_TZOUT1-
C 13 LCD_TZOUT1- LCD_TZOUT2- AF49 LVDSB_DATA#1 AY47 C
RH142 2.2K_0402_5%
13 LCD_TZOUT2- AF45 LVDSB_DATA#2 DDPC_0N AY49
2 1 UMA_CRT_DATA LVDSB_DATA#3 DDPC_0P AY43
RH144 2.2K_0402_5% LCD_TZOUT0+ AH43 DDPC_1N AY45
13 LCD_TZOUT0+ AH49 LVDSB_DATA0 DDPC_1P BA47
LCD_TZOUT1+
13 LCD_TZOUT1+ LCD_TZOUT2+ AF47 LVDSB_DATA1 DDPC_2N BA48
13 LCD_TZOUT2+ AF43 LVDSB_DATA2 DDPC_2P BB47
LVDSB_DATA3 DDPC_3N BB49
DDPC_3P
UMA_CRT_B N48 M43

1 2 14 UMA_CRT_B P49 CRT_BLUE DDPD_CTRLCLK M36
UMA_CRT_B UMA_CRT_G
14 UMA_CRT_G T49 CRT_GREEN DDPD_CTRLDATA
RH156 150_0402_1% UMA_CRT_R
14 UMA_CRT_R CRT_RED
1 2 UMA_CRT_G AT45
DDPD_AUXN
CRT
RH152 150_0402_1% 14 UMA_CRT_CLK UMA_CRT_CLK T39 AT43
UMA_CRT_DATA M40 CRT_DDC_CLK DDPD_AUXP BH41 RH255 2 1 100K_0402_5%
14 UMA_CRT_DATA CRT_DDC_DATA DDPD_HPD
1 2 UMA_CRT_R
RH154 150_0402_1% BB43
UMA_CRT_HSYNC M47 DDPD_0N BB45
14 UMA_CRT_HSYNC UMA_CRT_VSYNC M49 CRT_HSYNC DDPD_0P BF44
14 UMA_CRT_VSYNC CRT_VSYNC DDPD_1N BE44
DDPD_1P BF42
2 1 CRT_IREF T43 DDPD_2N BE42
RH138 1K_0402_0.5% T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N BG42
DDPD_3P
PANTHER-POINT_FCBGA989
PCHB0@
B B
om
.c
ts
re
ec
A A
irs

PCH_CRT/LVDS/HDMI
pa
Custom 0.2
QFKAA
5 4 3 2 1
re
op
pt
.la
w
w
w
5 4 3 2 1
UH1E
AY7
RSVD1 AV7
BG26 RSVD2 AU3
BJ26 TP1 RSVD3 BG4
BH25 TP2 RSVD4
BJ16 TP3 AT10
BG16 TP4 RSVD5 BC8
AH38 TP5 RSVD6
D AH37 TP6 AU2 D
AK43 TP7 RSVD7 AT4
AK45 TP8 RSVD8 AT3
C18 TP9 RSVD9 AT1
N30 TP10 RSVD10 AY3
H3 TP11 RSVD11 AT5
AH12 TP12 RSVD12 AV3
AM4 TP13 RSVD13 AV1
AM5 TP14 RSVD14 BB1
+3VS Y13 TP15 RSVD15 BA3
K24 TP16 RSVD16 BB5
L24 TP17 RSVD17 BB3
AB46 TP18 RSVD18 BB7
1 2 PCH_GPIO54 AB45 TP19 RSVD19 BE8
TP20 RSVD20
RSVD
RH318 8.2K_0402_5% BD4
1 2 PCH_GPIO4 RSVD21 BF6
RH319 8.2K_0402_5% RSVD22
1 2 PCI_PIRQB# B21 AV5 NV_ALE
RH320 8.2K_0402_5% M20 TP21 RSVD23 AV10
1 2 PCI_PIRQC# AY16 TP22
DF_TVS RSVD24
RH321 8.2K_0402_5% BG46 TP23 AT8
1 2 PCH_GPIO52 TP24 RSVD25
RH324 8.2K_0402_5% AY5
1 2 PCH_GPIO53 RSVD26 BA2
RH323 8.2K_0402_5% U3RXDN1_R BE28 RSVD27
29 U3RXDN1_R USB3Rn1
1 2 PCI_PIRQA# U3RXDN2_R BC30 AT12
29 U3RXDN2_R USB3Rn2 RSVD28
RH325 8.2K_0402_5% BE32 BF3
1 2 ODD_DA# BJ32 USB3Rn3 RSVD29
RH322 8.2K_0402_5% U3RXDP1_R BC28 USB3Rn4
29 U3RXDP1_R USB3Rp1
1 2 PCH_GPIO55 U3RXDP2_R BE30
29 U3RXDP2_R USB3Rp2
RH326 8.2K_0402_5% BF32
1 2 PCH_GPIO2 BG32 USB3Rp3 C24 USB20_N0
C USB3Rp4 USBP0N USB20_N0 29 C
RH327 8.2K_0402_5% U3TXDN1 AV26 A24 USB20_P0 USB-LEFT1 Intel Anti-Theft Techonlogy
29 U3TXDN1 USB3Tn1 USBP0P USB20_P0 29
1 2 PCH_GPIO50 U3TXDN2 BB26 C25 USB20_N1
29 U3TXDN2 USB3Tn2 USBP1N USB20_N1 29
RH328 8.2K_0402_5% AU28 B25 USB20_P1 USB-LEFT2 High=Endabled
USB3Tn3 USBP1P USB20_P1 29
1 2 PCH_GPIO51 AY30 C26 USB20_N2 NV_ALE
USB3Tn4 USBP2N USB20_N2 25
RH329 8.2K_0402_5% U3TXDP1 AU26 A26 USB20_P2 USB-Right1 Low=Disable(floating)
1 2 PCI_PIRQD# 29
29
U3TXDP1
U3TXDP2
U3TXDP2 AY26 USB3Tp1
USB3Tp2
USBP2P
USBP3N
K28 USB20_N3
USB20_P2
USB20_N3
25
25
*
RH283 8.2K_0402_5% AV28 H28 USB20_P3 USB-Right2
USB3Tp3 USBP3P USB20_P3 25 +1.8VS
1 2 PCH_GPIO5 AW30 EHCI 1 E28
RH290 8.2K_0402_5% USB3Tp4 USBP4N D28
USBP4P C28 NV_ALE 1 @ 2
USBP5N A28 RH164 1K_0402_5%
USBP5P C29
USBP6N B29
PCI_PIRQA# K40 USBP6P N28
PCI_PIRQB# K38 PIRQA# USBP7N M28
PIRQB# USBP7P
PCI
PCI_PIRQC# H38 L30 USB20_N8
PIRQC# USBP8N USB20_N8 28
PCI_PIRQD# G38 K30 USB20_P8 Card Reader
PIRQD# USBP8P USB20_P8 28
G30 USB20_N9
USBP9N USB20_N9 26
PCH_GPIO50 C46 E30 USB20_P9 WiMax
REQ1# / GPIO50 USBP9P USB20_P9 26
USB
PCH_GPIO52 C44 C30
PCH_GPIO54 E40 REQ2# / GPIO52 USBP10N A30
REQ3# / GPIO54 EHCI 2 USBP10P L32 USB20_N11
USBP11N USB20_N11 13
PCH_GPIO51 D47 K32 USB20_P11 Int. Camera
GNT1# / GPIO51 USBP11P USB20_P11 13
28 CLK_PCI_TPM_PCH 2 1 CLK_PCI_TPM_PCH_R PCH_GPIO53 E42 G32
22_0402_5% R314 PCH_GPIO55 F46 GNT2# / GPIO53 USBP12N E32
GNT3# / GPIO55 USBP12P C32
USBP13N A32
PCH_GPIO2 G42 USBP13P
Add new PCI CLK to TPM PIRQE# / GPIO2
ODD_DA# G40
25 ODD_DA# PIRQF# / GPIO3
PCH_GPIO4 C42 C33 USBBIAS 1 2
PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# RH165 22.6_0402_1%
PIRQH# / GPIO5
B B33
Within 500 mils B
PCI_PME# K10 USBRBIAS
T80 PAD PME#
PLT_RST# C6 A14 USB_OC#0 USB-LEFT
5,26,27,28,31,32 PLT_RST# PLTRST# OC0# / GPIO59 USB_OC#0 29
K20 USB_OC#1 USB-Right
OC1# / GPIO40 USB_OC#1 25
B17 USB_OC#2
22_0402_5% 1 2 RH167 CLK_EC_R H49 OC2# / GPIO41 C16 SLP_CHG#
31 CLK_PCI_EC CLKOUT_PCI0 OC3# / GPIO42 SLP_CHG# 29
22_0402_5% 1 2 RH166 CLK_PCH H43 L16 USB_OC#4
17 CLK_PCILOOP CLKOUT_PCI1 OC4# / GPIO43 +3VALW_PCH
22_0402_5% 1 2 RH284 CLK_SIO J48 A16 USB_OC#5
32 CLK_PCI_DDR CLKOUT_PCI2 OC5# / GPIO9
om
CLK_PCI_TPM_PCH_R K42 D14 USB_OC#6
CLKOUT_PCI3 OC6# / GPIO10
1
H40 C14 USB_OC#7

CH22 CLKOUT_PCI4 OC7# / GPIO14 USB_OC#6 1 2
47P_0402_50V8J RH209 10K_0402_5%
2
@ @ PANTHER-POINT_FCBGA989 SLP_CHG# 1 2
2 1 ODD_DA# PCHB0@ RH196 10K_0402_5%
180P_0402_50V8J CH15 USB_OC#4 1 2
RH200 10K_0402_5%
USB_OC#1 1 2
.c
by ESD requestion and place near CPU RH192 10K_0402_5%
Boot BIOS Strap
PCH_GPIO51 PCH_GPIO19 Boot BIOS Loaction
@ USB_OC#2 1 2
ts
2 1 PLT_RST# LPC RH177 10K_0402_5%
100P_0402_50V8J CH104 0 0 USB_OC#5 1 2
Reserved RH183 10K_0402_5%
0 1 USB_OC#7 1 2
PCI RH201 10K_0402_5%
1 0
A
1K_0402_5%
1K_0402_5%
2
2
@
@
1 RH285
1 RH286
PCH_GPIO51
PCH_GPIO19
PCH_GPIO19 16
1 1 SPI * re USB_OC#0 1
RH188
2
10K_0402_5%
A
ec
A16 Swap Override Strap
Low= A16 swap override Enable
PCH_GPIO55 * High= A16 swap override Disable
irs
1K_0402_5% 2 @ 1 RH287 PCH_GPIO55 2010/09/03 2012/12/31 Title

PCH_PCI/USB/NAND
Custom 0.2
QFKAA
pa
5 4 3 2 1
re
op
pt
.la
w
w
w
5 4 3 2 1
+3VS
+3VALW_PCH UH1F
ODD_EN# 1 2
CHP3_SERDBG T7 C40 ODD_EN# RH288 10K_0402_5%
2 1 EC_LID_OUT# 14 CHP3_SERDBG BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# 34 GATEA20 1 2
RH204 1K_0402_5% PCH_GPIO1 A42 B41 PCH_GPIO69 RH182 10K_0402_5%
1 2 EC_SMI# TACH1 / GPIO1 TACH5 / GPIO69 KB_RST# 1 2
RH205 10K_0402_5% PCH_GPIO6 H36 C41 PCH_GPIO70 RH184 10K_0402_5%
1 2 PCH_GPIO12 TACH2 / GPIO6 TACH6 / GPIO70 PCH_GPIO69 1 2
RH289 10K_0402_5% EC_SCI# E38 A40 PCH_GPIO71 RH291 10K_0402_5%
31 EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71
D 1 2 PCH_GPIO28 PCH_GPIO70 1 2 D
RH202 10K_0402_5% 31 EC_SMI# EC_SMI# C10 RH315 10K_0402_5%
1 2 PCH_GPIO57 GPIO8 PCH_GPIO71 1 2
RH207 10K_0402_5% PCH_GPIO12 C4 RH203 10K_0402_5%
LAN_PHY_PWR_CTRL / GPIO12
+3VS EC_LID_OUT# G2 P4 GATEA20
31 EC_LID_OUT# GPIO15 A20GATE GATEA20 31
AU16
1 2 PCH_GPIO34 PCH_GPIO16 U2 PECI
RH180 10K_0402_5% SATA4GP / GPIO16 P5 KB_RST#
2 1 RCIN# KB_RST# 31
CHP3_SERDBG
GPIO
RH292 1K_0402_5% PCH_GPIO17 D40 AY11 H_PWRGOOD
1 2 TACH0 / GPIO17 PROCPWRGD H_PWRGOOD 5
PCH_GPIO1
CPU/MISC
RH190 10K_0402_5% BT_DET# T5 AY10 PCH_THRMTRIP# 1 2
1 2 BT_DET# SCLOCK / GPIO22 THRMTRIP# H_THERMTRIP# 5
RH191 390_0402_5%
RH185 10K_0402_5% E8 T14
1 2 OPTIMUS_EN# GPIO24 INIT3_3V#
RH193 10K_0402_5% PCH_GPIO27 E16 AY1 NV_CLE This signal has weak internal
1 2 ODD_DETECT# GPIO27 DF_TVS
RH178 200K_0402_5% PCH_GPIO28 P8 pull-up, can't be pulled low
1 2 PCH_GPIO6 GPIO28 AH8
RH197 10K_0402_5% PCH_GPIO34 K1 TS_VSS1
1 2 PCH_GPIO16 STP_PCI# / GPIO34 AK11
RH179 10K_0402_5% PCH_GPIO35 K4 TS_VSS2
T81 PAD GPIO35
1 2 EC_SCI# AH10
RH293 10K_0402_5% ODD_DETECT# V8 TS_VSS3
1 2 25 ODD_DETECT# SATA2GP / GPIO36 AK10
PCH_GPIO39
RH194 10K_0402_5% PCH_GPIO37 M5 TS_VSS4
1 2 PCH_GPIO48 SATA3GP / GPIO37
C RH181 10K_0402_5% OPTIMUS_EN# N2 P37 C
1 2 PCH_GPIO49 SLOAD / GPIO38 NC_1
RH195 10K_0402_5% PCH_GPIO39 M3
1 2 PCH_GPIO17 SDATAOUT0 / GPIO39
RH186 10K_0402_5% PCH_GPIO48 V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
PCH_GPIO49 V3 BG48
SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
PCH_GPIO57 D6 BH3
GPIO57 VSS_NCTF_17
BH47
1 2 PCH_GPIO37 VSS_NCTF_18
RH198 10K_0402_5% A4 BJ4
2 @ 1 PCH_GPIO27 VSS_NCTF_1 VSS_NCTF_19
RH199 10K_0402_5% A44 BJ44
VSS_NCTF_2 VSS_NCTF_20
Follow Compal ORB
and Intel Check list 460603 V1.5 A45 BJ45
NCTF
A46 BJ46
A5 BJ5
A6 BJ6
B3 C2 DMI & FDI Termination Voltage
B47 C48
Set to VCC when HIGH
BD1 D1 NV_CLE
B VSS_NCTF_9 VSS_NCTF_27 B
GPIO28 Set to VSS when LOW
3D_DET# BD49 D49
On-Die PLL Voltage Regulator +1.8VS +1.8VS
BE1 E1
* H: Enable 3D_DET# H L
L: Disable BE49 E49
1
1
om
BF1 F1 RH187 RH210
RH206 1 @ 2 1K_0402_5% PCH_GPIO28 VSS_NCTF_13 VSS_NCTF_31
SKU Non3D 3D 2.2K_0402_5% 2.2K_0402_5%
BF49 F49
2
2
DH54
PANTHER-POINT_FCBGA989 NV_CLE 2 1 2 1
H_SNB_IVB# 5,11
PCHB0@ RH189 1K_0402_5%
.c
PMEG2010AEH_SOD123
GPIO8 OPTIMUS_EN# HDD2_DET#
ts
Integrated Clock Chip Enable (Removed)
H: Disable OPTIMUS_EN# H L HDD2_DET# H L
* L: Enable
RH298 1 @ 2 1K_0402_5% EC_SMI#

SKU NonOPT Optimus SKU ONE HDD re TWO HDD
ec
A A
Integrated clock enable functionality
is achieved by soft-strap
The current default is clock enable
irs

PCH_CPU/GPIO
pa
Custom 0.2
QFKAA
5 4 3 2 1
re
op
pt
.la
w
w
w
5 4 3 2 1
+1.05VS_VCCP UH1G POWER +3VS
PJ4 @ 1300mA RH299 LH1

2 1 1U_0402_6.3V6K +1.05VS_PCH AA23 U48 +VCCA_DAC 0.1U_0402_10V7K 1 2+VCCA_DAC_R 2 1
PCH Power Rail Table
2 1 AC23 VCCCORE[1] 1mA VCCADAC
1 1 1_0603_1% BLM18PG181SN1D_0603 Refer to PCH EDS R1.0
JUMP_43X118 AD21 VCCCORE[2] CH35 CH36 CH37
1 1 1 1
CRT
CH32 CH33 CH31 CH34 AD23 VCCCORE[3] U47 0.01U_0402_25V7K 10U_0603_6.3V6M
VCCCORE[4] VSSADAC
S0 Iccmax
D AF21 Voltage Rail Voltage D
Current (A)
VCC CORE
10U_0603_6.3V6M AF23 VCCCORE[5] 2 2
2 2 2 2 AG21 VCCCORE[6] +3VS
AG23 VCCCORE[7]
VCCCORE[8]
V_PROC_IO 1.05 0.001
1U_0402_6.3V6K 1U_0402_6.3V6K AG24 1mA AK36 +VCCA_LVDS 1 2
AG26 VCCCORE[9] VCCALVDS RH208 0_0603_5%
AG27 VCCCORE[10] AK37
VCCCORE[11] VSSALVDS
V5REF 5 0.001
AG29
AJ23 VCCCORE[12]
VCCCORE[13] +1.8VS
LVDS
AJ26 AM37 V5REF_Sus 5 0.001
AJ27 VCCCORE[14] VCCTX_LVDS[1] LH2
AJ29 VCCCORE[15] AM38 +VCCTX_LVDS 0.01U_0402_25V7K 2 1
AJ31 VCCCORE[16] VCCTX_LVDS[2] BLM18PG181SN1D_0603
VCCCORE[17] 1 Vcc3_3 3.3 0.228
+1.05VS_PCH 60mA AP36 CH40
VCCTX_LVDS[3] CH38 CH39 22U_0805_6.3V6M
AP370.01U_0402_25V7K VccADAC 3.3 0.063
AN19 VCCTX_LVDS[4] 2
VCCIO[28]
VccADPLLA 1.05 0.08
BJ22 +3VS
This pin can be left as NC if PAD T82 VCCAPLLEXP
On-Die VR is enabled (Default) V33 VccADPLLB 1.05 0.08
VCC3_3[6]
HVCMOS
AN16
VCCIO[15]
1
AN17 CH42 VccCore 1.05 1.7
VCCIO[16] V34 0.1U_0402_10V7K
VCC3_3[7]
AN21 2 VccDMI 1.1 0.047
VCCIO[17] +VCCAFDI_VRM +1.5VS
AN26 RH221
VCCIO[18] 0_0603_5% VccIO 1.05 3.711
AN27 AT16 +VCCAFDI_VRM 1 2
C VCCIO[19] 3709mA VCCVRM[3] C
+1.05VS_PCH AP21 +VCCP_VCCDMI RH213 +1.05VS_VCCP VccASW 1.05 0.903
VCCIO[20] 0_0603_5%
1U_0402_6.3V6K AP23 AT20 +VCCP_VCCDMI 1 2
VCCIO[21] VCCDMI[1]
1 VccSPI 3.3 0.01
+1.05VS_PCH
DMI
1 1 1 1 1 AP24
VCCIO[22]
VCCIO
CH43 CH45 CH46 CH47 CH44 RH214 CH48
AP26 AB36 +1.05VS_VCC_DMI 2 1 1U_0402_6.3V6K VccDSW 3.3 0.001
10U_0603_6.3V6M 1U_0402_6.3V6K VCCIO[23] 75mA VCCCLKDMI 0_0805_5% 2
2 2 2 2 2 1
AT24
VCCIO[24] CH49 VccDFTERM 1.8 0.002
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
AN33 2
VCCIO[25]
VccRTC 3.3 N/A
AN34 AG16 +1.8VS
+3VS VCCIO[26] VCCDFTERM[1]
VccSus3_3 3.3 0.095
BH29 AG17
VCC3_3[3] VCCDFTERM[2]
DFT / SPI
1 1
CH50 190mA VccSusHDA 3.3 0.01
0.1U_0402_10V7K AJ16 CH51
VCCDFTERM[3] 0.1U_0402_10V7K
2 +VCCAFDI_VRM AP16 2 VccVRM 1.5 0.167
VCCVRM[2] AJ17
VCCDFTERM[4]
This pin can be left as NC if BG6
PAD T83 VccAFDIPLL
VccCLKDMI 1.05 0.07
On-Die VR is enabled (Default) +3VS
+1.05VS_PCH AP17 VccSSC 1.05 0.095

VCCIO[27] V1
FDI
20mA VCCSPI
+VCCP_VCCDMI AU20 1 VccDIFFCLKN 1.05 0.055
B VCCDMI[2] B
CH53
PANTHER-POINT_FCBGA989 1U_0402_6.3V6K VccALVDS 3.3 0.001
PCHB0@ 2
VccTX_LVDS 1.8 0.04

+3VALW to +3V_PCH
m
Vgs=-4.5V,Id=3A,Rds<97mohm
+3VALW +3VALW_PCH
PJ2
@
o
2 1
2 1
JUMP_43X79
.c
QH2 AO3413_SOT23
20K_0402_5%~D
S
3 1
ts
0.1U_0402_10V7K~D
0.01U_0402_25V7K
G
1
2
0.1U_0402_25V6
1
CH99
CH102
1
2
2
@
re
RH1
CH98
A PCH_PWR_EN# 2 1 A
23,34 PCH_PWR_EN#
RH3 47K_0402_5%
ec
irs
PCH_POWER-1
Custom 0.2
QFKAA
pa
5 4 3 2 1
re
op
pt
.la
w
w
w
5 4 3 2 1
+3VS +5VALW JUMP_43X39 +5VALW_PCH

@ PJ5
LH5 2 1
1 2 +3VS_VCC_CLKF33 2 1
10UH_LB2012T100MR_20% 1 1 This pin can be left as NC if QH6
CH73 CH74 On-Die VR is enabled (Default) AO3413_SOT23
+3VALW_PCH
D
10U_0603_6.3V6M 1U_0402_6.3V6K 3 1
2 2 UH1J POWER +1.05VS_PCH
1
0.1U_0402_25V6
0.1U_0402_10V7K~D
PAD
20K_0402_5%~D
1
AD49 N26
CH80
G
1 T84 1
2
CH55 VCCACLK VCCIO[29]
RH228
1 2
D 0.1U_0402_10V7K P26 D
CH59
T16 VCCIO[30] CH56
@ 2 VCCDSW3_3 3mA P28 1U_0402_6.3V6K 2 1 2 @
"@" Avoid leakage 22,34 PCH_PWR_EN#
2
CH58 VCCIO[31] 2 RH4 47K_0402_5%
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
0.1U_0402_10V7K T29
+3VS_VCC_CLKF33 T38 VCCIO[33] +3VALW_PCH
VCC3_3[5] Change RH232, RH237 to 10 ohm by follow Compal ORB abd Intel CRB
T23
PAD T85 BH23 VCCSUS3_3[7]
This pin can be left as NC if VCCAPLLDMI2 T24
1
CH60 +3VALW_PCH
119mA VCCSUS3_3[8]
On-Die VR is enabled (Default) +1.05VS_PCH AL29 0.1U_0402_10V7K +5VALW_PCH +3VALW_PCH
VCCIO[14] V23
VCCSUS3_3[9] 2
USB
1
2
1
+VCCSUS AL24 V24
DCPSUS[3] VCCSUS3_3[10] CH61 RH232 DH3
1
CH54 P24 0.1U_0402_10V7K 10_0402_5%
1U_0402_6.3V6K VCCSUS3_3[6] 2 CH751H-40PT_SOD323-2
@ AA19
1
2
+1.05VS_PCH 2 VCCASW[1] T26 +PCH_V5REF_SUS
VCCIO[34] +1.05VS_PCH
AA21 1010mA 1
VCCASW[2] CH63
AA24 1mA M26 +PCH_V5REF_SUS
VCCASW[3] V5REF_SUS 0.1U_0402_10V7K
AA26 @ 2
Clock and Miscellaneous

1 1 VCCASW[4]
CH64 CH65 AN23 +VCCA_USBSUS CH62 1 2 1U_0402_6.3V6K
AA27 DCPSUS[4]
22U_0805_6.3V6M VCCASW[5] AN24
2 2 VCCSUS3_3[1] +3VALW_PCH
AA29
22U_0805_6.3V6M VCCASW[6] 1 2
AA31 CH66 0.1U_0402_10V7K +5VS +3VS
VCCASW[7] CH63 & CH71 are
C C
1U_0402_6.3V6K AC26 P34 +PCH_V5REF_RUN
different by Intel CRB.
VCCASW[8] 1mA V5REF
2
+3VALW_PCH
1 1 1
CH67 CH68 CH69 AC27 RH237 DH4
+1.05VS_PCH VCCASW[9] N20 10_0402_5%
VCCSUS3_3[2]
PCI/GPIO/LPC
1U_0402_6.3V6K 1U_0402_6.3V6K AC29 1 CH751H-40PT_SOD323-2
LH7 BLM18PG181SN1D_2P 2 2 2 VCCASW[10] N22 CH70
1
1 2 +1.05VS_VCCADPLLA AC31 VCCSUS3_3[3] 1U_0402_6.3V6K +PCH_V5REF_RUN
VCCASW[11] P20
VCCSUS3_3[4] 2 1
LH8 BLM18PG181SN1D_2P AD29 CH71
1 2 +1.05VS_VCCADPLLB VCCASW[12] P22
CH93 CH95 AD31 VCCSUS3_3[5] +3VS 1U_0402_6.3V6K
VCCASW[13] 2
1 10U_0603_6.3V6M 1 10U_0603_6.3V6M
1 1 W21 AA16
VCCASW[14] VCC3_3[1]
+3VS 1
W23 W16 CH72
2 2 VCCASW[15] VCC3_3[8] 0.1U_0402_10V7K
2 CH94 2 CH96 W24 T34
1U_0402_6.3V6K 1U_0402_6.3V6K VCCASW[16] VCC3_3[4] 2
W26 1 2
VCCASW[17] CH75
W29 0.1U_0402_10V7K +3VS
VCCASW[18]
W31 AJ2
+1.05VS_PCH VCCASW[19] VCC3_3[2] +1.05VS_SATA3 +1.05VS_PCH
1
RH244 W33 RH242
2 1 +VCCDIFFCLK VCCASW[20] AF13 CH76 2 1
VCCIO[5] 0.1U_0402_10V7K
0_0603_5% +VCCRTCEXT N16 2 0_0805_5%
1 DCPRTC 1
CH79 1 AH13 CH77
1U_0402_6.3V6K CH78 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3
B 2 VCCVRM[4] VCCIO[13] 2 B
2
AF14
+1.05VS_PCH +1.05VS_VCCDIFFCLKN +1.05VS_VCCADPLLA BD47 VCCIO[6]
VCCADPLLA 80mA This pin can be left as NC if
SATA
RH247
VCCAPLLSATA
AK1 T86 PAD
2 1 +1.05VS_VCCDIFFCLKN +1.05VS_VCCADPLLB BF47 +VCCAFDI_VRM On-Die VR is enabled (Default)
1
VCCADPLLB 80mA
0_0603_5% CH81 AF11 +VCCAFDI_VRM
1U_0402_6.3V6K +VCCDIFFCLK AF17 VCCVRM[1] +1.05VS_VCC_SATA +1.05VS_PCH
VCCIO[7] 55mA
om
AF33 RH246
2 AF34 VCCDIFFCLKN[1] AC16 +1.05VS_VCC_SATA 2 1
+1.05VS_VCCDIFFCLKN AG34 VCCDIFFCLKN[2] VCCIO[2] 0_0805_5%
+1.05VS_PCH VCCDIFFCLKN[3] AC17
VCCIO[3] 1
CH82
AG33 AD17 1U_0402_6.3V6K
VCCSSC 95mA VCCIO[4]
1 2
CH84
1U_0402_6.3V6K +VCCSST V16 +1.05VS_PCH
DCPSST
.c
2 1
0.1U_0402_10V7K
+1.05VM_VCCSUS T17 T21 +VCCME_22 RH300 2 1 0_0402_5%
CH85 V19 DCPSUS[1] VCCASW[22]
2 DCPSUS[2]
MISC
ts
+1.05VS_VCCP V21 +VCCME_23 RH301 2 1 0_0402_5%
RH249 VCCASW[23]
+1.05VS_PCH
1mA
CPU
1 2 0.1U_0402_10V7K +V_CPU_IO BJ8

RH303 @ V_PROC_IO T19 +VCCME_21 RH302 2 1 0_0402_5%
2 1 +1.05VM_VCCSUS 0_0603_5% VCCASW[21]
1 1 1
0_0603_5% 1
CH83
CH86
4.7U_0603_6.3V6K
CH87 CH88
0.1U_0402_10V7K
+RTCVCC
0.1U_0402_10V7K A22 10mA P32 re +3VALW_PCH

RTC
2 2 2 VCCRTC VCCSUSHDA
HDA
1U_0402_6.3V6K
A @ A
2 1 1 1 1
CH89 CH90 CH91 PANTHER-POINT_FCBGA989 CH92
ec
PCHB0@ 0.1U_0402_10V7K
1U_0402_6.3V6K 0.1U_0402_10V7K
2 2 2 2

rs
PCH_POWER-2
Custom 0.2
QFKAA
ai
5 4 3 2 1
r ep
op
pt
.la
w
w
w
5 4 3 2 1
UH1I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
UH1H B15 VSS[163] VSS[263] K7
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
D AA34 VSS[4] VSS[83] AK8 B7 VSS[170] VSS[270] L48 D
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
C AD43 VSS[36] VSS[115] AP42 BF22 VSS[202] VSS[302] T47 C
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
B AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36 B
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
VSS[77] VSS[156] VSS[243] VSS[349]
m
AK12 AY22 G18 BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
PANTHER-POINT_FCBGA989 G28 VSS[246] VSS[352]
PCHB0@ G36 VSS[247]
G48 VSS[248]
co
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
VSS[255]
.
H32
H34 VSS[256]
VSS[257]
ts
F3
VSS[258]
PANTHER-POINT_FCBGA989
A
PCHB0@
re A
ec
rs
PCH_GND
Custom 0.2
QFKAA
ai
5 4 3 2 1
p
re
op
pt
.la
w
w
w
5 4 3 2 1
SATA HDD SATA ODD Conn (for 14")

Conn. +5VS
Place closely JHDD SATA CONN. GND
JODD
1
1.2A 2 SATA_PTX_C_DRX_P2 C376 1 2 0.01U_0402_25V7K
A+ SATA_PTX_DRX_P2 16
3 SATA_PTX_C_DRX_N2 C377 1 2 0.01U_0402_25V7K
A- SATA_PTX_DRX_N2 16
1 1 1 4
GND
1
C357 C358 C359 5 SATA_PRX_DTX_N2 C378 1 2 0.01U_0402_25V7K
B- SATA_PRX_C_DTX_N2 16
C356 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 6 SATA_PRX_DTX_P2 C375 1 2 0.01U_0402_25V7K
B+ SATA_PRX_C_DTX_P2 16
2 10U_0805_6.3V6M 7
2 2 2 GND
8
DP ODD_DETECT# 21
9 +5VS_ODD
+5V 10 +5VS_ODD
+5V Place components closely ODD CONN.
D 11 ODD_DA# 1.6A D
MD ODD_DA# 20
14 12
Close to JHDD 15 GND1 GND 13 1 1 1
JHDD GND2 GND
1
C379
1 SANTA_206001-1 C355 @ C354 @ C380 C360
GND 2 SATA_PTX_C_DRX_P0 C369 1 2 0.01U_0402_25V7K @ 10U_0805_6.3V6M 10U_0805_6.3V6M 1U_0402_6.3V6K 0.1U_0402_10V7K
SATA_PTX_DRX_P0 16
2
RX+ 3 SATA_PTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K 2 2 2
RX- SATA_PTX_DRX_N0 16
4 0.1U_0402_10V7K
GND 5 SATA_PRX_DTX_N0 C368 1 2 0.01U_0402_25V7K
TX- SATA_PRX_C_DTX_N0 16
6 SATA_PRX_DTX_P0 C370 1 2 0.01U_0402_25V7K
TX+ SATA_PRX_C_DTX_P0 16
7
GND
SATA ODD Conn (for 15" 17")
8 JODDB @
3.3V +3VS
9 1
3.3V 10 1 2 SATA_PTX_C_DRX_P2_R R79 1 2 0_0402_5% SATA_PTX_C_DRX_P2
3.3V 11 2 3 SATA_PTX_C_DRX_N2_R R80 1 2 0_0402_5% SATA_PTX_C_DRX_N2
GND 12 3 4
GND 13 4 5 SATA_PRX_DTX_N2_R R81 1 2 0_0402_5% SATA_PRX_DTX_N2
GND 14 5 6 SATA_PRX_DTX_P2_R R82 1 2 0_0402_5% SATA_PRX_DTX_P2
5V +5VS 6
15 7
5V 16 7 8 ODD_DETECT#
5V 17 8 9
GND 9 +5VS_ODD
18 10
Reserved 19 10 11 ODD_DA#
23 GND 20 11 12
24 GND 12V 21 12 13
GND 12V
12V
22 GND
GND
14 Had confirm with ME that
SUYIN_127043FB022G278ZR ACES_88058-120N this symbol is the same as connector list
C
ODDB demand C
@
Power Button & RUSB connector

+5VALW W=80mils
2.5A +USB_VCCA For EMI
U14
2 6 2 1
3 IN OUT 7 C361 1000P_0402_50V7K delete +USB_VCCA capacitance
4 IN OUT 8
29,31 USB_EN#
1 EN/ENB OUT 5
USB_OC#1 20
(place in SB will be better)
GND OCB
1
SY6288DCAC_MSOP8
SA00004KB00 C362
4.7U_0805_10V4Z
SA00003TV00 2@
R77 0_0402_5%
1 @ 2
L54
B 20 USB20_N2 USB20_N2 1 2 USB20_N2_R B
1 2
20 USB20_P2 USB20_P2 4 3 USB20_P2_R JUSIO

4 3 1
WCM-2012-900T_0805 USB20_P3_R 2 1
USB20_N3_R 3 2
1 @ 2 4 3
R88 0_0402_5% USB20_P2_R 5 4
5
om
USB20_N2_R 6
7 6
R73 0_0402_5% ON/OFFBTN# 8 7
31,33 ON/OFFBTN# 8
1 @ 2 +5VS 1 2 +5VS_PWR_ON_LED 9
R22 10 9
+USB_VCCA 10
L53 390_0402_5% 11
USB20_N3 1 2 USB20_N3_R 12 11
20 USB20_N3 1 2 12
13
14 GND
GND
.c
20 USB20_P3 USB20_P3 4 3 USB20_P3_R
4 3 ACES_88058-120N
WCM-2012-900T_0805 @
1 @ 2
R87 0_0402_5%
ts
A
re A
ec
rs

SATA-HDD/ODD/USB
ai
0.2
QFKAA
5 4 3 2 1
p
re
op
pt
.la
w
w
w
Slot 1 Half PCIe Mini Card-WLAN/ WiMax WLAN&BT Combo module circuits
+3V_WLAN
BT BT
on module on module
2
RM17
+3V_WLAN +3V_WLAN
Enable Disable
8.2K_0402_5%
5
UM4 UM5
1 1
P
31 AOAC_WLAN_PWR_EN# IN1 5,20,27,28,31,32 PLT_RST# IN1
4WLAN_OFF# 4 WLAN_RST#_R BT_ON# H L
2 O 2 O
31 WL_OFF# IN2 31 WLAN_RST# IN2
2
RM21
SN74AHC1G08DCKR_SC70-5 SN74AHC1G08DCKR_SC70-5 100K_0402_5%
3
@ For RF
BT_ON 1 R327 2 E51_RXD_R
31 BT_ON
1K_0402_5%
1
WL_OFF# 1 2 WLAN_RST# 1 2
RM18 0_0402_5% RM19 0_0402_5%
@
For isolate Intel Rainbow Peak and
Compal Debug Card.
40 mils +1.5VS
+3V_WLAN +1.5VS_WLAN
For SED For SED
1
0.1U_0402_10V7K 0.1U_0402_10V7K
1 1 1 1 1 1 PJ33
1
1
PAD-OPEN 2x2m
CM1 CM2 CM3 C253 CM7 CM8 CM9 C254 @
47P_0402_50V8J @ @ @ 47P_0402_50V8J
2
2
2 2 2 @ 2 2 2 @
2
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z
+1.5VS_WLAN
+3V_WLAN
JWLAN +3VALW TO +3V_WLAN
EC_SWI# 1 2
18,27 EC_SWI#
+3V_WLAN BT_ON 10_0402_5%2BT_CTRL_R
3
5
1
3
2
4
4
6
for AOAC and WOWL
@ R1443 7 5 6 8
17 CLKREQ_WLAN# 7 8 +3VALW +3VS
9 10
9 10
1
11 12
17 CLK_WLAN# 11 12 +3VALW
C266 13 14
17 CLK_WLAN 13 14
47P_0402_50V8J 15 16
2
@ 15 16
1
2
17 18 R1456 C907 Vgs=-4.5V,Id=3A,Rds<97mohm
+1.5VS_WLAN 19 17 18 20 WLAN_OFF# 100K_0402_5%
19 20
1
21 22 WLAN_RST#_R 0.1U_0402_10V7K
23 21 22 24 1 PJ30
17 PCIE_PRX_WLANTX_N2
2
23 24
1
3
S
25 26 PAD-OPEN 2x2m
17 PCIE_PRX_WLANTX_P2 25 26 G
C260 27 28 AOAC_WLAN_PWR_EN# 1 2 2 AO3413_SOT23 @
47P_0402_50V8J 29 27 28 30 Q210
PM_SMBCLK 11,12,17
2
@ 31 29 30 32 47K_0402_5% D
17 PCIE_PTX_C_WLANRX_N2 PM_SMBDATA 11,12,17 2
2
33 31 32 34
17 PCIE_PTX_C_WLANRX_P2 33 34 +3V_WLAN
WLAN/ WiFi 35 36 WiMax R1457 C908
35 36 USB20_N9 20
37 38 USB20_P9 20 0.01U_0402_25V7K
39 37 38 40 1
+3V_WLAN 39 40
41 42 LED_WIMAX#
43 41 42 44 LED_WIMAX# 33
need short PJ30 if system
45 43 44 46 WIMAX@
45 46 don't support AOAC or WOWL
R16 47 48 LED_WIMAX# 1 2 +5VS
10_0402_5%2 49 47 48 50 RM7 100K_0402_5%
31 E51_TXD 1 2 49 50
E51_RXD_R 51 52 WIMAX@
31 E51_RXD 51 52
0_0402_5% 53 54 1 2
R17 G1 G2 RM181 200K_0402_5%
Debug card using
@ BELLW_80003-7041
Green Clock
+3VALW +3VL
0.1U_0402_10V7K
0.1U_0402_10V7K
1 1 PCH_X1_R_R 1 GCLK@ 2 PCH_X1_R

PCH_X1_R 17
RCL1 0_0402_5%
CCL8 CCL1
GCLK@ GCLK@
2 2
2
GCLK@ LAN_X1_R_R 1 GCLK@ 2 LAN_X1_R
UCL1 22U_0805_6.3V6M LAN_X1_R 27
+3V_LAN GCLK@ RCL2 33_0402_5%
CCL7
1 1
2 10
0.1U_0402_10V7K
+3VALW VDD VBAT +RTCBATT

1 +3VL 15 11 CCL10
+V3.3A NC 5P_0402_50V8C
CCL2 8 9 PCH_RTCX1_R 2 GCLK@
+3V_LAN VDDIO_25M_A 32K PCH_RTCX1_R 16
om
GCLK@ 3 12
2 +1.05VS_VCCP VDDIO_25M_B NC
CLK_X2 1 5 PCH_X1_R_R
EMI request 11/06
CLK_X1 16 XTAL_OUT 25M_B 6 LAN_X1_R_R
XTAL_IN 25M_A
4
+1.05VS_VCCP VSS
7
VSS
0.1U_0402_10V7K
13
17 VSS 14
1 Thermal Pad VDD_RTC_OUT +RTCVCC
.c
CCL3
GCLK@ SLG3NB244VTR_TQFN16_2X3 1
2
CCL6
2.2U_0603_6.3V6K
ts
2 GCLK@
LAN_X1_R_R 1 @ 2
CLK_X1 1
1
YCL1
GND
GCLK@
25MHZ 20PF X3G025000DK1H-X
GND
3
3 CLK_X2
RCL5
re
Reserved for Swing Level adjustment
0_0402_5%
ec
1 2 4 1 ( Close GCLK side )
CCL4 CCL5
18P_0402_50V8J 18P_0402_50V8J
2 GCLK@ 2 GCLK@

irs

PCIe-WLAN/JET/3G/TV/GCLK
0.2
QFKAA
pa

re
op
pt
.la
w
w
w
A B C D E
UL1 +3V_LAN
Add test point +LAN_VDD10
CL3 to CL6 close to Pin 27,39,47,48
CL7 to CL8 close to Pin 12,42
17 PCIE_PRX_C_LANTX_P1 CL1 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_P1 22 31 for pin37 on DVT
HSOP LED3/EEDO 37 LL1 8111FVB@ 1 2
LED1/EESK TL1
17 PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_N1 23 40 +LAN_REGOUT 1 2 CL3 0.1U_0402_10V7K
HSON LED0 2.2UH +-5% NLC252018T-2R2J-N 1 2
PCIE_PTX_C_LANRX_P1 17 30 RL2 2 @ 1 10K_0402_5% 1 1 CL4 0.1U_0402_10V7K
17 PCIE_PTX_C_LANRX_P1 HSIP EECS Layout Note: LL1 must be
LAN_EN PCIE_PTX_C_LANRX_N1 18 32 RL1 2 @ 1 10K_0402_5% 1 2
17 LAN_EN 17 PCIE_PTX_C_LANRX_N1 HSIN EEDI
2
within 200mil to Pin36, CL13 CL9 CL5 0.1U_0402_10V7K
G
8105ELDO@ 2N7002_SOT23-3 CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_10V7K 1 2
CLKREQ_LAN# 1 3 LANCLK_REQ# 16 1 LAN_MDI0+ 200mil to LL1 8111FVB@ 2 2 8111FVB@ CL6 0.1U_0402_10V7K
17 CLKREQ_LAN# CLKREQB MDIP0
QL53 2 LAN_MDI0- 1 2
S
PLT_RST# 25 MDIN0 4 LAN_MDI1+ 8111FVB@ CL7 0.1U_0402_10V7K
1 5,20,26,28,31,32 PLT_RST# PERSTB MDIP1 1
5 LAN_MDI1- 1 2
CLK_LAN 19 MDIN1 7 LAN_MDI2+ 8111FVB@ CL8 0.1U_0402_10V7K
17 CLK_LAN REFCLK_P NC/MDIP2
CLK_LAN# 20 8 LAN_MDI2-
17 CLK_LAN# REFCLK_N NC/MDIN2
18111FVB@ 2 10 LAN_MDI3+
RL28 0_0402_5% NC/MDIP3 11 LAN_MDI3-
LAN_X1 43 NC/MDIN3
CKXTAL1 +LAN_VDD10 +LAN_EVDD10
+3VS 8105ELDO@ LAN_X2 44 13 +LAN_VDD10 CL19, CL20,CL21 close to pin 13,29,45, respectively
CKXTAL2 DVDD10 +LAN_VDD10
RL24 2 1 10K_0402_5% LANCLK_REQ# 29 1 2 CL22 close to pin 3, respectively
DVDD10 41 LL2 0_0603_5%
DVDD10 CL23,CL24,CL25 close to pin 6,9,41, respectively
EC_SWI# 28 1 1
18,26 EC_SWI# LANWAKEB 1 2
+3V_LAN ISOLATE# 26 27 CL18 CL17 CL19 0.1U_0402_10V7K
ISOLATEB DVDD33 +3V_LAN
RL25 2 @ 1 10K_0402_5% EC_SWI# 39 1U_0402_6.3V6K 0.1U_0402_10V7K 1 2
DVDD33 2 2 CL20 0.1U_0402_10V7K
14 12 +3V_LAN 1 2
RL21 2 @ 1 10K_0402_5% 15 NC/SMBCLK AVDD33 42 CL21 0.1U_0402_10V7K
RL22 1 @ 2 1K_0402_5% 38 NC/SMBDATA AVDD33 47 1 2
+3V_LAN GPO/SMBALERT AVDD33 Close to Pin 21
48 8111FVB@ CL22 0.1U_0402_10V7K
AVDD33 1 2
ENSWREG 33 8111FVB@ CL23 0.1U_0402_10V7K
+3VS LAN_EN 18111FVB@ 2 ENSWREG 21 +3V_LAN +LAN_VDDREG 1 2
EVDD10 +LAN_EVDD10
RL26 0_0402_5% +LAN_VDDREG 34 8111FVB@ CL24 0.1U_0402_10V7K
35 VDDREG 3 1 2 1 2
VDDREG AVDD10 +LAN_VDD10
6 8111FVB@ LL3 0_0603_5% 1 1 8111FVB@ CL25 0.1U_0402_10V7K
AVDD10
1
9
1 2 46 AVDD10 45 CL28 CL29
1K_0402_5% RL5 2.49K_0402_1% RSET AVDD10 4.7U_0603_6.3V6K 0.1U_0402_10V7K
RL6 24 36 +LAN_REGOUT 8111FVB@ 2 2 8111FVB@
@ 49 GND REGOUT
60 mils
2
PGND
For P/N and footprint
ISOLATE# 1 2 WOL_EN#
2 RL433 0_0402_5% RTL8111F-CGT_QFN48_6x6
Please place them to ISPD page 2
Placement near to YL1
8111FVB@
RL8 GCLK@ UL1

RL7 1 2 LAN_X2
26 LAN_X1_R
15K_0402_5% RTL8105E RTL8111E/F 0_0402_5%
Sx Enable Sx Disable S0
Wake up Wake up Pin14 NC NC CL43 10PF_0402_50V9 8105E-VL/VD 8105E-VL/VD
1 2 1 2 +3V_LAN
8111F/F-VB
Pin15 NC 10K ohm PD RL29 22_0402_5% 8105E-VD 10/100M
GCLK@
PWM Mode LDO Mode 8105ELDO@
WOL_EN# LOW HIGH HIGH GCLK@
1
Pin38 NC 1K ohm PH RL4 0 ohm NC
RL4 (Pull High)
0_0402_5%
8111FVB@ NC 0 ohm
+3VALW TO +3V_LAN NOGCLK@ YL1 25MHZ_20PF_7V25000016 RL23 (Pull Down)
2
ENSWREG
LAN_X1 1 3 LAN_X2
1 3
1
+3VALW
GND GND RL23
+3VALW 0_0402_5%
1 2 4 1
CL26 CL27 8105ELDO@
27P_0402_50V8J 27P_0402_50V8J
2
1
+3VALW_PCH NOGCLK@ NOGCLK@

2 2 2
RL147 CL483
100K_0402_5% @
@ 0.1U_0402_10V7K
PAD-OPEN 2x2m
1
1
1
2
S
@ RL432 @ QL51 PJ32
1 2 2
G
LAN Conn.
PJ29
31 WOL_EN# PAD-OPEN 2x2m

@ @ +3V_LAN
47K_0402_5% 2 AO3413_SOT23 D
1
3 @ JRJ45 3
2
2
CL482 RJ45_MIDI0+ 1
PR1+
0.01U_0402_25V7K Vgs=-4.5V,Id=3A,Rds<97mohm
1 UL3 RJ45_MIDI0- 2
2 PR1-
1
CL682 LAN_MDI0+ 1 16 RJ45_MIDI0+ RJ45_MIDI1+ 3 For ESD
TD+ TX+ PR2+
1
CL681 1U_0402_6.3V6K LAN_MDI0- 2 15 RJ45_MIDI0- CL39 1000P_0402_50V7K
4.7U_0805_10V4Z 1 3 TD- TX- 14 2 1 1 2 RJ45_MIDI2+ 4 D92
1
@ 2 4 CT CT 13 RL11 75_0402_1% PR3+
NC NC AZC199-02SPR7G_SOT23-3
om
5 12 CL40 1000P_0402_50V7K RJ45_MIDI2- 5 @
NC NC PR3-
3
6 11 2 1 1 2
LAN_MDI1+ 7 CT CT 10 RJ45_MIDI1+ RL12 75_0402_1% RJ45_MIDI1- 6
1
3
@ LAN_MDI1- 8 RD+ RX+ 9 RJ45_MIDI1- PR2-
CL35 RD- RX- RJ45_MIDI3+ 7 9
0.1U_0402_25V6 PR4+ GND 10
+3V_LAN rising time (10%~90%) need > 1ms and <100ms. D99 @ 2 Place CL35 colse 10/100M transformer_NS681695 RJ45_MIDI3- 8 GND
LAN_MDI1+ 6 3 LAN_MDI0+ UL4 8111FVB@ PR4-
to UL3
I/O4 I/O2
2
SANTA_130452-S
.c
LAN_MDI2+ 1 16 RJ45_MIDI2+ 8111FVB@ @ D93
LAN WOL
LAN_EN ISOLATEB
2
LAN_MDI2- 2 TD+ TX+ 15 RJ45_MIDI2- CL41 1000P_0402_50V7K 8111FVB@
TD- TX- AZC199-02SPR7G_SOT23-3
S0 Sx S0 Sx +3V_LAN 5
VDD GND
2 3
CT CT
14 2 1 1 2 @
1
4 13 RL13 75_0402_1%
NC NC
---------------------------------------------- 5 12 CL42 1000P_0402_50V7K
1
NC NC
ts
6 11 2 1 1 2 For ESD
0 0 0 0 1 1 LAN_MDI1- 4
I/O3 I/O1
1 LAN_MDI0- LAN_MDI3+ 7 CT
RD+
CT
RX+
10 RJ45_MIDI3+ RL15 75_0402_1%
LAN_MDI3- 8 9 RJ45_MIDI3- 8111FVB@ 8111FVB@
0 1 0 0 1 1 AZC099-04S.R7G_SOT23-6 RD- RX-
1 0 1 1 1 1
4
*
1 1 1 1 1 0* LAN_MDI2+ 6
D100
I/O4
@
I/O2
3 LAN_MDI3+
1
2
CL34
0.1U_0402_25V6
re
10/100M transformer_NS681695
RJ45_GND
CL36
1 2
1000P_1808_3KV7K 1
CL37
220P_0402_50V6K
1
LANGND
CL38
@
4.7U_0603_6.3V6K
4
ec
5 2 Place CL34 colse 2 2
+3V_LAN
S3: after SUSP# assert low over 100ms VDD GND
to UL4
S4/S5: after SYSON assert low over 100ms
LAN_MDI2- 4 1 LAN_MDI3-
I/O3 I/O1
AZC099-04S.R7G_SOT23-6 Security Classification Compal Secret Data Compal Electronics, Inc.
irs
2/9: Add for ESD request THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-LAN-RTL8105E/8111F
Custom 0.2
QMLE4 LA-8864P
pa
A B C D E
re
op
pt
.la
w
w
w
5 4 3 2 1
CardReader Conn.
Add R2957 0 ohm to protect +3VS

JCRIO
14
R2957 13 GND
D 1 2 +3VS_CR 12 GND D
+3VS 12
0_0603_5% 11
USB20_N8_R 10 11
USB20_P8_R 9 10
8 9
HP_R 7 8 USB20_N8 1 2 RR67 USB20_N8_R
30 HP_R 7 20 USB20_N8
HP_L 6 0_0402_5%
30 HP_L 6
5 LR9 @
MIC1_L 4 5 3 4
30 MIC1_L 4 3 4
MIC1_R 3
30 MIC1_R 3
MIC_SENSE 2
30 MIC_SENSE 2
NBA_PLUG 1 2 1
30 NBA_PLUG 1 2 1
WCM-2012-900T_0805
ACES_88058-120N USB20_P8 1 2 RR66 USB20_P8_R
@ 20 USB20_P8
0_0402_5%
C C
TPM1.2 on board CT2 CT3

0.1U_0402_10V7K 0.1U_0402_10V7K
TPM9655@ TPM9655@
CT4
0.1U_0402_10V7K
TPM9655@ +3VS
0.1U_0402_10V7K 0.1U_0402_10V7K +VSB_TPM RT10 2 1 0_0603_5% +3VS

TPM9655@
1
1 2 TPM_XTALI 2 2 2 RT13 2 RT9 2 1 0_0603_5% +3VALW
CT1 22P_0402_50V8J 0_0603_5% TPM9635@
TPM9635@ CT2 CT3 CT4 TPM9655@ CT5
TPM9635@ TPM9635@ TPM9635@ TPM9635@
2
1
1 1 1 +VDD_TPM 1 0.1U_0402_10V7K CT5
2
@ RT1 0.1U_0402_10V7K
YT1 10M_0402_5% TPM9655@
32.768KHZ_12.5P_1TJF125DP1A000D +VSB_TPM
B TPM9635@ 0.1U_0402_10V7K B
1
UT1
24
19
10
5
1 2 TPM_XTALO
CT6 22P_0402_50V8J
VDD
VDD
VDD
VSB
TPM9635@ LPC_AD0 26
16,31,32 LPC_AD0 LAD0
LPC_AD1 23
16,31,32 LPC_AD1 LAD1
LPC_AD2 20
16,31,32 LPC_AD2 LAD2
LPC_AD3 17 6 TPM_GPIO PAD @ T61
16,31,32 LPC_AD3 LAD3 GPIO
m
LPC_FRAME# 22 2 TPM_GPIO2 PAD @ T62
16,31,32 LPC_FRAME# LFRAME# GPIO2
5,20,26,27,31,32 PLT_RST# PLT_RST# 16 Base I/O Address
28 LRESET#
LPC_PD#
LPCPD#
0 = 02Eh
SERIRQ 27 1 =*04Eh +3VS
16,31 SERIRQ SERIRQ
21
20 CLK_PCI_TPM_PCH LCLK TPM9635@
o
SLB 9635 TT 1.2
1
@ 1 2 1 @ 2 0_0402_5%
+VSB_TPM 10P_0402_50V8J CT7 RT4 10_0402_5% 15 8 RT5 1 2 TPM9635@
RT11 1 2 0_0402_5% CLKRUN# TEST1 9 RT3
TESTB1/BADD
.c
TPM9635@ 4.7K_0402_5%
1
2
PP
RT7 3
NC
2
@ 4.7K_0402_5% TPM_XTALO 14 12 TPM9655@
XTALO NC
ts
1 0_0402_5% RT6
2
+3VS TPM_XTALI 13 NC RT12 1 2 PLT_RST# 4.7K_0402_5%

XTALI/32K IN
@
1
GND
GND
GND
GND
1
1
RT8
RT2
TPM9635@
TPM9635@
0_0402_5%
RT8 TPM9655@
0_0402_5%
re SLB 9635 TT 1.2_TSSOP28
25
18
11
4
4.7K_0402_5% TPM9635@
2
2
A A
ec
LPC_PD#

rs
PCIe-CardReader RTS5129/TPM
Custom 0.2
QFKAA
i
pa
5 4 3 2 1
re
op
pt
.la
w
w
w
5 4 3 2 1
+5VALW
Sleep & Charge Function
USB20_DN0 1 2 RR44 USB20_N0
0_0402_5% @
PJ31
1
USB20_DP0 1 2 RR45 USB20_P0
RB73 0_0402_5% 2 1
4.7K_0402_5% 2 1
+5VALW 2.5A W=60mils
@ PAD-OPEN 2x2m
2 U15 @ +USB_VCCB For EMI Q8
CEN 1 8 SLP_CHG# UR3
USB20_DN0 2 CEN CB 7 USB20_N0 SLP_CHG# 20 2 6 2 1 1 3
S
DM TDM 6 USB20_N0 20 IN OUT +USB_VCCC +USB_VCCB
1
USB20_DP0 3 USB20_P0 3 7 CR38 1000P_0402_50V7K

SELCDP 4 DP TDP 5 USB20_P0 20 USB_CHG_EN# 4 IN OUT 8
RB74 +5VALW AO3413_SOT23
SELCDP VDD 31 USB_CHG_EN# EN/ENB OUT
4.7K_0402_5% 9 1 5 1 2 @
G
USB_OC#0 20 +5VALW
2
@ Thermal Pad GND OCB R568 @ 100K_0402_5%
1
SLG55584AVTR_TDFN8_2X2 1 1 SY6288DCAC_MSOP8
2
D CB25 USB_EN# D
SA00004KB00 CR39
25,31 USB_EN#
0.1U_0402_16V7K CB49 4.7U_0805_10V4Z
+5VALW @ 10U_0603_6.3V6M SA00003TV00 2@
2 2 To EC
@
+USB_VCCB
Pull-up for SLGC55584AV
1
W=80mils +USB_VCCC
RB75 W=80mils
4.7K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_10V7K
@ 1
1 1 1 0.1U_0402_10V7K
2
SLP_CHG# SELCDP Function CR46 + CR40 CR44 CR45 1

1 1 1
SELCDP DCP autodetect with + CR47 CR42 CR43 CR41
0 X 2 2 2 2 @
mouse/keyboard wakeup
1
220U_6.3V_M 1000P_0402_50V7K 2 2 2 2
RB76 1 0 S0 charging with SDP only
4.7K_0402_5% 220U_6.3V_M 4.7U_0805_10V4Z 1000P_0402_50V7K
@
Pull-down for SLGC55584V 1 1 S0 charging with CDP or SDP only
2
C C
1 @ 2 RR19 U3RXDP1_R_L
20 U3RXDP1_R 0_0402_5%
LR1 IUSB30@
3 4
3 4
2 1 DR7 @
2 1 1 1
U3TXDP1_R_L 10 9 U3TXDP1_R_L
KINGCORE WCM-2012HS-670T JUSBA
1 2 RR20 U3RXDN1_R_L U3TXDN1_R_L 2 2 9 8 U3TXDN1_R_L U3TXDP1_R_L 9
20 U3RXDN1_R @ 0_0402_5% 1 SSTX+
+USB_VCCB VBUS
U3RXDP1_R_L 4 4 7 7 U3RXDP1_R_L U3TXDN1_R_L 8
CR25 1 2 0.1U_0402_10V7K U3TXDP1_C 1 @ 2 RR32 U3TXDP1_R_L USB20_N0_L 2 SSTX-
20 U3TXDP1 5 5 D-
0_0402_5% U3RXDN1_R_L 6 6 U3RXDN1_R_L 7
GND
IUSB30@ LR2 IUSB30@ USB20_P0_L 3 10
3 4 3 3 U3RXDP1_R_L 6 D+ GND 11
3 4 4 SSRX+ GND 12
8 U3RXDN1_R_L 5 GND GND 13
2 1 SSRX- GND
2 1 YSCLAMP0524P_SLP2510P8-10-9 OCTEK_USB-09EAEB
IUSB30@ KINGCORE WCM-2012HS-670T @
CR24 1 2 0.1U_0402_10V7K U3TXDN1_C 1 2 RR22 U3TXDN1_R_L
20 U3TXDN1
@ 0_0402_5%
USB20_DP0 1 @ 2 RR26 USB20_P0_L

0_0402_5%
DR1
LR3 IUSB30@ @
3 4 USB20_P0_L 2
3 4 2 1
USB20_N0_L 3 1
2 1 3
2 1
WCM-2012-900T_0805 AZC199-02SPR7G_SOT23-3
USB20_DN0 1 2 RR25 USB20_N0_L
@ 0_0402_5% Change ESD Diode for EMI request
B B
1 @ 2 RR42 U3RXDP2_R_L
20 U3RXDP2_R 0_0402_5%
KINGCORE WCM-2012HS-670T
1 2
1 2
JUSBB
4 3 DR8 @ U3TXDP2_R_L 9
om
4 3 1 1 SSTX+
U3TXDP2_R_L 10 9 U3TXDP2_R_L
+USB_VCCC
1
LR5 IUSB30@ U3TXDN2_R_L 8 VBUS
2 2 SSTX-
1 2 RR40 U3RXDN2_R_L U3TXDN2_R_L 9 8 U3TXDN2_R_L USB20_N1_L 2
20 U3RXDN2_R @ 0_0402_5% 7 D-
4 4 GND
IUSB30@ U3RXDP2_R_L 7 7 U3RXDP2_R_L USB20_P1_L 3 10
CR34 1 2 0.1U_0402_10V7K U3TXDP2_C 1 @ 2 RR43 U3TXDP2_R_L U3RXDP2_R_L 6 D+ GND 11
20 U3TXDP2 5 5 SSRX+ GND
0_0402_5% U3RXDN2_R_L 6 6 U3RXDN2_R_L 4
GND GND
12
KINGCORE WCM-2012HS-670T U3RXDN2_R_L 5 13
1 2 3 3 SSRX- GND
1 2 OCTEK_USB-09EAEB
.c
8 @
4 3
4 3 YSCLAMP0524P_SLP2510P8-10-9
LR6 IUSB30@
CR35 1 2 0.1U_0402_10V7K U3TXDN2_C 1 2 RR41 U3TXDN2_R_L
20 U3TXDN2
@ 0_0402_5%
ts
IUSB30@
1 @ 2 RR39 USB20_P1_L
20 USB20_P1
0_0402_5%
DR4
LR4 IUSB30@ @
3 4 USB20_P1_L 2
3 4 2 1
1
A
20 USB20_N1
2
1
2
WCM-2012-900T_0805
@
2 RR38
0_0402_5%
1
1
USB20_N1_L
USB20_N1_L 3
re
3
AZC199-02SPR7G_SOT23-3
Change ESD Diode for EMI request

A
ec
rs
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

USB3.0
Custom 0.2
ai
5 4 3 2 1
ep
o pr
pt
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w
w
w
5 4 3 2 1
35mA for 3.3V level

close to pin 25 close to pin 38 RA18
UA1 +3VS 1 2 0.1U_0402_16V4Z +DVDD_IO +AVDD 0.1U_0402_10V7K 0.1U_0402_10V7K 1 2 +5VS
RA28 0_0603_5% 2 1 2 1 1 0_0603_5%
MIC1_R_R 4.7U_0603_6.3V6K CA58 MIC1_R_C_R 22 1 +DVDD_IO 1
MIC1_R DVDD
1
MIC1_R_L 4.7U_0603_6.3V6K CA57 MIC1_R_C_L 21 9 +3VS_DVDD CA4 CA42 CA47 CA37 CA50 CA39
MIC1_L DVDD_IO CA3 @ 10U_0603_6.3V6M
MIC2_R 17 25 +AVDD 10U_0805_6.3V6M 1 2 1 2 2
2
MIC2_L 16 MIC2_R AVDD1 38 +AVDD 2 10U_0603_6.3V6M 10U_0603_6.3V6M
MIC2_L AVDD2
31 39 +PVDD 0.1U_0402_16V4Z
+MIC1_VREFO_L MIC1_VREFO_L PVDD1
30 46 +PVDD 1 2 +3VS_DVDD LA6
+MIC1_VREFO_R MIC1_VREFO_R PVDD2 +3VS
29 RA17 0_0603_5% 1 +PVDD 1 2 0.1U_0402_10V7K
+MIC2_VREFO MIC2_VREFO +5VS
1
D D
1 2 PBY160808T-601Y-N_2P 1
1
15 45 SPKR+ CA46 CA45 CA33 0.1U_0402_10V7K
14 LINE2_R SPK_OUT_R+ 44 SPKR- 10U_0805_6.3V6M CA35 CA34 CA36
2
LINE2_L SPK_OUT_R- 2 close to pin39 10U_0805_6.3V6M
2
2 1 2
20 40 SPKL+ 10U_0603_6.3V6M
MONO_OUT SPK_OUT_L+ 41 SPKL-
1 2 MONO_IN 12 SPK_OUT_L-
PCBEEP place close to chip
CA59 100P_0402_50V8J 75_0402_1% 1
0.01U_0402_25V7K 10 33 RA19 HP_R 28 CA32 0.1U_0402_10V7K
16 AZ_SYNC_HD SYNC HPOUT_R
@ CA65 1 2 32 RA20
11 HPOUT_L 75_0402_1% HP_L 28
16 AZ_RST_HD# RESET# 2
close to pin19 5
SDATA_OUT AZ_SDOUT_HD 16
close to pin 28 8 AZ_SDIN0_HD_R 2 1
19 SDATA_IN AZ_SDIN0_HD 16
2 RA30 1AC_JDREF RA23 33_0402_5%
10U_0603_6.3V6M 1 2CA60 20K_0402_1% 28 JDREF 6 AZ_BITCLK_HD
27 LDO_CAP BCLK AZ_BITCLK_HD 16
2 1CPVEE 34 VREF
AC_VREF 2.2U_0603_10V6K 35 CPVEE 23
CA54
CBN NC
@ CA51 For EMI
1 1 2 1 36 24 AZ_BITCLK_HD 2 1 1 2 @
CA53 2.2U_0603_10V6K CBP NC 48 10_0402_5% RA29 please place near codec
CA55 CA56 NC 10P_0402_50V8J
2.2U_0603_6.3V6K 2
2 2 13 INT_MIC_DATA 3 GPIO0/DMIC_DATA 26
@ INT_MIC_CLK_R
0.1U_0402_10V7K GPIO1/DMIC_CLK AVSS1 37
AVSS2 42
SENSE_A 13 PVSS1 43
2 @ 1 SENSE_B 18 SENSE_A PVSS2 7
RA34 20K_0402_1% SENSE_B DVSS
47 AGND EC Beep
C 31 EC_MUTE#
4 EAPD
PD# Thermal Pad
49
31 EC_BEEP#
1 RA51 2 Beep sound C
47K_0402_5%
ALC259-VC2-CG_MQFN48_6X6
For EMI PCI Beep CA70

1 RA52 2 1 2 MONO_IN
16 PCH_SPKR
RA42
INT_MIC_CLK_R DGND 47K_0402_5%
0.1U_0402_10V7K
13 INT_MIC_CLK
FBMA-10-100505-301T
CAM@ EC_MUTE# Internal AMP
1 Hight Enable
LOW Disable
2
CA52 CAM@
220P_0402_50V7K RA49 CA69
2 100P_0402_50V8J
4.7K_0402_5%
1
EC_MUTE#
2W 4ohm =40mil placement near Audio Codec
2
1W 8ohm =20mil
Analog MIC SPKL+ 2
LA7
1 SPK_L1
RA50
4.7K_0402_5%
+MIC2_VREFO 0_0603_5% 2
CA71 To solve noise issue
1
@ 2
10U_0603_6.3V6M CA74
1 1U_0402_6.3V4Z
2 @
1
CA72 1
RA24 @
4.7K_0402_5% LA8 10U_0603_6.3V6M
SPKL- 2 1 1 SPK_L2
AMIC@
B 0_0603_5% B
Ext.MIC/LINE IN JACK
2
LA9
AMIC@ AMIC@ SPKR+ 2 1 SPK_R1
CA26 RA25 JMIC 0_0603_5% 2
MIC2_L 2 1 1U_0402_6.3V4Z 2 1 1K_0402_5% INT_MIC 1 CA76
1
m
2 @
2 10U_0603_6.3V6M RA47 2 1
1 2 +MIC1_VREFO_R
CA27 3 CA73 1K_0402_5% RA48 2.2K_0402_5%
MIC2_R 2 1 1U_0402_6.3V4Z 2 1 1K_0402_5% 1 2 4 GND 1U_0402_6.3V4Z MIC1_R_R 2 1
GND 2 MIC1_R 28
CA28 RA26 220P_0402_50V7K CA75 @
AMIC@ AMIC@ AMIC@ @ 1
co
ACES_50271-0020N-001
@ LA10 10U_0603_6.3V6M MIC1_R_L 2 1
1 MIC1_L 28
close to Codec SPKR- 2 1 SPK_R2 1K_0402_5%
0_0603_5% RA45 2 1 +MIC1_VREFO_L
RA46 2.2K_0402_5%
s.
SPK Conn. 1
3
t
2
Sense Pin Impedance Codec Signals Function place close to chip CA63 1 2 0.1U_0603_50V7K
39.2K
20K
PORT-I (PIN 32, 33)
PORT-B (PIN 21, 22)

Headphone out
Ext. MIC
28 MIC_SENSE 2
RA32
1
20K_0402_1%
SENSE_A CA61 1
CA66 1
re
2 0.1U_0603_50V7K
2 0.1U_0603_50V7K
SPK_R1
SPK_R2
SPK_L1
SPK_L2
DA10 AZ5125-02S.R7G_SOT23-3
@ 1
2
3
4
JSPK
1
2
3
ec
CA62 1 2 0.1U_0603_50V7K 4
SENSE A ACES_85204-0400N
1 2 3 @
A
10K PORT-C (PIN 23, 24) 28 NBA_PLUG
RA33 39.2K_0402_1% 1 A
RA31 0_0603_5% 2
5.1K (PIN 48) DA11 AZ5125-02S.R7G_SOT23-3
irs
@
39.2K PORT-E (PIN 14, 15)
SENSE B 20K PORT-F (PIN 16, 17)

pa
10K PORT-H (PIN 20) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 control
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
5 4 3 2 1
re
op
pt
.la
w
w
w
5 4 3 2 1
+3VL +3VL 0_0402_5% RB1

1 2 H_PROCHOT# 5
42 VR_HOT#
0.1U_0402_10V7K 0.1U_0402_10V7K 1000P_0402_50V7K CB3 1
1 1 1 1 1 1 0.1U_0402_10V7K D
CB1 CB2 CB5 CB7 1 2 QB1 1
0.1U_0402_10V7K H_PROCHOT#_EC 2 CB8
For EMI CB4 CB6 G 47P_0402_50V8J
2 2 2 2 2 2
111
125
0.1U_0402_10V7K 1000P_0402_50V7K SSM3K7002F_SC59-3 S 2
22
33
96
67
9
CLK_PCI_EC UB1 3
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
1
RB3 BATT_TEMPA 1 2
10_0402_5% CB9 100P_0402_50V8J
@ GATEA20 1 21 WL_BT_LED#
D 21 GATEA20 GATEA20/GPIO00 GPIO0F WL_BT_LED# 33 D
KB_RST# 2 23 EC_BEEP# ACIN_D 1 2
21 KB_RST# EC_BEEP# 30
2
SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 CB10 100P_0402_50V8J

1 16,28 SERIRQ SERIRQ GPIO12
CB11 LPC_FRAME# 4 27
16,28,32 LPC_FRAME# LPC_FRAME# ACOFF/GPIO13
22P_0402_50V8J LPC_AD3 5
16,28,32 LPC_AD3 LPC_AD3
@ LPC_AD2 7 PWM Output
2 16,28,32 LPC_AD2 LPC_AD2 +3VS
LPC_AD1 8 63 BATT_TEMPA
16,28,32 LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMPA 35
LPC_AD0 10 64
16,28,32 LPC_AD0 LPC_AD0LPC & MISC GPIO39 65 ADP_I
ADP_I/GPIO3A ADP_I 35,36
CLK_PCI_EC 12 AD Input 66 TV tuner
20 CLK_PCI_EC CLK_PCI_EC GPIO3B
PLT_RST# 13 75
5,20,26,27,28,32 PLT_RST# PCIRST#/GPIO05 GPIO42 temperature
EC_RST# 37 76 UMA_ENBKL
+3VL EC_RST# IMON/GPIO43 UMA_ENBKL 19
RB2 EC_SCI# 20
21 EC_SCI# EC_SCII#/GPIO0E
47K_0402_5% AOAC_WLAN_PWR_EN# 38
26 AOAC_WLAN_PWR_EN# GPIO1D
1 2 EC_RST# 68 H_PROCHOT#_EC 1 @ 2
DAC_BRIG/GPIO3C 70 EN_DFAN1 RB6 10K_0402_5%
EN_DFAN1/GPIO3D EN_DFAN1 5
1 2 DA Output 71 PCH_SUSPWRDN# PCH_SUSPWRDN# 18
CB12 0.1U_0402_10V7K KSI0 55 IREF/GPIO3E 72 SUSACK#
KSI0/GPIO30 CHGVADJ/GPIO3F SUSACK# 18
KSI1 56
KSI2 57 KSI1/GPIO31
KSI2/GPIO32 Reserve this signal to EC by SW demand
KSI3 58 83 EC_MUTE#
KSI4 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 USB_EN#
EC_MUTE# 30 2011/10/18a +3VL
KSI4/GPIO34 USB_EN#/GPIO4B USB_EN# 25,29
KSI5 60 85
KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK 33
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 33
KSO1 40 LID_SW# 1 2
KSO2 41 KSO1/GPIO21 RB35 47K_0402_5%
KSO3 42 KSO2/GPIO22 97 VGATE
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 VGATE 18,42
KSO4 43 98 WOL_EN# +5VS
KSO4/GPIO24 WOL_EN/GPXIOA01 WOL_EN# 27
KSO5 44 99 PWRME_CTRL
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH
PWRME_CTRL 16
TP_CLK 1 2
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH 35
RB8 4.7K_0402_5%
C KSO7/GPIO27 SPI Device Interface C
KSO8 47
KSO9 48 KSO8/GPIO28 119 TP_DATA 1 2
KSI[0..7] KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120 RB9 4.7K_0402_5%
32 KSI[0..7] VCIN0_PH connect to
KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 power portion (9012 only)
KSO[0..15] KSO12 51 128
32 KSO[0..15] KSO12/GPIO2C SPICS#/GPIO5A
KSO13 52 SYSON 1 2
KSO14 53 KSO13/GPIO2D RB10 4.7K_0402_5%
KSO15 54 KSO14/GPIO2E 73
RB12 2.2K_0402_5% 81 KSO15/GPIO2F ENBKL/GPIO40 74
1 2 EC_SMB_CK1 82 KSO16/GPIO48 PECI_KB930/GPIO41 89
+3VL KSO17/GPIO49 FSTCHG/GPIO50 DRAMRST_CNTRL_EC 7
1 2 EC_SMB_DA1 90 BATT_FULL_LED#
BATT_CHG_LED#/GPIO52 BATT_FULL_LED# 33
RB13 2.2K_0402_5% 91 WLAN_RST#
CAPS_LED#/GPIO53 WLAN_RST# 26
EC_SMB_CK1 77 GPIO 92
35,36 EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54
RB15 2.2K_0402_5% EC_SMB_DA1 78 93 BATT_CHG_LOW_LED#
35,36 EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_CHG_LOW_LED# 33
+3VS 1 2 EC_SMB_CK2 EC_SMB_CK2 79 SM Bus 95 SYSON
17 EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON 38
1 2 EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON
17 EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON 42
RB16 2.2K_0402_5% 127
PM_SLP_S4#/GPIO59 PM_SLP_S4# 18
PM_SLP_S3# 6 100 PCH_RSMRST#

18 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 PCH_RSMRST# 18
PM_SLP_S5# 14 101 EC_LID_OUT# PROCHOT_IN connect VCOUT0_PH_L 1 2
18 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# 21 VS_ON 37
EC_SMI# 15 102 PROCHOT_IN to power portion (9012 only) RB34 0_0402_5%
21 EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 PROCHOT_IN 35
16 103 H_PROCHOT#_EC VCOUT0_PH connect to power portion (9012 only)
17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 VCOUT0_PH_L VCOUT0_PH connect
USB_CHG_EN# 18 GPIO0B VCOUT0_PH/GPXIOA07 105 BKOFF#
29 USB_CHG_EN# GPIO0C GPO BKOFF#/GPXIOA08 BKOFF# 13 to power portion (9012 only)
BT_ON 19 GPIO 106 PBTN_OUT# RB18
26 BT_ON GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# 18
25 107 PCH_PWR_EN NV-GPU GPS function control pin 330K_0402_5%
EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_PWR_EN 34
FAN_SPEED1 28 108 SA_PGOOD connect to a OR-gate 2 1 +3VL
5 FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 SA_PGOOD 41
WL_OFF# 29
26 WL_OFF# EC_PME#/GPIO15 in the power portion
E51_TXD 30
26 E51_TXD EC_TX/GPIO16
E51_RXD 31 110 ACIN_D ACIN_D 2 1
26 E51_RXD EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN 18,36
PM_PWROK 32 112 EC_ON_R RB751V40_SC76-2 DB1
B 5,18 PM_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 B
PWR_SUSP_LED# 34 114 ON/OFFBTN#
33 PWR_SUSP_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFFBTN# 25,33
36 GPI 115 LID_SW#
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# 33
116 SUSP#
SUSP#/GPXIOD05 SUSP# 34,38,39,40
117
RB20 GPXIOD06 118 EC_PECI 1 2 H_PECI
PECI_KB9012/GPXIOD07 H_PECI 5
AGND/AGND
0_0402_5% 122 RB19 43_0402_1% SUSP# 1 2

1 2 123 XCLKI/GPIO5D 124 +EC_V18R RB21 10K_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND
18 CLK_EC XCLKO/GPIO5E V18R

1
GND0
VR_ON 1 2
om
CB15 RB23 10K_0402_5%
1
1 4.7U_0805_10V4Z
@ RB22 CB16 KB9012QF-A3_LQFP128_14X14 2
11
24
35
94
113
69
1 2 SUSP# 100K_0402_5% 20P_0402_50V8

CB14 180P_0402_50V8J
2
2
.c
Close to EC
EC_ON_R 1 2
EC_ON 37
RB36 2.2K_0402_5%
ts
1
CB50
Voltage Comparator Pins FOR 9012 A3 1U_0402_6.3V6K
2
A
VCIN0 pin109
VCIN1 pin102
VCOUT0 pin104
>1.2V
HIGH
<1.2V
LOW
re
For KB9012 EC_ON low pulse work around
A
ec
VCOUT1 pin103 LOW HIGH
RB27
100K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
irs
1 2 E51_TXD 2010/12/22 2011/12/22 Title

LPC-EC-KB9012&930
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
pa
5 4 3 2 1
Compal Electronics, Inc.

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SPI Flash (128KB) Lid SW LPC Debug Port Place the JDB under DDR DIMM.
JDB @
1
1 +3VS
2
2 3
3 4 PLT_RST# 5,20,26,27,28,31
CLK_PCI_DDR
4 5 CLK_PCI_DDR 20
5 6 LPC_FRAME# 16,28,31
6 7 LPC_AD3 16,28,31
7 8 LPC_AD2 16,28,31
8 9 LPC_AD1 16,28,31
9 10 LPC_AD0 16,28,31
10 11
GND 12
GND
E-T_3801K-F10N-01L
C457 R393
1 2 1 2 CLK_PCI_DDR
22P_0402_50V8J 22_0402_5%
@ @
For EMI
KEYBOARD CONN. G-Sensor
JKB
1 KSO0 1 2
1 2 KSO15 C406 100P_0402_50V8J
2 3 KSO14 KSO1 1 2
3 4 KSO13 C405 100P_0402_50V8J
4 5 KSO12 KSO2 1 2
5 6 KSO11 C404 100P_0402_50V8J
6 7 KSO10 KSO3 1 2
7 8 KSO9 C408 100P_0402_50V8J
8 9 KSO8 KSI0 1 2
9 10 KSO7 C425 100P_0402_50V8J
10 11 KSI7 KSO4 1 2
11 12 KSI6 C407 100P_0402_50V8J
12 13 KSO6 KSI1 1 2
13 14 KSI5 C431 100P_0402_50V8J
14 15 KSO5 KSI2 1 2
15 16 KSI4 C422 100P_0402_50V8J
16 17 KSI3 KSI3 1 2
17 18 KSI2 C423 100P_0402_50V8J
18 19 KSI1 KSI4 1 2
19 20 KSO4 C424 100P_0402_50V8J
20 21 KSI0 KSO5 1 2
21 22 KSO3 C409 100P_0402_50V8J
22 23 KSO2 KSI5 1 2
26 23 24 KSO1 C427 100P_0402_50V8J
27 GND 24 25 KSO0 KSO6 1 2
GND 25 C411 100P_0402_50V8J
ACES_50524-02501-001 KSI6 1 2
C429 100P_0402_50V8J
@ KSI7 1 2
C421 100P_0402_50V8J
KSO7 1 2
KSI[0..7] C412 100P_0402_50V8J
KSI[0..7] 31 1 2
KSO8
KSO[0..15] C415 100P_0402_50V8J
KSO[0..15] 31 1 2
KSO9
m
C416 100P_0402_50V8J
KSO10 1 2
C417 100P_0402_50V8J
KSO11 1 2
co
C418 100P_0402_50V8J
KSO12 1 2
C419 100P_0402_50V8J
KSO13 1 2
C413 100P_0402_50V8J
KSO14 1 2
.
C410 100P_0402_50V8J
KSO15 1 2
ts
C420 100P_0402_50V8J
For EMI
Close to JKB
re
ec
rs
Debug/KB
ai
0.2
QFKAA
p
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5 4 3 2 1
Power Button Touchpad Connector
SW4 +3VL +5VS +5VALW

1 2 JTP
1
3 4 +3VL 2 1
TP_CLK 3 2
G
G
31 TP_CLK TP_DATA 4 3
6 NTC017-DA1J-D160T_4P
5 31 TP_DATA 4
2
5
R395 LID_SW# 6 5
31 LID_SW# BATT_FULL_LED# 7 6
31 BATT_FULL_LED# BATT_CHG_LOW_LED# 8 7
100K_0402_5%
D 31 BATT_CHG_LOW_LED# PWR_SUSP_LED# 9 8 D
For debug
1
ON/OFFBTN# 31 PWR_SUSP_LED# HDD_LED# 10 9
ON/OFFBTN# 25,31 10
1 2 WL_BT_LED_R# 11 13
31 WL_BT_LED# 12 11 G1 14
1 R801 0_0402_5%
C458 12 G2
For debug 0.1U_0402_25V6 WIMAX_LED# 1 2 ACES_50504-0120N-001
@ R802 @ 0_0402_5% @
2
SW3
1 2
3 4 For EMI request Mount R802 and un-mount R801

G
G
NTC017-DA1J-D160T_4P When Wlan LED need Blinking

6
5
CPU VGA PCH

WiMAX LED LED_WIMAX# 26
Screw Hole
2
H1 H2 H3 H4 H5 H8
R819 H_4P2 H_4P6 H_4P2x4P6 H_3P5 H_3P0 H_3P0
2 1 6 1 @ @ @ @ @ @
+3VS
10K_0402_5%
1
1
1
5
WIMAX@ Q156A
2N7002DW-T/R7_SOT363-6
3 4 WIMAX@
Q156B 2N7002DW-T/R7_SOT363-6
WIMAX@
C C
WIMAX_LED#
SATA LED SATA_LED# 16
2
R820
2 1 6 1
+3VS
10K_0402_5%
5
Q5534A PTH
NPTH
HDD_LED# 3 4 2N7002KDWH_SOT363-6
H7 H10 H11 H12 H13 H14 H15 H17 H9 H16

Q5534B H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0x4P0N H_3P0N
2N7002KDWH_SOT363-6 @ @ @ @ @ @ @ @ @ @
1 2
1
1
1
1
@ 0_0402_5%
R4534
H18 H19
H_3P0 H_3P0
@ @
1
PCB Fedical Mark PAD
FD1 FD2 FD3 FD4
B @ @ @ @ B
1
1
1
ISPD
om
ZZZ
PCB LA-8862P
.c
PJP1 45@
s
PJP1
UH1 HM70R1@
A
r UH1 HM76R3@et
Panther Point BD82HM70
A
ec
Panther Point BD82HM76

irs

TP/PWR/LED/Screw/ISPD
0.2
QFKAA
a
5 4 3 2 1
ep
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A B C D E
+3VALW TO +3VS +5VALW TO +5VS

Vgs=10V,Id=9A,Rds=18.5mohm +1.8VS
+3VALW +3VS Vgs=10V,Id=9A,Rds=18.5mohm +5VALW +5VS +5VALW
2
4.7U_0805_10V4Z +5VS
2
1 1 1 1 R470
Q29 C460 4.7U_0805_10V4Z Q30 C462 R5545 470_0805_5%
470_0805_5%
470_0805_5%
8 1 C459 8 1 C461 For EMI 10K_0402_5%
D S D S
2
7 2 1U_0402_6.3V6K 7 2 1U_0402_6.3V6K
1
6 D S 3 2 2 6 D S 3 2 2
0.1U_0402_10V7K
0.1U_0402_10V7K
R406 R407
1
5 D S 4 5 D S 4 PCH_PWR_EN#
D G D G 2 2 22,23 PCH_PWR_EN#
C822 C821
1
SI4800BDY_SO8 1 R409 2 SI4800BDY_SO8 1 R410 2 D Q190
+VSB +VSB
3 1
3 1
1 2 SUSP 1
0.022U_0402_25V7K
0.01U_0402_25V7K
120K_0402_5% @
4.7U_0805_10V4Z
200K_0402_5% @
4.7U_0805_10V4Z
1 1 1 1
1
1
1
6
6
C466 1 1 D G
C465 R412 Q10A C467 C468 R413 Q11A 2 Q5527 S 2N7002_SOT23-3
31 PCH_PWR_EN
3
820K_0402_5% Q10B 820K_0402_5% Q11B G
1
2 2 2 SUSP 5 2 2 @ 2 SUSP 5 S SB570020110
3
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002E-T1-E3_SOT23-3
2
2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 R5529
4
4
1
1
100K_0402_5%
2
Un-used Dual MOS
For S3 CPU Power Saving

+5VALW +0.75VS +1.05VS_VCCP
2
2
R422 R421 R468
100K_0402_5% 22_0805_5% 470_0805_5%
1
1
SUSP
5,9 SUSP
6
39,41 VCCP_PWRGOOD 1 2 0.75VR_EN 0.75VR_EN 38
1
R158 220K_0402_5% Q6A D Q189 D Q60
2 SUSP 2 2N7002_SOT23-3
3
2 G G
2 31,38,39,40 SUSP# 2
Q6B S 2N7002_SOT23-3 S
3
2N7002DW-T/R7_SOT363-6
1
SUSP 5
2N7002DW-T/R7_SOT363-6
4
+5VS_ODD
+5VS TO +5VS_ODD
2
R457
470_0805_5%
6 1
Q53A
2 ODD_EN#
2N7002DW-T/R7_SOT363-6
1
+5VS
3 3
+3VS +5VS
2
C471 Vgs=-4.5V,Id=3A,Rds<97mohm
R441 0.1U_0402_10V7K
10K_0402_5%
2
1
3
S
R440 Q45 PJ28
2
1
G
om
4 3 1 2 2 JUMP_43X79
21 ODD_EN#
@ +5VS_ODD
1
2N7002DW-T/R7_SOT363-6 47K_0402_5% 2
D
1
Q53B AO3413_SOT23
1
C217
0.01U_0402_25V7K
1
1
1
C680
C679 1U_0402_6.3V6K
.c
4.7U_0805_10V4Z 2
@ 2
ts
4
re 4
ec
rs

DC-DC INTERFACE
ai
0.2
QFKAA
A B C D E
p
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A B C D
PL1
HCB2012KF-121T50_0805 PH1 under CPU botten side :
1 2
VIN CPU thermal protection at 93 +-3 degree C Please locate these parts
PL2
Near EC chip
HCB2012KF-121T50_0805 Recovery at 56 +-3 degree C
ADPIN 1 2
@ PJP1
1
+3VL
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
+
100P_0402_50V8J
1
1
1
1
1
2 31,36 ADP_I 1
+
PC2
PC4
PC1
PC3
12.1K_0402_1%
2
1
1K_0402_1%
3
2
2
2
-
PR4
PR1
4
-
SINGA_2DW-0005-B03
2
PR2 PR5
0_0402_5% 0_0402_5%
1 2 1 2
100K_0402_1%_TSM0B104F4251RZ
31 PROCHOT_IN 31 VCIN0_PH
1
2
20K_0402_1%
PH1
PR3
2
1
PL3
HCB2012KF-121T50_0805
1 2
@ VMB
PJP2 PL4
1 HCB2012KF-121T50_0805
1 2 1 2
2 3 BATT+
EC_SMCA PQ1
3 4 EC_SMDA TP0610K-T1-GE3_SOT23-3
4 5 TS_A
0.01U_0402_25V7K
5 6
10U_0805_25V6K
6 7
S
3 1
D
2 2
+VSBP
PJSOT24CW_SOT323-3
7 B+
1
1
1
PC6
PC7
CCM_C250137GR007M262ZR PC5
0.22U_0603_25V7K
0.1U_0603_25V7K
PD1
1000P_0402_50V7K
100K_0402_1%
2
PC9
G
1
2
PR6
@
PC8
2
2
VL
2
2
@ PD2 PR7
PJSOT24CW_SOT323-3 22K_0402_1%
2 1 2 VSB_N_001
1VSB_N_003
1
3 PR8
100K_0402_1%
1 2 PR9
EC_SMB_CK1 31,36
1
PR10 100_0402_1% 0_0402_5% D
1 2VSB_N_002 2 PQ2
18,37 POK
1 2 G SSM3K7002FU_SC70-3
EC_SMB_DA1 31,36
PR11 100_0402_1%
.1U_0402_16V7K
S
3
1
PC10
PJP3
1 2 2 1
@ PR12 6.49K_0402_1%
+3VL +VSBP +VSB
2
PAD-OPEN 2x2m
1 2
BATT_TEMPA 31
@ PR13 1K_0402_1%
3 3
RTC Battery
om
- PBJ1 + PR14
560_0603_5%
PR15
560_0603_5%
2 1 1 2 1 2 +RTCBATT
.c
@ MAXEL_ML1220T10
ts
SP093MX0000
re
ec
4 4
irs

PWR-DCIN / BATT CONN / OTP
pa
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS SAMSUNG
A B C D
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A B C D
for reverse input protection
1
PQ209 D
2
G SI1304BDL-T1-GE3_SC70-3
S
3
PR225 PR226
1 2 1 2
1
1M_0402_5% 3M_0402_5% 1
VIN PQ203 P1 PQ205 P2 B+ PQ207

TPCA8057-H_PPAK56-8-5 DMG4406LSS_SO8 PR211 PL201 DMG4406LSS_SO8
0.01_1206_1% 1UH_NRS4018T1R0NDGJ_3.2A_30%
1 1 8 1 4 1 2 8 1
2 2 7 7 2
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
5 3 3 6 2 3 6 3
0.1U_0402_25V6
2200P_0402_50V7K
0.1U_0402_25V6
5 5
PC216
1
1
1
1
1
1
1
PC213
PC212
PC211
PC215
PC214
0_0402_5%
0.01U_0402_50V7K
@ PR231
1
1
0_0402_5%
PC231
PR232
4
4
4
1
VIN
PC234
2
2
2
2
2
2
@ @ @
PC230
2
1
2
2
2
@
2
PD230
2
BQ24725_ACDRV_1 BAS40CW_SOT323-3
BQ24725_BATDRV 1 2BQ24725_BATDRV_1
0.047U_0402_25V7K PR233
1 1
1 2
10_1206_1%
4.12K_0603_1%
PC237
PR228
PC236 1 2
0.1U_0402_25V6
5
1
1
2.2_0603_5%
PR229
PD231
2
BQ24725_VCC
0.1U_0402_25V6
0.1U_0603_25V7K
RB751V-40_SOD323-2
PQ201
1
PC238
AON7408L
PC235
BQ24725_BST 2
BQ24725_REGN2
DH_CHG 4
2
PC239
4.12K_0603_1%
2
4.12K_0603_1%
BQ24725_LX
2
2
1
1 2 BATT+
PR234
PR235
DH_CHG
PL202
1U_0603_25V6K PC205 4.7UH_ETQP3W4R7WFN_5.5A_20% PR222
3
2
1
1 2 0.02_1206_1%
BQ24725_ACP
BQ24725_ACN
BQ24725_LX 1 2 CHG 1 4
2
1U_0603_25V6K
5
2 3
20
19
18
17
16
PU200
2200P_0402_50V7K
0.01U_0402_50V7K
1
CSON1
CSOP1
4.7_1206_5%
FDMC7692S_MLP8-5
PHASE
HIDRV
VCC
BTST
REGN
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
21
PR206
PAD
0.1U_0402_25V6
0.1U_0402_25V6
PC224
PC225
PC222
PC221
PC223
1
1
1
1
1 15 4
PQ202
DL_CHG
ACN LODRV @
PC241
PC240
2
1
1
2
2
2
2 14 @
680P_0402_50V7K
ACP GND PR236
3
2
1
2
2
1
BQ24725RGRR_VQFN20_3P5X3P5 10_0603_1%
PC206
BQ24725_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP
1
PR237
2
6.8_0603_5%
BQ24725_ACDRV 4 12 SRN1 2 CSON1 @
2
ACDRV SRN
+3VALW 1 2 BQ24725_ACOK 5 11 BQ24725_BATDRV PC242

@ PR238 10K_0402_1% ACOK BATDRV 0.1U_0603_16V7K
ACDET Remember to change PC124 from SE000006S80
IOUT
SDA
ILIM
SCL
to SE025104K80 (2011-02-22)
1 2 +3VALW
+3VL
6
10
PR239 10K_0402_1%
3
PR241 3
BQ24725_ILIM 1 2
0.01U_0402_25V7K
1 2
18,31 ACIN
100K_0402_1%
PR240 10K_0402_1% 150K_0402_1%
PC243
PR242
1
BQ24725_ACDET
om
VIN
1 2
2
154K_0402_1%
PR243
2
1
270K_0402_1%
PR244
Vin Dectector & ILIM

2
.c
EC_SMB_CK1 31,35
2.4 < Vdetect < 3.15V
s
0.1U_0402_25V6
100P_0402_50V8J
66.5K_0402_1%
1
1
Min. Typ Max.

PC246
PR245
100_0402_5%
PC244
et
PR246
EC_SMB_DA1 31,35
H-->L 17.296V
2
L-->H 17.7V
2
ILIM and external DPM 3A

r ADP_I 31,35
100P_0402_50V8J
ec
1
PC245
4
Please locate the RC 4
2
Near EC chip
2011-02-22
irs

a
PWR-CHARGER
ep
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS SAMSUNG 0.2
A B C D
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A B C D E
2VREF_8205
1
PC333
1U_0603_16V6K
2
1 1
PR330 PR350
13K_0402_1% 30K_0402_1%
1 2 1 2
PR331 PR351
B+ 3/5V_B+
20K_0402_1% 20K_0402_1%
3/5V_B+
PL331 1 2 FB_3V FB_5V 1 2
HCB2012KF-121T50_0805
1 2 +3VLP
ENTRIP2
ENTRIP1
PR337 PR357
2200P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
120K_0402_1%
0.1U_0402_25V6
120K_0402_1%
4.7U_0805_25V6-K
1 2 1 2
1
1
1
1
1
PC353
PC354
PC339
PC340
PC338
PC358
6
1
PU330
2
2
2
2
5
REF
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
1
PC341
4 10U_0805_6.3V6M 25
PQ331 P PAD
2
AON7408L
7 24 4 PQ351
VO2 VO1 AON7408L
1
2
3
PC335 8 23 PR355 PC355
0.1U_0402_10V7K PR333 VREG3 PGOOD 2.2_0402_5% 0.1U_0402_10V7K
1 2 BST1_3V 1 2 BST_3V 9 22 BST_5V 1 2 BST1_5V 1 2
3
2
1
2 2.2_0402_5% BOOT2 BOOT1 2
PL332 UG_3V 10 21 UG_5V PL352
4.7UH_ETQP3W4R7WFN_5.5A_20% UGATE2 UGATE1 2.2UH_ETQP3W2R2WFN_8.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
5
5
LG_3V 12 19 LG_5V
LGATE2 LGATE1
SKIPSEL
1
1
4.7_1206_5%
4.7_1206_5%
VREG5
PR356
PR336
1 1
GND
VIN
220U_6.3V_M
220U_6.3V_M
NC
EN
PC331
PC351
+ 4 4 +
POK 18,35
@ PR334 @
1 SNUB_3V 2
SNUB_5V 2
13
14
15
16
17
18
499K_0402_1% RT8205LZQW(2)_WQFN24_4X4
2 1 2 PQ352 2
3/5V_B+ FDMC7692S_MLP8-5
1
2
3
3
2
1
680P_0402_50V7K
PQ332
1
680P_0402_50V7K
FDMC7692S_MLP8-5
VL
1
PC336
PC356
PR338 PC342
100K_0402_1% 1U_0603_10V6K
2
2
2
1
@ @
PC359
4.7U_0805_10V6K
2
3/5V_B+
1
ENTRIP1
ENTRIP2
2VREF_8205
PC360
2
0.1U_0603_25V7K
3 3
6
D D
PQ333A 2N_3_5V_001 5 PQ333B
SSM6N7002FU_US6 G G SSM6N7002FU_US6
om
S S
1
PR339 PJP333
100K_0402_5% PJP352 2 1
+3VLP +3VL
.c
PR340 1 2 1 2 (5A,200mils ,Via NO.= 10)
2.2K_0402_1% VL +5VALWP +5VALW
PAD-OPEN 2x2m
1
1 2
PAD-OPEN 4x4m
31 EC_ON PR341
PQ334
DRC5115E0L_SOD323-3 PJP332 2
PJP353
1
s
0_0402_5% 1 2 VL +5VL
+3VALWP +3VALW (4A,120mils ,Via NO.= 8)
1 2 2 PAD-OPEN 2x2m
31 VS_ON
et
PAD-OPEN 4x4m
4.7U_0805_25V6-K
1
PC343
r
2
ec
4 4
rs

ai
PWR-3.3VALWP/5VALWP
Custom 0.2
ep
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS QCLA4 LA-8861P M/B
A B C D E
o pr
pt
.la
w
w
w
5 4 3 2 1
0.75Volt +/- 5%
TDC 0.7A
Peak Current 1A
PL151
HCB1608KF-121T30_0603
D B+ 1 2 1.5V_B+ D
PR155 2
BST_1.5V 1 BOOT_1.5V +1.5V
2.2_0402_5%
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
4.7U_0805_25V6-K
DH_1.5V +0.75VSP
1
1
0.22U_0402_10V6K
PC153
PC158
PC154
PC157
PC155
SW_1.5V
10U_0805_6.3V6K
10U_0805_6.3V6K
10U_0805_6.3V6K
2
2
2
1
1
PC260
PC262
PC261
@
1
5
DL_1.5V
16
17
18
19
20
PU150
2
2
PHASE
UGATE
BOOT
VLDOIN
VTT
21 @
PAD
4 15 1
LGATE VTTGND
PQ151 PR152 14 2
PL152 AON7408L 20K_0402_1% PGND VTTSNS
1
2
3
1UH_FDSD0630-H-1R0M-P3_11A_20% 1 2CS_1.5V
2 1 13 3
+1.5VP PC159 CS RT8207MZQW_WQFN20_3X3 GND
5
1U_0603_10V6K
1 2 12 4 VTTREF_1.5V
PR157 VDDP VTTREF
1
1 5.1_0603_5%
1 2 11 5 +1.5VP
390U_2.5V_M
C VDD_1.5V C
+ VDD VDDQ
PC152
PR156 4
PGOOD
1
4.7_1206_5%
TON
PQ152 +5VALW PC161
FB
S5
S3
SNUB_+1.5VP 2
1
2 FDMC7692S_MLP8-5 0.033U_0402_16V7K
2
PC160
1
2
3
10
6
1U_0603_10V6K
+5VALW
2
PR154
10.2K_0402_1%
FB_1.5V 2 1 +1.5VP
TON_1.5V
1
PC156
680P_0402_50V7K
2
Mode Level +0.75VSP VTTREF_1.5V
2
PR158
S5 L off off
1
887K_0402_1% PR160 PC162
S3 L off on PR159 1.5V_B+ 1 2 10K_0402_1% .1U_0402_16V7K
S0 H on on 0_0402_5%
2
1 2 EN_1.5V
1
31 SYSON
Note: S3 - sleep ; S5 - power off
EN_0.75VSP
1 @ PC163 @ PR161
0.1U_0402_10V7K 0_0402_5%
B 2 1 B
2
34 0.75VR_EN
PR162
0_0402_5%
m
PJP152 2 1
1 2 31,34,39,40 SUSP#
PAD-OPEN 4x4m
co 1
PJP153
1 2 (12A,480mils ,Via NO.= 24) @ PC164
+1.5VP +1.5V 0.1U_0402_10V7K
2
PAD-OPEN 4x4m
.
ts
PJP76
+0.75VSP
1
PAD-OPEN 3x3m
2
+0.75VS (1A,40mils ,Via NO.= 3)
re
ec
A A
rs
Security Classification Compal Secret Data

Title
Issued Date 2010/07/20 Deciphered Date 2012/12/31
PWR-1.5VP / +0.75VSP
ai
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom SAMSUNG 0.2
5 4 3 2 1
p
re
op
pt
.la
w
w
w
5 4 3 2 1
PL401
HCB1608KF-121T30_0603
+1.05VSP_B+ 2 1
B+
+3VS
2200P_0402_50V7K
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
1
1
1
PC401
PC407
PC408
PC403
D D
2
2
PR401
5
100K_0402_1%
2
PR405 PC405
2.2_0402_5% 0.22U_0402_10V6K 4 PQ401
34,41 VCCP_PWRGOOD
PU400 1 2 BST1_+1.05VSP 1 2 AON7518
TPS51212DSCR_SON10_3X3
PR402 1 10 BST_+1.05VSP
3
2
1
60.4K_0402_1% PGOOD VBST
1 2 TRIP_+1.05VSP 2 9 UG_+1.05VSP UG_+1.05VSP1 PL402
TRIP DRVH 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
EN_+1.05VSP 3
EN SW
8 SW_+1.05VSP 1 2 +1.05VSP
5
PR404 FB_+1.05VSP 4 7
0_0402_5% VFB V5IN +5VALW
330U_D2_2.5VY_R15M
1
1 2 RF_+1.05VSP 5 6 LG_+1.05VSP 1
31,34,38,40 SUSP# TST DRVL
1
+
PC402
11 PR406
TP
1
PC410 4 4.7_1206_5%
1
1U_0603_10V6K PQ402
1 SNUB_+1.05VSP2
@ PC411 PR407 TPCA8059 2
0.1U_0402_16V7K 470K_0402_1%
2
1
PC412
2
3
2
1
C .1U_0402_16V7K C
2
@ PC413 @ PR408 PC406
1000P_0402_50V7K 1.2K_0402_1% 680P_0402_50V7K
2
1 2 +1.05VSP1 1 2 +1.05VSP
PR409 PR410
4.99K_0402_1% 100_0402_1%
2 1 VCCIO_SENSE1 2 1
VCCIO_SENSE 8
2
PR414
10K_0402_1%
1
PJP402
1 2
PAD-OPEN 4x4m
PJP403
1 2
B +1.05VSP +1.05VS_VCCP(12A,480mils ,Via NO.= 24) B
PAD-OPEN 4x4m
m
co
t s.
re
ec
A A
rs

Title
PWR-V1.05SP
ai
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom SAMSUNG 0.2
5 4 3 2 1
ep
o pr
pt
.la
w
w
w
A B C D
1 1
PU180
SY8033BDBC_DFN10_3X3
PL181 PL182
4
HCB1608KF-121T30_0603 1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2 VIN_1.8VSP 10 2 LX_1.8VSP 1 2
PG
+5VALW PVIN LX +1.8VSP
9 3
68P_0402_50V8J
PVIN LX
1
1
1
8
PC188
PC184
4.7_1206_5%
SVIN
PR186
22U_0805_6.3V6M PR181
6 20K_0402_1%
2
5 FB
22U_0805_6.3V6M
22U_0805_6.3V6M
2
2
EN
1
NC
NC
TP
PC182
PC183
FB_1.8VSP
11
2
31,34,38,39 SUSP#
SNUB_1.8VSP
1 2 EN_1.8VSP
1
PR183
0_0402_5% PR182
0.1U_0402_10V7K
1
10K_0402_1%
PC187
2
@ PR184
680P_0603_50V7K
47K_0402_5%
PC186
2
@ PJP182
1 2 (3A,120mils ,Via NO.= 6)
+1.8VS
2
2 +1.8VSP 2
PAD-OPEN 4x4m
3 3
m
. co
e ts
e cr
4 4
rs

i

pa
PWR-1.8VSP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS SAMSUNG 0.2
A B C D
re
op
pt
.la
w
w
w
5 4 3 2 1
The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability. VID [0] VID[1] VCCSA Vout
0 0 0.9V
D D
0 1 0.8V
1 0 0.725V
1 1 0.675V
output voltage adjustable network
2
PC805
680P_0402_50V7K
1
SNUB_+VCCSA
+VCC_SAP
TDC 4.2A
Peak Current 6A
2
PR801 OCP current 7.2A
4.7_1206_5%
1
PL803 PU801 PL801
HCB1608KF-121T30_0603 SY8037BDCC_DFN12_3X3 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
+5VALW 1 2 +VCCSA_PWR_SRC 12
PVIN LX
1 +VCCSA_PHASE 1 2 +VCCSAP
11 2
PC815 PVIN LX
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
68P_0402_50V8J 10 3 PR804 SA_PGOOD 31
SVIN LX
2
100K_0402_5%
PC801
PC802
PC803
PC804
22U_0805_6.3V6M
22U_0805_6.3V6M
2200P_0402_50V7K
0.1U_0603_25V7K
2
+VCCSAP_FB 1 9 4 2 1
C 2 FB PG +3VS C
1
1
PC818
PC819
PC820
PC817
1
8 5 +VCCSA_EN 1 2
VOUT EN
GND
2
2
2
1 7 6 PR806
VID1 VID0 0_0402_5%
0.1U_0402_10V7K
13
PR812
1
100_0402_5%
PC809
2
2
34,39 VCCP_PWRGOOD 2 1
1K_0402_5%
1K_0402_5%
PR802
PR805
2
@ PR811
0_0402_5%
1
2 1
+VCCSA_SENSE 9
H_VCCSA_VID0 9
H_VCCSA_VID1 9
PJP801
B +VCCSAP 1 2 +VCCSA B
PAD-OPEN 4x4m
om
.c
ts
re
ec
A A
irs

Title
pa

PWR-VCC_SAP
C SAMSUNG 0.2
5 4 3 2 1
re
op
pt
.la
w
w
w
5 4 3 2 1
PUT CLOSE
TO GT
Inductor
PR502 PC502 PC503
10_0402_1% 3300P_0402_50V7K .1U_0402_16V7K
1 2 FBA3 1 2 1 2
1500P_0402_50V7K
560P_0402_50V7K
D D
PR503 PR504
75K_0402_1%
2
1
2
8.06K_0402_1% 806_0402_1% 1 2
TRBSTA# 1 2 FBA1 1 2
PC504
PC505
PR506
PR505 PH503 PR507 PC506
1
24K_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
PR509 PC508 @ <BOM Structure>
2
1
1
PC507 10_0402_1% 680P_0402_50V7K 2 PR508 1 NTC_PH203 1.65K_0402_1% 1000P_0402_50V7K
0.033U_0402_16V7K 1 2 FBA2 1 2 PC509 1 2 10P_0402_50V8J
165K_0402_1% HF: 1.65K
2
PR511 PC510 2P: install
1 2 1 2 COMPA1 1 2 1 PR512 2 SWN2A 2P: 1.65K
1P: @ 1P: 1K
PR510 5.11K_0402_1% 2200P_0402_25V7K 80.6K_0603_1% CSREFA
1
1K_0402_1% PC511 TSENSEA
2
1 PR513 2 SWN1A @ PR514 0.047U_0402_16V7K
0_0402_5%
80.6K_0603_1% PR515 5.49K_0402_1%
1
CSP1A 1 2
SWN1A 43
2
2
2
21.5K_0402_1%
CSCOMPA
PC512
9 VCC_AXG_SENSE
1
2
2
1000P_0402_50V7K
1PR516
13.7K_0402_1%
1
PC513 CSREFA 2P: install PH504
1
1000P_0402_50V7K
PR517
CSREFA 43 1P: @
2
@ PR518 PC514 100K_0402_1%_TSM0B104F4251RZ
9 VSS_AXG_SENSE
PC515 0_0402_5% 0.047U_0402_16V7K
1
CSP2A
CSP1A
1 2
1
TRBSTA#
CSP2A 1 2
DROOPA
CSSUMA
TSENSEA
SWN2A 43
2
COMPA
.1U_0402_16V7K PR519
FBA
IMONA
DIFFA
ILIMA
5.49K_0402_1%
PR501 PR520 2P: 36K

2_0603_5% 1 2 PUT CLOSE
+5VS 1 2 36K_0402_1% 1P: 26.1K
61
60
59
58
57
56
55
54
53
52
46
51
50
49
48
47
+1.05VS_VCCP PU500 TO V_GT
C C
PC501 HOT SPOT
PAD
TRBSTA#
TSNSA
VSNA
VSPA
DIFFA
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
6132_PWMA 43
2.2U_0603_10V7K
1 2 6132_VCC
1 45 PR523 PC518
VCC PWMA
1
PR521 2 44 BST3 1 2 BST3_1 1 2

PC517 PC516 0_0402_5% 3 VDDBP BSTA 43 4.7_0603_5% 0.22U_0402_10V6K +5VS
54.9_0402_1%
VRDYA HGA HG3 43

2
.1U_0402_16V7K .1U_0402_16V7K 1 2 VR_ON_CPU 4 42

130_0402_1%
31 VR_ON SW3 43
2
VR_SVID_DAT1 5 EN SWA 41 PC519

PR524
PR522
SDIO LGA LG3 43

PR526 VR_SVID_ALRT# 6 40 BST2 1 PR525 2 BST2_1 1 2 2Phase: @
PR528 10K_0402_1% VR_SVID_CLK 7 ALERT# BST2 39 4.7_0603_5% 0.22U_0402_10V6K
SCLK HG2 HG2 43 1Phase: install
1
95.3K_0402_1% 1 2 VBOOT 8 38 Option for
SW2 43
1
1 2VR_SVID_DAT1 1 2 ROSC_CPU 9 VBOOT NCP6132BMNR2G_QFN60_7X7 SW2 37 @ PR531

8 VR_SVID_DAT ROSC LG2 LG2 43 1 phase GFX
PR527 0_0402_5% CPU_B+ 1 2 VRMP 10 36 6132P_VCCP 1 2 1 2 0_0402_5%
8 VR_SVID_ALRT# VRMP PVCC
VR_HOT# 11 35 PR530 0_0402_5% PC520 2.2U_0603_10V7K
8 VR_SVID_CLK VRHOT# PGND
PR529 VGATE 12 34 1 2
0.01U_0402_25V7K
LG1 43 +5VS
2
1K_0402_1% 13 VRDY LG1 33 PR532 0_0402_5% CSP2A
+1.05VS_VCCP +3VS VSN SW1 SW1 43
1
14 32
PC521
VSP HG1 HG1 43

DIFF_CPU 15 31 BST1 1 2 BST1_1 1 2
CSCOMP
DIFF BST1
TRBST#
PR533
CSSUM
DROOP
DRVEN
CSREF
2
COMP
1
TSNS
CSP3
CSP2
CSP1
4.7_0603_5% PC522
PWM
IOUT
ILIM
2
PC523 PR534 PR535 0.22U_0402_10V6K
FB
47P_0402_50V8J 75_0402_1% 10K_0402_5% +5VS
1
22
16
17
18
19
20
21
23
24
25
26
27
28
29
30
3P: 73.2K
2
1 PR536 2
31 VR_HOT# 18,31 VGATE 2P: 41.2K
1
FB_CPU 73.2K_0402_1% Option for 3Phase: @
TRBST#
PR538 COMP_CPU 2 phase CPU @ PR537

2Phase: install
DROOP
TSENSE
2 ILIM_CPU
1 2 VSN 0_0402_5%
8 VSSSENSE 6132_PWM 43
1
0_0402_5%
IMON
PC524
DRVEN 43
2
PR540 1000P_0402_50V7K CSP3 1 PR539 2 CSP3
SWN3 43
2
1
1 2 VSP PC526 5.76K_0402_1%
8 VCCSENSE
1
0_0402_5% 1 2 @ PR542
21K_0402_1%
0_0402_5% PC525 3P: install

B .1U_0402_16V7K 0.047U_0402_16V7K B
2P: @
2
PR543 CSP1 CSREF TSENSE
2
1 2 PC527 2 122P_0402_50V8J CSP2
1
m
1K_0402_1% CSP3
CSP2 1 PR544 2
SWN2 43
1
5.76K_0402_1%
PR541
1
PR545 PC528 PR547 PC529 @ PR546
1 2FB_CPU1 1 2 2 1COMP_CPU12 1 0_0402_5% PC530
PR548 PC531 49.9_0402_1% 6.04K_0402_1% 0.047U_0402_16V7K
co 2
1 2FB_CPU3 1 2 680P_0402_50V7K 2200P_0402_50V7K CSREF
13.7K_0402_1%
2
2
10_0402_1%
CSREF 43
CSCOMP
0.033U_0402_16V7K PH502
PR550
2
PR551 PR552 CSP1 1 PR549 2

SWN1 43
1
TRBST# 1 2 FB_CPU2 1 2 PC532 5.76K_0402_1% 100K_0402_1%_TSM0B104F4251RZ
1
1000P_0402_50V7K @ PR553
0.033U_0402_16V7K
1
1
s.
8.06K_0402_1% 806_0402_1% 0_0402_5% PC533
PC534 0.047U_0402_16V7K
2
CSSUM CSREF
2
2
1 2
et
PC535 1500P_0402_50V7K 1 PR554 2 SWN1
160K_0603_1% PUT CLOSE
23.7K_0402_1%
2
.1U_0402_16V7K
@ 1 2 1 PR556 2 SWN2 TO VCORE

PC536
PC537 330P_0402_50V7K 160K_0603_1% HOT SPOT

PR555
1 2 1 2
r 1 PR559 2 SWN3
1
PR557 PR558 160K_0603_1%

ec
PR560 PC538 75K_0402_1% 165K_0402_1%
CSCOMP 1 2 DROOP 1 2 CSREF
806_0402_1% 1000P_0402_50V7K 2 1
PH501 220K_0402_5%_ERTJ0EV224J
rs
A A
PUT CLOSE
TO VCORE
Phase 1
i
Inductor
pa

PWR-CPU_CORE
re
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom QCL70 0.2
5 4 3 2 1
op
pt
.la
w
w
w
5 4 3 2 1
CPU_B+ CPU_B+
5
5
0.1U_0402_25V6
0.1U_0402_25V6
10U_0805_25V6K
2200P_0402_25V7K
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1
1
1
1
1
1
PC543
PC546
PC541
PC544
PC540
PC545
PC539
PC542
AON7518
AON7518
AON7518
AON7518
2
2
2
2
2
2
2
4 4 4 4
PQ503
PQ501
PQ505
PQ507
42 HG1 42 HG2
+CPU_CORE +CPU_CORE
@ @
3
2
1
3
2
1
3
2
1
3
2
1
D D
PL511 PL512
0.36UH_FDUE1030D-H-R36M=P3_32A_20% 0.36UH_FDUE1030D-H-R36M=P3_32A_20%
1 4 1 4
42 SW1 42 SW2
1
2 3 2 3
5
5
PR564
PR563 4.7_1206_5%
4.7_1206_5%
2
PR565 PR566
1SNUB_CPU1
2
4 PQ502 V1N_CPU 2 1 4 PQ504 V2N_CPU 2 1 CSREF
SNUB_CPU2
42 LG1 CSREF 42 42 LG2
TPCA8057 TPCA8057
10_0402_1% 10_0402_1%
SWN1 42 SWN2 42
3
2
1
3
2
1
PC547
680P_0402_50V7K
1
PC548
PL516
HCB2012KF-121T50_0805 680P_0402_50V7K
2
B+ 2 1
CPU_B+
PL517
HCB2012KF-121T50_0805
2 1
CPU_B+
1 1
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_25V7K
1
1
1
1
+ +
PC550
PC549
PC551
PC552
@ PC553 PC554 @ PC555
0.1U_0603_25V7K 100U_25V_M 100U_25V_M
2
2
2
5
5
2 2
QC 45W CPU (HF)
AON7518
solution: 3+2
MOS: cpu_core --> 上上2(AON7518) 下1(FDMS0308AS)
2(AON7518)下1(FDMS0308AS)
AON7518
4 4 PQ511
PQ509
42 HG3
C Gfx_core --> C
@
QC 45W CPU DC 35W CPU
+CPU_CORE VID1=0.9V VID1=1.05V
3
2
1
3
2
1
PL513
IccMax=94A IccMax=53A QC 45W CPU
上上1(AON7518) 下1(FDMS0308AS)
0.36UH_FDUE1030D-H-R36M=P3_32A_20%
42 SW3
1 4 Icc_Dyn=66A Icc_Dyn=43A solution: 3+2
Icc_TDC=56A Icc_TDC=33A MOS: cpu_core -->
1
2 3
5
R_LL=1.9m ohm R_LL=1.9m ohm

PR568
OCP~110A OCP~65A
Gfx_core -->
4.7_1206_5%
2
4 PQ506
42 LG3
TPCA8057 DC 35W CPU
上上1(AON7518) 下1(FDMS0308AS)
SNUB_CPU3
solution: 2+1
V3N_CPU 2 PR5691 CSREF
MOS: cpu_core -->
3
2
1
10_0402_1% Gfx_core -->

1
PC556
680P_0402_50V7K SWN3 42
2
CPU_B+
CPU_B+ 2Phase: install
B
PR570 1Phase:: @ B
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_25V7K
BSTA1 1 2 BSTA1_1
1
1
1
4.7_0603_5%
PC559
PC560
PC558
PC561
5
0.1U_0402_25V6
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
0.22U_0402_10V6K
1
2
2
2
1
5
1
PC557 BSTA2 1 PR571 2 BSTA2_1

PC564
PC565
PC562
PC563
om
PC566
2
1
4.7_0603_5% 0.22U_0402_10V6K
AON7518
AON7518
2
2
4 4
PQ513
PQ515
AON7518
AON7518
2
PU501 4 4
PQ517
PQ519
1 9 @ +GFX_CORE
BST FLAG PU502 +GFX_CORE
3
2
1
3
2
1
2 8 HG1A PL514 1 9 @
42 6132_PWMA PWM DRVH BST FLAG
PR573 FDUM0640J-H-R36M=P3
3
2
1
3
2
1
2 1EN_GFX1 3 7 SW1A 1 2 2 8 HG2A PL515
42 DRVEN EN SW 42 6132_PWM PWM DRVH
2K_0402_1% FDUM0640J-H-R36M=P3
.c
2 1VCC_GFX1
2 1 4 6 DRVEN 2 PR577 1EN_GFX2 3 7 SW2A 1 2
VCC GND EN SW
5
PR575 PR576 2K_0402_1%

1
+5VS 0_0402_5% 0_0402_5% 5 LG1A +5VS 2 1VCC_GFX2

2 1 4 6
DRVL VCC GND
5
PR578 PR579
1
1
NCP5911MNTBG_DFN8_2X2 PR580 0_0402_5% 0_0402_5% 5

DRVL
ts
4.7_1206_5% 1
PC567 4 2 PR581 1 NCP5911MNTBG_DFN8_2X2 PR582
CSREFA 42
1SNUB_GFX1
2
2
2.2U_0603_10V7K PC570 4.7_1206_5%

PQ508 10_0402_1% 2.2U_0603_10V7K LG2A 4 2 1 CSREFA
2
2
TPCA8057
2 1 PQ510 PR583
SWN1A 42
re
SNUB_GFX2
3
2
1
TPCA8057 10_0402_1%
PC568 PR584
3
2
1
0_0402_5% 2 1
680P_0402_50V7K SWN2A 42
2
PR585
0_0402_5%
1
ec
PC569
680P_0402_50V7K
2
A A
irs
QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Icc_Dyn=37A Icc_Dyn=20.2A Security Classification Compal Secret Data
Title
2009/12/01 2010/12/31
pa
Icc_TDC=38A Icc_TDC=21.5A Issued Date Deciphered Date

R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS QCL70
5 4 3 2 1
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5 4 3 2 1
+CPU_CORE +CPU_CORE
+GFX_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.
1
1
1
1
5 x 22 µF (0805)
PC1101 PC1102 PC1103 PC1104 PC1105 +GFX_CORE
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
Socket Bottom 5 x (0805) no-stuff
2
2
2
2
sites
D D
7 x 22 µF (0805)
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1
2 x (0805) no-stuff
PC1151
PC1157
PC1153
PC1155
PC1156
PC1158
PC1152
PC1154
Socket Top
1
1
1
1
PC1106 PC1107 PC1108 PC1109 PC1110
2 2 2 2 2 2 2 2
sites
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2
2
2
2
+CPU_CORE +1.05VS_VCCP
1 1 1 1 1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1
22U_0805_6.3V6M
22U_0805_6.3V6M
330U_D2_2V_Y
22U_0805_6.3V6M
22U_0805_6.3V6M
330U_D2_2V_Y
330U_D2_2V_Y
PC1111 PC1112 PC1113 PC1114 PC1115 1 1 1 1
PC751
PC755
PC759
PC1159
PC1161
PC1166
PC1160
PC1162
PC752
PC761
PC1164
PC1165
PC753
PC754
PC760
PC756
PC757
PC758
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M + + +
2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2
1 1 1 1 1
22U_0805_6.3V6M
1 1
330U_D2_2V_Y
330U_D2_2V_Y
PC1116 PC1117 PC1118 PC1119 PC1120 1
PC763
PC765
PC762
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M + +
2 2 2 2 2
+CPU_CORE
C 2 2 2 C
1 1 1 1 1
1 1 1 1 1 1
+ PC1127 + PC1128 + PC1129 + PC1130 + PC1131
PC1121 PC1122 PC1123 PC1124 PC1125 PC1126 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 2 2 2 2 2
Chief River 330uF*9m 470uF*4.5m 22uF 10uF
B B
8layer for DC CPU 16 10
4
8layer for QC CPU 5 16 10
om
6layer for DC CPU 5 16 10
.c
6layer for QC CPU 4 1 16 10
ts
GFX_CORE DC 2 12
re GFX_CORE QC 3 12
ec
A A
1.05V_VCCP 2 12
irs

PWR - PROCESSOR DECOUPLING
pa
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS QCLA4 LA-8861P M/B 0.2
5 4 3 2 1
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NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------------------
1. 2011/09/29 P51-PWR_+3VALWP/+5VALWP Change PU330 to RT8205L Change source
2. 2011/09/29 P53-PWR_ +1.05VS_VCCP/+16VSP Change PU400 to RT8237C Change source
3. 2011/09/29 P54-PWR_+VCCSAP/1.8VSP Change PU450 to SY8037B Change source
4. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change HMOS to MDV1525 Change source
5. 2011/09/29 P53-PWR_ +1.05VS_VCCP/+16VSP Change HMOS to MDV1525 Change source
6. 2011/09/29 P49-PWR_BATTERY CONN / OTP Change PD5,PD6 to SCA00001G00 ESD team request
7. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PR589 from 348 to 8.06k FAE suggestion
8. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PR590 from 3.65k to 806 FAE suggestion
10. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PC574 from 680P to 0.033u FAE suggestion
12. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PR548 from 1.21k to 8.06k FAE suggestion
13. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PR550 from 10.7k to 806 FAE suggestion
16. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Add snubber and boost resistor For 3x3 H-MOS solution
17. 2011/09/29 P49-PWR_BATTERY CONN / OTP Add PR22 30k,PR27 100k, PR32 0 Ohm For 120W adapter protect(9012)
18. 2011/09/29 P51-PWR_+3VALWP/+5VALWP Change PC360 to SE000006R80 Change source
19. 2011/09/29 P49-PWR_BATTERY CONN / OTP Add PR17 14k, PR33 0 Ohm For CPU temperature protect(9012)
20. 2011/09/29 P51-PWR_+3VALWP/+5VALWP Add PR373 0 Ohm For 3/5V always power on(9012)
om
.c
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Power PIR
Custom 0.2
QFKAA
pa
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5 4 3 2 1
HW PIR (Product Improve Record)

QCLA4,5 LA-7201P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.0 TO 0.1
GERBER-OUT DATE: 2011/12/30
---------------------------------------------------------------------------------------------------------------------
1 11/24 33 Change P33 ALC280 schematic to ALC259 schematic. For audio function
2 11/24 34 Change JEXMIC.4 JACK_SENSE to MIC_SENSE. For audio function
3 11/24 35 Delete UB3,RB26,CB18,RH296 For delete CIR function
4 11/24 6,13,21 Delete QC1,RC4,C261,U17,R147,R103,R360,R392,R390,R1441~1442,R361,R106,RH304 For LVDS only
5 11/24 6,13,17 Delete Q23,C293,R62,R389,R120,R79,R97,L60,R262~265,R299~300,RH275,R1440 For LVDS only
D
6 11/24 6,13 Delete CPU_EDP_HPD,+LCD_VDD_R,+PANEL_VDD,LVDS_ENVDD,+3VS_LVDSDDC For LVDS only D
7 11/24 13 Delete D15 BOM structure and JLVDS.10 connect to +3VS For LVDS function
8 11/24 13 Add J17 connector and change JLVDS from 40 to 30 pin connector. For LVDS function
9 11/24 20 Delete USB20_N13,USB20_P13 For no Glasses free 3D Panel
10 11/24 13 Change RC82 BOM structure from IEDP@ to @. For LVDS function
11 11/24 5,17 Change RC157,RC158,RH119,RH203 BOM structure from LVDS@ to mount. For LVDS function
12 11/24 17 Delete CLK_CPU_EDP#,CLK_CPU_EDP For LVDS only
13 11/24 15 Delete CEC schematic and JHDMI.13 HDMI_CEC net For no CEC support
14 11/24 15 Delete R570,D55 and change U9.4 HDMI_HPD_R to HDMI_HPD For HDMI HPD
15 11/25 15 Change L8~11 to SM070001U00 For HDMI signal
16 11/25 15 Delete U9.5 from +5VL to +5VS For HDMI HPD
17 11/25 33 Change Audio codec schematic For ALC259-VC2
18 11/25 17,29 Delete CH16,CH18,card reader schematic For RTS5129
19 11/25 26 Delete FP & B-CAS schematic For no support FP & B-CAS function
20 11/25 35,37 Delete JFUN,R8,R1466~1467,D90 For no support JFUN
21 11/25 20,27 Delete USB20_N10,USB20_P10,USB20_N12,USB20_P12 For no support TV tuner & 3G
22 11/25 27 Delete RH181 & 3G,B-CAS,JET schematic For no support TV tuner & 3G
23 11/25 16,27 Delete mSATA schematic For no support mSATA function
24 11/25 27 Delete RCL3,271@ component and net OSC_IN_R_R,OSC_IN_R For no support S&M function
25 11/25 6 Change RC3 from 1Kohm to 10Kohm (SD028100280) For no support eDP function
26 11/25 35 Delete UB1.89 HDPACT,UB1.86 HDPLOCK,UB1.68 HDPINT For no support G-SENSOR function
27 11/28 35 Change PCH_PWR_EN from UB1.70 to UB1.68 and add UB1.70 EN_DFAN1 For support RPM FAN
28 11/28 5,35 Delete C1~4,R1~2,D1 and UB1.26 FANPWM For no support PWM FAN
C C
29 11/29 25 Delete S&C schematic For no support S&C
30 11/29 31,32 Delete USB3.0 Host schematic For no support external USB3.0 host IC
31 11/30 38 change R409 from 120K_1% to 120K_5% For change tolerance
32 11/30 33 change RA17 from 0_1% to 0_5% For change tolerance
33 11/30 13 Delete R260 and short directly For reduce circuit
34 12/01 16 change DH1 from @ to NOGCLK@ For BOM control
m
35 12/01 37 Add SW4 For Debug
36 12/01 36 Delete U21,C453,C452 For LID on small board
co
37 12/02 35 Delete CPSETIN For delete EC930 schematic
38 12/02 16 Add JRTC,CH9,DH8,DH9,R227 For non-rechargeable RTC schematic
39 12/02 36 Delete JBLG schematic For non-keyboard led schematic
s.
40 12/05 36 Modify JKB pin define For meet SS KB Matrix
41 12/05 13 Change location from J17 to JLVDS1 For location naming
42 12/06 35 Delete UB1.85 SM_SENSE# For no support S&M
43
44
45
12/06
12/06
12/07
25
38
25
Modify JUSIO pin define
Delete R425 and 0.75VR_EN#
Add JODDB
For small board connect
For Power circuit connect
r
For 15" ODD connector
et
ec
46 12/07 15 Change U9.5 connect from +5VS to +HDMI_5V_OUT For prevent leakage issue
47 12/08 29 Change JCRIO pin define For small board connect
48 12/12 21 Change UH1.K1 and RH180.2 from BT_ON# to PCH_GPIO34 For common GPIO pins on EC side
rs
49 12/12 35 UB1.18 and RB11 connect to BT_ON# For common GPIO pins on EC side
50 12/12 25,35,37 Delete PWR_ON_LED# net For common GPIO pins on EC side
ai
B
51 12/12 25 Change JUSIO pin define For LED behavior B
52 12/12 16 Delete CH9,DH8,DH9,R277,JRTC For RTC change to rechargeable

53 12/13 21 Delete Q51 and change PCH_WL_BT_LED to PCH_GPIO69 For change WL_BT_LED# to EC GPIO
ep
54 12/13 35 UB1.21 connect WL_BT_LED# For change WL_BT_LED# to EC GPIO

55 12/13 37 Change Q156B.3 from WL_BT_LED# to WIMAX_LED# and connect to R802 For WLAN LED behavior
56 12/13 35 Delete UB1.127 (USB_OC#0) and UB1.17 (USB_OC#1) For no support USB S&C
pr
57 12/13 20,29 Add TPM schematic For TPM function

58 12/13 27 Delete Q36 For change BT_ON# to EC GPIO
o
59 12/13 14,30,37 Change JCRT,JUSBA,JUSBB,JTP symbol For connector list update

60 12/13 25,29 Change JUSIO,JCRIO symbol For connector list update
pt
61 12/14 27 Change UCL1 to SLG3NB244VTR For green clock

62 12/14 29 Change UT1.5 and RT7.1 net from +3VALW to +3VALW_PCH For ErP Lot6 function
.la
63 12/14 21 Add RH181 and connect ISDBT_DET, delete RH297 For no support TV tuner
64 12/14 21 Change RH194 from 100K 5% to 10K 5% For update resistor value
65 12/14 21 Change RH315.2 connect +3VS and BOM structure to mount For update resistor value
w
66 12/14 37 Change ZZZ P/N to DA60000T600 For update PCB P/N

67 12/14 37 Move D89 to TP small board For Move to TP small board
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68 12/15 16~24 Change UH1 P/N to SA00005FH30 For update UH1 P/N
69 12/15 30 Change CR40 P/N to SF000002Y00 For layout limitation
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70 12/15 33 Delete RA53 For common design

71 12/15 25 Delete C381~4 For placement update
72 12/15 30 Delete RR23~24,CR26,RR36~37,CR29 For connect GND directly
A 73 12/15 9 Delete CC67 For not reserve A
74 12/19 16 Delete T67~T69 For not reserve

75 12/19 29 Change YT1 form SJ132P7KW10 to SJ100004Z00 (small package) For change to small size
76 12/19 29 Change CT2, CT3, CT4, CT5 from SE095104K80 to SE102104K00 For BOM reduce
77 12/19 29 Change JCRIO to SP010015H00 For follow connector list
78 12/20 13 Delete JLVDS.28 (+LCD_INV) For prevent issue
79 12/20 37 Modify H1~H17 For Update screw hole
HW-PIR
Custom 0.2
QCLA4,5 LA-8862P M/B
5 4 3 2 1
5 4 3 2 1
HW PIR (Product Improve Record)

---------------------------------------------------------------------------------------------------------------------
80 12/20 35 Change UB1.68 (PCH_PWR_EN) to UB1.107 For EC common
81 12/20 35 Change UB1.73 (UMA_ENBKL) to UB1.76 For Update screw hole
82 12/20 21 Change RH198 from 100k to 10k For follow Intel checklist
83 12/20 05 Change UC1.5 from +3VALW to +3VALW_PCH For design change
84 12/20 16 Modify SATA_LED# to10k (RH29) +5VS pull high & 20k (RH35) pull low For design change
D
85 12/20 17 Change CLKREQ_CR#,CLKREQ_USBA30#,CLKREQ_USB30# to PCH_GPIO25, 26, 44 For design change D
86 12/20 20,23 Change CH104 to 100p and CH71 to 0402 For design change
87 12/20 27,35 Change BT_ON# netname to BT_ON and UA4 to UM4 For design change
88 12/20 27 Modify LED_WIMAX# to 100k +5VS pull high & 200k pull low For design change
89 12/20 35 Delete CB13 For design change
90 12/20 33 Change CA3,CA46,CA36 to 0805_6.3V6M For cost down
91 12/20 38 Delete R5534 and short directly For design change
92 12/20 37 Changr R819 from +5VS to +3VS For design change
93 12/20 5,25 Changr C13,C17,C356,C355,C354 to 0805_6.3V6M and unmount C354 For cost down
94 12/20 35 Delete UB2,CB17,RB25 and connect UB1.127 to PM_SLP_S4#, UB1.14 to PM_SLP_S5# For cost down
95 12/20 35 Delete RB24,RB28,RB4,RB5,RB7,R37 and change UB1.119,117,75,64,27,16 to NC For cost down
96 12/21 28 Change symbol from SP021105131 For apply symbol
97 12/21 35 Change TP_CLK,TP_DATA pull high to +5VS For TP spec
98 12/21 13 Unmount D84 For reserve
99 12/22 15,25,30 Swap L9,L11,LR1,LR2,L53,L54 signal For swap signal
100 12/22 30 Swap U3TXDP1_R_L and U3TXDN1_R_L, swap U3RXDP1_R_L and U3RXDN1_R_L For swap signal
101 12/23 14,15 Change F1,F2 to SP040003A00 For component common
102 12/24 29 Change RR66~67 to mount, LR9 to unmount For choke reserved
103 12/24 37 Cancel H6, H17 (FAN stand-off) and change H4 to H_3P3 (VGA) For ME drawing update
104 12/24 28 Change PJ29 from JUMP_43X118 to JUMP_43X39 For layout concern
105 12/24 38 Delete R105, add PJ30 to contact +3VS & +3V_WLAN For no support AOAC function
106 12/26 36 Update JDB symbol and modify pin define For connector list update and pin define for customer's request
107 12/26 13,17 Delete RH282, change RH116 to mount, JLVDS1.2 contact LVDS_SEL For update pin define and BOM reduce
C C
108 12/26 13 JLVDS1.1&11&12 contact GND For LVDS cable smooth route and BOM reduce
109 12/26 33 Move RA32 & RA33 to Audio/B For AMIC function
110 12/26 29 JCRIO.11 contact SENSE_A, JCRIO.12 contact INT_MIC For AMIC function
111 12/26 36 Swap JKB connector pin define For latest keyboard spec
112 12/26 29 Swap LR9 pin define For layout concern
113 12/27 29 Swap JCRIO pin define For layout concern
m
114 12/27 37 Update JTP pin define For PIN define rule
115 12/27 29 Update TPM schematic For co-lay SLB9635 and SLB9655
co
116 12/27 28 Add CL35 and un-mount For EMI request
117 12/27 21 Change CIR_EN# to PCH_GPIO39 and ISDBT_DET to PCH_GPIO48 For schematic update
118 12/27 21 Change HDD2_DET# to PCH_GPIO57 and LNB_EN to PCH_GPIO70 For schematic update
s.
119 12/27 21 Change 3D_DET# to PCH_GPIO71 For schematic update
120 12/27 20,30,35 Add S&C schematic For reserve S&C schematic
121 12/27 33 Add Analog MIC schematic For Analog MIC
122 12/27
124 12/27
28
123 12/27 11,21
11
Change RL8.2 from LAN_X1 to LAN_X2
Add D54,RH210,RH100,QC9 and delete RC117,RC118
Change QC7,QC8 to always mount
For vendor recommendation
et
For Ivy/Sandy bridge M1/M3 co-lay solution
r
For Ivy/Sandy bridge M1/M3 co-lay solution
ec
125 12/27 38 Change R158 from 100Kohm to 220Kohm For intel S3 power reduce sequence between +1.5VS_CPU and +0.75VS
126 12/27 33 Add CA64 0402 cap @ on SENSE_A For audio sense A pin
127 12/28 30 Change R569 to PJ31 For S&C function
rs
128 12/28 30 Add RH4,CH80 For prevent abnormal turn on

129 12/28 30 Add CH99,CH102 and delete CH97 For prevent abnormal turn on and do soft start
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B
130 12/29 38 Change R5545 from 100k to 10k For prevent abnormal turn on and do soft start B
131 01/03 28 Change UL3,UL4 from SP050006N00 to SP050005Z00 For update transformer P/N
132 01/03 29 change UT1 P/N from SA00000GG40 to SA00000GG60. For TPM firmware update
ep
133 01/03 27 change R1456,R1457,C907,C908,Q210 to @ For TPM firmware update

pr

o
---------------------------------------------------------------------------------------------------------------------
1 02/01 28 Add PJ32 and connect +3VALW_PCH & +3V_LAN For power saving
pt
2 02/02 29 Change JCRIO.2 to connect MIC_SENSE and JCRIO.1 to connect NBA_PLUG For change pin define
3 02/02 33 Delete sense_A off page,CA64 and add RA32,RA33 For sense A circuit
4 02/02 37 Change JTP from SP010015H00 to SP01001BF10 For connector list
.la
5 02/02 33 Add JMIC connector SP02000RO00 For connector list

6 02/02 27 Change JWLAN from SP07000JP00 to SP07000TB00 For connector list
7 02/02 38 Change Q44A to Q6B and delete Q44 For component reduce
w
8 02/02 16 Delete T67~69 For common design

9 02/03 35 UB1.38 connect AOAC_WLAN_PWR_EN# and UB1.91 connect WLAN_RST# For WLAN Power on/off and WLAN reset
w
10 02/03 27 Change R1456,R1457,C907,C908,Q210 to mount For WLAN Power on/off and WLAN reset
11 02/03 27 change R1457.1 to connect AOAC_WLAN_PWR_EN# For WLAN Power on/off and WLAN reset
w
12 02/03 27 Change JWLAN.22 to connect WLAN_RST#_R For WLAN Power on/off and WLAN reset
13 02/03 27 Change C260,CM7,CM8,CM9,C254 to connect +1.5VS_WLAN For WLAN Power on/off and WLAN reset
14 02/03 27 ADD PJ33 (PJ33 don't short),UM5,RM19,RM21 and +1.5VS_WLAN (power) For WLAN Power on/off and WLAN reset
A A
15 02/03 27 Change UM4.1 to connect AOAC_WLAN_PWR_EN# For WLAN Power on/off and WLAN reset
16 02/06 28 Change CL63 from SE120102K80 to SE120102K90 For sourcer suggestion
17 02/06 37 Change H18,H19 to H_3P0N For ME drawing update
18 02/08 21 Change UH1.T7 from HDMI_HPD to CHP3_SERDBG For Eureka Serial POST GPIO
19 02/08 21 Change RH292 from 10Kohm to 1Kohm and delete T66 For Eureka Serial POST GPIO
20 02/08 21 Change UH1.T7 from HDMI_HPD to CHP3_SERDBG and connect to JCRT.4 For Eureka Serial POST GPIO

HW-PIR
Custom 0.2
5 4 3 2 1
5 4 3 2 1

---------------------------------------------------------------------------------------------------------------------
21 02/08 27 Add TL1 test point For LAN FAE suggestion
22 02/09 15 Add D94~D96 on HDMI signal For ESD request
23 02/09 27 Add D99,D100 on LAN signal For ESD request
24 02/09 14 DEL D3~D5 and add D97,D98 on CRT signal For ESD request
25 02/09 7,31 Add RC74 and net DRAMRST_CNTRL_EC connect RC74.1 & UB1.89 For DS3 function reserve
26 02/09 25 Add R79~82 For reduce SATA signals reflection
D
27 02/14 11 Change CD7 from SF000002O00 (H=5.9) to SF000002Z00 (H=4.4) For thermal issue D
C C
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A A

HW-PIR
Custom 0.2
5 4 3 2 1

Samsung NP350V5X QCLA4QCLA5 LA-8862P Schematic

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Samsung NP350V5X QCLA4QCLA5 LA-8862P Schematic

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Eureka 14" & 15" 2

LA-8862P REV 0.2 Schematic

Security Classification Compal Secret Data Compal Electronics, Inc.

rPGA-989 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1

page 5,6,7,8,9,10 1.5V DDRIII 1066/1333/1600 MT/s

CRT FDI X8 DMI X4

USB30 4x USB Right USB Left

5V 480MHz USB port 8 USB port 11

page 15 Intel PCH USB20 3x PCIeMini Card PCIeMini Card

Cardreader PCIe Gen1 1x SATA Gen3 port 0 5V 6GHz(600MB/s)

Power Circuit DC/DC EC SMBus

DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 1.8A +1.8VS

Ipeak=6A, Imax=4.2A, Iocp min=8A DESIGN CURRENT 13.5A +1.5V

N-CHANNEL DESIGN CURRENT 5A +1.5V_CPU

DESIGN CURRENT 1A +0.75VS

Ipeak=6A, Imax=4.A, Iocp min=8 DESIGN CURRENT 6A +VCCSA

Imax=0.3A, Iocp min=0.8A DESIGN CURRENT 0.3A +16VS

Ipeak=5A, Imax=3.5A, Iocp min=6.2A DESIGN CURRENT 7.5A +3VALW

P-CHANNEL DESIGN CURRENT 0.1A +3V_LAN

Ipeak=14A, Imax=9.8A, Iocp min=16.92A DESIGN CURRENT 15A +1.05VS_VCCP

Security Classification Compal Secret Data Compal Electronics, Inc.

( O MEANS ON X MEANS OFF )

+0.75VS BTO Option Table

S1 explain WIN8 Green CLK NOGCLK Internal 10/100M Giga

PCH SM Bus Address

Power Device HEX Address

G3 LOW LOW LOW

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

JTAG & BPM

FAN Control Circuit

Security Classification Compal Secret Data Compal Electronics, Inc.

PEG_ICOMPI and RCOMPO signals should be

PCI EXPRESS* - GRAPHICS

Security Classification Compal Secret Data Compal Electronics, Inc.

AB6 DDRA_CLK0 AE2 DDRB_CLK0

DDR SYSTEM MEMORY B

5 H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2

11,17 DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL

CC37 2010/09/03 2012/12/31 Title

JCPUF POWER +1.05VS_VCCP

AF26 VCC19 VCCIO18 F14

Y34 VCC51 +1.05VS_VCCP +1.05VS_VCCP

V34 VCC61 AJ29 H_CPU_SVIDALRT# 1 2

VCC62 VIDALERT# VR_SVID_ALRT# 42

R27 VCC88 AJ35 VCCSENSE_R RC94 1 2 0_0402_5%

P28 VCC97 RC96 RC98

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR3 -1.5V RAILS

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 41

330U_B2_2.5VM_R15M 1U_0402_6.3V6K TYCO_2013620-2_IVY BRIDGE

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

CFG Straps for Processor

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR_A_D1 7 DQ0 DQ5 8 DDR_A_DQS#[0..7] 7

DDR_A_D35 143 144

203 SA1 SCL 204 PM_SMBCLK 12,17,26

CD26 VTT VTT

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

Date: Thursday, February 16, 2012 Sheet 11 of 48