$= XILINX’ XC9572XL High Performance CPLD S057 (v2.0) April 3, 2007 Product Specification Features + Snspin-to-pin logic delays + System frequency up to 178 MHz + 72macrocells with 1,600 usable gates + Available in small footprint packages: ~ 44-pin PLCC (34 user 1/0 pins) - 44-pin VFP (34 user I/O pins) - 48-pin CSP (38 user 1/0 pins) - 64-pin VFP (52 user I/O pins) - 100-pin TOFP (72 user 1/0 pins) Pb-free available for all packages + Optimized for high-performance 3.3V systems = Low power operation - 5V tolerant I/O pins accept SV, 3.3V, and 2.6V signals = 3.3V or 2.5V output capability + Advanced 0.35 micron feature size CMOS Fast FLASH™ technology + Advanced system features: - _ In-system programmable - Superior pin-locking and routability with Fast CONNECT™ Il switch matrix - Extra wide §4-input Function Blocks = Upto 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin = Input hysteresis on all user and boundary-scan pin inputs > Bus-hold circuitry on all user pin inputs + Full IEEE Standard 1149.1 boundary-scan (JTAG) + Fast concurrent programming + Enhanced data security features Excellent quality and reliability + Endurance exceeding 10,000 progranverase cycles: + 20,year data retention - ESD protection exceeding 2,000V + Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TOFP package WARNING: Programming temperature range of Ta= 0" Cto 470°C Description ‘The XC9572XL is a 3.3V CPLD targeted for highperfor mance, low-voltage applications in leading-edge communi- cations and computing systems. It is comprised of four 54V 18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns. See Figure 2 for overview Power Estimation Power dissipation in CPLDs can vary substantially depend- ing on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addi- tion, unused productterms and macrocells are automati- cally deactivated by the software to further conserve power. For a general estimate of Igg, the following equation may be used: leet = MCyo(0.175*P Tas + 0.345) + MCyp(0.052°P Typ +0.272) + 0.04*MCrog(MCug *MCrp)*f where: MCyg = # macrocells in high-speed configuration PTs = average number of high-speed product terms per macrocell MCyp=#macrocells in low power configuration PT p= average number of low power product terms per macrocell f= maximum clock frequency MCTOG = average % of flip-flops toggling per clock (12%) This calculation was derived from laboratory measurements of an XC9500XL part filed with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual lec value varies with the design application and should be veri fied during normal system operation. Figure 1 shows the above estimation in a graphical form. For a more detailed discussion of power consumption in this device, see Xilinx (©2008 Xan, me, Aight esened, anu taderarks, registered tademarks pars, and dscaimers are a sted at pnnwaline comlegal Fam ‘Al other ademas and eitredademarts ae the prope ofthe especie ones. Al Speceatons are subjetto change wiout ete. S057 (v2.0) April 3, 2007 Product Specification yxilinx.com 1XC9572XL High Performance CPLD SLxIUNX application note XAPP114, “Understanding XC9500xL, CPLD Power. 7a wie 04 Miz 30 300 «80 Clock Frequency (MHz) 200 Figure 1: Typical lcc vs. Frequency for XC9572XL 3 wr ver {| Tras |<—~[__ test Proorarming Contr -———>| |} —__— $4» Funation vo KJ 18. Block 1 rt [ Macrocets "0 * ~ 11018 Io ii "e = Funation : 2 Block : 2 ‘Macrocells. : vo | é * 110 18 + | locks 2 ea 8 ttt g Se cS | 2 7 Function <° 6 |e Block 3 vo K=4_— g Macrocels ~ & * to 18 vo E> i i + f voreck [>| Ste Function vorasr = Function vosts K=3—? |< 1 Macrocols Figure 2: XC9572XL Architecture Function Block outputs (indicated by the bold line) drive the VO Blocks directly. S057 (v2.0) April 3, 2007 Product SpecificationEXXILINX” XC9572XL High Performance CPLD Absolute Maximum Ratings(2) ‘Symbol Description Value Units Veo ‘Supply voltage ratatve To GND aT ao Vv Vin Taput vorRage relative to GND OSES v Vis___| Voltage appliedto &-state output™ IESE Vv Tere __| Storage temperature (ambient) BETO 150 °C Ty ‘anction temperature aE *C Wotex 1. Maximum DC undershoot belowGND must be limited'o either 0.5V or 10 mA, whichever s easier to achieve. During transtions, the device pins may undershoot to-2.0 V of overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and wih the forcing current being imted to 200 mA. External HO vottage may not exceed Vocint BY 4.0V. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conations snot implied. Exposure to Absolute Maximum Ratings conditions for extended periods of ime may affect device reliability. 3. For soldering guidelines and thermal considerations, see the Device P ackaaing infomation on the Xilinx website. For Pb-fee packages, see XAPP 427, Recommended Operation Conditions ‘Syinbol Parameter tin [Max] Units Voom | Supply vottage for ntarmal ogic | Commercial Ta= OC To 70% | 3.0 36 v and input buffers THaUSHTAlTa= OCIS FESS | 3.0 3 V Veo | SUBBIY Valage Tor output drivers for 3.3V operation a0 3s v ‘Supply Vottage Tor output divers for Z5V operation zz 27 v Vic | Low-level input vatage o oa v Vie | oPTever input voraae = 55 v Vo | Outputvarags T—[Veoo | —V Quality and Reliability Characteristics ‘Symbor Parameter Min Max Units Tor Data Retention 20 = Years Nee: Programferase Cycles (Endurance) 70,000 = oyeles Veso _| Electrostatic Discharge ESD) 7000 = Vors DC Characteristic Over Recommended Operating Conditions ‘Symbor Parameter Test Conditions Min Max_| Units Von | Output high voltage for 3.3V outputs rome a = Vv ‘Output high voltage for 2.5V outputs 500 WA WeVeco | Vv Vor | Output Tow voltage for 3.3V outputs | To. = 8.0 mA uw [Vv Output Tow voltage for 2.6 outputs | To, = S00 nA ut _[_¥ Ti | Wnput Teakage current Voo = Max, Vin= GND oF Von : ao | aA Tia __ | WO Righ-Z leakage current Vo = Max, Vin= GND oF Veo. : zo | a Ta | WO Righ-Z Teakage current Veo = Max, Vocio 5 =| ae Vin = GND of 3.6V Voo Min=Viy = 5.5 : =50_| oA Gn___| WO capacitance Vin= OND, f= TO MFE : 10 | oF Tec | Operating supply current Vin= OND, No Toad, f= 10 MAE DO Cypeay mA (low power mode, active) S057 (v2.0) April 3, 2007 wwwxitin.com 3 Product SpecificationXC9572XL High Performance CPLD SLxIUNX AC Characteristics ‘XCOSTOXL-S | XC9STIXL-T | XC9STOXL-10 symbol Parameter Min] Max | Min] Max | Min | Max_| Units Teo [WO to output vand 7 so | - | 7s | - | 100 [ns Teu__ | VO setup time before GCK a7 Ce 7s Ta _ | WO hold time after GOK v : 7 5 7 =f as Teo _| GOK to output valid 5 af | es | de | TeveTem_| Multiple FB internal operating frequency -__ [ies | - | 1250] - | 1000 | Mee Tpsu___| VO setup time before p-term clock input 7 | ve | - | 2t | - ns Tex [WO hold time after p-term clock input zz | af | ee 7s Teco _ | Ptarm clock output valid 5 a5 | - | 77 | - | 02 | 1s Toe _[ GTS to output valid - pao pf - [so | - | 7 [os Too _ | OTS to output disable - pao pf - [so | - | 7 [os Troe __| Product term O€ to output enabled 5 7 | - | 35 | - | 0 [1s Trop __| Product term O€ to output disabled 5 7 | - | 35 |_-_| 10 [18 Tao _| GSR to output valid -_ [too | - | 20] - | #5 | ns Tpao _| Perm SIR to output valid -_ [wos | - | 26] - | 153 | 1s Twn _| SOK pulse width (High or Low) 7 | a 7s Taerew_| Asynchronous presetreset pulse width a0] os | - | mo] - 7S (High or Low) Tous _| P-term clock pulse width (High or Low) a0 | os | - | mo]- 7s Vresr Sm Output Type] Vecio | Vrest | Rt Re ou Device Output o——¢ aav | 33av_ | 208 | 360m | 35 pF é asv | 25v | 2500 | 6600 | 35 pF Re 4 wewwexilinx.com S057 (v2.0) April 3, 2007 Product SpecificationELxIUINX XC9572XL High Performance CPLD Internal Timing Parameters XCOSTOXL-5 | XCOSTOXLT | XCO572XL-10 Symbol Parameter Win | Max [Min | Max | Min | Max] units Buffer Delays Tin [ input buffer delay : 1S = 2 35] 8 Toon | GOK butter delay = TH TS Tas Tosa | GSR butter delay i 20 = at a5 |S Tors | OTS buffer delay 5 a0 = 50 = 70 [as Tour | Output buffer delay : 20 = 2 301s Tey _ | Output butter enablerdisable delay i 7 = a v 15 Product Term Control Delays Tero | Product term clock delay = TS = 2 = aT] as Tersa_| Product term setireset delay = To Tt 78 [as Terre | Product term 3-state delay = a5 72 TS] _as Internal Register and Combinatorial Delays Teor_| Combinatorial logic propagation delay 5 os = TS = 7] as Teur_| Register setup time 2 = 26 a0 5 TS. Ta _ | Register hota time TH = 22 5 as 5 15 Tecsu_| Register clock enable setup ime 2 5 26 = a0 5 i Teouo_| Register clock enable hold time TH = 22 5 a5 : i Toor _| Register clock to output valid time = oF os > 70 [as Tror_| Reaister asyne. SIR to output delay = iy ot T0_ |S Trar_| Register asyne. SiR recover bafore clock | 50 75 10.0 i Tioi_| intemal logic delay : To = Ts 78 [as Troup | Intemal Tow power logie delay i ao = a 73s Feedback Delays Te] Fast CONNECT Il feedback delay : 7 = a5 a2] 0s Time Radars Tera _ | eremental product term allocator delay = oT = os = 70] as Tetew | Slewate limited delay : a0 = a0 4 [as S057 (v2.0) April 3, 2007 wwwxitin.com 5 Product SpecificationXC9572XL High Performance CPLD SLxIUNX XC9572XIE 1/0 Pins\4) “ton | boar ascan| | tion | macro Bscan siock | “eat | pces | vase | csea | vase |ratoo | order | | stock | cat | pcas | vase | esas | vase | rat00 | order 7 71-?-t-)-Lele|fs ~>7t-.-t-p- i) pe Te eS ere a] oe see 7 app pepe pe par] os ps ea 7 TP Le a] [ST ES TS ee es ae er ee Te ps pe per pe pas fe] 3 ee 7 TPL] STII OP LL T z Epa ce at arse] fo ac T TARO Br SOT a Bs] | om 8 as ar a 70 ape] se Deepa T TE BT aa Be TEU] aT BS] | We a 3s] Tapp se] [a TOE L] STIE T [ea ar ar a | ae] [ @ [eles] s | w | T 1S Ea @ [ele [else se | w | 7 76 ~P-)- >). | pe a ew (alee; 2] se | wo | T @flsils [s|;s lo | mel s @[eleralys | = | @ | The pee] oe Dee] Te eee ee ea 23s pp = ps] eos eS Zep. pL Es pe] ee TS ee ese ee] Eee Se] Ze pepe pepe ps jm] fete p-)- pe) ees 27 pp app] LLL Te ee ees ee ee oa Zee ar ore peor as] es 2p f= pp ee] eo ZR SRT rR Oa as] Ee ee ze f= p= pepe pe] le pe pe ze pp pe] ee es 7 ee reer se ere] ee ee ee Ze psp pe7pe pt pm] lee pepe pes ps pee 2 fae f= pp ee] ee ee Te pepe ese ae] eee ee 2 fae f= ppb pee] ee = Note 1. Global contrat pin 2. GTSt fer Ta100. 3. GTSt fr PC44, Va4s, C548, and VOSS 44. The pin-outs are the same for Pb-Ree versions ofpackages. 6 vawwxilire.com S0S7 (v2.0) Api 3, 2007 Product SpecificationELxIUINX XC9572XL High Performance CPLD XC9572XL Global, JTAG and Power Pins(") Pin Type PCaT vor Csi vast TOTO0 TOISGRT 7 7 a 75 7 TOISCKT i TT 56 7 Hi TOIGCRS 7 7 AT 7 I TOISTST z 3 Eg 3 TOIGTST o 3 Fe z TOIGSR a Fi oF oF ry TOK iT 7 Ai 3 7 Tor iE z 33 8 % D0 7] HF SE 5 Hi TS Te 0 KE 5 7 Veon 330 Tat 75,35 CFT aT 557,98 Vooio 2.5¥13.3V a 26 oF 26, 55 75, 38, 51, 88 ‘GND 70,357 17,35 REDLFS | AE] OH, BE 69, 75,84, 100 To Connects ss = = ss 27, 19, 24, 34, 43, 46, 73, 80 Wotex 1. The pin-outs are the same for Pb-tee versions of packages. S057 (v2.0) April 3, 2007 Product SpecificationXC9572XL High Performance CPLD SLxIUNX Device Part Marking and Ordering Combination Information LN XILINX XCO5xxXXL + To144 Device Type Package = Thistine not related to device Speed pe part number 1+ 7G Operating Range —}—* o = ATTA Hotes: ‘Sample package wth part marking 1. Duetothe small size of chip scale packages, part marking on these packages doesnot followthe above ‘sample and the complete part number cannet be included in the marking. Part marking on chip scale packages by line Line 1 = x (xilinx logo), then truncated part number (no XC), Le, 95xxxXL, Line 2= Not related to device part number. Line 3 = Not related to device part number. Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C1 = C848, C2= CSG48. peed Device Ordering and | (pin-to-pin | Pkg. | No. of Operating Part Marking Number | delay) | Symbol | Pins Package Type Rangel"! OSTIRL- SPORT ms PCa | aepin Plastic Lead Chip Carrier (PL XCUSTIRL- VOMIT ns | Vout | aepin ‘Quad Flat Pack (VOFP) c USTIRL-SCSTECT 75 a5 | aa Tip Stale Package (CSPI XCUSTIRL-AVOEIT ns vast _| 6epin ‘Quad Flat Pack (VOFP) c USTIRL-STOTOUC 1s__| TATOO | Topi Thin Ouad Frat Pack (TUFFY USTIRL-TPCRIT mS | PCa | Senin Plastic Lead Chip Carrier (PL XCGSTIRL VOMIT Tans | Vaud aepin ‘Quad Flat Pack (VOFP) c USTIRL- CSTE 75 a5 [aa Tip Stale Package (CSPI XCUSTIRL-TVOSIT Tans | Vasa] 6epin ‘Quad Flat Pack (VOFP) c TSTIRL- TOTO mS_| TOTO] Topi Thin Ouad Frat Pack (TUFFY USTIRL-TPCMMT mS | PCa | Senin Plastic Lead Chip Carrier (PL T XCGSTIRL VOUT Tans | Vaud aepin ‘Quad Flat Pack (VOFP) T USTIRL-TCSAET 75 a5 [aa Tip Stale Package (CSPI T XCUSTIXLTVOGAT Tans | voed_| 6&pin ‘Quad Flat Pack (VOFP) T USTIRL-TTOTOOT mS_| TOTO] Too-pIA Thin Ouad Frat Pack (TUFFY T USTIRL-TOPCMIT Tons | PCs] apn Plastic Lead Chip Carrier (PL XCGSTIXLTOVOEET Tons | Vous] apn ‘Quad Flat Pack (VOFP) c USTIRLTOCSTET Tons a5 [ae al Tip Stale Package (CSPI XCGSTIXLTOVOBET Tons | Voed_| 6&pin ‘Quad Flat Pack (VOFP) c SSTIRLTOTOTOUC Tons | TOToo | Topi Thin Ouad Frat Pack (TUFFY USTIRL-TOPCMAT Tons | PCs] apn Plastic Lead Chip Carrier (PL T XCUSTIXLTOVOAA Tons | Vaud] apn ‘Quad Flat Pack (VOFP) T USTIRL-TOCSAET Tons a5 | ae Tip Stale Package (CSPI T XCGSTIXL TOVOEA Tons | Vaed_| 6&pin ‘Quad Flat Pack (VOFP) T GSTIRL-TOTOTOOT Tons ToToo | Toran Thin Ouad Frat Pack (TUFFY T tes C= Commercial: Ta = 0° to +70°C; | = Industrial: Tq=—40" to +85°C 8 wwoxitinx.com, S057 (v2.0) April 3, 2007 Product SpecificationEXXILINX” XC9572XL High Performance CPLD spent Device Ordering and | (pin-to-pin | Pkg. | No. of Operating Part Marking Number delay) _| Symbol | Pins Package Type Rangel) C957 OXL-SPCGEC ons PCG44 | 4&pin | Plastic Lead Chip Carrer (PLCC), Pb-free Cc XC957TIXL-SCSG4BC ons CSGa8 | 48-ball Chip Scale Package (CSP), Pb-free Cc XC95TIXL-TPCGEC 750s PCG44 | 4&pin | Plastic Lead Chip Carrer (PLCC), Pb-free Cc XC957TOXL-TCSGSBC 7.5 ns CSGa8 | 48-ball Chip Scale Package (CSP); Pb-free Cc ‘C957 2XL-7PCG4AT 750s PCG44 | 4&pin | Plastic Lead Chip Carrer (PLCC), Pb-free T XC9572XL-7CSG4ET 7.5 ns CSGa8 | 48-ball Chip Scale Package (CSP); Pb-free T ‘XC9572XL-TOPCG4EC TOns PCG44 | 4&pin | Plastic Lead Chip Carrier (PLCC), Pb-free Cc ‘XC957TOXL-TOCSG4EC TOns CSGa8 | 48-ball Chip Scale Package (CSP), Pb-free Cc ‘XC9572XL-TOP CG 44T TOns PCG44 | 4&pin | Plastic Lead Chip Carrer (PLCC), Pb-free T ‘XC9572XL-T0CSC4BI TOns CSGa8 | 48-ball Chip Scale Package (CSP), Pb-free T Device —__ Devices —__1 se SFE Bao ined By beyea ti Dewar aovaga.ar i 3 Product SpecificationXC9572XL High Performance CPLD SLxIUNX Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT htto:wwwxilinx comiwarranty him, THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF UFE, USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Further Reading The following Xilin« links go to relevant XC9S00XL CPLD documentation, including XAPP111, Using the XC9S00XL Timing Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down. Data Sheets, Application Notes, and White Papers. Packaging Revision History ‘The following table shows the revision history for this document Date Version Revision 09728198 1.0 __| initial Xiinx release 08/28/01 11 [Added V044 package 06720102 12 | Updated Ic equation, page 1. Updated Component Availabilty table. Added additional hy test conditions and measurements to DC Characteristics table 5127103 13 | Updated Teo, trom 260 to 220°C. Added Part Marking and updated Ordering Information 08721103 14 [Updated Package Device Marking Pin 1 orientation 7104 15 __ [Added Pb-tres documentation ‘Oart5I08 16 [Added Tapaew Specification to AC Characteristics. 04728105 17 __ | No change to documentation 715105 1.8 ___ | Move to Product Specification 03722106 78 [Add Warranty Disclaimer ‘8103107 20 [Add programming temperature range warning on page 1 10 ‘wwwxiline.com S057 (v2.0) April 3, 2007 Product Specification