Assignment No #02

Submitted To:
Engr. M Ubaidullah
Submitted By:
Muhammad Usama Saghar
Roll Number:
2019-CPE-27
Subject:
Microprocessor Systems (CPE-312)

Department of Computer Engineering

UCE&T
Bahauddin Zakariya University, Multan.
Q: Discuss the interrupt system of 8086 . What is interrupt pointer? What is types of
interrupt?
Interrupt:
Interrupt is the method of creating a temporary halt during program execution and allows peripheral
devices to access the microprocessor. The microprocessor responds to that interrupt with
an ISR (Interrupt Service Routine), which is a short program to instruct the microprocessor on how to
handle the interrupt.
Whenever an interrupt occurs the processor completes the execution of the current instruction and starts
the execution of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a program that tells the
processor what to do when the interrupt occurs. After the execution of ISR, control returns back to the
main routine where it was interrupted.

In 8086 microprocessor following tasks are performed when microprocessor encounters an interrupt:

1. The value of flag register is pushed into the stack. It means that first the value of SP (Stack
Pointer) is decremented by 2 then the value of flag register is pushed to the memory
address of stack segment.
2. The value of starting memory address of CS (Code Segment) is pushed into the stack.
3. The value of IP (Instruction Pointer) is pushed into the stack.
4. IP is loaded from word location (Interrupt type) * 04.
5. CS is loaded from the next word location.
6. Interrupt and Trap flag are reset to 0.
The different types of interrupts present in 8086 microprocessor are given by:

1. Hardware Interrupts –
Hardware interrupts are those interrupts which are caused by any peripheral device by
sending a signal through a specified pin to the microprocessor. There are two hardware
interrupts in 8086 microprocessor. They are:
• (A) NMI (Non Maskable Interrupt) – It is a single pin non maskable hardware
interrupt which cannot be disabled. It is the highest priority interrupt in 8086
microprocessor. After its execution, this interrupt generates a TYPE 2 interrupt.
IP is loaded from word location 00008 H and CS is loaded from the word
location 0000A H.
• (B) INTR (Interrupt Request) – It provides a single interrupt request and is
activated by I/O port. This interrupt can be masked or delayed. It is a level
triggered interrupt. It can receive any interrupt type, so the value of IP and CS
will change on the interrupt type received.
2. Software Interrupts –
These are instructions that are inserted within the program to generate interrupts. There are
256 software interrupts in 8086 microprocessor. The instructions are of the format INT type
where type ranges from 00 to FF. The starting address ranges from 00000 H to 003FF H.
These are 2 byte instructions. IP is loaded from type * 04 H and CS is loaded from the next
address give by (type * 04) + 02 H. Some important software interrupts are:
• (A) TYPE 0 corresponds to division by zero(0).
• (B) TYPE 1 is used for single step execution for debugging of program.
 • (C) TYPE 2 represents NMI and is used in power failure conditions.
• (D) TYPE 3 represents a break-point interrupt.
• (E) TYPE 4 is the overflow interrupt.

Interrupt Pointer:
The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for
type2 is 00008H and ……so on. The first five pointers are dedicated interrupt pointers. i.e.
TYPE 0 interrupt represents division by zero situation.
• TYPE 1 interrupt represents single-step execution during the debugging of a program.
• TYPE 2 interrupt represents non-maskable NMI interrupt.
• TYPE 3 interrupt represents break-point interrupt.
• TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and interrupts
from 32 to Type 255 are available for hardware and software interrupts.
INT 3-Break Point Interrupt Instruction
It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the program so that
when the processor reaches there, then it stops the normal execution of program and follows the break-
point procedure.
Its execution includes the following steps −
• Flag register value is pushed on to the stack.
• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of the word location 3×4 = 0000CH
• CS is loaded from the contents of the next word location.
• Interrupt Flag and Trap Flag are reset to 0
INTO - Interrupt on overflow instruction
It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As the name
suggests it is a conditional interrupt instruction, i.e. it is active only when the overflow flag is set to 1 and
branches to the interrupt handler whose interrupt type number is 4. If the overflow flag is reset then, the
execution continues to the next instruction.
Its execution includes the following steps −
• Flag register values are pushed on to the stack.
• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of word location 4×4 = 00010H
• CS is loaded from the contents of the next word location.
• Interrupt flag and Trap flag are reset to 0
Q: Explain the concept of pipelining in 8086? Discuss its advantages and disadvantages?

Pipelining

1. The process of fetching the next instruction when the present instruction is being executed is
called as pipelining.
2. Pipelining has become possible due to the use of queue.
3. BIU (Bus Interfacing Unit) fills in the queue until the entire queue is full.
4. BIU restarts filling in the queue when at least two locations of queue are vacant.

Types of Pipelining
It is divided into 2 categories:

1. Arithmetic Pipeline

2. Instruction Pipeline

Arithmetic Pipeline:

Arithmetic pipelines are usually found in most of the computers. They are used for floating point
operations, multiplication of fixed point numbers etc. For example: The input to the Floating Point Adder
pipeline is:

X = A*2^a

Y = B*2^b

Here A and B are mantissas (significant digit of floating point numbers), while a and b are exponents.

The floating point addition and subtraction is done in 4 parts:

1. Compare the exponents.

2. Align the mantissas.

3. Add or subtract mantissas

4. Produce the result.

Registers are used for storing the intermediate results between the above operations.

Instruction Pipeline:

In this a stream of instructions can be executed by overlapping fetch, decode and execute phases of an
instruction cycle. This type of technique is used to increase the throughput of the computer system.
An instruction pipeline reads instruction from the memory while previous instructions are being executed
in other segments of the pipeline. Thus we can execute multiple instructions simultaneously. The pipeline
will be more efficient if the instruction cycle is divided into segments of equal duration.

Pipeline Conflicts

There are some factors that cause the pipeline to deviate its normal performance. Some of these factors
are given below:

1. Timing Variations

All stages cannot take same amount of time. This problem generally occurs in instruction processing
where different instructions have different operand requirements and thus different processing time.

2. Data Hazards

When several instructions are in partial execution, and if they reference same data then the problem
arises. We must ensure that next instruction does not attempt to access data before the current instruction,
because this will lead to incorrect results.

3. Branching

In order to fetch and execute the next instruction, we must know what that instruction is. If the present
instruction is a conditional branch, and its result will lead us to the next instruction, then the next
instruction may not be known until the current one is processed.

4. Interrupts

Interrupts set unwanted instruction into the instruction stream. Interrupts effect the execution of
instruction.

5. Data Dependency

It arises when an instruction depends upon the result of a previous instruction but this result is not yet
available.

Advantages of pipelining:

• The execution unit always reads the next instruction byte from the queue in BIU. This is faster
than sending out an address to the memory and waiting for the next instruction byte to come.
• In short pipelining eliminates the waiting time of EU and speeds up the processing. -The 8086
BIU will not initiate a fetch unless and until there are two empty bytes in its queue. 8086 BIU
normally obtains two instruction bytes per fetch.
Disadvantages of pipelining:

1. While pipelining can severely cut the time taken to execute a program, there are problems that
cause it to not work as well as it perhaps should.
2. The three stages of the instruction execution process do not necessarily take an equal amount of
time, with the time taken for 'execute' being generally longer than 'fetch'. This makes it much
harder to synchronise the various stages of the different instructions.
3. Also, some instructions may be dependent on the results of other earlier instructions. This can
arise when data produced earlier needs to be used or when a conditional branch based on a
previous outcome is used.

Q: Draw and explain the architecture of 8086?

Architecture of 8086
A Microprocessor is an Integrated Circuit with all the functions of a CPU however, it cannot be used
stand alone since unlike a microcontroller it has no memory or peripherals.
8086 does not have a RAM or ROM inside it. However, it has internal registers for storing
intermediate and final results and interfaces with memory located outside it through the System Bus.
In case of 8086, it is a 16-bit Integer processor in a 40 pin, Dual Inline Packaged IC.
The size of the internal registers (present within the chip) indicate how much information the processor
can operate on at a time (in this case 16-bit registers) and how it moves data around internally within
the chip, sometimes also referred to as the internal data bus.
8086 provides the programmer with 14 internal registers, each 16 bits or 2 Bytes wide.

Memory segmentation:
• To increase execution speed and fetching speed, 8086 segments the memory.
• It’s 20 bit address bus can address 1MB of memory, it segments it into 4 64kB segments.
• 8086 works only with four 64KB segments within the whole 1MB memory.
The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit (BIU), and The
Execution Unit (EU). These are explained as following below.

The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the System Bus. It performs
various machine cycles such as memory read, I/O read etc. to transfer data between memory and I/O
devices.
BIU performs the following functions-

• It generates the 20 bit physical address for memory access.

• It fetches instructions from the memory.
• It transfers data to and from the memory and I/O.
• Maintains the 6 byte prefetch instruction queue (supports pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a prefetch queue and an Address
Generation Circuit.
Instruction Pointer (IP):
• It is a 16 bit register. It holds offset of the next instructions in the Code Segment.
• IP is incremented after every instruction byte is fetched.
• IP gets a new value whenever a branch instruction occurs.
• CS is multiplied by 10H to give the 20 bit physical address of the Code Segment.
• Address of the next instruction is calculated as CS x 10H + IP.
Example:
CS = 4321H IP = 1000H

then CS x 10H = 43210H + offset = 44210H

This is the address of the instruction.

Code Segment register:

CS holds the base address for the Code Segment. All programs are stored in the Code Segment and
accessed via the IP.
Data Segment register:
DS holds the base address for the Data Segment.
Stack Segment register:
SS holds the base address for the Stack Segment.
Extra Segment register:
ES holds the base address for the Extra Segment.
Address Generation Circuit:
• The BIU has a Physical Address Generation Circuit.
• It generates the 20 bit physical address using Segment and Offset addresses using the
formula:
• Physical Address
 = Segment Address x 10H + Offset Address

6 Byte Pre-fetch Queue:

• It is a 6 byte queue (FIFO).
• Fetching the next instruction (by BIU from CS) while executing the current instruction is
called pipelining.
• Gets flushed whenever a branch instruction occurs.

The Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU, Special purpose registers,
Instruction Register and Instruction Decoder and the Flag/Status Register.

1. Fetches instructions from the Queue in BIU, decodes and executes arithmetic and logic
operations using the ALU.
2. Sends control signals for internal data transfer operations within the microprocessor.
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine cycles.
8086 has four 16 bit general purpose registers AX, BX, CX and DX. Store intermediate values during
execution. Each of these have two 8 bit parts (higher and lower).
• AX register:
It holds operands and results during multiplication and division operations. Also an
accumulator during String operations.
• BX register:
It holds the memory address (offset address) in indirect addressing modes.
• CX register:
It holds count for instructions like loop, rotate, shift and string operations.
• DX register:
It is used with AX to hold 32 bit values during multiplication and division.
Arithmetic Logic Unit (16 bit):
Performs 8 and 16 bit arithmetic and logic operations.
Special purpose registers (16-bit):
• Stack Pointer:
Points to Stack top. Stack is in Stack Segment, used during instructions like PUSH, POP,
CALL, RET etc.
 • Base Pointer:
BP can hold offset address of any location in the stack segment. It is used to access random
locations of the stack.
• Source Index:
It holds offset address in Data Segment during string operations.
• Destination Index:
It holds offset address in Extra Segment during string operations.
Instruction Register and Instruction Decoder:
The EU fetches an opcode from the queue into the instruction register. The instruction decoder decodes
it and sends the information to the control circuit for execution.
Flag/Status register (16 bits):
It has 9 flags that help change or recognize the state of the microprocessor.
6 Status flags:
1. carry flag(CF)
2. parity flag(PF)
3. auxiliary carry flag(AF)
4. zero flag(Z)
5. sign flag(S)
6. overflow flag (O)
Status flags are updated after every arithmetic and logic operation.

3 Control flags:
1. trap flag(TF)
2. interrupt flag(IF)
3. direction flag(DF)
These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI, STI, etc.

The Control flags are used to control certain operations.

Q: How many interrupts lines does 8086 have?
Interrupt:
An interrupt is a condition that halts the microprocessor temporarily to work on a different task and
then return to its previous task. Interrupt is an event or signal that request to attention of CPU. This halt
allows peripheral devices to access the microprocessor.
Whenever an interrupt occurs the processor completes the execution of the current instruction and starts
the execution of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a program that tells the
processor what to do when the interrupt occurs. After the execution of ISR, control returns back to the
main routine where it was interrupted.
In 8086 microprocessor following tasks are performed when microprocessor encounters an interrupt:

1. The value of flag register is pushed into the stack. It means that first the value of SP (Stack
Pointer) is decremented by 2 then the value of flag register is pushed to the memory address of
stack segment.
2. The value of starting memory address of CS (Code Segment) is pushed into the stack.
3. The value of IP (Instruction Pointer) is pushed into the stack.
4. IP is loaded from word location (Interrupt type) * 04.
 5. CS is loaded from the next word location.
Interrupt and Trap flag are reset to 0.

8086 microprocessor have 5 interrupt lines.

Q: Explain the concept of CISC and RISC technology. How these technology are
facilitating in improvement of today process?
Central Processing Unit Architecture operates the capacity to work from “Instruction Set Architecture” to
where it was designed. The architectural designs of CPU are RISC (Reduced instruction set computing)
and CISC (Complex instruction set computing). CISC has the ability to execute addressing modes or
multi-step operations within one instruction set. It is the design of the CPU where one instruction
performs many low-level operations. For example, memory storage, an arithmetic operation and loading
from memory. RISC is a CPU design strategy based on the insight that simplified instruction set gives
higher performance when combined with a microprocessor architecture which has the ability to execute
the instructions by using some microprocessor cycles per instruction.

RISC AND CISC ARCHITECTURE

Hardware designers invent numerous technologies & tools to implement the desired architecture in order
to fulfill these needs. Hardware architecture may be implemented to be either hardware specific or software
specific, but according to the application both are used in the required quantity. As far as the processor
hardware is concerned, there are 2 types of concepts to implement the processor hardware architecture.
First one is RISC and other is CISC.

CISC Architecture

The CISC approach attempts to minimize the number of instructions per program, sacrificing the number
of cycles per instruction. Computers based on the CISC architecture are designed to decrease the memory
cost. Because, the large programs need more storage, thus increasing the memory cost and large memory
becomes more expensive. To solve these problems, the number of instructions per program can be reduced
by embedding the number of operations in a single instruction, thereby making the instructions more
complex.
 CISC Architecture

• MUL loads two values from the memory into separate registers in CISC.
• CISC uses minimum possible instructions by implementing hardware and executes operations.
• Instruction Set Architecture is a medium to permit communication between the programmer and
the hardware. Data execution part, copying of data, deleting or editing is the user commands used
in the microprocessor and with this microprocessor the Instruction set architecture is operated.
• The main keywords used in the above Instruction Set Architecture are as below

Instruction Set: Group of instructions given to execute the program and they direct the computer by
manipulating the data. Instructions are in the form – Opcode (operational code) and Operand. Where,
opcode is the instruction applied to load and store data, etc. The operand is a memory register where
instruction applied.

Addressing Modes: Addressing modes are the manner in the data is accessed. Depending upon the type
of instruction applied, addressing modes are of various types such as direct mode where straight data is
accessed or indirect mode where the location of the data is accessed. Processors having identical ISA may
be very different in organization. Processors with identical ISA and nearly identical organization is still not
nearly identical.
CPU performance is given by the fundamental law

Thus, CPU performance is dependent upon Instruction Count, CPI (Cycles per instruction) and Clock
cycle time. And all three are affected by the instruction set architecture.

Instruction Count of the CPU

This underlines the importance of the instruction set architecture. There are two prevalent instruction set
architectures

Examples of CISC PROCESSOR

IBM 370/168 – It was introduced in the year 1970. CISC design is a 32 bit processor and four 64-bit
floating point registers.
VAX 11/780 – CISC design is a 32-bit processor and it supports many numbers of addressing modes and
machine instructions which is from Digital Equipment Corporation.
Intel 80486 – It was launched in the year 1989 and it is a CISC processor, which has instructions varying
lengths from 1 to 11 and it will have 235 instructions.

CHARACTERISTICS OF CISC ARCHITECTURE

• Instruction-decoding logic will be Complex.

• One instruction is required to support multiple addressing modes.
• Less chip space is enough for general purpose registers for the instructions that are 0operated
directly on memory.
• Various CISC designs are set up two special registers for the stack pointer, handling interrupts, etc.
• MUL is referred to as a “complex instruction” and requires the programmer for storing functions.

RISC Architecture
RISC (Reduced Instruction Set Computer) is used in portable devices due to its power efficiency. For
Example, Apple iPod and Nintendo DS. RISC is a type of microprocessor architecture that uses highly-
optimized set of instructions. RISC does the opposite, reducing the cycles per instruction at the cost of the
number of instructions per program Pipelining is one of the unique feature of RISC. It is performed by
overlapping the execution of several instructions in a pipeline fashion. It has a high performance advantage
over CISC.

RISC Architecture

RISC processors take simple instructions and are executed within a clock cycle

RISC ARCHITECTURE CHARACTERISTICS

• Simple Instructions are used in RISC architecture.

• RISC helps and supports few simple data types and synthesize complex data types.
• RISC utilizes simple addressing modes and fixed length instructions for pipelining.
• RISC permits any register to use in any context.
• One Cycle Execution Time
• The amount of work that a computer can perform is reduced by separating “LOAD” and “STORE”
instructions.
 • RISC contains Large Number of Registers in order to prevent various number of interactions with
memory.
• In RISC, Pipelining is easy as the execution of all instructions will be done in a uniform interval
of time i.e. one click.
• In RISC, more RAM is required to store assembly level instructions.
• Reduced instructions need a less number of transistors in RISC.
• RISC uses Harvard memory model means it is Harvard Architecture.
• A compiler is used to perform the conversion operation means to convert a high-level language
statement into the code of its form.

RISC & CISC Comparison

MUL instruction is divided into three instructions

“LOAD” – moves data from the memory bank to a register
“PROD” – finds product of two operands located within the registers
“STORE” – moves data from a register to the memory banks
The main difference between RISC and CISC is the number of instructions and its complexity.

SEMANTIC GAP

Both RISC and CISC architectures have been developed as an attempt to cover the semantic gape.

With an objective of improving efficiency of software development, several

powerful programming languages have come up, viz., Ada, C, C++, Java, etc. They provide a high level of
abstraction, conciseness and power. By this evolution the semantic gap grows. To enable efficient
compilation of high level language programs, CISC and RISC designs are the two options.

CISC designs involve very complex architectures, including a large number of instructions and addressing
modes, whereas RISC designs involve simplified instruction set and adapt it to the real requirements of user
programs.
Multiplication of two Numbers in Memory

If the main memory is divided into areas that are numbered from row1:column 1 to row 5 :column 4. The
data is loaded into one of four registers (A, B, C, or D). To find multiplication of two numbers- One stored
in location 1:3 and other stored in location 4:2 and store back result in 1:3.

The Advantages of RISC architecture

• RISC(Reduced instruction set computing)architecture has a set of instructions, so high-level

language compilers can produce more efficient code
• It allows freedom of using the space on microprocessors because of its simplicity.
• Many RISC processors use the registers for passing arguments and holding the local variables.
• RISC functions use only a few parameters, and the RISC processors cannot use the call instructions,
and therefore, use a fixed length instruction which is easy to pipeline.
• The speed of the operation can be maximized and the execution time can be minimized.
Very less number of instructional formats, a few numbers of instructions and a few addressing
modes are needed.

Advantages of CISC architecture

• Microprogramming is easy assembly language to implement, and less expensive than hard wiring
a control unit.
• The ease of micro coding new instructions allowed designers to make CISC machines upwardly
compatible:
• As each instruction became more accomplished, fewer instructions could be used to implement a
given task.