DATA SHEET val NHS March 1994 HM 65262 16Kx1 VERY LOW POWER CMOS SRAM FEATURES « ACCESS TIME = 300 MILS WIDTH PACKAGE COMMERCIAL : 70 ns (max) » TTLCOMPATIBLE INPUTS AND OUTPUTS: MILITARYANDUSTRIAL : 70/85 ns (max) ASYNCHRONOUS ern oo SINGLE 5 VOLT SUPPLY STANDBY : 2.0 uW (typ) = EQUAL CYCLE AND ACCESS TIME DATA RETENTION : 0.8 LW (typ) « GATED INPUTS : NO PULL-UP/DOWN = WIDE TEMPERATURE RANGE :~ 55 TO + 125°C RESISTORS ARE REQUIRED INTRODUCTION ‘The HM 65262 is a very low power CMOS static RAM organized as 16384 x 1 bits. tis manufactured using he MHS high performance CMOS technology. ‘The HM 65262 is a “Pure CMOS SRAM" utlsing an array of six transistor (6T) memory cells permitting the lowest possible standby supply current (typical value = 0.1 wA) over the full temperature range. The high stability of the 6T cell provides excellent protection against soft errors due to noise. Easy memory expansion is provided by an active low chip select (CS) and active low output enable (OE) and three state drivers. All inputs and outputs of the HM 65262 are TTL compatible and operate from single 5V supply thus simplifying system design. ‘The HM 65262 is 100 % processed following the test methods of MIL STD 883C and/or ESA/SCC 9000, making itideally suitable for mitary/space applications ‘that demand superior levels of performance and reliability. The information contained herein is subject to change without notice. No responsibilty is assumed by MATRA MHS SA for using tis publication and/or ‘reuits described herein nor fr any possible lfeiagements of patents or other rights of third parties which may resut from is use HM 65262/Rev.2.0 MH 5868456 0003510 44e gee eee ee es ee eg eg ee gE ee Eee Ee ego Ee gE eeHM 65262 INTERFACE PIN CONFIGURATION Plastic 300 mits, 20 pins, DIL Leo, 20 pins. (Ceramic 300 mis, 20 pins, DIL aot 20 vec, at C2 19h 13, A203 sep ate 2 ass pant 2 45 te A10 am As C6 18[3 49 a a6 C7 +4 as ovr Dout Cs 130047 wo +2001N Gnb E10 pes Pinout DIL 20 pins (top view) Pinout LCC 20 pins (top view) BLOCK DIAGRAM 7 ) A a : 7 _— 1 ROW FOW a = 1 |apoRESs| — [DeooDER| bet Uy ea ae ae ' BUFFERS | 5 | (1OF 128) fi2g . 1 a3 t > oN ——_+ ‘COLUVDECODER (1 OF 1 moroorcune > dour COLUMN ADDRESS BUFFERS Ww ATABADANOAN AS AB haNHS eo es2eamev20 @™ 5868456 0003511 329 aLOGIC SYMBOL vec 1 S. Ww 40 i oN os 3 fs 4s 26: a7, 4a pour Aa, 0 an ae m3 — ono PIN NAMES ‘AO-A13_: Address inputs |W: Write enable Din: Input VCC: Power Dout _: Output GND_: Ground [CS —_:Chip select TRUTH TABLE [€S | W | DATAIN | DaTA-OUT| MODE ee ez Z__| Deselect Cyne Vaid | Read | ute | vata z Write Ulow, Ho high, X= Wor L, Z= High impedance ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Supply voltage to GND potential : 0:3 V to +7.0V Input or Output voltage applied : (Gnd - 0.3 V) to (Veo +03V) OPERATING RANGE Storage temperature : - 65°C to + 160°C ‘OPERATING VOLTAGE ‘OPERATING TEMPERATURE Military ©) Voo + 10% = 55°C to + 125°C Industrial €9) I Voc 10 % o = 40°C to + 85°C ‘Commercial €3) | Voo#10% =0°C 10+ 70°C | RECOMMENDED DC OPERATING CONDITIONS { PARAMETER DESCRIPTION MINIMUM TYPICAL | MAXIMUM | UNIT Voc ‘Supply voltage 45 5.0 Sia] aaa. Gnd Ground 0.0 0.0 00 Vv VIL (1) | Input low voltage =03 0.0 08 Vv VIH Input high voltage 22 = Veo +0.3V 7 Note: 1. ViLmin=—03 V or— 1.0 V pulse width 50 rs. — CAPACITANCE PARAMETER | DESCRIPTION _ ‘MINIMUM TYPICAL | MAXIMUM | UNIT Cin (@ | Input capacitance = = 8 pF Cout (2) | Output capacitance Zz = = I 8 a Note: 2 TA 2500, = 1 MHz, Vs = 50, these parametrs ae ot 1006s ELECTRICAL CHARACTERISTICS DC PARAMETER PARAMETER DESCRIPTION _ MINIMUM TYPICAL | MAXIMUM | UNIT 1X (3) | Input leakage current 10 = jee) pA T1OZ____ (3) | Output leakage current =10 = 10 nA [VOL _(4) { Output low voltage = = 04 Vv [VOH (4) | Output high voltage Pe = = Vv Notes : 3. Gnd< Vn VE. 6 0$2Voo-03V, but=0mA 7. GSS VI eut=0 mA, Vin Gree. 8. Vecmax but = Oma t=1 Mir and S MAM, Vin = GndVox =z mA 36 HM e5262/Rev.20 M@™@ 5868456 0003513 17)DATA RETENTION MODE MHS CMOS RAM's are designed with battery backup 2. CS must be kept between Voc + 0.3 V and 70 % of in mind. Data retention voltage and supply current are ‘Voc during the power up and power down transitions. guaranteed over temperature. The following rules 3. The RAM can begin operation > 55 ns after Voc re- Insure data retention : aches the minimum operating (4.5 V). 1. Chip select (CS) must be held high during data reten- tion ; within Vcc to Vec - 0.2 V. TIMING DATARETENTION MODE DATA RETENTION CHARACTERISTICS PARAMETER DESCRIPTION MINIMUM a | wax | unr | [vecDR Voc for data retention 20 = eS Vv | TCDR Chip deselected to data 0.0 = = ns retention time TR __| Operation recovery time TAVAV (10) = = ns ICCDR1 (11) | Data retention current @ 20 : HM-65262(8)-9 - on 20 yA HM-65262(8).2 - ot 20.0 HA HM-652620-5, - ot 30.0 yA HM-652620-9 | - ot 30.0 BA HM-65262C-2 - [oa 200.0 A {CCDR2 (11) | Data retention current @ 30V : HM-65262(8)}-9 - 03 30 WA HM-65262(8).2 - 03 30.0 nA HM-65262C-5 - 03 50.0 HA | HM-65262C-9 - 03 50.0 BA L HM-65262C-2_ = Ga 0.3 300.0 HA Notes: 9. TA=250, 10. TAVAV= Read cyte time. 11, CS Vee, Vin= Greer, ths parameter is only test io Vor =2V. sm esasonon.20 7 HS M™ 5868456 0003514 034 aAC PARAMETERS ‘AC CONDITIONS : Input pulse levels: Gnd to 3.0V Input timing reference levels. =: 1.5V Input rise :5ns Output load 2 TTTL gate + 100 pF WRITE CYCLE : COMMERCIAL (- 5) SPECIFICATION SYMBOL PARAMETER = S5052 ee unr | VALUE TAVAV Write cycle time 70 70 ns, min TAWL ‘Address set-up time 0 0 “ns min TAVWH ‘Address valid to end to write 55 55 ns min TOVWH Data set-up time _ 40 40 ns min TELWH CS low to write end 55 55 ns min _TWLOZ _ (12) | Write low to high Z 40 40 ns max TTWLwH _| Write puise width 55 55 ns min TWHAX ‘Address hold to end of write 0 0 ns min TWHDX Data hold time 0 0 ns rin TWHOX (12) | Write high to low Z 0 ns ‘min WRITE CYCLE : INDUSTRIAL (~ 9) AND MILITARY (- 2) SPECIFICATION SYMBOL PARAMETER Soe | ue? | 85282 ur | VALUE TAVAV | Write eyele time “70 85 85 ns min | TAVWL Address set-uptime |. 0 0 ns “min TAVWH Address valid to end of write | 55 65 65 ns min’ TOVWH Data set-up time [4 45 45 ns min | LTELWH CS low to write end 55 6 6 | os min TWLOZ (12) | Write low to high Z 50 50 50 ns max 8] TWLWH Write pulse width 55 65 65 ns min TWHAX _| Address hold to end of write 0 Oe) ns min ‘TWHDX Data hold time 70 0 0 ns min TWHOX (12) | Write high to low Z : 0 Oo ns. ‘min Note : 12, The data input set-up and hold timing should be referenced tothe rising edge ofthe signal that terminates the wite, 88 HM 65262/Rev.2.0 M@™ 5668456 0003515 T7y mm ae eeeWRITE CYCLE 1 (W CONTROLLED) (note 13) ow ATA VALD * [owecce. Crrwwax our a Leeman a WRITE CYCLE 2 (CS CONTROLLED) (note 13) WAV ‘ADDRESS a Ww pin DATAIN VALID HIGH INPEDANGE pour DATA UNDEFINED Note : 18, The intemal wrt of he meriory is dained by the overap of CS LOW and W LOW. Both signals must be LOW toinfateawrie and ether signal can terminate a wt by ging HIGH, The data input stip and hold timing should be referenced to he rising edge cf the signal that teinates the writ, tM 5620 29 mS M@™ 5868456 0003516 900READ CYCLE : COMMERCIAL (- 5) SPECIFICATION SYMBOL PARAMETER 65352 UNIT VALUE (TAVAV READ oycle time 70 70 ns rnin TAVQV Address access time 70 70 as max TAVOX ‘Address valid to ow Z 5 5 ns rnin TELQV _ Chip-select access time 70 70 ns max TELQZ CS low to lowZ 5 5 ns rnin TEHQZ __| CShighto highZ | 40 ns max READ CYCLE : INDUSTRIAL (- 9) AND MILITARY (- 2) SPECIFICATION 65262 65262 65262 SYMBOL PARAMETER a - Coa | UNT | VALUE | TAVAV READ cycle time 70 |__ 88 8 ns rnin TAVOV Address access time | 70 85 as ns max TAVOX Address valid to low Z 5 5 5 ns | min TELQV Chip-select access time 70 85 e 85 ns max TELOX TSlowtolowZ 5 5 5 ns min TEHOZ GS high to high Z mz 4 | 40 ns max READ CYCLE nb 1 aooress a Ss reat EH anne our READ CYCLE nb 2 zz ‘0RESS |. ____ twav —___1 | | al 1 ( f — revo F a= cour —{ X ial e10 HM 65262/Rev.2.0 MH 5668456 0003517 847 mmBURN-IN SCHEMATICS Fww41 7 20) vec F2-ww 2 19] WW F14 F3- Ww 3 18 -WW-— F143 F4-ww 4 17 WW F12 F5 WW 5 16 WW Fit Fe-ww— 6 Tet oe eee F7-WW447 14-9 cons sv NC-WW 8 13 -WW— F8 NC = Non connected so-W— 9 12;-WW— Fo. GND 10 11 WW 81 ORDERING INFORMATION PACKAGE DEVICE TYPE GRADE LEVEL HM 3 B -5:R a = S a i 16 kx 1 very low power | : Military static RAM Commercial 100% 25°C Probe 0 Chip form B =high speediiow current : Industrial 1 - Ceramic 20 pins Blank: standard speed/iow IL STD 883 Class B or S 300 mits, current Dice Miltary program 3- Plastic 20 pins C: standard : Tape & Reel option 300 mils. : Tape & Reel / Dry pack option 4- LCC 20 pins + Dry pack option 526270420 en mS @™ 5468456 0003518 733