Save trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com CBES Scheme » (COTO) ‘Third Semester B.E. Degree Examination, June/July 2017 Analog and Digital Electronics ‘Time: 3 rs. Ma i 80 Note: Answer any FIVE full questions, choosing one full question from each module. 4 Modute-1 BL a. Explain with help of a circuit diagram and characteristic curvdg waking N-channel DE z MOSFET. i (2 Marks) a List and explain any one application of FET and its workig@ Rh ROUMBiagram. (04 Marks) i on £2 2 a. Explain the performance paramsters of operational pi (08 Marks) Be 'b. Mention and explain the working of any two applicaNys of operational amplifier. (08 Marks) ae ae 2&3 a. What is logical gate? Realize (A +B)-C) LAND Gates. (4 Marks) ee b. Describe positive and Negative logic. Listhe & 2es between them. (0 Marks) i © Find the minimal SOP (sum of prod ing Booleon functions using K-map 7 D. f@,b.ed=Tm6, 7,9 19 4,5, 11) i f@bed=xM (2.3.4 hs) (08 marks) is ae R LE + 0. Using ovine ~oicctusky Nella he folowing Bookean equation = F¢@, 6,6, d= Sm, 1, 2gAmbP. Lgl. 14,15). (ontarns) aa 6. Define Hazard. Expl Sof Haracds 6Mtaris) a 22 5 a What is moltiplexggd Des BRING co 1 rauluploxer (MUX) using two 16 to 1 MUX and one fF 210 | MUX (4 aris) 7 b. Show How us ‘oder and multi input OR gates, following Boolean Expressions : can be realized si sly 3 Fi Gb.) ), Fa (a, by 6) = Em (0, 5), Fs (a,b, €)= Em (1, 2.3.7) (os Marks) 2g Des jer using PLA. (07 Marks) o2 2 OR FE 6 0. implcRgnt the Boolean function expressed by SOP f(b, 6 d) = Em (h 2.5, 6 9 12) as 3 Mux (04 Marks) me b nitude comparator? Design and explain 2 bit magnitude comparator. (08 Marks) | Ditferentiate between combinational and sequential circuit (o4Marks) i o i Modute-4 5 th a neat logic diagrams and truth table. Explain the working of JK master slave Flip-Flop & nig with its implementation using NAND Gates. (10 Marks) Derive the characteristic equation for SR, D and JK Flip-Flop. (06 Marks) S 1 of2 S_. | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com oR 8 4. Using Negative Edge triggered D-Flip Flop. Draw 3 Logic diagram of 4 biffgerial ‘out (SISO) Register. Draw the waveform to shifl Binary number 1010 into thi jar) ». Explain with neat diagram How shift Register can be applied for serial addition, (07 Marks) ©. Differentiate between synchronous and Asynchronous counter @ i Man) Module: 9a, Design Asynchronous counter forthe sequences 0 +4 —+ 7 4. Using S. R Flip-Flop. (2 Maris) &. With neat diagram. Explain Digital Clock (oomane) or 10 a, Explain 2 bit simultaneous A/D converter Wo saris b. What is Binary Ladder? Explain the Binary Ladder input oF 1000. (@6.marts) S @ » » « 20f2 BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiative