Lb Operation: (DE) < (VIL), DE<-DE + 1, HL HL + 1,BC—BC-1 OpCode: — LDI Operands: (SP), HL a} ap afo}a}afo}1) 60 1} of 1] 0} 0] 0]}0/ 0] A0 Description: A byte of data is transferred from the memory location addressed, by the contents of the HL register pair to the memory location addressed by the contents of the DE register pair. Then both these register pairs are incremented and the BC (Byte Counter) register pair is decremented. M Cycles T States 4MHz ET. 4 164,4,3, 5) 4000 Condition Bits Affected: LOIR Operation: (DE) (HL), DECADE +1, HL—HL+ 1, BC Fes BC-1 OpCode: LDIR Operands: Bs tl Pops] sfofs] TPoT* 1+] *] °]o]o] Description: This -byte instruction transfers s byte of data from the memory losation auddressed by the contents of the HL registerpair othe memory loation addressed hy the DE register pair. Both these register pairs are ineremented and the BC (Byte Counter) register pair it decremented. If docrementing causes the BC to goto zer, the instruction is terminated. IBC isnot 220, the program counter is docremontod by two end tho instruction is repeated. Inerupts are recognized and two reffesh cycles are executed ater each data tansfer. When BC is set to z=ro prior to instruction exevation, the instretion oops through 64 Kbyes, For BC +0: Mcycles —T'States_ 4 MHZ ELT. 5 214.4355) 525 For BC= 0: Mcycls TStatos_ 4 MHz ELT. 4 164.4,3.9) 4.00)LDD Operation: (DE) < (HL), DE< DE -1, HL CHL-I, BC BC-1 Op Code: LDD Operands: — 1fafrfoftfife]s]e afol+fo]s]ofofolas Description: This 2-byte instruction transfers a byte of data from the memory location addressed by the contents of the HL register pair to the memory location addressed by the contents of the DE register pair. Then both of these register pairs including the BC (Byte Counter) register pair are decremented. M Cycles T States 4 MHz ET. 4 16 4,4,3,5) 4.00 Condition Bits Affected: LOOR Operation: (DE) — (HL), DE De 1, HL HL, BC BCI OpCode: LDR Operands: — 1] +[* Jo] +] +[o[+]eo 1[o[+] 1] 4] ofo oles Description; This 2-byte instruction transfers byte of data from the memory location addressed by the contents of the HL register patr tothe memory location addressed by the contents of the DE register pair. Then bothot these rezistes, as well as the BC (Byte Counter), are decremented. If “decrementing causes BC to 20 to zero, the instruction is terminated. IF [BC is not zeto, the program counler is decremented by two and the instruction is repeated. Interrupts are recognized and two refresh cycles cexecuteafter each data transfer. When BC is set to zero, priorto instruction execution, the instruction loops through 6 Kbytes ForBC #0: M cycles TStates 4 MHz ET. 3 2144,3,5,3) 3.25 For BC = 0:cPI A+ (HL), HL © HL #1, BC BC-1 Pl afajafofs]r[o[1]e 1fo]1]ofo]ofofoja Description: ‘The contents of the memory location addressed by the HL register is compared with the contents of the Accumulator. In case of a true compare, a condition bitis set. Then HL is ineremented and the Byte Counter (register pair BC) is decremented, M Cycles T States 4 MHzE.T. 4 16 (4, 4,3, 5) 4.00 cPIR Operation: AHL),HL © HLH, BC< BC OpCode: CPR Operands: — Teel [ef] *)°[*]*]°]e]e|s]™ Description: The contnts ofthe memory location addressed by the HL register par ‘compared with the contets of he Accumulator In case ofa true.compare, 3 condition bit is set. HL isineremented and the Byte Counter (register pair [RO is decremented. IF decrementing causes BC to goto zero or fA =CHL), the instruction is temninated. ITEC isnot zero ad A + (HL), the program counter deceemerted by two and the instruction is peated. eterupts are reongnized and two refresh cycles are exevtted after cach data transfer, IF BC is set to zero before instruction execution, the instrction Loops through 64 Klytes if no match is found, ForBC +0 and A + (HL) Mecycles TStates = 4MHZ ET. 5 214,4,3,5,5) 528 ForBC=Oand A= (HL: M cycles TStates — 4MHz ELT. 4 164,4,3,5) 400cPD Operation: A (HL), HL HL-I, BC -BC-1 Op Code: CPD Operands: — a] +[sfo[s[1[o [1] eo ios feo[+[of[o][s] Description: The contents of the memory location addressed by the HL register pair is ‘compared with the contents of the Accumulator. In case of a true compare, a condition bit is set. The HL and Byte Counter (register pair BC) are decremented. M Cycles T States 4MHz E.T. 4 164, 4,3, 5) 4.00 Zawartosé akumulatora jest poréwnywana z zawartoscia komérki o adresie zawartym w HL, w przypadku pozytywnego poréwnania odpowiedni bit warunkowy jest ustawiany. cPDR Operation; A-(HL), HL HL-1,8C-BC-1 Op code: cPDR Operands: — te pops tsfo [sj pols fsfsfolols] Description: ‘The contents of the memory leationadcessd by the HL ester pairs compared withthe contents ofthe Accumulator In case ofa truecompare, ‘scondtion bi is et. The HL and RC (Ryte Counter) register pairs are decremented If decrementing causes the BC togo to zero or if A= (HL), the inert ie terminated. IRC not zero and A = (HL), the program ‘counte is decremented by two and the instruction i repeated. Interrupts are recognized and two refer cycles etacute after each data tanec When [BC is set to zero, prior to insttctior execution, the instruction loops trough 64 Kbytes if no match is Found For BC 0and A = (HL) Mcycles —TStates_ 4 MHz ET. 5 GEIS) 525 For BC=Oand A = (HL): Moycles States 4 MHz EL. 4 164.43,5) 400 Poréwnanie zawartosei akumulatora i komorki pamigci zawartej w HL. Adres HL jest dekrementowany. Licznik petli jest dekrementowany. Gdy A=(HL) lub BC=0000 instrukeja jest przerwana.Rozkazy arytmetyczne 8-mio bitowe