EE141- Spring 2003

Lecture 4
Design Rules
CMOS Inverter
MOS Transistor Model

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Today’s lecture

Design Rules

The CMOS inverter at a glance

An MOS transistor model for manual
analysis

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 Important!

Labs start next week

You must show up in one of the lab sessions
next week

If you don’t show up you will be dropped from
the class
» Unless you let me know that you still want to be in
the class

Homework 2 will be posted later today. Due
next Thursday, February 6.

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Design Rules

Jan M. Rabaey

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 3D Perspective
Polysilicon Aluminum

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Design Rules

Interface between designer and process

engineer

Guidelines for constructing process masks

Unit dimension: Minimum line width
» scalable design rules: lambda parameter
» absolute dimensions (micron rules)

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 CMOS Process Layers
Layer Color Representation

Well (p,n) Yellow

Active Area (n+,p+) Green
Select (p+,n+) Green
Polysilicon Red
Metal1 Blue
Metal2 Magenta
Contact To Poly Black
Contact To Diffusion Black
Via Black

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Layers in 0.25 µm CMOS process

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 Intra-Layer Design Rules
Same Potential Different Potential

9 2
0
Well or Polysilicon
6
10 2
3 3
Active Metal1
Contact
or Via 2
3 Hole 3
2 2 4
Select Metal2

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Transistor Layout
Transistor

3 2

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 Vias and Contacts
2
4
Via
1 1
5
Metal to
Metal to 1 Poly Contact
Active Contact 3 2

2
2

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Select Layer
2
Select
3
2

1
3 3

2 5

Well
Substrate
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 CMOS Inverter Layout
GND In VD D

A A’

Out

(a) Layout

A A’
n
p-substrate Field
n+ p+ Oxide
(b) Cross-Section along A-A’
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Layout Editor

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 Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

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Sticks Diagram
V DD 3

In Out
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
1 “compaction” program

GND

Stick diagram of inverter

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 CMOS Inverter
MOS Transistor

Jan M. Rabaey

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What is a Transistor?

A MOS Transistor A Switch!

|VGS |
VGS ≥ VT
Ron
S D

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 NMOS and PMOS

NMOS Transistor PMOS Transistor

G G
V GS >0 V GS <0

S D S D

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The CMOS Inverter: A First

Glance
V DD

V in V out

CL

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 CMOS Inverter

N Well VDD

VDD PMOS
λ
2λ

Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS

NMOS
GND

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Two Inverters
Share power and ground

Abut cells

VDD Connect in Metal

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Switch Model of CMOS Transistor
|VGS |

Ron

|VGS | > |VT|

|VGS | < |VT |

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CMOS Inverter
First-Order DC Analysis

VDD V DD

Rp
VOL = 0
VOH = VDD
Vout VM = f(Rn, Rp)
V out

Rn

V in ⫽ VDD V in ⫽ 0
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 CMOS Inverter: Transient Response
VDD VDD

Rp tpHL = f(R on.CL)

= 0.69 RonCL

Vout
Vout
CL
CL
Rn

Vin ⫽ 0 Vin ⫽ VDD

(a) Low-to-high (b) High-to-low
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CMOS Properties

Full rail-to-rail swing

Symmetrical VTC

Propagation delay function of load
capacitance and resistance of transistors

No static power dissipation

Direct path current during switching

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 The MOS Transistor
Polysilicon Aluminum

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MOS Transistors -
Types and Symbols
D D

G G

S S

NMOS Enhancement NMOS Depletion

D D

G G B

S S

PMOS Enhancement NMOS with

Bulk Contact

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 Threshold Voltage: Concept

+
S VG S D
G
–

n+ n+

n-channel Depletion
region
p-substrate

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The Threshold Voltage

Threshold

Fermi potential

2φF is approximately - 0.6V for p-type substrates

γ – the body factor
VT0 is approximately 0.45V for our process

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 The Body Effect
0 .9

0.8 5

0 .8

0.7 5

0 .7
V (V)

0.6 5
T

0 .6

0.5 5

0 .5

0.4 5

0 .4
-2.5 -2 -1 .5 -1 -0.5 0
V (V)
BS

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The Drain Current

Charge in the channel is controlled by the gate voltage:

Drain current is proportional to charge and velocity:

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 The Drain Current
Combining velocity and charge:

Integrating over the channel:

Transconductance:

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Transistor in Linear
Linear (Resistive) mode
VGS VDS
S
G ID
D

n+ – V(x) + n+

L x

p-substrate

MOS transistor and its bias conditions

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 Transistor in Saturation
VGS

VDS > VGS - VT

G

D
S

- +
n+ VGS - VT n+

Pinch-off

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Saturation
For VGD < VT, the drain current saturates

k′ W
I D = n (VGS − VT )2
2 L

Including channel-length modulation

k′ W
I D = n (VGS − VT )2 (1 + λVDS )
2 L

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 Modes of Operation
Cutoff:

VGS < VT ID = 0

Resistive:
k′ W  2 
VT < VGS ; VGS − VT > VDS ID = n (V
 GS − V )V
T DS −
VDS

2 L  2 
Saturation:

VT < VGS ; VGS − VT < VDS k′ W

I D = n (VGS − VT )2
2 L
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Current-Voltage Relations
A Good Ol’ Transistor
-4
x 10
6
VGS= 2.5 V

Resistive Saturation
4
VGS= 2.0 V
I D (A)

3 Quadratic
VDS = VGS - VT Relationship
2
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

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 A model for manual analysis

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Current-Voltage Relations
The Deep-Submicron Era
-4
x 10
2.5

VGS= 2.5 V
Early Saturation
2

VGS= 2.0 V
1.5
ID (A)

Linear
1
VGS= 1.5 V Relationship

0.5 VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

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 Velocity Saturation
υ n (m/s)
υsat = 105
Constant velocity

Constant mobility (slope = µ)

ξc = 1.5 ξ (V/µm)

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Velocity Saturation
ID
Long-channel device

VGS = VDD
Short-channel device

V DSAT VGS - V T VDS

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 ID versus VGS
-4
x 10 x 10
-4
6 2.5

5
2

4 linear
quadratic 1.5
I D (A)

ID (A)
3

1
2

1 0.5

quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)

Long Channel Short Channel

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ID versus VDS
-4 -4
x 10 x 10
6 2.5
VGS= 2.5 V
VGS= 2.5 V
5
2
Resistive Saturation
4 VGS= 2.0 V
VGS= 2.0 V 1.5
ID (A)
ID (A)

3
VDS = VGS - VT 1 VGS= 1.5 V
2
VGS= 1.5 V
0.5 VGS= 1.0 V
1
VGS= 1.0 V

0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VDS(V) VDS(V)

Long Channel Short Channel

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 Including Velocity Saturation

Approximate velocity:

And integrate current again:

In deep submicron, there are four regions of operation:

(1) cutoff, (2) resistive, (3) saturation and (4) velocity saturation
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Regions of Operation

Long Channel Short Channel

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 An Unified Model
for Manual Analysis

S D

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Regions of Operation
-4
x 10
2.5

VDS=VDSAT
2
Velocity
Linear
Saturated
1.5
ID (A)

0.5
VDSAT=VGT

VDS=VGT
Saturated
0
0 0.5 1 1.5 2 2.5
V DS (V)
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 A PMOS Transistor
-4
x 10
0
VGS = -1.0V

-0.2
VGS = -1.5V

-0.4
ID (A)

VGS = -2.0V
-0.6 Assume all variables
negative!
-0.8
VGS = -2.5V

-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)

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Transistor Model
for Manual Analysis

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 The Transistor as a Switch

VGS ≥ VT
Ron ID
V GS = VD D
S D
Rmid

R0

V DS
VDD/2 VDD

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The Transistor as a Switch

5
x 10
7

5
(Ohm )

4
eq

3
R

0
0.5 1 1.5 2 2 .5
V (V)
DD

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 The Transistor as a Switch

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Future Perspectives

25 nm MOS transistor (Folded Channel)

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