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VHDL
- VHDL laø ngoân ngöõ moâ taû phaàn cöùng.
- VHDL khoâng phaân bieät chöõ vieát hoa vaø chöõ thöôøng.
databus Databus DataBus DATABUS
- VHDL laø ngoân ngöõ “ñònh daïng töï do”.
if (a=b) then
if (a=b) then
if (a =
b) then
NguyenTrongLuat 1
nand2 mux2to1
d0
a
z d1 y
b
sel
NguyenTrongLuat 2
LIBRARY
khai baùo thö vieän
ENTITY
thöïc theå
ARCHITECTURE
kieán truùc
NguyenTrongLuat 3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a a : IN STD_LOGIC;
z
b b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
NguyenTrongLuat 4
IN
OUT
BUFFER
IN INOUT
IN
OUT
NguyenTrongLuat 6
ARCHITECTURE
Moâ taû thieát keá beân trong cuûa khoái, chæ roõ moái quan heä
giöõa caùc ngoõ vaøo vaø ngoõ ra.
ARCHITECTURE model OF nand_gate IS
a BEGIN
z
b z <= a NAND b;
END model;
NguyenTrongLuat 7
* Söï khaùc nhau giöõa Tín hieäu (Signal) vaø Bieán (Variable)
- Pheùp gaùn bieán (Variable) cho giaù trò töùc thôøi, pheùp gaùn
cuûa tín hieäu (signal) bò treã (delay)
- Tín hieäu (Signal) coù theå quan saùt daïng soùng (waveform),
nhöng bieán (Variable) thì khoâng.
NguyenTrongLuat 9
a <= ’1’; -- giaù trò gaùn ñaët giöõa 1 daáu nhaùy ñôn ‘ ’
a <= b(2); -- a <= b(2),
b <= "0000”; -- giaù trò gaùn ñaët giöõa 1 daáu nhaùy keùp “ ”
c <= B”0000”; -- B laø kyù hieäu cô soá 2 (coù theå boû)
d <= -- bieåu dieãn töøng nhoùm 4 bit phaân caùch _
”0110_0111”;
e <= X”AF67”; -- X laø kyù hieäu cô soá 16 (Hex)
f <= O”723”; -- O laø kyù hieäu cô soá 8 (Octal)
b <= c; -- b(3) <= c(0), b(2) <= c(1),
-- b(1) <= c(2), b(0) <= c(3)
d(7 downto 6)<= ”11”;
c(0 to 2)<= e(7 downto 5);
NguyenTrongLuat 12
a <= ”0000”;
b <= ”1111”;
c <= a & b; -- c = “00001111”
e <= ’0’ & ’0’ & ’0’ & ’0’ & ’1’ & ’1’ &
’1’ & ’1’; -- e = “00001111”
NguyenTrongLuat 13
* / MOD REM
NguyenTrongLuat 16
COMPONENT and2
x1
y PORT (x1,x2:IN STD_LOGIC;
x2 y: OUT STD_LOGIC);
END COMPONENT;
- Ñeå keát noái component caáp thaáp, thöïc hieän leänh thay theá trò
soá component (component instantiation) PORT MAP.
Coù 2 caùch: * Keát hôïp vò trí (positional association)
* Keát hôïp theo teân (named association)
NguyenTrongLuat 17
COMPONENT component_name
port declarations;
END COMPONENT;
...
Label: component_name PORT MAP (
port_name1 => sig_name1,
port_name2 => sig_name2 );
COMPONENT and2
PORT (x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
user1: and2 PORT MAP ( x1 => a, x2 => b,
y => c );
...
NguyenTrongLuat 18
COMPONENT component_name
port declarations;
END COMPONENT;
...
Label: component_name PORT MAP (
sig_name1, sig_name2, ... );
COMPONENT and2
PORT (x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
user1: and2 PORT MAP ( a, b, c );
...
NguyenTrongLuat 19
a
VD: Thieát keá XOR 3 ngoõ vaøo b
u1_out
- Moâ taû luoàng döõ lieäu di chuyeån töø ngoõ vaøo ñeán ngoõ ra.
- Caùc phaùt bieåu naøy ñöôïc thöïc thi cuøng thôøi ñieåm, vì vaäy thöù
töï caùc phaùt bieåu laø nhö nhau
NguyenTrongLuat 21
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xor3 IS
PORT ( a, b, c : IN STD_LOGIC;
result : OUT STD_LOGIC);
END xor3;
ARCHITECTURE dataflow OF xor3 IS
SIGNAL u1_out: STD_LOGIC;
BEGIN
u1_out <= a XOR b; Result <= u1_out XOR c;
Result <= u1_out XOR c; u1_out <= a XOR b;
END dataflow;
NguyenTrongLuat 22
Pheùp gaùn tín hieäu theo ñieàu kieän (Condition Signal Assigment)
WHEN - ELSE
signal_name <= value1 WHEN condition1 ELSE
{value2 WHEN condition2 ELSE}
valueN ;
xnor2 a b c
VD: xnor2
a 0 0 1
c 0 1 0
b
1 0 0
1 1 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xnor2 IS
PORT ( a, b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END xnor2;
ARCHITECTURE dataflow1 OF xnor2 IS
BEGIN
c <= ’1’ WHEN a = ’0’ AND b = ’0’ ELSE
’0’ WHEN a = ’0’ AND b = ’1’ ELSE
’0’ WHEN a = ’1’ AND b = ’0’ ELSE
’1’ WHEN a = ’1’ AND b = ’1’ ELSE
’0’ WHEN OTHERS;
END dataflow1;
NguyenTrongLuat 24
Pheùp gaùn tín hieäu coù choïn loïc (Select Signal Assigment)
WITH – SELECT - WHEN
WITH select_signal SELECT
signal_name <= value1 WHEN const1_of_select_signal,
{value2 WHEN const2_of_select_signal,}
valueN WHEN OTHERS;
LIBRARY ieee;
mux2to1
USE ieee.std_logic_1164.all;
d0 ENTITY mux2to1 IS
d1 y PORT ( d0, d1 : IN STD_LOGIC;
sel : IN STD_LOGIC;
sel y : OUT STD_LOGIC);
END mux2to1;
ARCHITECTURE dataflow2 OF mux2to1 IS
sel y BEGIN
0 d0 WITH sel SELECT
y <= d0 WHEN ’0’,
1 d1
d1 WHEN OTHERS;
END dataflow2;
NguyenTrongLuat 25
xnor2 a b c
VD: xnor2
a 0 0 1
c 0 1 0
b
1 0 0
1 1 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xnor2 IS
PORT ( a, b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END xnor2;
ARCHITECTURE dataflow2 OF xnor2 IS
SIGNAL ab : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
ab <= a & b;
WITH ab SELECT
c <= ’1’ WHEN ”00” | ”11”,
’0’ WHEN OTHERS;
END dataflow2;
NguyenTrongLuat 27
GENERIC
- Laø caáu truùc ñeå ñöa 1 haèng soá vaøo trong entity gioáng khai baùo
CONSTANT.
- Tieän lôïi cuûa generic laø coù theå söû duïng noù trong pheùp gaùn
thay theá trò soá töông ñöông component (component
instantitation), ñeå söû duïng caùc giaù trò haèng soá khaùc nhau khi
tham chieáu component.
ENTITY entity_name IS
GENERIC (
generic_name1: data_type := default_values;
generic_name2: data_type := default_values;
)
PORT (
port_name: mode data_type;
... )
END entity_name;
NguyenTrongLuat 29
NguyenTrongLuat 30
- Moâ taû söï ñaùp öùng cuûa ngoõ ra theo ngoõ vaøo.
- Söû duïng phaùt bieåu PROCESS chöùa caùc leänh ñöôïc thöïc thi
tuaàn töï, phuï thuoäc vaøo thöù töï cuûa noù
- Caùc phaùt bieåu tuaàn töï (Sequential statement): cho pheùp moâ taû
hoaït ñoäng tuaàn töï cuûa caùc tín hieäu
* Phaùt bieåu IF
* Phaùt bieåu CASE
* Phaùt bieåu LOOP
NguyenTrongLuat 31
PROCESS
- Process thöïc hieän caùc leänh beân trong noù 1 caùch tuaàn töï.
Vì vaäy thöù töï cuûa caùc leänh raát quan troïng.
- Process ñöôïc kích hoaït khi coù söï thay ñoåi cuûa 1 tín hieäu.
NguyenTrongLuat 33
NguyenTrongLuat 36
i:=0;
WHILE (i<10) LOOP
s <= i;
i := i+1;
END LOOP;
NguyenTrongLuat 37
- Heä toå hôïp coù theå ñöôïc thöïc hieän baèng caùc phaùt bieåu ñoàng
thôøi (concurent statement) vaø tuaàn töï (sequential statement).
- Phaùt bieåu tuaàn töï (sequent statement) ñöôïc duøng trong moâ taû
haønh vi (dataflow description)
NguyenTrongLuat 38
BOÄ COÄNG
fulladder
x
y
s s=x⊕ y⊕ z A
c D
z c=xy +yz +xz D
E
R
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fulladder IS
PORT ( x , y , z : IN STD_LOGIC;
s , c : OUT STD_LOGIC);
END fulladder;
NguyenTrongLuat 39
adder4
Boä coäng 4 bit adder4 söû duïng pheùp coäng soá hoïc
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC;
a, b : IN STD_LOGIC_VECTOR(3 downto 0);
s : OUT STD_LOGIC_VECTOR(3 downto 0);
Cout : OUT STD_LOGIC);
END adder4;
ARCHITECTURE Arithmetic OF fulladder IS
SIGNAL sum : STD_LOGIC_VECTOR(4 downto 0);
BEGIN
sum <= (’0’& a ) + b + Cin ;
s <= sum(3 downto 0) ;
Cout <= sum(4) ;
END Arithmetic;
Leänh USE ieee.std_logic_signed.all cho pheùp söû duïng
goùi (package) std_logic_signed, ñeå thöïc hieän pheùp toaùn soá
hoïc treân caùc tín hieäu std_logic.
NguyenTrongLuat 41
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux16 IS Söû duïng
PORT (
d : IN STD_LOGIC_VECTOR(15 downto 0); GENERATE
c : IN STD_LOGIC_VECTOR(3 downto 0);
f : OUT STD_LOGIC);
END mux16;
ARCHITECTURE Structure2 OF mux16 IS
SIGNAL w : STD_LOGIC_VECTOR(0 to 3);
COMPONENT mux4
PORT (
d0 , d1 , d2 , d3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(1 downto 0);
y : OUT STD_LOGIC);
END COMPONENT;
BEGIN
G0: FOR i IN 0 to 3 GENERATE
MUXES: mux4 PORT MAP (
d(4*i),d(4*i+1),d(4*i+2),d(4*i+3),c(1 downto 0),w(i));
END GENERATE;
M4: mux4 PORT MAP (w(0),w(1),w(2),w(3),c(3 downto 2),f);
END Structure2;
NguyenTrongLuat 44
dec2x4
en x1 x0 y3 y2 y1 y0
BOÄ GIAÛI MAÕ x0
y0
0 X X 0 0 0 0
D
E
y1 1 0 0 0 0 0 1 C
LIBRARY ieee; x1 1 0 1 0 0 1 0
USE ieee.std_logic_1164.all; y2 1 1 0 0 1 0 0
O
ENTITY dec2x4 IS en 1 1 1 1 0 0 0 D
PORT ( en : IN STD_LOGIC;
y3 E
x : IN STD_LOGIC_VECTOR(1 downto 0); R
y : OUT STD_LOGIC_VECTOR(3 downto 0));
END dec2x4;
ARCHITECTURE flow OF dec2x4 IS
SIGNAL ARCHITECTURE flow2 OF
temp: STD_LOGIC_VECTOR(3 downto 0); dec2x4 IS
BEGIN SIGNAL
WITH x SELECT en_x: STD_LOGIC_VECTOR(
temp <= ”0001” WHEN ”00” , 2 downto 0);
”0010” WHEN ”01” , BEGIN
”0100” WHEN ”10” , en_x <= en & x;
”1000” WHEN ”11” , WITH en_x SELECT
”0000” WHEN OTHERS; f <= ”0001” WHEN ”100” ,
y <= temp WHEN en = ’1’ ”0010” WHEN ”101” ,
ELSE ”0000”; ”0100” WHEN ”110” ,
END flow; ”1000” WHEN ”111” ,
”0000” WHEN OTHERS;
NguyenTrongLuat END flow2; 45
LIBRARY ieee;
Thieát keá IC DECCODER 74138
USE ieee.std_logic_1164.all;
ENTITY dec138 IS
PORT ( c, b, a : IN STD_LOGIC;
g1,g2a,g2b: IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(7 downto 0));
END dec138;
ARCHITECTURE flow OF dec138 IS
SIGNAL
data: STD_LOGIC_VECTOR(2 downto 0);
temp: STD_LOGIC_VECTOR(7 downto 0);
BEGIN
data <= c & b & a;
WITH data SELECT temp <= ”11111110” WHEN ”000” ,
”11111101” WHEN ”001” ,
”11111011” WHEN ”010” ,
”11110111” WHEN ”011” ,
”11101111” WHEN ”100” ,
”11011111” WHEN ”101” ,
”10111111” WHEN ”110” ,
”01111111” WHEN ”111” ,
”11111111” WHEN OTHERS;
y <= temp WHEN (g1 AND NOT g2a AND NOT g2b) = ’1’
ELSE ”11111111”;
END flow;
NguyenTrongLuat 46
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dec3to8 IS
PORT (x : IN STD_LOGIC_VECTOR(2 downto 0);
Söû duïng en: IN STD_LOGIC;
PROCESS
y : OUT STD_LOGIC_VECTOR(7 downto 0));
END dec3to8;
ARCHITECTURE behavior OF dec3to8 IS
BEGIN
PROCESS (x, en)
BEGIN
y <= ”11111111”;
Phaùt bieåu IF (en = ’1’) THEN
CASE x IS WHEN ”000” => y(0) <= ’0’;
If …. WHEN ”001” => y(1) <= ’0’;
WHEN ”010” => y(2) <= ’0’;
Case …. WHEN ”011” => y(3) <= ’0’;
WHEN ”100” => y(4) <= ’0’;
WHEN ”101” => y(5) <= ’0’;
WHEN ”110” => y(6) <= ’0’;
WHEN ”111” => y(7) <= ’0’;
BOÄ GIAÛI MAÕ END CASE;
38 END IF;
END PROCESS;
END behavior;
NguyenTrongLuat 47
encoder
i0
x0 BOÄ MAÕ HOÙA ÖU TIEÂN
i1
x1 E
i2 i3 i2 i1 i0 x1 x0 v N
v 0 0 0 0 d d 0 C
i3 0 0 0 1 0 0 1 O
0 0 1 X 0 1 1 D
0 1 X X 1 0 1 E
LIBRARY ieee;
1 X X X 1 1 1
USE ieee.std_logic_1164.all; R
ENTITY encoder IS
PORT ( i : IN STD_LOGIC_VECTOR(3 downto 0);
x : OUT STD_LOGIC_VECTOR(1 downto 0);
v : OUT STD_LOGIC);
END encoder;
ARCHITECTURE flow OF encoder IS
BEGIN WITH i SELECT
x <= ”11” WHEN i(3) = ’1’ ELSE x <=”00” WHEN ”0001” ,
”01” WHEN ”0010”|”0011”,
”10” WHEN i(2) = ’1’ ELSE ”10” WHEN ”0100”
”01” WHEN i(1) = ’1’ ELSE to ”0111”,
”00” ; ”11” WHEN OTHERS;
v <= ’0’ WHEN i = ”0000” WITH i SELECT
V <=’0’ WHEN ”0000”,
ELSE ’1’; ’1’ WHEN OTHERS;
END flow;
NguyenTrongLuat 49
LIBRARY ieee;
USE ieee.std_logic_1164.all; Söû duïng
ENTITY encoder2 IS
PORT ( i : IN STD_LOGIC_VECTOR(3 downto 0);
PROCESS
x : OUT STD_LOGIC_VECTOR(1 downto 0);
v : OUT STD_LOGIC);
END encoder2;
ARCHITECTURE behavior OF encoder2 IS
BEGIN PROCESS (i)
PROCESS (i) BEGIN
BEGIN x <= ”00”;
IF i(3) = ’1’ THEN x <= ”11”; IF i(1)=’1’ THEN x <=”01”;
ELSIF i(2) = ’1’THEN END IF;
x <= ”10”; IF i(2)=’1’ THEN x <=”10”;
ELSIF i(1) = ’1’THEN END IF;
x <= ”01”; IF i(3)=’1’ THEN x <=”11”;
ELSIF x <= ”00”; END IF;
END IF; v <= ’1’;
END PROCESS; IF i=”0000” THEN v <=’0’;
v <= ’0’ WHEN i = ”0000” END IF;
ELSE ’1’; END PROCESS;
END behavior;
NguyenTrongLuat 50
- Heä tuaàn töï chæ ñöôïc thöïc hieän baèng caùc phaùt bieåu tuaàn töï
(sequential statement).
- Thöïc hieän: maïch choát, FF, thanh ghi, boä ñeám, maùy traïng
thaùi.
- Bieán (Variable) chæ toàn taïi cuïc boä trong Process, vì vaäy muoán
laáy giaù trò cuûa bieán ra ngoaøi Process thì ta phaûi gaùn bieán cho
tín hieäu (Signal).
- Trong Process, bieán ñöôïc caäp nhaät giaù trò sau moãi phaùt bieåu;
coøn tín hieäu chæ ñöôïc caäp nhaät ôû cuoái Process.
NguyenTrongLuat 53
MAÏCH CHOÁT
Dlatch
LIBRARY ieee;
D Q USE ieee.std_logic_1164.all;
ENTITY Dlatch IS
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
Clk Q END Dlatch;
ARCHITECTURE behavior OF Dlatch IS
BEGIN
PROCESS (D, Clk)
clk D Q+ Q+ BEGIN
0 X Q Q IF Clk = ’1’ THEN
1 0 0 1 Q <= D;
1 1 1 0 Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
NguyenTrongLuat 54
LIBRARY ieee;
FLIP - FLOP
USE ieee.std_logic_1164.all; Dflipflop
ENTITY Dflipflop IS
PORT (D, Clk : IN STD_LOGIC; D Q
Q, Qn : OUT STD_LOGIC);
END Dflipflop;
ARCHITECTURE behavior OF Dflipflop IS
BEGIN clk Q
PROCESS (Clk)
BEGIN
IF Clk’event AND Clk = ’1’ THEN
Q <= D; IF rising_edge(clk) THEN
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
- clk’event phaùt hieän söï thay ñoåi tín hieäu clk töø 0 leân 1 hoaëc töø 1 veà 0.
- Goùi std_logic_1164 coù ñònh nghóa 2 haøm (function): rising_edge ñeå phaùt
hieän caïnh leân vaø falling_edge ñeå phaùt hieän caïnh xuoáng cuûa tín hieäu.
NguyenTrongLuat 55
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DFF IS
PORT (D, Clk, Pr, Cl : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
Pr END DFF;
ARCHITECTURE behavior OF DFF IS
D Q
BEGIN
DFF PROCESS (Clk, Pr, Cl)
BEGIN
Clk Q IF Pr = ’0’ THEN Q <= ’1’;
Cl Qn <= ’0’;
ELSIF Cl = ’0’ THEN Q <= ’0’;
Qn <= ’1’;
ELSIF Clk’event AND Clk = ’0’ THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
NguyenTrongLuat 56
LIBRARY ieee;
USE ieee.std_logic_1164.all
USE ieee.std_logic_unsigned.all;
ENTITY Upcnt4 IS
PORT ( Clk, Rst : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Upcnt4;
ARCHITECTURE Behavioral OF Upcnt4 IS
SIGNAL count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS (Clk, Rst)
Boä ñeám BEGIN
coù reset IF rising_edge(clk) THEN
ñoàng boä IF Rst ='1' THEN
count <= (others=>'0');
ELSE
count <= count + "0001";
END IF;
END IF;
END PROCESS; Söû duïng tín hieäu count thay cho bieán count.
Q <= count;
Tín hieäu count ñöôïc gaùn cho ngoõ ra Q beân
END Behavioral;
ngoaøi Process.
NguyenTrongLuat 59
LIBRARY ieee;
USE ieee.std_logic_1164.all BOÄ ÑEÁM LEÂN
USE ieee.std_logic_unsigned.all; THAÄP PHAÂN
ENTITY Upcnt10 IS
PORT ( Clk, Rst : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Upcnt10;
ARCHITECTURE Behavioral OF Upcnt10 IS
BEGIN
PROCESS (Clk, Rst)
VARIABLE count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
IF Rst ='1' THEN
count := (others=>'0');
ELSIF rising_edge(clk) THEN
IF count = "1001" then
count := (others=>'0');
ELSE count := count + "0001";
END IF;
END IF;
Q <= count;
END PROCESS;
END Behavioral;
NguyenTrongLuat 60
LIBRARY ieee;
USE ieee.std_logic_1164.all BOÄ ÑEÁM 4 bit
USE ieee.std_logic_unsigned.all; LEÂN / XUOÁNG
ENTITY Updncnt4 IS
PORT ( Clk, Rst, Updn: IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Updncnt4;
ARCHITECTURE Behavioral OF Updncnt4 IS
SIGNAL count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS (Clk, Rst)
BEGIN
IF Rst = ’1’ THEN
count <= (others =>’0’); Updn Q0
ELSIF rising_edge(Clk) THEN Q1
IF Updn = ’1’ THEN Rst Q2
count <= count + ”0001”;
Clk Q3
ELSE count <= count - ”0001”;
END IF; Updncnt4
END IF;
END PROCESS;
Q <= count;
END Behavioral;
NguyenTrongLuat 61
S
I
S siso
O LIBRARY ieee;
Serin
USE ieee.std_logic_1164.all;
ENTITY siso IS
GENERIC (n : NATURAL := 8); Serout
PORT (Clk, Serin : IN STD_LOGIC;
Serout : OUT STD_LOGIC); Clk
END siso;
ARCHITECTURE shiftreg OF siso IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
reg <= reg(n-2 downto 0) & Serin;
END IF;
END PROCESS;
Serout <= reg(n-1);
END shiftreg;
NguyenTrongLuat 63
piso
LIBRARY ieee; Clk
USE ieee.std_logic_1164.all; ShLd
ENTITY piso IS Serin
GENERIC (n: NATURAL := 8); n
PORT (Serin, Clk, ShLd : IN STD_LOGIC; D Serout
D : IN STD_LOGIC_VECTOR(n-1 downto 0);
Serout : OUT STD_LOGIC);
END piso;
ARCHITECTURE shiftreg OF piso IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
IF ShLd = ’0’ THEN
reg <= D;
ELSE reg <= reg(n-2 downto 0) & Serin; P
END IF; I
END PROCESS;
Serout <= reg(n-1);
S
END shiftreg; O
NguyenTrongLuat 64
- Maùy traïng thaùi höõu haïn ñöôïc thieát keá deã daøng baèng phaùt
bieåu PROCESS.
- Vieäc chuyeån traïng thaùi ñöôïc moâ taû trong Process vôùi danh
saùch caûm nhaän (sensitivity list) laø clock vaø tín hieäu reset baát
ñoàng boä.
- Ngoõ ra coù theå ñöôïc moâ taû baèng caùc phaùt bieåu ñoàng thôøi
(concurrenrt) naèm ngoaøi process.
- Coù 2 kieåu FSM: MOORE vaø MEALY
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Output Outputs
function
Present State Register: thanh ghi traïng thaùi hieän taïi löu giöõ 1
traïng thaùi hieän taïi, seõ chuyeån traïng thaùi khi coù xung clock.
Next state function: haøm traïng thaùi keá tieáp laø maïch toå hôïp phuï
thuoäc vaøo ngoõ vaøo vaø traïng thaùi hieän taïi
Output function: haøm ngoõ ra laø maïch toå hôïp phuï thuoäc vaøo traïng
thaùi hieän taïi
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- Process Haøm ngoõ ra coù theå thay theá baèng caùc phaùt bieåu
ñoàng thôøi (concurrent statement)
- Process 2 vaø 3 coù theå keát hôïp thaønh 1 Process.
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PROCESS(ps_state )
CASE ps_state IS
WHEN state_1 =>
output <= ’...’;
WHEN state_2 =>
output <= ’...’;
...
END CASE;
END PROCESS;
Coù theå thay theá process naøy baèng phaùt bieåu ñoàng thôøi
output <= ... ;
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S0 S0 S1 0
LIBRARY ieee;
USE iee.std_logic_1164.all; S1 S2 S1 0
ENTITY Moore_FSM IS S2 S0 S3 0
PORT ( S3 S2 S1 1
clock, rerset, x: IN std_logic;
z: OUT std_logic);
END Moore_FSM;
ARCHITECTURE behavior OF Moore_FSM IS
TYPE state IS (S0, S1, S2, S3);
SIGNAL pr_state, nx_state: state;
BEGIN
regst: PROCESS(clk, reset)
BEGIN
IF reset = ’1’ THEN pr_state <= S0;
ELSIF (clock = ’1’ and clock’event) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
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MEALY
FSM
FSM kieåu MEALY ñöôïc moâ taû baèng 2 PROCESS
Output Outputs
function
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LIBRARY ieee;
USE ieee.std_logic_1164.all; Dflipflop
ENTITY Dflipflop IS
PORT (D, Clk : IN STD_LOGIC; D Q
Q, Qn : OUT STD_LOGIC);
END Dflipflop;
ARCHITECTURE behavior OF Dflipflop IS
clk Q
BEGIN
PROCESS (Clk)
BEGIN
IF Clk’event AND Clk = ’1’ THEN
Q <= D;
Qn <= NOT Q;
END IF;
ARCHITECTURE behavior OF Dflipflop IS
END PROCESS;
BEGIN
END behavior;
PROCESS
BEGIN
WAIT UNTIL Clk’event AND Clk = ’1’;
Q <= D; Qn <= NOT Q;
END PROCESS;
END behavior;
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