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8 7 6 5 4 3 2 1

1
Schematic Page Description :
D D

01 -- Page Description 19 -- PCH 1/6 (DMI/FDI/VIDEO) 39 -- ADP AC IN & HDD12V


02 -- System Block Diagram 20 -- PCH 2/6(SATA/RTC/HDA/LPC) 41 -- V_AXG (ISL6314)
03 -- Power Map 21 -- PCH 3/6(PCIE/USB/CLK/NV) 42 -- DDR3 1.5V(TPS51116)
04 -- Power Sequence 1/2 22 -- PCH 4/6(GPIO/CPU) 43 -- CPU_VTT(ISL6314CRZ)
05 -- Power Sequence 2/2 23 -- PCH 5/6(POWER) 44 -- CPU_CORE (NCP5392)
06 -- Clock 24 -- PCH 6/6(GND) 45 --1.05V_PCH, 1.05V_ME,1.8V
07 -- SMBus Block Diagram 25 -- MXM 3.0 46 -- Discharge Circuit
C C

08 -- GPIO list 26 --AUDIO CODEC ALC269 47 -- CHANGE LIST1


09 -- CLOCK GENERATOR 27 --LINE OUT/CRT 48 -- CHANGE LIST2
10 -- MCP 1/7(CLK/CTRL/MISC) 28 --JMB380 (Card Reader/1394) 49 -- ANNOTATIONS
11 -- MCP 2/7(DDR3 CHANNEL A) 29 -- SATA HDD/ODD
12 -- MCP 3/7(DDR3 CHANNEL B) 30 --MINI PCIE(WLAN/TV/IR/BT)
13 -- MCP 4/7(PCIE/DMI) 31 --ON BOARD USB
14 -- MCP 5/7( VCCP) 32 --LCD PANEL/INVERTER
15 -- MCP 6/7(MISC/VCC) 33 --LAN(RTL8111DL)
B B

16 -- MCP 7/7(GND) 34 --LAN Transformer & RJ45


17 -- DDR3 CHA DIMM0 35 --FAN/D board/CCD/PS2
18 -- DDR3 CHB DIMM0 36 -- EC ITE 8512N/FLASH
37 -- XDP
38 -- SCREW HOLE

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
Page Description
Date: Tuesday, March 16, 2010 Sheet 1 of 49
8 7 6 5 4 3 2 1
5 4 3 2 1

Block Diagram :
D D

VRM 11.1 Channel A DDR3 DIMM


CPU Core Lynnfield/ SO-DIMM0 CLOCK Generator
NCP5392 Clarkdale Dual channel DDR3 CK505
800/1066/1333MHz 1.5V
Processor Channel B DDR3 DIMM 14.318MHz

SO-DIMM1
MXM CNN (Graphics) 64-bit/45nm Reset Circuit
Mobile PCI-E Module PCIE 2.0 x16(PEG) LGA1156
TYPE-A (314 pin) (37.5x37.5mm) LED Indicator
(95W) VTT_CPU
1.1V MAIN SW CNN
LVDS

LCD Panel CNN FDI PECI DMI


AUO/CHIMEI (*1) x4
(21'' 16:10)
C Converter From EC 25MHz C
Backlight control

ADPIN LCD Panel CNN


CNN AUO/CHIMEI LVDS Ibex Peak PCI-E x1 PCIE 3 GB LAN RJ45 CNN
System Power (21'' 16:10) (Non-MXM option) Realtek
ADPIN
VIN
PCH RTL8111DL
6 in 1
+5VPCU/+3VPCU
MAINON CARD READER CNN
12VCC SATA HDD(3.5") SATA 0 PCIE 5
SATA II QLLT1071
GFX_VR_EN V_AXG
DCIN/VIN (25x25mm) (JMICRO JMB385)
SUSON SATA ODD SATA 1
+1.5V_SUS
MAINON (3.5W)
CPU_VTT_1.1V PCIE 1 Mini PCIE1
VRON REAR USB x4 USB 0,1,8,11
+VCC_CORE USB 2.0 USB 5 WLAN CNN
USB 2.0
S5_PWRON +5V_S5 USB 2,3
SIDE USB x2
SUSD +5V_S5_USB
B
+5VPCU USB Dongle x1 USB 9
PCIE 2 Mini PCIE2 B
MAIND +5V
USB 12 TV Tuner CARD CNN
S5_PWRON +3V_S5 USB 4
CAREMA with
MIC RTC
+3VPCU MAIND +3V Battery
BLUE TOOTH USB 10 Annt.
MAINON +1.8V 8Mb SPI
+5V_S5 32.768KHz SPI Ignition
LPC FW
MAINON +1.05V
+1.5V_SUS
AUDIO CODEC EC/KBC
ALC269Q Azailia 32.768KHz
INT SPK AMP. LQFP48 ITE8512
CNN(2Wx2) LQFP128

INT MIC Head MIC Line


On WCM Phone IN Out FAN CTRL 2Mb SPI IR IR
A
(CPU/ BIOS RECEIVER Blaster A

System) ROM

Quanta Computer Inc.


PROJECT : ZN2
(*1)FDI - Used only for the Clarkdale processor. Size Document Number Rev
A
Block Diagram
Date: Tuesday, March 16, 2010 Sheet 2 of 49
5 4 3 2 1
5 4 3 2 1

Power Rail Destination Voltage S0 Current


VIN 3
+12V
+VCC_CORE Lynnfield : 0.65V~1.4V MAINON
90A(TDC)
Default for initial power up 1.1V

for 92W TDP SKU 10A (TDC)


0.5~1.3V
V_AXG for 79W TDP SKU 16A (TDC) Adaptor NCP1587

D
+1.1V_VTT Lynnfield : Memory controller 1.045V~1.1V~1.155V 30A(TDC) S5_Power_ON D

& shared cache


Ibex Peak : DMI 1.1V 0.065A
Ibex Peak : CPU_IO 1.05V~1.1V~1.16V 0.001A MOS

G
+5V_S5
Lynnfield : Internal processor PLL 1.71V~1.8V~1.89V 1.1A

S
+1.8V
Ibex Peak : Internal PLL & VRMs 1.71V~1.8V~1.89V 0.196A
Ibex Peak : Dual channel NAND I/F 1.71V~1.8V~1.89V 0.156A
+1.5V_SUS Lynnfield : CPU I/O Voltage for DDRIII 1.425V~1.5V~1.575V 6A MAINON
DIMM : +5VPCU

SMDDR_VTERM DDRIII Terminator: 0.75V 2A MOS +5V

G
D

S
+1.05V Ibex Peak : VccCore 0.998V~1.05V~1.1V 1.629A
Ibex Peak : Vcc core I/O buffer 0.998V~1.05V~1.1V 3.251A
Ibex Peak : DMI buffer voltage 0.998V~1.05V~1.1V 0.065A
Ibex Peak : Display PLL A power 0.998V~1.05V~1.1V 0.075A
Ibex Peak : Display PLL B power 0.998V~1.05V~1.1V 0.075A NCP1587
S5_Power_ON

+1.5V Mini PCIE : +1.5V(WLAN)

MOS

G
C +3V_S5 C

S
+3V
Ibex Peak : I/O buffer voltage 3.14V~3.3V~3.47V 0.357A MAINON +3V
Ibex Peak : Display DAC Analog power 3.14V~3.3V~3.47V 0.069A
CH7308 : LVDD
+3VPCU
ALC662 : DVDD
MOS LDO

G
Mini PCIE : +3.3V(WLAN) D +1.8V
G
CAREMA

S
OP
S

+1.5V_SUS
MAINON SUSON MAINON +1.5V
Ibex Peak : Core well Ref. voltage 4.75V~5V~5.25V 0.001A
SATA ODD
SATA HDD(2.5'' x SSD)
ALC662S : AVDD
LDO +1.05V

G
G D
Touch Screen TPS51116RGE OP

S
+5V LCD Panel S
USB: x 12 ports 5V 6A
B SMDDR_VTERM B

MXM_12V
HDD_12V

Ibex Peak : Intel Management Engine 3.14V~3.3V~3.47V 0.086A


+3V_S5 +1.1V_VTT
Ibex Peak : Suspend well I/O Buffer 3.14V~3.3V~3.47V 0.168A
Ibex Peak : HD Audio controller 3.14V~3.3V~3.47V 0.006A NCP1589A
Suspend Voltage
LAN 82578DM : VDD
CLK Gen.CK505 : VDD
EC(IT8512) : VSTBY MAINON +12V power up

SPI FLASH ROM

+5V_S5 Ibex Peak : Suspend well Ref. Voltage 4.75V~5V~5.25V 0.001A


V_AXG
NCP5380
INVERTER : Vin
FAN_CPU

A GFX_VR_EN A
+3VPCU

+VCC_CORE
+5VPCU NCP5392TMNR2G

15VPCU

Quanta Computer Inc.


VIN VRON
PROJECT : ZN2
Size Document Number Rev
A
Power Map
Date: Tuesday, March 16, 2010 Sheet 3 of 49
5 4 3 2 1
5 4 3 2 1

5 4
Power Sequence S5_Power_ON

DC Jack
6
DVDD12/EVDD12
+3V_S5 MOS

G
6
+1.1V_VTT USB Port LAN
CPU VIN

DDR3
12

D
+1.5V_SUS RTL811DL 3
CPU_VTT_PG 3
+3VPCU
Clarkdale MAINON
D 6 11 D

+3V_S5
Lynnfield

+5V_S5
SMDDR_VTERM
LDO 12
D +3V
12

D
+1.8V OP
G MOS

G
S

RTC MAINON
11
H_PWRGOOD
MEM_PWRGD
RTC_RST#

3.3V Leavel NCP1587


S5_Power_ON
+VCCRTC

shift to 1.1V 5

other PCI/PCIe device 6

+5V_S5 MOS

G
1 2
+1.5V_SUS_PG

D
+3V_S5 3
HWPG
6 3V&5V_PCU_PG
15
PROCPWRGD

logical AND of the PCH’s PWROK and SYS_PWROK


+5V_S5 +1.1V_VTT_PG +5VPCU
6 AND
+1.05V_PG
+3V
CPU_VTT_PG 3.3V Leavel 11
12 V_AXG_PG
15 Control VR delay for meet chipset spec 12
+5V

D
+5V
shift to 1.1V
12 MOS

G
AND

C C

+1.05V
PCH 12
MAINON
+1.8V 11
SYS_PWROK

12 PROCPWRGD
15
MEPWROK

PWROK_EC
PWROK

+1.1V_VTT
12 SYS_PWROK
MAINON MAINON
AND 11 11
VR_READY
6
ICH_SUSCLK

12
LDO MOS +1.5V_SUS

G
D
+1.05V 12 TPS51116RGE
OP +1.5V

S
G
SYS_PWROK be used on the platform to indicate that the processor VR power is

S
good and therefore it can be connected to the same source as PWROK on PCH.

VR_READY
CLOCK Gen EN
6
SYS_PWROK

SMDDR_VTERM
ICH_PWBTN#
For platform not supporting Intel AMT it can be

ICH_RSMRST#

MAINON 11
SUSB#

SUSC#

+12V
connected to PWROK.

B
NCP1587 B
10 9 8 7

MAINON 11
4
ITE
PWRBTSW#
ITE8512
+1.1V_VTT
NCP1589A
EC
S5_Power_ON

GFX_VR_EN 13
+VCCRTC
+3V_S5
MAINON

+3VPCU
HWPG

+3V

IronLake will drive Gfx_VR_EN when VTT ramps


VRON

VRON

14
V_AXG NCP5380
12

3 1
15

16 16 11 5
VRON 16

A
17 A

+VCC_CORE
Control signal NCP5392TMNR2G
RTC Power

PCU Power
VR_READY
S5 Power

S0 Power Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
Power Sequence 1/2
Date: Tuesday, March 16, 2010 Sheet 4 of 49
5 4 3 2 1
5 4 3 2 1

5
POWER SEQUENCE

9ms,min
+VCCRTC

D Voltage Rails D
RTC_RST#
Power Voltage S0 S3 S4 S5 PCU G3 Ctl Signal
+VCCRTC 3V ON ON ON ON ON ON
VIN 19.5V ON ON ON ON ON OFF Adaptor in
VIN/+5VPCU/+3VPCU
+5VPCU 5V ON ON ON ON ON OFF Adaptor in
Minimum duration of PWRBTN# assertion = 16ms
+3VPCU 3.3V ON ON ON ON ON OFF Adaptor in EC

+5V_S5 5V ON ON ON ON OFF OFF S5_PWRON PCH SUS, NBSWON#


+3V_S5 3.3V ON ON ON ON OFF OFF S5_PWRON Sys Management, PCH Resume Well, Intel HD Audio, USB, WLAN,

+1.5V_SUS 1.5V ON ON OFF OFF OFF OFF SUSON DDR3 Memory


S5_PWRON
SMDDR_VTERM 0.75V ON OFF OFF OFF OFF OFF SUSON DDR3 Memory

+12V 12V ON OFF OFF OFF OFF OFF MAINON

+5V
+3V_S5/+5V_S5
5V ON OFF OFF OFF OFF OFF MAINON SATA, PCI REF
10ms,min
+3V 3.3V ON OFF OFF OFF OFF OFF MAINON PCI Express*, SATA, HV CMOS,CRT, Band Gap voltages, Intel HD Audio
20ns,min
+1.5V 1.5V ON OFF OFF OFF OFF OFF MAINON mini PCIe, Intel HD Audio ICH_RSMRST#
see PCH EDS P.380
+1.05V 1.05V ON OFF OFF OFF OFF OFF MAINON PCH core, PCH PLL voltages, PCH CLK Buffer, SATA, USB, PCH fuse,Display Link, Display Port, PCIe

+1.8V 1.8V ON OFF OFF OFF OFF OFF MAINON LVDSIO, SFR, FLASH
ICH_SUSCLK 100ms,min
Clock

OFF
+1.1V_VTT 1.1V / 1.05V ON OFF OFF OFF OFF MAINON CPU VTT, FDI,PEG, DMI, VCCTTADDR, PCH DMI,PCH V_CPU_IO

V_AXG ???V ON OFF OFF OFF OFF OFF GFX_VR_EN mini PCIe, Intel HD Audio
ICH_PWRBTN# 16ms,min
+VCC_CORE ???V ON OFF OFF OFF OFF OFF VRON CPU Core

C SUSC# (S4) 30us,min C

Power Voltage S0 S3 S4 S5 PCU G3 SUSB# (S3)


VIN_MXM

+5V_MXM SUSON
+3V_MXM

USBVCC2 +1.5V_SUS/SMDDR_VTERM
3VPCU_EC

LCDVCC
MAINON
CCD_PWR

VIN_LCD
+1.5V/+3V/+1.8V/+5V
VDDA_CODEC

+1.1V_VTT/+1.05V/V_AXG

+12V
VTT stable to VTTPWRGOOD = 0.0001ms~500ms

CPU_VTT_PG

HWPG
IronLake will drive Gfx_VR_EN when VTT ramps

GFX_VR_EN
B B

V_AXG

99ms,min
VRON

+VCC_CORE

VR_READY/SYS_PWROK

CK_PWRGD_R

CLK_BUF_BCLK (CK505 Clock)


Clock

PWROK_EC 3ms~20ms
And logic (VR_READY&PWROK_EC)
1ms,min
PCHPWROK/MEPWROK 99ms,min
VDDQ must be stable for >= 100ns before DRAM_PWROK assertion

1ms,min
MEM_PWRGD

100ms,min
H_PWRGOOD

A 1ms,min A
SUS_STAT#

60us,min
PLTRST#

500us,min
SPI data

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
Power Sequence 2/2
Date: Tuesday, March 16, 2010 Sheet 5 of 49
5 4 3 2 1
5 4 3 2 1

CPU
D
Clarkdale D

Lynnfield

CLKOUT_DP [120MHz] (reserved)


CLK_CPU_BCLK [133MHz]

CLK_PCIE_DMI [100MHz]
C C

MXM card CLK_PCIE_VGAN [100MHz]


CLK_BUF_DREFCLK [96MHz]

CLK_BUF_PCIE_3GPLL [100MHz]

TV card CLK_PCH_SRC1[100MHz]

Clock
WLAN card CLK_PCH_SRC3 [100MHz]

PCH CLK_BUF_DREFSSCLK [100MHz]

CLK_PCH_SRC2 [100MHz]
Gen.
CLK_BUF_BCLK [133MHz]
CLK_PCIE_LOM [100MHz]

CLK_PCI_775 [33MHz]
CLK_ICH_14M [14.318MHz]

B B

Card LAN EC
reader 8111DL ITE8512
JMB380
Crystal
14.318MHz

Crystal
32.768KHz
Crystal
32.768KHz
Ex X'tal
Crystal
24.576MHz
Crystal
25MHz
Crystal
32.768KHz
Ex X'tal Ex X'tal
(RTC) (reserved)

Ex X'tal Ex X'tal Ex X'tal

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
Clock
Date: Tuesday, March 16, 2010 Sheet 6 of 49
5 4 3 2 1
5 4 3 2 1

7
SMBCLK/SMBDAT
Clock

D DDR CHA SO-DIMM DDR CHB SO-DIMM D

Mini PCIe Slot Mini PCIe Slot

PCH
XPD
C C

EDID EEPRom

B
SML0CLK/SML0DAT SMBCLK1
MXM B

LPC EC
SMBCLK0 SMBCLK2 External Thermal IC

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
SMBus Block Diagram
Date: Tuesday, March 16, 2010 Sheet 7 of 49
5 4 3 2 1
5 4 3 2 1

8
NAME GPIO/PIN I/O DESCRIPTION ACTIVE NAME GPIO/PIN I/O DESCRIPTION ACTIVE

I INITAL : HIGH / ACTIVE : LOW I

B B
D D

I I
I I

O O

O O

I I

O O

O O

O O

O O

C I I C

O O

O O

O O

O O

I I

I I

I I

I I

I I
B B

I I

I I

I I

O O

O O

O O

I I

I I

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
GPIO List
Date: Tuesday, March 16, 2010 Sheet 8 of 49
5 4 3 2 1
5 4 3 2 1

9
1.05V to 3.3V from external power supply
Clock Generator L35 *BKP1608HS181T_6_1.5A +3V
80mA(20mil)
+VDDIO_CLK L34 BKP1608HS181T_6_1.5A +1.05V
C428 C421 C413 C424

+3V U16 0.1U/16V_4 0.1U/16V_4 10U/10V/Y5V_8


10U/10V/Y5V_8
180ohm/1.5A 150mA(20mil)
D BKP1608HS181T_6_1.5A +3V_CLK 1 Place each 0.1uF cap as close as C308 may be can save D
L31 VDD_DOT
5 VDD_27 VDD_SRC_I/O 15 possible to each VDD IO pin. Place
C405 C418 C138 C128 C129 C145 C146 17 18 the 10uF caps on the VDD_IO plane.
VDD_SRC VDD_CPU_I/O
24 VDD_CPU
4.7U/10V_8 4.7U/10V_8 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 29 3 CLK_BUF_DREFCLKP_R RP16 1 2 0X2 CLK_BUF_DREFCLKP 21
VDD_REF DOT_96 CLK_BUF_DREFCLKN_R
DOT_96# 4 3 4 CLK_BUF_DREFCLKN 21
CLK_SDATA 31
CLK_SCLK SDA
32 SCL 27M 6 TP49
27M_SS 7 TP50

21 CLK_ICH_14M CLK_ICH_14M R385 33_J_4 CPU_SEL 30 10 CLK_BUF_PCIE_3GPLLP_R RP13 1 2 0X2 CLK_BUF_PCIE_3GPLLP 21


REF_0/CPU_SEL SRC_1/SATA CLK_BUF_PCIE_3GPLLN_R
SRC_1#/SATA# 11 3 4 CLK_BUF_PCIE_3GPLLN 21
C431 33P/50V_4 13 CLK_BUF_DREFSSCLKP_R RP12 1 2 0X2 CLK_BUF_DREFSSCLKP 21
SRC_2 CLK_BUF_DREFSSCLKN_R
SRC_2# 14 3 4 CLK_BUF_DREFSSCLKN 21

1
XTAL_IN 28
Y3 XTAL_IN +3V
14.318MHZ XTAL_OUT 27 16 R104 10K_J_4
XTAL_OUT *CPU_STOP#

2
C427 33P/50V_4 2 20
VSS_DOT CPU_1 TP47
8 VSS_27 CPU_1# 19 TP48
9 23 CLK_BUF_BCLKP_R RP11 1 2 0X2 CLK_BUF_BCLKP 21
VSS_SATA CPU_0 CLK_BUF_BCLKN_R
12 VSS_SRC CPU_0# 22 3 4 CLK_BUF_BCLKN 21
C CLK_ICH_14M C
21 VSS_CPU
26 25 CK_PWRGD_R
C437 VSS_REF CKPWRGD/PD#
33 GND

*10P/50V_4 9LRS3197

B +3V +3V B
SMBus CLK Enable
CPU_CLK select +1.05V R367
+3V R400

2.2K_J_4
R392 R399 2 10K_J_4

3 1 CLK_SDATA
21 ICH_SMBDATA CLK_SDATA 17,18,30,32,37
*10K_J_4 *10K_J_4 R373 CK_PWRGD_R
19,44 VR_READY
Q18
CPU_SEL 2N7002K 0_J_4

R390 C436 R370 C410


+3V *10K_J_4

*10P/50V_4 0.22u/10V/X5R_4
10K_J_4
R401

2.2K_J_4
2

A A
0 1
3 1 CLK_SCLK
21 ICH_SMBCLK CLK_SCLK 17,18,30,32,37
Quanta Computer Inc.
CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q19
2N7002K
(default) PROJECT :ZN2
Size Document Number Rev
A
Clock Generator
Date: Tuesday, March 16, 2010 Sheet 9 of 49
5 4 3 2 1
5 4 3 2 1

CN3E
GFX_VR_EN R126 *0_J_4 dGPU_PRSNT# 22,25,36 10
+1.1V_VTT
21 DPCLK_PCH AA8 BCLK_DP1 BCLK_ITP_DP AK39
XDP_CPU_BCLK_P 37
120MHz DP REFCLK 21 DPCLK_PCH# Y8 BCLK_DN1 BCLK_ITP_DN AK40 XDP_CPU_BCLK_N 37
AA7 R327
22 CLK_CPU_BCLKP BCLK_DP0
133MHz CPU BCLK AA6 U33 H_VID7
22 CLK_CPU_BCLKN BCLK_DN0 VID7 H_VID7 44
U34 H_VID6
H_CPURST_N VID6 H_VID5 H_VID6 44
AF34 RSTIN_N VID_5_CSC2 U35
R287 0_J_4 VCCPW RGOOD1 H_VID4 H_VID5 44
22 H_PW RGOOD AH36 VCCPWRGOOD1 VID_4_CSC1 U36 H_VID4 44 NU_for LFD CPU.
R280 0_J_4 VCCPW RGOOD0 AH35 U37 H_VID3
D VCCPWRGOOD0 VID_3_CSC0 H_VID3 44 D
AG37 U38 H_VID2 +1.1V_VTT 8.2K_J_4
36,43 CPU_VTT_PG VTTPWRGOOD VID2_MSID2 H_VID2 44
AH37 U39 H_VID1 GFX_VR_EN
19 MEM_PW RGD SM_DRAMPWROK VID1_MSID1 H_VID1 44
U40 H_VID0
VID0_MSID0 H_VID0 44
22,36 H_PECI AG35 PECI
GFX_VR_EN F12 GFX_EN 1K_F_6 R325 GFX_VR_EN
GFX_VR_EN 41
AG38 PSI_N GFX_VID6 J11 G_VID7 41
44 VCCP_PSI_N

*4.7K_J_4
H_CATERR_N AG39 G11 R7
CATERR_N GFX_VID5 G_VID6 41
H_PROCHOT_N AH34 C12
PROCHOT_N GFX_VID4 G_VID5 41
H_THERMTRIP_N AF35 E11
THERMTRIP_N GFX_VID3 G_VID4 41
19 PM_SYNC AH39 PM_SYNC GFX_VID2 E12 G_VID3 41

3
+1.1V_VTT 10K_F_4 R339 B12 Q1
GFX_VID1 G_VID2 41
R340 *0_J_4 PM_EXT_TS#1 AB4 G10 2
18 PM_EXTTS#1 PM_EXT_TS_N1 GFX_VID0 G_VID1 41
R337 *0_J_4 PM_EXT_TS#0 AB5 F6 GFX_IMON R336 0_F_6
17 PM_EXTTS#0 PM_EXT_TS_N0 GFX_IMON
+1.1V_VTT 10K_F_4 R338 near the processor socket.(NU_for LFD CPU.) *TR NPN MMBT3904 40V 0.2A

1
R15 20_F_4 H_COMP3 C11 T35
R13 20_F_4 H_COMP2 B11 COMP3 VCC_SENSE VCC_SENSE 44
COMP2 VSS_SENSE T34
R29 49.9_F_4 H_COMP1 AF2 VSS_SENSE 44
R289 49.9_F_4 H_COMP0 AF36 COMP1 TP_MCP_FC_AG40
COMP0 FC_AG40 AG40 1 TP2
AF39 VTT_SELECT R6
R28 130_F_4 SM_RCOMP2AE1 VTT_SELECT TP_MCP_FC_AE38 *0_J_4 VTT_SELECT_VID3 43
SM_RCOMP2 FC_AE38 AE38 1 TP3
R27 24.9_F_4 SM_RCOMP1AD1 AE35
R31 100_F_4 SM_RCOMP0 SM_RCOMP1 VTT_SENSE VSENSE_DIE_CPU0_VTT_P 43
AG1 SM_RCOMP0 VSS_SENSE_VTT AE36 VSENSE_DIE_CPU0_VTT_N 43
A13 VCCGT_SENSE_P +1.1V_VTT
CPU_TMS VAXG_SENSE VCCGT_SENSE_N VCCGT_SENSE_P 41
37 CPU_TMS AN40 TMS VSSAXG_SENSE B13 VCCGT_SENSE_N 41
CPU_TCK0 AN37
37 CPU_TCK0 CPU_TDI TCK CPU_TDO
37 CPU_TDI AM37 TDI TDO AM38
CPU_TDO 37

R295
TDI_TDO_M AF37 AF38 TDI_TDO_M
CPU_TRST_N TDI_M TDO_M
37 CPU_TRST_N AM39 TRST_N
T40 ISENSE
C ISENSE H_ISENSE 44 C
L11 CFG17 VSS_280 T39
H7 CFG16

51_F_4
*1.5K_F_4 R326 XDP_CPU_CFG15K12 AK38
CFG15 SKTOCC_N
K9 CFG14
R9 *51_F_4 PM_SYNC L8 AK37
CFG13 PREQ_N XDP_CPU_PREQ_N 37
J12 AJ38 XDP_CPU_PRDY_N
CFG12 PRDY_N XDP_CPU_DBR_N XDP_CPU_PRDY_N 37
A02 K8 CFG11 DBR_N AL40 SYS_RST_N 19,37
R288 *49.9_F_4 H_PECI K10 AK34 XDP_CPU_PRDY_N
CFG10 TAPPWRGOOD XDP_CPU_PW RGD 37
H12 CFG9 CPU_RESETOBS_N AL39
R284 49.9_F_4 H_PROCHOT_N CPU_RESET_OUT_N 37
+1.1V_VTT G12 CFG8
*1.5K_F_4 R333 XDP_CPU_CFG7 F9 AK31
R290 51_F_4 H_THERMTRIP_N *1.5K_F_4 R332 XDP_CPU_CFG6 E9 CFG7 BPM_N7
CFG6 BPM_N6 AK30
*1.5K_F_4 R331 XDP_CPU_CFG5 H9 AL30 +1.1V_VTT +1.1V_VTT
R8 49.9_F_4 H_CATERR_N *1.5K_F_4 R328 XDP_CPU_CFG4 H10 CFG5 BPM_N5
CFG4 BPM_N4 AM31
*1.5K_F_4 R330 XDP_CPU_CFG3 F10 AK32
R10 *51_F_4 CPU_RESET_OUT_N *1.5K_F_4 R329 XDP_CPU_CFG2 E10 CFG3 BPM_N3
CFG2 BPM_N2 AK33
*1.5K_F_4 R335 XDP_CPU_CFG1 G8 AL32
CFG1 BPM_N1

3
R281 *49.9_F_4 H_PW RGOOD *1.5K_F_4 R334 XDP_CPU_CFG0 E8 AL33
CFG0 BPM_N0
A02
5/10
CN CPU SOCKET SMD LGA1156 2 Q13 R296 D34
T17
*FDV301N *10K_J_4 *BAS316

1
VID[7:0] : 00101110 =>1.325V@VCC,Max
2009B FMB processors supported +1.1V_VTT
C296
B +1.1V_VTT *1U/16V_6 B

CFG H L Notes 0 1 1 1 0 1 0 0 Thermal Trip R292


Q14
0 H:1x16, L:2x8

2
*62_J_4 *MMBT3904
R273 R272 R274 R275 R276 R277 R278 R279
1 RSVD H_THERMTRIP_N 1 3 SYS_SHDN#
SYS_SHDN# 40
2 RSVD
3 NORM RSVD LANE REVERSAL
*1K_F_4

*1K_F_4

*1K_F_4

*1K_F_4
R293 *0_J_4 PCH_THERMTRIP#
PCH_THERMTRIP# 22
1K_F_4

1K_F_4

1K_F_4

1K_F_4

4 DISABLE ENABLE DP PRESENCE


CAD NOTE:
5 RSVD PLACE TDO TERMINATION NEAR XDP CONNECTOR
6 RSVD PLACE TCK/TDI/TMS END TERMINATION NEAR CPU
H_VID0 +1.1V_VTT
CFG 0-6 all internal PULL-UP H_VID1
H_VID2
H_VID3 R286
H_VID4
H_VID5 H_PROCHOT_N
H_VID6
H_VID7 *2.21K_F_4
Need to be placed close to processor

3
Q12
to minimize ESD risk R298 R297 R299 R300 R301 R302 R303 R304 VR_HOT R285 2
44 VR_HOT
A A
100_J_4 TR NPN MMBT3904 40V 0.2A

1
R282 1K_F_4
21,22,28,30,33 PLTRST# XDP_PFRST_N 37
*1K_F_4

*1K_F_4

*1K_F_4

*1K_F_4

1K_F_4

1K_F_4
1K_F_4

1K_F_4

R291 1.3K_F_4 H_CPURST_N 1.1V level

R283 C304 Quanta Computer Inc.


A02 - 0.1U/16V/X7R_4
PROJECT : ZN2
PDG1.5 change 665 _F_4 Size Document Number Rev
A
MCP (CLK/CTRL/MISC)
Date: Tuesday, March 16, 2010 Sheet 10 of 49
5 4 3 2 1
5 4 3 2 1

11
17 M_A_DQ[63:0]
M_A_A[15:0] 17
CN3A
M_A_DQ63 AP40 AR10 M_A_A15
D SA_DQ63 SA_MA15 D
M_A_DQ62 AP39 AT11 M_A_A14
M_A_DQ61 SA_DQ62 SA_MA14 M_A_A13
AU39 SA_DQ61 SA_MA13 AU24
M_A_DQ60 AU38 AW11 M_A_A12
M_A_DQ59 SA_DQ60 SA_MA12 M_A_A11
AN39 SA_DQ59 SA_MA11 AU13
M_A_DQ58 AN38 AT19 M_A_A10
M_A_DQ57 SA_DQ58 SA_MA10 M_A_A9
AT40 SA_DQ57 SA_MA9 AW12
M_A_DQ56 AT39 AU14 M_A_A8
M_A_DQ55 SA_DQ56 SA_MA8 M_A_A7
AW37 SA_DQ55 SA_MA7 AW13
M_A_DQ54 AV36 AV14 M_A_A6
M_A_DQ53 SA_DQ54 SA_MA6 M_A_A5
AW34 SA_DQ53 SA_MA5 AY13
M_A_DQ52 AY34 AW14 M_A_A4
M_A_DQ51 SA_DQ52 SA_MA4 M_A_A3
AU37 SA_DQ51 SA_MA3 AU15
M_A_DQ50 AV37 AV15 M_A_A2
M_A_DQ49 SA_DQ50 SA_MA2 M_A_A1
AY35 SA_DQ49 SA_MA1 AY15
M_A_DQ48 AW35 AW18 M_A_A0
M_A_DQ47 SA_DQ48 SA_MA0
AW33 SA_DQ47
M_A_DQ46 AU33 AU12 M_BA_A2 M_BA_A2 17
M_A_DQ45 SA_DQ46 SA_BS2 M_BA_A1
AW30 SA_DQ45 SA_BS1 AU19 M_BA_A1 17
M_A_DQ44 AV30 AV20 M_BA_A0 M_BA_A0 17
M_A_DQ43 SA_DQ44 SA_BS0
AU34 SA_DQ43
M_A_DQ42 AV33 AT20 M_A_RAS# M_A_RAS# 17
M_A_DQ41 SA_DQ42 SA_RAS_N M_A_CAS#
AU31 SA_DQ41 SA_CAS_N AU22 M_A_CAS# 17
M_A_DQ40 AU30 AT22 M_A_W E# M_A_W E# 17
M_A_DQ39 SA_DQ40 SA_WE_N
AN30 SA_DQ39
M_A_DQ38 AR29 AK23 1 TP39
M_A_DQ37 SA_DQ38 SA_CS_N7 TP38
AR27 SA_DQ37 SA_CS_N6 AL23 1
M_A_DQ36 AN26 AM22 1 TP41
M_A_DQ35 SA_DQ36 SA_CS_N5 TP42
AP30 SA_DQ35 SA_CS_N4 AK22 1
M_A_DQ34 AP28 AU23 1 TP37
C M_A_DQ33 SA_DQ34 SA_CS_N3 TP6 C
AT28 SA_DQ33 SA_CS_N2 AU21 1
M_A_DQ32 AN27 AW24 M_CS#_A1 M_CS#_A1 17
M_A_DQ31 SA_DQ32 SA_CS_N1 M_CS#_A0
AW7 SA_DQ31 SA_CS_N0 AV21 M_CS#_A0 17
M_A_DQ30 AV7
M_A_DQ29 SA_DQ30
AV5 SA_DQ29 SA_ODT3 AY24
M_A_DQ28 AU5 AW23
M_A_DQ27 SA_DQ28 SA_ODT2
AY8 SA_DQ27 SA_ODT1 AV24 M_ODT_A1 M_ODT_A1 17
M_A_DQ26 AU8 AV23 M_ODT_A0 M_ODT_A0 17
M_A_DQ25 SA_DQ26 SA_ODT0
AY5 SA_DQ25
M_A_DQ24 AW5 AY10 1 TP7
M_A_DQ23 SA_DQ24 SA_CKE3
AV4 SA_DQ23 SA_CKE2 AV10 1 TP44
M_A_DQ22 AV2 AW10 M_CKE_A1 M_CKE_A1 17
M_A_DQ21 SA_DQ22 SA_CKE1
AT1 SA_DQ21 SA_CKE0 AU10 M_CKE_A0 M_CKE_A0 17
M_A_DQ20 AT3
M_A_DQ19 SA_DQ20
AW4 SA_DQ19 SA_CKP3 AP19
M_A_DQ18 AW3 AN19
M_A_DQ17 SA_DQ18 SA_CKN3
AU2 SA_DQ17 SA_CKP2 AN21
M_A_DQ16 AT4 AP21
M_A_DQ15 SA_DQ16 SA_CKN2 M_CLK_DDR_A1
AR4 SA_DQ15 SA_CKP1 AP18 M_CLK_DDR_A1 17
M_A_DQ14 AP1 AN18 M_CLK_DDR#_A1 M_CLK_DDR#_A1 17
M_A_DQ13 SA_DQ14 SA_CKN1 M_CLK_DDR_A0
AM2 SA_DQ13 SA_CKP0 AR22 M_CLK_DDR_A0 17
M_A_DQ12 AM3 AR21 M_CLK_DDR#_A0 M_CLK_DDR#_A0 17
M_A_DQ11 SA_DQ12 SA_CKN0
AR2 SA_DQ11
M_A_DQ10 AR3
M_A_DQ9 SA_DQ10
AN2 SA_DQ9
M_A_DQ8 AN3 AL10
M_A_DQ7 SA_DQ8 SA_DQSP8
AK2 SA_DQ7 SA_DQSN8 AM10
M_A_DQ6 AK1 AR39 M_A_DQS7
SA_DQ6 SA_DQSP7 M_A_DQS7 17
M_A_DQ5 AH2 AR38 M_A_DQS#7
SA_DQ5 SA_DQSN7 M_A_DQS#7 17
B M_A_DQ4 AG2 AW36 M_A_DQS6 B
SA_DQ4 SA_DQSP6 M_A_DQS6 17
M_A_DQ3 AL1 AV35 M_A_DQS#6
SA_DQ3 SA_DQSN6 M_A_DQS#6 17
M_A_DQ2 AL2 AV32 M_A_DQS5
SA_DQ2 SA_DQSP5 M_A_DQS5 17
M_A_DQ1 AJ4 AW32 M_A_DQS#5
SA_DQ1 SA_DQSN5 M_A_DQS#5 17
17 M_DM_A[7:0] M_A_DQ0 AH1 AR28 M_A_DQS4
SA_DQ0 SA_DQSP4 M_A_DQS4 17
AT29 M_A_DQS#4
SA_DQSN4 M_A_DQS#4 17
M_DM_A7 AT38 AY6 M_A_DQS3
SA_DM7 SA_DQSP3 M_A_DQS3 17
M_DM_A6 AU35 AW6 M_A_DQS#3
SA_DM6 SA_DQSN3 M_A_DQS#3 17
M_DM_A5 AW31 AU4 M_A_DQS2
SA_DM5 SA_DQSP2 M_A_DQS2 17
M_DM_A4 AN29 AU3 M_A_DQS#2
SA_DM4 SA_DQSN2 M_A_DQS#2 17
M_DM_A3 AV6 AP2 M_A_DQS1
SA_DM3 SA_DQSP1 M_A_DQS1 17
M_DM_A2 AU1 AP3 M_A_DQS#1
SA_DM2 SA_DQSN1 M_A_DQS#1 17
M_DM_A1 AN1 AK3 M_A_DQS0
SA_DM1 SA_DQSP0 M_A_DQS0 17
M_DM_A0 AJ2 AJ3 M_A_DQS#0
SA_DM0 SA_DQSN0 M_A_DQS#0 17
AM11 SA_ECC_CB7 SM_DRAMRST# AV8 DDR3_DRAMRST# 17,18
AK11 SA_ECC_CB6
AL9 SA_ECC_CB5
AK9 SA_ECC_CB4
AP11 SA_ECC_CB3 1/10
AR11 SA_ECC_CB2 R26
AN10 SA_ECC_CB1
AP10 SA_ECC_CB0 SA_DIMM_VREF AF3 DIMM_VREFA VREF_DQ_DDRA 17
0_J_4
CN CPU SOCKET SMD LGA1156 A02

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
MCP (DDR3 CHANNEL A)
Date: Tuesday, March 16, 2010 Sheet 11 of 49
5 4 3 2 1
5 4 3 2 1

12

D 18 M_B_DQ[63:0] D
M_B_A[15:0] 18
CN3B
M_B_DQ63 AL36 AV11 M_B_A15
M_B_DQ62 SB_DQ63 SB_MA15 M_B_A14
AJ35 SB_DQ62 SB_MA14 AY12
M_B_DQ61 AM34 AW28 M_B_A13
M_B_DQ60 SB_DQ61 SB_MA13 M_B_A12
AN35 SB_DQ60 SB_MA12 AW15
M_B_DQ59 AJ37 AW16 M_B_A11
M_B_DQ58 SB_DQ59 SB_MA11 M_B_A10
AJ36 SB_DQ58 SB_MA10 AY25
M_B_DQ57 AM35 AY16 M_B_A9
M_B_DQ56 SB_DQ57 SB_MA9 M_B_A8
AL35 SB_DQ56 SB_MA8 AT17
M_B_DQ55 AP37 AU16 M_B_A7
M_B_DQ54 SB_DQ55 SB_MA7 M_B_A6
AN34 SB_DQ54 SB_MA6 AW17
M_B_DQ53 AT35 AV17 M_B_A5
M_B_DQ52 SB_DQ53 SB_MA5 M_B_A4
AP34 SB_DQ52 SB_MA4 AY18
M_B_DQ51 AP36 AU17 M_B_A3
M_B_DQ50 SB_DQ51 SB_MA3 M_B_A2
AN33 SB_DQ50 SB_MA2 AV18
M_B_DQ49 AT36 AU18 M_B_A1
M_B_DQ48 SB_DQ49 SB_MA1 M_B_A0
AR35 SB_DQ48 SB_MA0 AU20
M_B_DQ47 AT33
M_B_DQ46 SB_DQ47 M_BA_B2
AR34 SB_DQ46 SB_BS2 AV12 M_BA_B2 18
M_B_DQ45 AR31 AW25 M_BA_B1 M_BA_B1 18
M_B_DQ44 SB_DQ45 SB_BS1 M_BA_B0
AT31 SB_DQ44 SB_BS0 AU25 M_BA_B0 18
M_B_DQ43 AM32
M_B_DQ42 SB_DQ43
AR33 SB_DQ42 SB_RAS_N AW26 M_B_RAS# M_B_RAS# 18
M_B_DQ41 AP31 AW27 M_B_CAS# M_B_CAS# 18
M_B_DQ40 SB_DQ41 SB_CAS_N M_B_W E#
AT32 SB_DQ40 SB_WE_N AU26 M_B_W E# 18
M_B_DQ39 AT26
M_B_DQ38 SB_DQ39
AP25 SB_DQ38 SB_CS_N7 AK24 1 TP36
M_B_DQ37 AP22 AL24 1 TP34
C M_B_DQ36 SB_DQ37 SB_CS_N6 C
AT23 SB_DQ36 SB_CS_N5 AM24 1 TP35
M_B_DQ35 AR26 AM23 1 TP40
M_B_DQ34 SB_DQ35 SB_CS_N4 TP4
AR25 SB_DQ34 SB_CS_N3 AV29 1
M_B_DQ33 AP23 AV26 1 TP5
M_B_DQ32 SB_DQ33 SB_CS_N2 M_CS#_B1
AN23 SB_DQ32 SB_CS_N1 AW29 M_CS#_B1 18
M_B_DQ31 AT9 AY27 M_CS#_B0 M_CS#_B0 18
M_B_DQ30 SB_DQ31 SB_CS_N0
AL8 SB_DQ30
M_B_DQ29 AR6 AU28
M_B_DQ28 SB_DQ29 SB_ODT3
AN8 SB_DQ28 SB_ODT2 AV27
M_B_DQ27 AM8 AU29 M_ODT_B1 M_ODT_B1 18
M_B_DQ26 SB_DQ27 SB_ODT1 M_ODT_B0
AR9 SB_DQ26 SB_ODT0 AU27 M_ODT_B0 18
M_B_DQ25 AR7
M_B_DQ24 SB_DQ25
AT6 SB_DQ24 SB_CKE3 AV9 1 TP8
M_B_DQ23 AP5 AU9 1 TP46
M_B_DQ22 SB_DQ23 SB_CKE2 M_CKE_B1
AN7 SB_DQ22 SB_CKE1 AY9 M_CKE_B1 18
M_B_DQ21 AM4 AW8 M_CKE_B0 M_CKE_B0 18
M_B_DQ20 SB_DQ21 SB_CKE0
AL5 SB_DQ20
M_B_DQ19 AR5 AR19
M_B_DQ18 SB_DQ19 SB_CKP3
AP6 SB_DQ18 SB_CKN3 AR18
M_B_DQ17 AN5 AN17
M_B_DQ16 SB_DQ17 SB_CKP2
AL6 SB_DQ16 SB_CKN2 AN16
M_B_DQ15 AK7 AT15 M_CLK_DDR_B1 M_CLK_DDR_B1 18
M_B_DQ14 SB_DQ15 SB_CKP1 M_CLK_DDR#_B1
AJ7 SB_DQ14 SB_CKN1 AR15 M_CLK_DDR#_B1 18
M_B_DQ13 AG4 AR17 M_CLK_DDR_B0 M_CLK_DDR_B0 18
M_B_DQ12 SB_DQ13 SB_CKP0 M_CLK_DDR#_B0
AG6 SB_DQ12 SB_CKN0 AR16 M_CLK_DDR#_B0 18
M_B_DQ11 AL4
M_B_DQ10 SB_DQ11
AK6 SB_DQ10 SB_DQSP8 AR14
M_B_DQ9 AH7 AR13
M_B_DQ8 SB_DQ9 SB_DQSN8 M_B_DQS7
AG5 SB_DQ8 SB_DQSP7 AL37 M_B_DQS7 18
B M_B_DQ7 AE6 AM36 M_B_DQS#7 B
SB_DQ7 SB_DQSN7 M_B_DQS#7 18
M_B_DQ6 AF5 AR36 M_B_DQS6
SB_DQ6 SB_DQSP6 M_B_DQS6 18
M_B_DQ5 AC6 AR37 M_B_DQS#6
SB_DQ5 SB_DQSN6 M_B_DQS#6 18
M_B_DQ4 AC7 AP32 M_B_DQS5
SB_DQ4 SB_DQSP5 M_B_DQS5 18
M_B_DQ3 AJ8 AR32 M_B_DQS#5
SB_DQ3 SB_DQSN5 M_B_DQS#5 18
M_B_DQ2 AH8 AT25 M_B_DQS4
SB_DQ2 SB_DQSP4 M_B_DQS4 18
M_B_DQ1 AD6 AR24 M_B_DQS#4
SB_DQ1 SB_DQSN4 M_B_DQS#4 18
18 M_DM_B[7:0] M_B_DQ0 AD7 AR8 M_B_DQS3
SB_DQ0 SB_DQSP3 M_B_DQS3 18
AP8 M_B_DQS#3
SB_DQSN3 M_B_DQS#3 18
M_DM_B7 AK35 AN6 M_B_DQS2
SB_DM7 SB_DQSP2 M_B_DQS2 18
M_DM_B6 AM33 AM6 M_B_DQS#2
SB_DM6 SB_DQSN2 M_B_DQS#2 18
M_DM_B5 AN32 AH6 M_B_DQS1
SB_DM5 SB_DQSP1 M_B_DQS1 18
M_DM_B4 AN24 AJ5 M_B_DQS#1
SB_DM4 SB_DQSN1 M_B_DQS#1 18
M_DM_B3 AT7 AF4 M_B_DQS0
SB_DM3 SB_DQSP0 M_B_DQS0 18
M_DM_B2 AM7 AE5 M_B_DQS#0
SB_DM2 SB_DQSN0 M_B_DQS#0 18
M_DM_B1 AH4
M_DM_B0 SB_DM1
AE4 SB_DM0
AP13 SB_ECC_CB7
AN14 SB_ECC_CB6 2/10
AN12 SB_ECC_CB5
AM12 SB_ECC_CB4
AP14 SB_ECC_CB3
AN15 SB_ECC_CB2 R30
AT13 SB_ECC_CB1
AR12 AG3 DIMM_VREFB VREF_DQ_DDRB 18
SB_ECC_CB0 SB_DIMM_VREF

0_J_4
CN CPU SOCKET SMD LGA1156
A A

A02

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
MCP (DDR3 CHANNEL B)
Date: Tuesday, March 16, 2010 Sheet 12 of 49
5 4 3 2 1
5 4 3 2 1

13

CN3C
D 19 DMI_TXP3 W3 DMI_RXP3 DMI_TXP3 R2 DMI_RXP3 19 D
19 DMI_TXN3 W2 DMI_RXN3 DMI_TXN3 R3
DMI_RXN3 19
19 DMI_TXP2 U1 DMI_RXP2 DMI_TXP2 N1 DMI_RXP2 19
19 DMI_TXN2 V1 DMI_RXN2 DMI_TXN2 P1
DMI_RXN2 19 FDI_TXN[7:0] 19
19 DMI_TXP1 U3 DMI_RXP1 DMI_TXP1 N3 DMI_RXP1 19
U2 N2 FDI_TXN0
19 DMI_TXN1 DMI_RXN1 DMI_TXN1 DMI_RXN1 19
R1 L1 FDI_TXN1
19 DMI_TXP0 DMI_RXP0 DMI_TXP0 DMI_RXP0 19
T1 M1 FDI_TXN2
19 DMI_TXN0 DMI_RXN0 DMI_TXN0 DMI_RXN0 19 FDI_TXN3
FDI_TXN4
AC3 Y6 FDI_TXP7 FDI_TXN5
19 FDI_FSYNC1 FDI_FSYNC_1 FDI_TXP7
AC4 Y5 FDI_TXN7 FDI_TXN6
19 FDI_FSYNC0 FDI_FSYNC_0 FDI_TXN7
Y4 FDI_TXP6 FDI_TXN7
FDI_TXP6 FDI_TXN6
FDI_TXN6 Y3 CHB (FDI_TX[7:4]) FDI_TXP[7:0] 19
AD3 R8 FDI_TXP5
19 FDI_LSYNC1 FDI_LSYNC_1 FDI_TXP5
AD4 R7 FDI_TXN5 FDI_TXP0
19 FDI_LSYNC0 FDI_LSYNC_0 FDI_TXN5
W5 FDI_TXP4 FDI_TXP1
19 FDI_INT FDI_TXP4
W4 FDI_TXN4 FDI_TXP2
FDI_TXN4 FDI_TXP3 FDI_TXP3
AC2 FDI_INT FDI_TXP3 W8
R24 R22 R25 R21 R23 W7 FDI_TXN3 FDI_TXP4
FDI_TXN3 FDI_TXP2 FDI_TXP5
FDI_TXP2 U8
U7 FDI_TXN2 FDI_TXP6
FDI_TXN2 FDI_TXP1 FDI_TXP7
FDI_TXP1 V4 CHA (FDI_TX[3:0])
V3 FDI_TXN1
FDI_TXN1
*1K_F_4

*1K_F_4

*1K_F_4

*1K_F_4

*1K_F_4

U6 FDI_TXP0
FDI_TXP0 FDI_TXN0
FDI_TXN0 U5

PEG_RXP15 T3 R5 PEG_TXP15
25 PEG_RXP15 PEG_RXP15 PEG_TXP15 PEG_TXP15 25
PEG_RXN15 T4 R6 PEG_TXN15
25 PEG_RXN15 PEG_RXN15 PEG_TXN15 PEG_TXN15 25
PEG_RXP14 P3 M8 PEG_TXP14
C 25 PEG_RXP14 PEG_RXP14 PEG_TXP14 PEG_TXP14 25 C
PEG_RXN14 P4 N8 PEG_TXN14
25 PEG_RXN14 PEG_RXN14 PEG_TXN14 PEG_TXN14 25
PEG_RXP13 L2 N6 PEG_TXP13
25 PEG_RXP13 PEG_RXP13 PEG_TXP13 PEG_TXP13 25
PEG_RXN13 L3 N5 PEG_TXN13
25 PEG_RXN13 PEG_RXN13 PEG_TXN13 PEG_TXN13 25
A02 PEG_RXP12 J1 K7 PEG_TXP12
25 PEG_RXP12 PEG_RXP12 PEG_TXP12 PEG_TXP12 25
PEG_RXN12 K1 L7 PEG_TXN12
25 PEG_RXN12 PEG_RXN12 PEG_TXN12 PEG_TXN12 25
PEG_RXP11 J3 M4 PEG_TXP11
25 PEG_RXP11 PEG_RXP11 PEG_TXP11 PEG_TXP11 25
PEG_RXN11 J2 M3 PEG_TXN11
25 PEG_RXN11 PEG_RXN11 PEG_TXN11 PEG_TXN11 25
PEG_RXP10 G1 L6 PEG_TXP10
25 PEG_RXP10 PEG_RXP10 PEG_TXP10 PEG_TXP10 25
PEG_RXN10 H1 L5 PEG_TXN10
25 PEG_RXN10 PEG_RXN10 PEG_TXN10 PEG_TXN10 25
PEG_RXP9 G3 H8 PEG_TXP9
25 PEG_RXP9 PEG_RXP9 PEG_TXP9 PEG_TXP9 25
PEG_RXN9 G2 J8 PEG_TXN9
25 PEG_RXN9 PEG_RXN9 PEG_TXN9 PEG_TXN9 25
PEG_RXP8 E1 K3 PEG_TXP8
25 PEG_RXP8 PEG_RXP8 PEG_TXP8 PEG_TXP8 25
PEG_RXN8 F1 K4 PEG_TXN8
25 PEG_RXN8 PEG_RXN8 PEG_TXN8 PEG_TXN8 25
PEG_RXP7 D2 J6 PEG_TXP7
25 PEG_RXP7 PEG_RXP7 PEG_TXP7 PEG_TXP7 25
PEG_RXN7 E2 J5 PEG_TXN7
25 PEG_RXN7 PEG_RXN7 PEG_TXN7 PEG_TXN7 25
PEG_RXP6 C3 F7 PEG_TXP6
25 PEG_RXP6 PEG_RXP6 PEG_TXP6 PEG_TXP6 25
PEG_RXN6 D3 G7 PEG_TXN6
25 PEG_RXN6 PEG_RXN6 PEG_TXN6 PEG_TXN6 25
PEG_RXP5 B4 H4 PEG_TXP5
25 PEG_RXP5 PEG_RXP5 PEG_TXP5 PEG_TXP5 25
PEG_RXN5 C4 H3 PEG_TXN5
25 PEG_RXN5 PEG_RXN5 PEG_TXN5 PEG_TXN5 25
PEG_RXP4 A5 G6 PEG_TXP4
25 PEG_RXP4 PEG_RXP4 PEG_TXP4 PEG_TXP4 25
PEG_RXN4 B5 G5 PEG_TXN4
25 PEG_RXN4 PEG_RXN4 PEG_TXN4 PEG_TXN4 25
PEG_RXP3 B6 F3 PEG_TXP3
25 PEG_RXP3 PEG_RXP3 PEG_TXP3 PEG_TXP3 25
PEG_RXN3 C6 F4 PEG_TXN3
25 PEG_RXN3 PEG_RXN3 PEG_TXN3 PEG_TXN3 25
PEG_RXP2 A7 E5 PEG_TXP2
25 PEG_RXP2 PEG_RXP2 PEG_TXP2 PEG_TXP2 25
PEG_RXN2 A6 F5 PEG_TXN2
25 PEG_RXN2 PEG_RXN2 PEG_TXN2 PEG_TXN2 25
PEG_RXP1 B8 E7 PEG_TXP1
25 PEG_RXP1 PEG_RXP1 PEG_TXP1 PEG_TXP1 25
PEG_RXN1 C8 E6 PEG_TXN1
25 PEG_RXN1 PEG_RXN1 PEG_TXN1 PEG_TXN1 25
PEG_RXP0 C9 C7 PEG_TXP0
25 PEG_RXP0 PEG_RXP0 PEG_TXP0 PEG_TXP0 25
PEG_RXN0 D9 D7 PEG_TXN0
B
25 PEG_RXN0 PEG_RXN0 PEG_TXN0 PEG_TXN0 25 B
AA3 D11 PEG_COMPO
21 CLK_PCIE_DMI PEG_CLKP PEG_ICOMPI
100MHz (PCIE\DMI\FDI) 21 CLK_PCIE_DMI# AA4 PEG_CLKN PEG_ICOMPO C10
PEG_RCOMPO B10
A11 PEG_RBIAS
PEG_RBIAS
3/10 R14 R16
CN CPU SOCKET SMD LGA1156

750_F_4
49.9_F_4

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
MCP (PCIE/DMI)
Date: Tuesday, March 16, 2010 Sheet 13 of 49
5 4 3 2 1
5 4 3 2 1

14
+VCC_CORE +VCC_CORE +VCC_CORE
PLACE ALL 22UF, 0805 CAPS +1.1V_VTT

R40
CN3F
J22
INSIDE THE SOCKET CAVITY C28
CN3G
W6
VCC181 VCC101 VCC22 VTT67
R39 VCC180 VCC100 J21 C27 VCC21 VTT66 W1
D R38 J19 C13 C18 C351 C27 C10 C328 C333 C19 C352 C11 C12 C321 C25 V6 D
VCC179 VCC99 + VCC20 VTT65
R37 VCC178 VCC98 J18 C24 VCC19 VTT77 V2
R36 VCC177 VCC97 H40 C23 VCC18 VTT76 T2
R35 VCC176 VCC96 H38 B38 VCC17 VTT75 P8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

330U/2V_7343

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8
R34 VCC175 VCC95 H37 B37 VCC16 VTT74 P7
R33 VCC174 VCC94 H35 B35 VCC15 VTT73 P6
P40 VCC173 VCC93 H34 B34 VCC14 VTT72 N7
P39 VCC172 VCC92 H32 B32 VCC13 VTT71 M9
P38 VCC171 VCC91 H31 B31 VCC12 VTT70 M11
P37 VCC170 VCC90 H29 B29 VCC11 VTT69 M10
P36 VCC169 VCC89 H28 B28 VCC10 VTT68 L10
P35 VCC168 VCC88 H26 B26 VCC9 VTT62 AB7
P34 VCC167 VCC87 H25 B25 VCC8 VTT61 V8
P33 VCC166 VCC86 H23 B23 VCC7 VTT60 V7
N39 VCC165 VCC85 H22 A38 VCC_NCTF_1 VTT59 T8
N38 VCC164 VCC84 H20 A36 VCC6 VTT58 T7
N36 H19 C17 C21 C28 C339 C22 A35 T6
VCC163 VCC83 VCC5 VTT57
N35 VCC162 VCC82 G39 A33 VCC4 VTT64 AJ23
N33 VCC161 VCC81 G38 A27 VCC3 VTT63 AC5
M40 VCC160 VCC80 G36 A26 VCC2 VTT48 AK19

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8
M39 VCC159 VCC79 G35 A24 VCC1 VTT47 AJ19
M37 VCC158 VCC78 G33 A23 VCC0 VTT46 AJ17
M36 VCC157 VCC77 G32 VTT45 AE8
M34 VCC156 VCC76 G30 VTT44 AC8
M33 VCC155 VCC75 G29 VTT56 AL21
M30 VCC154 VCC74 G27 VTT55 AL20
M28 VCC153 VCC73 G26 VTT54 AK21
M27 VCC152 VCC72 G24 VTT53 AK20
M25 VCC151 VCC71 G23 +1.8V VTT52 AJ29
M24 VCC150 VCC70 G21 VTT51 AJ27
C R12 0_F_6 VCCPLL C
M22 VCC149 VCC69 G20 AG8 VCCPLL2 VTT50 AJ25
M21 VCC148 VCC68 F40 AF8 VCCPLL1 VTT49 AJ21

C29

C42

C47

C30

C44

C34
M19 VCC147 VCC67 F39 AF7 VCCPLL0 VTT12 Y38
M17 F37 Y37
L40
VCC146
VCC145
VCC66
VCC65 F36 PLACE ALL 22UF, 0805 CAPS VTT43
VTT42 Y36
L38 F34 Y35
VCC144 VCC64
INSIDE THE SOCKET CAVITY. VTT41

2.2U/6.3V_6

22U/6.3V_8

0.1U/16V/X7R_4

0.1U/16V/X7R_4

0.1U/16V/X7R_4

22U/6.3V_8
L37 VCC143 VCC63 F33 VTT40 Y34
L35 VCC142 VCC62 F31 VTT39 Y33
L34
L32
VCC141
VCC140
VCC61
VCC60
F30
F28
ON BOTTOM OF BOARD VTT11
VTT10
V40
V39
L31 VCC139 VCC59 F27 VTT9 V38
L29 VCC138 VCC58 F25 VTT38 V37
L28 VCC137 VCC57 F24 VTT37 V36
L26 VCC136 VCC56 F22 VTT36 V35
L25 VCC135 VCC55 F21 VTT35 V34
L23 VCC134 VCC54 E40 VTT34 V33
L22 VCC133 VCC53 E38 VTT33 AJ32
L20 VCC132 VCC52 E37 VTT32 AJ31
L19 E35 AG33
L17
VCC131
VCC130
VCC51
VCC50 E34 PLACE ALL 22UF, 0805 CAPS VTT31
VTT30 AF33
K39 E32 +1.1V_VTT AE40
K38
K36
VCC129
VCC128
VCC49
VCC48 E31
E29
INSIDE THE SOCKET CAVITY VTT8
VTT7 AE39
AE34
VCC127 VCC47 VTT29
K35 VCC126 VCC46 E28 VTT28 AE33
K33 E26 C327 C347 C338 C371 C353 C331 C372 C373 C320 C323 C334 C14 C16 C20 C23 C45 C46 C24 C359 AD40
VCC125 VCC45 VTT6
K32 VCC124 VCC44 E25 VTT5 AD39
K30 VCC123 VCC43 E23 VTT4 AD38
K29 VCC122 VCC42 E22 VTT27 AD37
22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8
K27 VCC121 VCC41 D39 VTT26 AD36
B K26 D38 AD35 B
VCC120 VCC40 VTT25
K24 VCC119 VCC39 D36 VTT24 AD34
K23 VCC118 VCC38 D35 VTT23 AD33
K21 VCC117 VCC37 D33 VTT3 AC40
K20 VCC116 VCC36 D32 VTT2 AC39
K18 VCC115 VCC35 D30 VTT1 AC38
K17 VCC114 VCC34 D29 VTT22 AC37
J40 VCC113 VCC33 D27 VTT21 AC36
J39 VCC112 VCC32 D26 VTT20 AC35
J37 VCC111 VCC31 D24 VTT19 AC34
J36 VCC110 VCC30 D23 VTT18 AC33
J34 VCC109 VCC_NCTF_2 C40 VTT0 AA38
J33 VCC108 VCC29 C39 VTT17 AA37
J31 VCC107 VCC28 C37 VTT16 AA36
J30 VCC106 VCC27 C36 VTT15 AA35
J28 VCC105 VCC26 C34 VTT14 AA34
J27 VCC104 VCC25 C33 7/10 VTT13 AA33
J25 VCC103 VCC24 C31
J24 VCC102 VCC23 C30 CN CPU SOCKET SMD LGA1156
+1.1V_VTT
6/10
CN CPU SOCKET SMD LGA1156

C365 C377
0.1U/16V/X7R_4

0.1U/16V/X7R_4

A A

Quanta Computer Inc.


For DMI bus split power plane
PROJECT : ZN2
Size Document Number Rev
A
MCP (VCCP)
Date: Tuesday, March 16, 2010 Sheet 14 of 49
5 4 3 2 1
5 4 3 2 1

15

D D

V_AXG +1.5V_SUS
+1.5V_SUS

VAXG tie to GND for LFD CPU. CN3H


CAVITY M16 AY26 C43 C32
VAXG48 VDDQ18
M15 VAXG47 VDDQ17 AY23
M14 VAXG46 VDDQ16 AY17
C35 C374 C362 C364 C363 C36 C379 L16 AY14
VAXG45 VDDQ15

22U/6.3V_8

22U/6.3V_8
L15 VAXG44 VDDQ14 AY11
L14 VAXG43 VDDQ13 AW9
K16 VAXG42 VDDQ12 AV28

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8
K15 VAXG41 VDDQ11 AV25
K14 VAXG40 VDDQ10 AV22
J16 VAXG39 VDDQ9 AV19
J15 VAXG38 VDDQ8 AV16
J14 VAXG37 VDDQ7 AV13
CN3D H17 AU11
VAXG36 VDDQ6
A12 RSVD_A12 RSVD_AM14 AM14 H15 VAXG35 VDDQ5 AT21
A4 RSVD_NCTF_A4 RSVD_AM15 AM15 H14 VAXG34 VDDQ4 AT18
AD2 RSVD_AD2 RSVD_AM16 AM16 G18 VAXG33 VDDQ3 AT10 SOCKET CAVITY
AE2 RSVD_AE2 RSVD_AM17 AM17 G17 VAXG32 VDDQ2 AJ15
AH40 RSVD_AH40 RSVD_AM18 AM18 G15 VAXG31 VDDQ1 AJ13
AJ39 RSVD_AJ39 RSVD_AM19 AM19 G14 VAXG30 VDDQ0 AJ11
AK12 RSVD_AK12 RSVD_AM20 AM20 PLACE BACKSIDE OF MCP CAVITY F19 VAXG29
AK13 RSVD_AK13 RSVD_AM21 AM21 F18 VAXG28
AK14 RSVD_AK14 RSVD_AM25 AM25 F17 VAXG27
AK15 RSVD_AK15 RSVD_AM26 AM26 F15 VAXG26
AK16 RSVD_AK16 RSVD_AM27 AM27 F14 VAXG25
C C
AK18 RSVD_AK18 RSVD_AM28 AM28 E20 VAXG24
AK25 RSVD_AK25 RSVD_AM29 AM29 E18 VAXG23
AK26 RSVD_AK26 RSVD_AM30 AM30 E17 VAXG22
AK27 RSVD_AK27 RSVD_NCTF_AU40 AU40 E15 VAXG21
AK28 RSVD_AK28 RSVD_NCTF_AV1 AV1 E14 VAXG20
AK29 RSVD_AK29 RSVD_NCTF_AV39 AV39 D21 VAXG19
AL12 RSVD_AL12 RSVD_NCTF_AW2 AW2 D20 VAXG18
AL14 RSVD_AL14 RSVD_NCTF_AW38 AW38 D18 VAXG17
AL15 RSVD_AL15 RSVD_NCTF_AY3 AY3 D17 VAXG16
AL17 RSVD_AL17 RSVD_NCTF_AY37 AY37 D15 VAXG15
AL18 RSVD_AL18 RSVD_NCTF_B3 B3 D14 VAXG14
AL26 RSVD_AL26 RSVD_NCTF_C2 C2 C21 VAXG13
AL27 RSVD_AL27 RSVD_NCTF_D1 D1 C20 VAXG12
AL29 J10 1 TP45 C18
RSVD_AL29 GFX_DPRSLPVR VAXG11
AM13 RSVD_AM13 RSVD_L12 L12 C17 VAXG10
TP43 1 XDP_TESTIN_N AN11 M12 C15
RSVD_TP RSVD_M12 VAXG9
C14 VAXG8
4/10 B18
B17
VAXG7
CN CPU SOCKET SMD LGA1156 VAXG6
B15 VAXG5
B14 VAXG4
A18 VAXG3
A17 VAXG2
A15 VAXG1
A14 VAXG0 8/10
CN CPU SOCKET SMD LGA1156

B B

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
MCP (MISC/VCC)
Date: Tuesday, March 16, 2010 Sheet 15 of 49
5 4 3 2 1
5 4 3 2 1

16

CN3I
D
CN3J D
Y7 VSS274 VSS68 AM5
W38 VSS273 VSS204 H6 C32 VSS135 VSS67 AM40
W37 VSS272 VSS203 H5 C29 VSS134 VSS66 AM1
W36 VSS271 VSS202 H39 C26 VSS133 VSS65 AL7
W35 VSS270 VSS201 H36 C22 VSS132 VSS64 AL38
W34 VSS269 VSS200 H33 C19 VSS131 VSS63 AL34
W33 VSS268 VSS199 H30 C16 VSS130 VSS62 AL31
V5 VSS267 VSS198 H27 C13 VSS129 VSS61 AL3
U4 VSS266 VSS197 H24 B9 VSS128 VSS60 AL28
T5 VSS265 VSS196 H21 B7 VSS127 VSS59 AL25
T38 VSS264 VSS195 H2 B39 CGC_TP_NCTF VSS58 AL22
T37 VSS263 VSS194 H18 B36 VSS126 VSS57 AL19
T36 VSS262 VSS193 H16 B33 VSS125 VSS56 AL16
T33 VSS261 VSS192 H13 B30 VSS124 VSS55 AL13
R4 VSS260 VSS191 H11 B27 VSS123 VSS54 AL11
P5 VSS259 VSS190 G9 B24 VSS122 VSS53 AK8
P2 VSS258 VSS189 G40 B16 VSS121 VSS52 AK5
N40 VSS257 VSS188 G4 AY7 VSS120 VSS52_1 AK4
N4 VSS256 VSS187 G37 AY4 VSS119 VSS51 AK36
N37 VSS255 VSS186 G34 AY36 VSS118 VSS50 AK17
N34 VSS254 VSS185 G31 AY33 VSS117 VSS49 AK10
M7 VSS253 VSS184 G28 AV38 VSS115 VSS48 AJ9
M6 VSS252 VSS183 G25 AV34 VSS114 VSS47 AJ6
M5 VSS251 VSS182 G22 AV31 VSS113 VSS46 AJ40
M38 VSS250 VSS181 G19 AV3 VSS112 VSS45 AJ34
M35 VSS249 VSS180 G16 AU7 VSS111 VSS44 AJ33
M32 VSS248 VSS179 G13 AU6 VSS116 VSS43 AJ30
M29 VSS247 VSS178 F8 AU36 VSS110_1 VSS42 AJ28
M26 VSS246 VSS177 F38 AU32 VSS110 VSS41 AJ26
C C
M23 VSS245 VSS176 F35 AT8 VSS109_1 VSS40 AJ24
M20 VSS244 VSS175 F32 AT5 VSS109 VSS39 AJ22
M2 VSS243 VSS174 F29 AT37 VSS108 VSS38 AJ20
M18 VSS242 VSS173 F26 AT34 VSS107 VSS37 AJ18
M13 VSS241 VSS172 F23 AT30 VSS105 VSS36 AJ16
L9 VSS240 VSS171 F20 AT27 VSS104 VSS35 AJ14
L4 VSS239 VSS170 F2 AT24 VSS103 VSS34 AJ12
L39 VSS238 VSS169 F16 AT2 VSS102 VSS33 AJ1
L36 VSS237 VSS168 F13 AT16 VSS101 VSS28 AH5
L33 VSS236 VSS167 F11 AT14 VSS100 VSS32 AH38
L30 VSS235 VSS166 E4 AT12 VSS99 VSS31 AH33
L27 VSS234 VSS165 E39 AR40 VSS98 VSS30 AH3
L24 VSS233 VSS164 E36 AR30 VSS98 VSS29 AG7
L21 VSS232 VSS163 E33 AR23 VSS97 VSS27 AG36
L18 VSS231 VSS162 E30 AR20 VSS96 VSS26 AG34
L13 VSS230 VSS161 E3 AR1 VSS95 VSS25 AF6
K6 VSS229 VSS160 E27 AP9 VSS94 VSS24 AF40
K5 VSS228 VSS159 E24 AP7 VSS93 VSS23 AF1
K40 VSS227 VSS158 E21 AP4 VSS92 VSS22 AE7
K37 VSS226 VSS157 E19 AP38 VSS91 VSS21 AE37
K34 VSS225 VSS156 E16 AP35 VSS90_1 VSS20 AE3
K31 VSS224 VSS155 E13 AP33 VSS90 VSS19 AD8
K28 VSS223 VSS154 D8 AP29 VSS87 VSS18 AD5
K25 VSS222 VSS153 D6 AP27 VSS86 VSS17 AC1
K22 VSS221 VSS152 D5 AP26 VSS85 VSS16 AB8
K2 VSS220 VSS151 D40 AP24 VSS84 VSS15 AB6
K19 VSS219 VSS150 D4 AP20 VSS83 VSS14 AB40
K13 VSS218 VSS149 D37 AP17 VSS82 VSS13 AB39
K11 VSS217 VSS148 D34 AP16 VSS81 VSS12 AB38
B J9 D31 AP15 AB37 B
VSS216 VSS147 VSS80 VSS11
J7 VSS215 VSS146 D28 AP12 VSS79 VSS10 AB36
J4 VSS214 VSS145 D25 AN9 VSS78 VSS9 AB35
J38 VSS213 VSS144 D22 AN4 VSS77 VSS8 AB34
J35 VSS212 VSS143 D19 AN36 VSS76 VSS7 AB33
J32 VSS211 VSS142 D16 AN31 VSS74 VSS6 AB3
J29 VSS210 VSS141 D13 AN28 VSS73 VSS5 AA5
J26 VSS209 VSS140 D12 AN25 VSS72 VSS4 A37
J23 VSS208 VSS139 D10 AN22 VSS71 VSS3 A34
J20 VSS207 VSS138 C5 AN20 VSS70 VSS2 A28
J17 VSS206 VSS137 C38 AN13 VSS69 VSS1 A25
J13 VSS205 VSS136 C35 AM9 VSS75 VSS0 A16
10/10
9/10 CN CPU SOCKET SMD LGA1156
CN CPU SOCKET SMD LGA1156

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
MCP (GND)
Date: Tuesday, March 16, 2010 Sheet 16 of 49
5 4 3 2 1
5 4 3 2 1

CHANNEL A DIMM 0
+1.5V_SUS
17
M_A_DQ[63:0] 11
11 M_A_A[15:0] +1.5V_SUS
CN4A
M_A_A0 98 5 M_A_DQ0
M_A_A1 A0 DQ0 M_A_DQ1 C386 C387
97 A1 DQ1 7 CN4B
M_A_A2 96 15 M_A_DQ2 R346
M_A_A3 A2 DQ2 M_A_DQ3 2.2U/6.3V_6 0.1U/16V/X7R_4
95 A3 DQ3 17 75 VDD1 VSS16 44
M_A_A4 92 4 M_A_DQ4 76 48
M_A_A5 A4 DQ4 M_A_DQ5 VDD2 VSS17
D 91 A5 DQ5 6 81 VDD3 VSS18 49 D
M_A_A6 90 16 M_A_DQ6 82 54 1K_F_4
M_A_A7 A6 DQ6 M_A_DQ7 VDD4 VSS19
86 A7 DQ7 18 87 VDD5 VSS20 55
M_A_A8 89 21 M_A_DQ8 C378C346C31 C39 88 60
M_A_A9 A8 DQ8 M_A_DQ9 VDD6 VSS21 VREF_DQ_DDRA
85 A9 DQ9 23 93 VDD7 VSS22 61

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4
M_A_A10 107 33 M_A_DQ10 94 65
M_A_A11 A10/AP DQ10 M_A_DQ11 VDD8 VSS23
84 A11 DQ11 35 99 VDD9 VSS24 66
M_A_A12 83 22 M_A_DQ12 100 71 R343 C385 C382
M_A_A13 A12/BC# DQ12 M_A_DQ13 VDD10 VSS25
119 A13 DQ13 24 105 VDD11 VSS26 72
M_A_A14 M_A_DQ14

PC2100 DDR3 SDRAM SO-DIMM


80 A14 DQ14 34 106 VDD12 VSS27 127

0.1U/16V/X7R_4

0.1U/16V/X7R_4
M_A_A15 78 36 M_A_DQ15 111 128
A15 DQ15 M_A_DQ16 VDD13 VSS28 1K_F_4

PC2100 DDR3 SDRAM SO-DIMM


DQ16 39 112 VDD14 VSS29 133
11 M_BA_A0 M_BA_A0 109 41 M_A_DQ17 117 134
M_BA_A1 BA0 DQ17 M_A_DQ18 VDD15 VSS30
11 M_BA_A1 108 BA1 DQ18 51 118 VDD16 VSS31 138
11 M_BA_A2 M_BA_A2 79 53 M_A_DQ19 123 139
M_CS#_A0 BA2 DQ19 M_A_DQ20 VDD17 VSS32
11 M_CS#_A0 114 S0# DQ20 40 124 VDD18 VSS33 144
11 M_CS#_A1 M_CS#_A1 121 42 M_A_DQ21 145
M_CLK_DDR_A0 S1# DQ21 M_A_DQ22 VSS34
11 M_CLK_DDR_A0 101 CK0 DQ22 50 +3V 199 VDDSPD VSS35 150
11 M_CLK_DDR#_A0 M_CLK_DDR#_A0 103 52 M_A_DQ23 151
M_CLK_DDR_A1 CK0# DQ23 M_A_DQ24 VSS36
11 M_CLK_DDR_A1 102 CK1 DQ24 57 77 NC1 VSS37 155
11 M_CLK_DDR#_A1 M_CLK_DDR#_A1 104 59 M_A_DQ25 122 156
M_CKE_A0 CK1# DQ25 M_A_DQ26 NC2 VSS38
11 M_CKE_A0 73 CKE0 DQ26 67 125 NCTEST VSS39 161
11 M_CKE_A1 M_CKE_A1 74 69 M_A_DQ27 162
M_A_CAS# CKE1 DQ27 M_A_DQ28 PM_EXTTS#0 VSS40 +1.5V_SUS
11 M_A_CAS# 115 CAS# DQ28 56 10 PM_EXTTS#0 198 EVENT# VSS41 167
11 M_A_RAS# M_A_RAS# 110 58 M_A_DQ29 DDR3_DRAMRST# 30 168
RAS# DQ29 11,18 DDR3_DRAMRST# RESET# VSS42
11 M_A_WE# M_A_WE# 113 68 M_A_DQ30 172
SA0_A_0 WE# DQ30 M_A_DQ31 VSS43
197 SA0 DQ31 70 VSS44 173
C SA1_A_0 201 129 M_A_DQ32 VREF_DQ_DDRA 1 178 C322 C324 C
SA1 DQ32 11 VREF_DQ_DDRA VREF_DQ VSS45
202 131 M_A_DQ33 VREF_CA_DDRA 126 179 R311
9,18,30,32,37 CLK_SCLK SCL DQ33 VREF_CA VSS46
200 141 M_A_DQ34 184 2.2U/6.3V_6 0.1U/16V/X7R_4
9,18,30,32,37 CLK_SDATA SDA DQ34 VSS47
143 M_A_DQ35 185
M_ODT_A0 DQ35 M_A_DQ36 VSS48
11 M_ODT_A0 116 ODT0 DQ36 130 2 VSS1 VSS49 189
11 M_ODT_A1 M_ODT_A1 120 132 M_A_DQ37 3 190
ODT1 DQ37 M_A_DQ38 VSS2 VSS50 1K_F_4
11 M_DM_A[7:0] 140 8 195

(204P)
M_DM_A0 DQ38 M_A_DQ39 VSS3 VSS51
11 DM0 DQ39 142 9 VSS4 VSS52 196
M_DM_A1 28 147 M_A_DQ40 +3V 13 VREF_CA_DDRA
M_DM_A2 DM1 DQ40 M_A_DQ41 VSS5
46 149 14
(204P)

M_DM_A3 DM2 DQ41 M_A_DQ42 VSS6


63 DM3 DQ42 157 19 VSS7
M_DM_A4 136 159 M_A_DQ43 20 R312 C9 C15
M_DM_A5 DM4 DQ43 M_A_DQ44 VSS8
153 DM5 DQ44 146 25 VSS9 SMDDR_VTERM

0.1U/16V/X7R_4

0.1U/16V/X7R_4
M_DM_A6 170 148 M_A_DQ45 C308 C307 26 203
M_DM_A7 DM6 DQ45 M_A_DQ46 VSS10 VTT1
187 DM7 DQ46 158 31 VSS11 VTT2 204
160 M_A_DQ47 32 1K_F_4
DQ47 VSS12

0.1U/16V/X7R_4

0.1U/16V/X7R_4
M_A_DQS0 12 163 M_A_DQ48 37 205
11 M_A_DQS0 DQS0 DQ48 VSS13 GND
M_A_DQS1 29 165 M_A_DQ49 38 206
11 M_A_DQS1 DQS1 DQ49 VSS14 GND
M_A_DQS2 47 175 M_A_DQ50 43
11 M_A_DQS2 DQS2 DQ50 VSS15
M_A_DQS3 64 177 M_A_DQ51
11 M_A_DQS3 DQS3 DQ51
M_A_DQS4 137 164 M_A_DQ52
11 M_A_DQS4 DQS4 DQ52
M_A_DQS5 154 166 M_A_DQ53
11 M_A_DQS5 DQS5 DQ53
M_A_DQS6 171 174 M_A_DQ54 DDR3-DIMM0_H=5.2_Standard
11 M_A_DQS6 DQS6 DQ54
M_A_DQS7 188 176 M_A_DQ55
11 M_A_DQS7 DQS7 DQ55
M_A_DQS#0 10 181 M_A_DQ56
11 M_A_DQS#0 DQS#0 DQ56
M_A_DQS#1 27 183 M_A_DQ57
11 M_A_DQS#1 DQS#1 DQ57
M_A_DQS#2 45 191 M_A_DQ58
11 M_A_DQS#2 DQS#2 DQ58
B M_A_DQS#3 62 193 M_A_DQ59 B
11 M_A_DQS#3 DQS#3 DQ59
M_A_DQS#4 135 180 M_A_DQ60
11 M_A_DQS#4 DQS#4 DQ60
M_A_DQS#5 152 182 M_A_DQ61
11
11
M_A_DQS#5
M_A_DQS#6
M_A_DQS#6 169
DQS#5 DQ61
192 M_A_DQ62 Place these Caps near So-Dimm0.
M_A_DQS#7 DQS#6 DQ62 M_A_DQ63 +1.5V_SUS
11 M_A_DQS#7 186 DQS#7 DQ63 194
+3V
DDR3-DIMM0_H=5.2_Standard C356 C366 C38 C41 C37 C341 C350 C360 C369 C33 C40 C8

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

0.1U/16V_4

0.1U/16V_4

0.1U/16V_4

0.1U/16V_4

0.1U/16V_4

330U/2V_7343
R306 *10K_F_4 PM_EXTTS#0 +

+3V SMDDR_VTERM

C305 C306 C298 C297 C303 C302 C300 C299 C301


SPD SA0 0
M_CLK_DDR_A0 R320 *100K_F_4 M_CLK_DDR#_A0 2.2U/6.3V_6 0.1U/16V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6

SPD SA1 0 M_CLK_DDR_A1 R318 *100K_F_4 M_CLK_DDR#_A1


A A
maybe can save

R307 0_J_4 SA1_A_0


R308 0_J_4 SA0_A_0
Quanta Computer Inc.
PROJECT :ZN2
Size Document Number Rev
A
DDR3 CHA DIMM 0
Date: Tuesday, March 16, 2010 Sheet 17 of 49
5 4 3 2 1
5 4 3 2 1

CHANNEL B DIMM 2 M_B_DQ[63:0] 12

+1.5V_SUS
+1.5V_SUS
18
12 M_B_A[15:0] CN5A
M_B_A0 98 5 M_B_DQ0
M_B_A1 A0 DQ0 M_B_DQ1 C381 C380
97 A1 DQ1 7 CN5B
M_B_A2 96 15 M_B_DQ2 R341
M_B_A3 A2 DQ2 M_B_DQ3 2.2U/6.3V_6 0.1U/16V/X7R_4
95 A3 DQ3 17 75 VDD1 VSS16 44
M_B_A4 92 4 M_B_DQ4 76 48
M_B_A5 A4 DQ4 M_B_DQ5 VDD2 VSS17
91 A5 DQ5 6 81 VDD3 VSS18 49
D M_B_A6 90 16 M_B_DQ6 82 54 D
M_B_A7 A6 DQ6 M_B_DQ7 VDD4 VSS19 1K_F_4
86 A7 DQ7 18 87 VDD5 VSS20 55
M_B_A8 89 21 M_B_DQ8 C349C367C354C358 88 60
M_B_A9 A8 DQ8 M_B_DQ9 VDD6 VSS21 VREF_DQ_DDRB
85 A9 DQ9 23 93 VDD7 VSS22 61

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4
M_B_A10 107 33 M_B_DQ10 94 65
M_B_A11 A10/AP DQ10 M_B_DQ11 VDD8 VSS23
84 A11 DQ11 35 99 VDD9 VSS24 66
M_B_A12 83 22 M_B_DQ12 100 71 R344 C383 C384
M_B_A13 A12/BC# DQ12 M_B_DQ13 VDD10 VSS25
119 A13 DQ13 24 105 VDD11 VSS26 72

0.1U/16V/X7R_4

0.1U/16V/X7R_4
M_B_A14 M_B_DQ14

PC2100 DDR3 SDRAM SO-DIMM


80 A14 DQ14 34 106 VDD12 VSS27 127
M_B_A15 78 36 M_B_DQ15 111 128
A15 DQ15 M_B_DQ16 VDD13 VSS28 1K_F_4

PC2100 DDR3 SDRAM SO-DIMM


DQ16 39 112 VDD14 VSS29 133
12 M_BA_B0 M_BA_B0 109 41 M_B_DQ17 117 134
M_BA_B1 BA0 DQ17 M_B_DQ18 VDD15 VSS30
12 M_BA_B1 108 BA1 DQ18 51 118 VDD16 VSS31 138
12 M_BA_B2 M_BA_B2 79 53 M_B_DQ19 123 139
M_CS#_B0 BA2 DQ19 M_B_DQ20 VDD17 VSS32
12 M_CS#_B0 114 S0# DQ20 40 124 VDD18 VSS33 144
12 M_CS#_B1 M_CS#_B1 121 42 M_B_DQ21 145
M_CLK_DDR_B0 S1# DQ21 M_B_DQ22 VSS34
12 M_CLK_DDR_B0 101 CK0 DQ22 50 +3V 199 VDDSPD VSS35 150
12 M_CLK_DDR#_B0 M_CLK_DDR#_B0 103 52 M_B_DQ23 151
M_CLK_DDR_B1 CK0# DQ23 M_B_DQ24 VSS36
12 M_CLK_DDR_B1 102 CK1 DQ24 57 77 NC1 VSS37 155
12 M_CLK_DDR#_B1 M_CLK_DDR#_B1 104 59 M_B_DQ25 122 156
M_CKE_B0 CK1# DQ25 M_B_DQ26 NC2 VSS38
12 M_CKE_B0 73 CKE0 DQ26 67 125 NCTEST VSS39 161
12 M_CKE_B1 M_CKE_B1 74 69 M_B_DQ27 162
M_B_CAS# CKE1 DQ27 M_B_DQ28 PM_EXTTS#1 VSS40 +1.5V_SUS
12 M_B_CAS# 115 CAS# DQ28 56 10 PM_EXTTS#1 198 EVENT# VSS41 167
12 M_B_RAS# M_B_RAS# 110 58 M_B_DQ29 DDR3_DRAMRST# 30 168
RAS# DQ29 11,17 DDR3_DRAMRST# RESET# VSS42
12 M_B_WE# M_B_WE# 113 68 M_B_DQ30 172
SA0_B_0 WE# DQ30 M_B_DQ31 VSS43
197 SA0 DQ31 70 VSS44 173
SA1_B_0 201 129 M_B_DQ36 VREF_DQ_DDRB 1 178 C325 C326
SA1 DQ32 12 VREF_DQ_DDRB VREF_DQ VSS45
C 202 131 M_B_DQ33 VREF_CA_DDRB 126 179 R316 C
9,17,30,32,37 CLK_SCLK SCL DQ33 VREF_CA VSS46
200 141 M_B_DQ34 184 2.2U/6.3V_6 0.1U/16V/X7R_4
7,30,32,37 CLK_SDATA SDA DQ34 VSS47
143 M_B_DQ35 185
M_ODT_B0 DQ35 M_B_DQ32 +3V VSS48
12 M_ODT_B0 116 ODT0 DQ36 130 2 VSS1 VSS49 189
12 M_ODT_B1 M_ODT_B1 120 132 M_B_DQ37 3 190
ODT1 DQ37 M_B_DQ38 VSS2 VSS50 1K_F_4
12 M_DM_B[7:0] 140 8 195

(204P)
M_DM_B0 DQ38 M_B_DQ39 VSS3 VSS51
11 DM0 DQ39 142 9 VSS4 VSS52 196
M_DM_B1 28 147 M_B_DQ41 13 VREF_CA_DDRB
M_DM_B2 DM1 DQ40 M_B_DQ43 C319 C317 VSS5
46 149 14
(204P)

M_DM_B3 DM2 DQ41 M_B_DQ40 VSS6


63 DM3 DQ42 157 19 VSS7
M_DM_B4 136 159 M_B_DQ42 20 R315 C330 C332
DM4 DQ43 VSS8

0.1U/16V/X7R_4

0.1U/16V/X7R_4
M_DM_B5 153 146 M_B_DQ44 25
DM5 DQ44 VSS9

0.1U/16V/X7R_4

0.1U/16V/X7R_4
M_DM_B6 170 148 M_B_DQ45 26 203 SMDDR_VTERM
M_DM_B7 DM6 DQ45 M_B_DQ46 VSS10 VTT1
187 DM7 DQ46 158 31 VSS11 VTT2 204
160 M_B_DQ47 32 1K_F_4
M_B_DQS0 DQ47 M_B_DQ48 VSS12
12 M_B_DQS0 12 DQS0 DQ48 163 37 VSS13 GND 205
M_B_DQS1 29 165 M_B_DQ49 38 206
12 M_B_DQS1 DQS1 DQ49 VSS14 GND
M_B_DQS2 47 175 M_B_DQ50 43
12 M_B_DQS2 DQS2 DQ50 VSS15
M_B_DQS3 64 177 M_B_DQ51
12 M_B_DQS3 DQS3 DQ51
M_B_DQS4 137 164 M_B_DQ52
12 M_B_DQS4 DQS4 DQ52
M_B_DQS5 154 166 M_B_DQ53
12 M_B_DQS5 DQS5 DQ53
M_B_DQS6 171 174 M_B_DQ54 DDR3-DIMM0_H=5.2_Standard
12 M_B_DQS6 DQS6 DQ54
M_B_DQS7 188 176 M_B_DQ55
12 M_B_DQS7 DQS7 DQ55
M_B_DQS#0 10 181 M_B_DQ56
12 M_B_DQS#0 DQS#0 DQ56
M_B_DQS#1 27 183 M_B_DQ57
12 M_B_DQS#1 DQS#1 DQ57
M_B_DQS#2 45 191 M_B_DQ58
12 M_B_DQS#2 DQS#2 DQ58
M_B_DQS#3 62 193 M_B_DQ59
12 M_B_DQS#3 DQS#3 DQ59
B M_B_DQS#4 135 180 M_B_DQ60 B
12 M_B_DQS#4 DQS#4 DQ60
M_B_DQS#5 152 182 M_B_DQ61
12
12
M_B_DQS#5
M_B_DQS#6
M_B_DQS#6 169
DQS#5 DQ61
192 M_B_DQ62 Place these Caps near So-Dimm0.
M_B_DQS#7 DQS#6 DQ62 M_B_DQ63 +1.5V_SUS
12 M_B_DQS#7 186 DQS#7 DQ63 194
+3V

C342 C370 C357 C368 C340 C348 C337 C375 C361 C376 C345 C25

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

10U/6.3V_6

0.1U/16V_4

0.1U/16V_4

0.1U/16V_4

0.1U/16V_4

0.1U/16V_4

330U/2V_7343
DDR3-DIMM0_H=5.2_Standard R305 *10K_F_4 PM_EXTTS#1
+
M_B_DQ32----JDIM4.130-----JDIM3.130
M_B_DQ36----JDIM4.129-----JDIM3.129

M_B_DQ41----JDIM4.147-----JDIM3.147
M_B_DQ43----JDIM4.149-----JDIM3.149
M_B_DQ42----JDIM4.159-----JDIM3.159
M_B_DQ40----JDIM4.157-----JDIM3.157

+3V SMDDR_VTERM

C309 C310 C311 C316 C315 C312 C314 C318 C313


SPD SA0 0 2.2U/6.3V_6 0.1U/16V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6

M_CLK_DDR_B0 R321 *100K_F_4 M_CLK_DDR#_B0


SPD SA1 1 maybe can save
A A
M_CLK_DDR_B1 R317 *100K_F_4 M_CLK_DDR#_B1

R310 0_J_4 SA0_B_0


+3V R309 0_J_4 SA1_B_0 Quanta Computer Inc.
PROJECT :ZN2
Size Document Number Rev
A
DDR3 CHB DIMM 0
Date: Tuesday, March 16, 2010 Sheet 18 of 49
5 4 3 2 1
5 4 3 2 1

IBEX PEAK-M (DMI,FDI,GPIO) IBEX PEAK-M (LVDS,DDI) 19


FDI_TXN[7:0] 13
U18C RN10 U18D
BA18 FDI_TXN0 IV@0X2 1 2 TXLOUT#0_R T48 BJ46
FDI_RXN0 FDI_TXN1 32 TXLOUT#0 TXLOUT0_R 32 INT_LVDS_BLON L_BKLTEN SDVO_TVCLKINN
13 DMI_RXN0 BC24 BH17 32 TXLOUT0
3 4 32 INT_LVDS_PWREN
T47 BG46
DMI0RXN FDI_RXN1 FDI_TXN2 L_VDD_EN SDVO_TVCLKINP
13 DMI_RXN1 BJ22 BD16
DMI1RXN FDI_RXN2 FDI_TXN3 RN9
13 DMI_RXN2 AW20 BJ16 TP19 Y48 BJ48
DMI2RXN FDI_RXN3 FDI_TXN4 IV@0X2 1 TXLOUT#1_R L_BKLTCTL SDVO_STALLN
13 DMI_RXN3 BJ20 BA16 32 TXLOUT#1
2 BG48
DMI3RXN FDI_RXN4 FDI_TXN5 TXLOUT1_R SDVO_STALLP
BE14 32 TXLOUT1 3 4 25,32 LCD_CLK AB48
FDI_RXN5 FDI_TXN6 L_DDC_CLK
D 13 DMI_RXP0 BD24 BA14 25,32 LCD_DAT Y45 BF45 D
DMI0RXP FDI_RXN6 FDI_TXN7 RN19 L_DDC_DATA SDVO_INTN
13 DMI_RXP1 BG22 BC12 FDI_TXP[7:0] 13 BH45
DMI1RXP FDI_RXN7 IV@0X2 1 TXLOUT#2_R R161 10K_F_4 SDVO_INTP
13 DMI_RXP2 BA20 32 TXLOUT#2 2 +3V AB46
DMI2RXP FDI_TXP0 TXLOUT2_R R169 10K_F_4 L_CTRL_CLK
13 DMI_RXP3 BG20 BB18 32 TXLOUT2 3 4 V48
DMI3RXP FDI_RXP0 FDI_TXP1 L_CTRL_DATA
BF17
FDI_RXP1 FDI_TXP2 RN20 R128 2.37K_F_4 LVD_IBG
13 DMI_TXN0 BE22 BC16 AP39 T51
DMI0TXN FDI_RXP2 FDI_TXP3 IV@0X2 1 TXLOUT#3_R LVD_IBG SDVO_CTRLCLK
13 DMI_TXN1 BF21 BG16 32 TXLOUT#3 2 AP41 T53
DMI1TXN FDI_RXP3 FDI_TXP4 TXLOUT3_R LVD_VBG SDVO_CTRLDATA
13 DMI_TXN2 BD20 AW16 32 TXLOUT3 3 4
DMI2TXN FDI_RXP4 FDI_TXP5 R127 0_J_4 LVD_VREFH
13 DMI_TXN3 BE18 BD14 AT43
DMI3TXN FDI_RXP5 FDI_TXP6 RN22 R119 0_J_4 LVD_VREFL LVD_VREFH
BB14 AT42 BG44
FDI_RXP6 FDI_TXP7 IV@0X2 1 TXUOUT#4_R LVD_VREFL DDPB_AUXN
13 DMI_TXP0
BD22 BD12 32 TXUOUT#4
2 BJ44
DMI0TXP FDI_RXP7 TXUOUT4_R IV@0X2 RN21 DDPB_AUXP
13 DMI_TXP1 BH21 32 TXUOUT4 3 4 AU38
DMI1TXP DDPB_HPD

LVDS
BC20 1 2 TXLCLK#_R AV53
13 DMI_TXP2 DMI2TXP RN23 32 TXLCLK# TXLCLK_R LVDSA_CLK#
13 DMI_TXP3
BD18 BJ14 FDI_INT 13 32 TXLCLK
3 4 AV51 BD42
DMI3TXP FDI_INT IV@0X2 1 TXUOUT#5_R LVDSA_CLK DDPB_0N
2 BC42

DMI
FDI
32 TXUOUT#5 TXUOUT5_R TXLOUT#0_R DDPB_0P
BF13 FDI_FSYNC0 13 32 TXUOUT5
3 4 BB47 BJ42
FDI_FSYNC0 TXLOUT#1_R LVDSA_DATA#0 DDPB_1N
BH25 BA52 BG42

Digital Display Interface


DMI_ZCOMP RN13 TXLOUT#2_R LVDSA_DATA#1 DDPB_1P
BH13 FDI_FSYNC1 13 AY48 BB40
R366 49.9_F_4 FDI_FSYNC1 IV@0X2 1 TXUOUT#6_R TXLOUT#3_R LVDSA_DATA#2 DDPB_2N
+1.05V BF25 32 TXUOUT#6 2 AV47 BA40
DMI_IRCOMP TXUOUT6_R LVDSA_DATA#3 DDPB_2P
BJ12 FDI_LSYNC0 13 32 TXUOUT6 3 4 AW38
FDI_LSYNC0 TXLOUT0_R DDPB_3N
BB48 BA38
For platform not supporting Intel AMT MEPWROKcan be RN12 TXLOUT1_R LVDSA_DATA0 DDPB_3P
BG14 FDI_LSYNC1 13 BA50
connected to PWROK. FDI_LSYNC1 IV@0X2 1 TXUOUT#7_R TXLOUT2_R LVDSA_DATA1
32 TXUOUT#7 2 AY49
TXUOUT7_R TXLOUT3_R LVDSA_DATA2
32 TXUOUT7 3 4 AV48 Y49
LVDSA_DATA3 DDPC_CTRLCLK
AB49
SYS_PWROK it can be connected to the same source as PWROK on PCH IV@0X2 RN11 DDPC_CTRLDATA
Request PWR to change the 1 2 TXUCLK#_R AP48
32 TXUCLK# LVDSB_CLK#
C 3 4 TXUCLK_R AP47 BE44 C
PWR net +3VPCU to be +3V_PCU instead. 32 TXUCLK LVDSB_CLK DDPC_AUXN
BD44
XDP_DBRST#_R TXUOUT#4_R DDPC_AUXP
10,37 SYS_RST_N T6 J12 PCIE_WAKE# 30,33 AY53 AV40
SYS_RESET# WAKE# TXUOUT#5_R LVDSB_DATA#0 DDPC_HPD
AT49
TXUOUT#6_R LVDSB_DATA#1
AU52 BE40
VR_READY TXUOUT#7_R LVDSB_DATA#2 DDPC_0N
M6 Y1 CLKRUN# 36 AT53 BD40
SYS_PWROK CLKRUN# / GPIO32 LVDSB_DATA#3 DDPC_0P
BF41
TXUOUT4_R DDPC_1N
AY51 BH41
LVDSB_DATA0 DDPC_1P
System Power Management

PCHPWROK R471 PCHPWROK_R B17 TXUOUT5_R AT48 BD38


0_J_4 PWROK TXUOUT6_R LVDSB_DATA1 DDPC_2N
AU50 BC38
TXUOUT7_R LVDSB_DATA2 DDPC_2P
AT51 BB36
R173 MEPWROK SUS_STAT# LVDSB_DATA3 DDPC_3N
K5 P8 TP29 BA36
0_J_4 MEPWROK SUS_STAT# / GPIO61 DDPC_3P

RSV_ICH_LAN_RST# A10 F3 R_ICH_SUSCLK R185 INT_CRT_BLU AA52 U50


LAN_RST# SUSCLK / GPIO62 *0_J_4 ICH_SUSCLK 36 27 INT_CRT_BLU CRT_BLUE DDPD_CTRLCLK
INT_CRT_GRE AB53 U52
27 INT_CRT_GRE INT_CRT_RED CRT_GREEN DDPD_CTRLDATA
27 INT_CRT_RED
AD53
MEM_PWRGD SLP_S5#_R CRT_RED
D9 E4 TP24
DRAMPWROK SLP_S5# / GPIO63
BC46
DDPD_AUXN
27 INT_CRT_DDCCLK V51 BD46
CRT_DDC_CLK DDPD_AUXP
36 ICH_RSMRST# C16 H7 SUSC# 36 27 INT_CRT_DDCDAT V53 AT38
RSMRST# SLP_S4# CRT_DDC_DATA DDPD_HPD
BJ40
SUS_PWR_ACK_R HSYNC_R DDPD_0N
M1 P12 SUSB# 36 27 INT_HSYNC Y53 BG40
SUS_PWR_DN_ACK / GPIO30 SLP_S3# VSYNC_R CRT_HSYNC DDPD_0P
27 INT_VSYNC Y51 BJ38
CRT_VSYNC DDPD_1N
BG38
DDPD_1P

CRT
P5 K8 SLP_M# R167 0_J_4 9/20 上上 BF37
36 ICH_PWRBTN# PWRBTN# SLP_M# DDPD_2N
B DAC_IREF AD48 BH37 B
SLP_M# should not be No Connect even if DAC_IREF DDPD_2P
AB51 BE36
R160 ACIN_R platform does not support M3 this signal can be tied to SLP_S3# signal CRT_IRTN DDPD_3N
36 PCH_ACIN P7 N2 BD36
*0_J_4 ACPRESENT / GPIO31 TP23 R153 DDPD_3P
1K_F_4 IbexPeak-M_R1P0
PM_BATLOW# A6 BJ10
BATLOW# / GPIO72 PMSYNCH PM_SYNC 10

PM_RI# F14 F6 PM_SLP_LAN# TP21


RI# SLP_LAN# / GPIO29
Not support Intel LAN, LAN_RST#
should be pulled down to GND via a IbexPeak-M_R1P0
8.2 kΩ – 10 kΩ resistor.
High --- AC power
Low --- battery

PCH Pull-high/low +3V_S5


+1.5V_SUS DRAMPWROK System PWR_OK
+3V
R465
PM_RI# R215 10K_J_4
CLKRUN# R424 8.2K_J_4 +3V_S5
PM_BATLOW# R460 8.2K_J_4 DELAY_VR_PWRGOOD need PU 2K to +3V.
XDP_DBRST#_R R154 10K_J_4 1.1K_F_4 C222 *0.1U/10V/X7R_4
A
PCIE_WAKE# R213 1K_J_4
PU at power side A

MEM_PWRGD
MEM_PWRGD 10

5
ICH_RSMRST# R476 10K_J_4 PM_SLP_LAN# R176 *10K_J_4 1 VR_READY 9,44
PCHPWROK 4
RSV_ICH_LAN_RST# R463 10K_J_4 SUS_PWR_ACK_R R448 10K_J_4 R464 C458 2
U9
PWROK_EC 32,36
Quanta Computer Inc.

3
VR_READY R165 *10K_J_4 ACIN_R R158 10K_J_4 0.22u/10V/X5R_4 R183 100K_J_4
3K_F_4 TC7SH08FU
PCHPWROK R198 10K_J_4 PROJECT : ZN2
close to R197 Size Document Number Rev
A
PCH (DMI/FDI/VIDEO)
Date: Tuesday, March 16, 2010 Sheet 19 of 49
5 4 3 2 1
5 4 3 2 1

RTC Circuitry
C462 12P/50V_4 IBEX PEAK-M (HDA,JTAG,SATA) 20

2
1
R480
Y6
+VCCRTC
+3VPCU 32.768KHZ U18A
R490 1K_J_4 20K_F_4 10M_J_4

3
4
2 1 R489 RTC_RST# RTC_X1 B13 D33
RTCX1 FWH0 / LAD0 LPC_LAD0 30,36
D46 RB500V C463 12P/50V_4 RTC_X2 D13 B33
RTCX2 FWH1 / LAD1 LPC_LAD1 30,36
C32 LPC_LAD2 30,36
R_3VRTC C468 FWH2 / LAD2
2 1 A32 LPC_LAD3 30,36
D45 RB500V RTC_RST# FWH3 / LAD3
C14
1U/16V_6 RTCRST#
C34
SRTC_RST# FWH4 / LFRAME# LPC_LFRAME# 30,36
D17
D SRTCRST# D
A34 PCH_DRQ#0 TP54

RTC

LPC
SM_INTRUDER# LDRQ0#
R484 +VCCRTC R475 1M_J_4 A16 F34 PCH_DRQ#1 TP28
20K_F_4 INTRUDER# LDRQ1# / GPIO23 R155 10K_J_4 +3V
1K_J_4 R515 SRTC_RST# PCH_INVRMEN A14 AB9
INTVRMEN SERIRQ IRQ_SERIRQ 36
D44 BAS316
TP52
C503
ACZ_BIT_CLK A30
1U/16V_6 HDA_BCLK
Intruder Detect: This signal can SATA0RXN
AK7 SATA_RXN0 29
ACZ_SYNC D29 AK6
be set to disable system if box HDA_SYNC SATA0RXP SATA_TX#0_R C102 0.01U/25V_4
SATA_RXP0 29
AK11 1st SATA HDD
1

detected open. SATA0TXN SATA_TX0_R C103 0.01U/25V_4 SATA_TXN0 29


P1 AK9
SHORT PAD 26 SPKR SPKR SATA0TXP SATA_TXP0 29
JP4 ACZ_RST# C30
HDA_RST#
HDA_SYNC (PCH strap pin) AH6 SATA_RXN1 29
2
1

SATA1RXN
AH5 SATA_RXP1 29
BT1 SATA1RXP SATA_TX#1_R C243 0.01U/25V_4
Internal weak pull-down 26 PCH_AZ_CODEC_SDIN0 G30
HDA_SDIN0 SATA1TXN
AH9
SATA_TXN1 29 SATA ODD
CR2032-SOCKET VCCVRM=>+1.8V (default) AH8 SATA_TX1_R C244 0.01U/25V_4
SATA1TXP SATA_TXP1 29
external pull-up F30
2

HDA_SDIN1
AF11
VCCVRM=>+1.5V R222 *10K_J_4 SATA2RXN
E32 AF9

IHDA
TP31 HDA_SDIN2 SATA2RXP
AF7
R223 *10K_J_4 SATA2TXN
TP30 F32 AF6
HDA_SDIN3 SATA2TXP
AH3
ACZ_SDOUT SATA3RXN
B29 AH1
HDA_SDO SATA3RXP
AF3
SATA3TXN
AF1
HDA_DOCK_EN# SATA3TXP
H32

SATA
HDA_DOCK_EN# / GPIO33
AD9
R219 10K_J_4 PCH_GPIO13 J30 SATA4RXN
+3V_S5 AD8
HDA_DOCK_RST# / GPIO13 SATA4RXP
AD6
SATA4TXN
AD5
SATA4TXP
PCH_JTAG_TCK M3 AD3
TP62 JTAG_TCK SATA5RXN
AD1
PCH_JTAG_TMS SATA5RXP
TP63 K3 AB3
JTAG_TMS SATA5TXN
C AB1 C
PCH_JTAG_TDI SATA5TXP
TP64 K1
JTAG_TDI

JTAG
PCH_JTAG_TDO J2 AF16 SATACOMP
TP65 JTAG_TDO SATAICOMPO R142
HDA Bus TP66
PCH_JTAG_RST# J4
TRST# SATAICOMPI
AF15 37.4_F_4 +1.05V

R468 33_J_4 ACZ_SYNC SPI_CLK_R BA2


26 PCH_AZ_CODEC_SYNC SPI_CLK
SPI_CS0#_R AV3
R469 33_J_4 ACZ_RST# SPI_CS0# R439 10K_J_4
26 PCH_AZ_CODEC_RST# +3V
+3V_S5 R118 10K_J_4 SPI_CS1# AY3 T3
SPI_CS1# SATALED# SATA_ACT# 29,30
R467 33_J_4 ACZ_SDOUT R131 43K_F_4 +3V
26 PCH_AZ_CODEC_SDOUT SPI_SI_R SATA_DET0#
AY1 Y9 TP76
SPI_MOSI SATA0GP / GPIO21

SPI
SPI_SO_R AV1 V1 SATA_DET1# TP77
SPI_MISO SATA1GP / GPIO19 R427 43K_F_4 +3V
R466 33_J_4 ACZ_BIT_CLK
26 PCH_AZ_CODEC_BITCLK PCH Strap Table IbexPeak-M_R1P0

C460 Pin Name Strap description Sampled Configuration ZN2 note


*27P/50V_4
0 = Default (weak pull-down 20K)
SPKR No reboot mode setting PWROK +3V R438 *10K_J_4 SPKR
1 = Setting to No-Reboot mode
Place all series terms close to PCH except for SDIN input
lines,which should be close to source.Placement of R773, R775, 1 = Default (weak pull-up 20K)
R776 & R777 should equal distance to the T split trace point. INIT3_3V Reserved PWROK Should not be pull-down
Basically, keep the same distance from T for all series
termination resistors. 0 = "top-block swap" mode
GNT3# / GPIO55 Top-Block Swap Override PWROK R461 *10K_J_4
1 = Default (weak pull-up 20K) PCI_GNT3# 21

B B

INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up +VCCRTC R477 330K_J_4 PCH_INVRMEN

GNT1# / GPIO51 Boot BIOS Selection 1 [bit-1] PWROK GNT1# GNT0# Boot Location Default weak pull-up on GNT0/1#
[Need external pull-down for LPC BIOS]
1 1 SPI +3V
R195 *1K_J_4
R188 *1K_J_4
PCH SPI 1 0 PCI
R196 *1K_J_4
GNT0# Boot BIOS Selection 0 [bit-0] PWROK PCI_GNT0# 21
R189 *1K_J_4
PCI_GNT1# 21
0 0 LPC
Should not be pull-down
+3V GNT2# / GPIO53 ESI strap (Server only) PWROK
U15 (weak pull-up 20K) USE GPIO PIN
SPI_CS0#_R 1 8
SPI_CLK_R CE# VDD
6
SPI_SI_R SCK R376 *1K_J_4 NV_ALE
5
SI NV_ALE Intel Anti-Theft HDD protection PWROK 0 = Disable (Internal pull-down 32ohm) +1.8V NV_ALE 21
SPI_SO_R R357 SPI_SO 2 7 R356 3.3K_F_4
0_J_4 SO HOLD#
3 4
C396 WP# VSS C397 R110 *1K_J_4 NV_CLE
NV_CLE DMI Termination voltage PWROK weak pull-down 32ohm +1.8V NV_CLE 21
*22P/50V_4 W25X32VSSIG 0.1U/10V/X7R_4

HDA_DOCK_EN#/GPIO33 Flash Descriptor Security PWROK 0 = Override R220 *1K_J_4


+3V R355 3.3K_F_4 +3V R221 *10K_J_4 HDA_DOCK_EN#
1 = Default (weak pull-up 20K)
SPI_MOSI iTPM function Disable MEPWROK 0 = Default (weak pull-down 20K) +3V R378 *1K_J_4 SPI_SI_R

1 = Enable
Should not be pull-up
A HDA_SDO Reserved RSMRST# (weak pull-down 20K)
A

Should not be pull-down +3V_S5 R187 10K_J_4


RSV_GPIO8 22
GPIO8 Reserved RSMRST# (weak pull-up 20K)
GPIO27 On-die PLL Voltage Regulator RSMRST# 0 = Disable
1 = Enable (weak pull-up 20K)
HDA_SYNC
On-die PLL PWR supply select RSMRST# 0 = 1.8V supply (weak pull-down 20K) use defaul (0 = 1.8V supply)
1 = 1.5V supply
Quanta Computer Inc.
GPIO15 Reserved RSMRST# 0 = TLS no Confidentiality
PROJECT : ZN2
+3V_S5 R148 1K_J_4 Size Document Number Rev
(weak pull-down 20K) CR_WAKE# 22
A
1 = TLS Confidentiality
PCH (SATA/RTC/HDA/LPC)
Date: Tuesday, March 16, 2010 Sheet 20 of 49
5 4 3 2 1
5 4 3 2 1

IBEX PEAK-M (PCI,USB,NVRAM) IBEX PEAK-M (PCI-E,SMBUS,CLK) 21


U18E
H40 AY9
AD0 NV_CE#0 U18B
N34 BD1
AD1 NV_CE#1
C44 AP15
AD2 NV_CE#2 RSV_SMBALERT#
A38 BD8 30 PCIE_RXN1 BG30 B9
AD3 NV_CE#3 PERN1 SMBALERT# / GPIO11
C36 30 PCIE_RXP1 BJ30
AD4 C417 PCIE_TXN1_C
0.1U/10V/X7R_4 PERP1 ICH_SMBCLK
J34
AD5 NV_DQS0
AV9 Mini WLAN + BT 30 PCIE_TXN1
BF29
PETN1 SMBCLK
H14 ICH_SMBCLK 9
A40 BG8 C416 PCIE_TXP1_C
0.1U/10V/X7R_4 BH29
AD6 NV_DQS1 30 PCIE_TXP1 PETP1 ICH_SMBDATA
D45 C8 ICH_SMBDATA 9
AD7 SMBDATA
E36 AP7 30 PCIE_RXN2 AW30
AD8 NV_DQ0 / NV_IO0 PERN2
H48 AP6 30 PCIE_RXP2 BA30
AD9 NV_DQ1 / NV_IO1 C121 PCIE_TXN2_C
0.1U/10V/X7R_4 PERP2 RSV_SML0ALERT#
D
E40
AD10 NV_DQ2 / NV_IO2
AT6 Mini TV 30 PCIE_TXN2
BC30
PETN2 SML0ALERT# / GPIO60
J14
D
C40 AT9 C120 PCIE_TXP2_C
0.1U/10V/X7R_4 BD30
AD11 NV_DQ3 / NV_IO3 30 PCIE_TXP2 PETP2 SMB_CLK_ME0
M48 BB1 C6
M45
AD12 NV_DQ4 / NV_IO4
AV6 AU30
SML0CLK For LAN

SMBus
AD13 NV_DQ5 / NV_IO5 33 PCIE_RXN3 PERN3 SMB_DATA_ME0
F53 BB3 33 PCIE_RXP3 AT30 G8
AD14 NV_DQ6 / NV_IO6 C123 PCIE_TXN3_C
0.1U/10V/X7R_4 PERP3 SML0DATA
M40
AD15 NV_DQ7 / NV_IO7
BA4 LAN 33 PCIE_TXN3
AU32
PETN3
PCIE_TXP3_C

NVRAM
M43 BE4 C122 0.1U/10V/X7R_4 AV32
AD16 NV_DQ8 / NV_IO8 33 PCIE_TXP3 PETP3 RSV_SML1ALERT# R411 *0_J_4
J36 BB6 M14
AD17 NV_DQ9 / NV_IO9 SML1ALERT# / GPIO74 SML1ALERT# 22,37
K48 BD6 BA32
AD18 NV_DQ10 / NV_IO10 PERN4 SMB_CLK_ME1 T14
F40 BB7 BB32 E10
AD19 NV_DQ11 / NV_IO11 PERP4 SML1CLK / GPIO58
C42 BC8 BD32
AD20 NV_DQ12 / NV_IO12 PETN4 SMB_DATA_ME1 T15
K46 BJ8 BE32 G12
AD21 NV_DQ13 / NV_IO13 PETP4 SML1DATA / GPIO75
M51 BJ6

PCI-E*
AD22 NV_DQ14 / NV_IO14
J52 BG6 28 PCIE_RXN5 BF33
AD23 NV_DQ15 / NV_IO15 PERN5 CL_CLK1 T8
K51 28 PCIE_RXP5 BH33 T13
AD24 PERP5 CL_CLK1

Controller
L34 BD3 NV_ALE Card Reader C415 PCIE_TXN5_C
0.1U/10V/X7R_4 BG32
AD25 NV_ALE NV_CLE NV_ALE 20 28 PCIE_TXN5 C414 PCIE_TXP5_C
0.1U/10V/X7R_4 PETN5 CL_DATA1 T10
F42 AY6 BJ32 T11
AD26 NV_CLE NV_CLE 20 28 PCIE_TXP5 PETP5 CL_DATA1
J40

Link
AD27 CL_RST1# T7
G46 BA34 T9
AD28 NV_RCOMP R382 32.4_F_4 PERN6 CL_RST1#
F44 AU2 AW34
AD29 NV_RCOMP PERP6
M47 BC34
AD30 PETN6

PCI
H36 AV7 BD34
AD31 NV_RB# PETP6 PEG_CLKREQ#_R R458 *0_J_4
H1 PEG_CLKREQ# 25
PEG_A_CLKRQ# / GPIO47
J50 AY8 AT34
C/BE0# NV_WR#0_RE# PERN7 PEG_A_CLKRQ# PD for FreeRun, due GPU not support.
G42 AY5 AU34
C/BE1# NV_WR#1_RE# PERP7 CLK_PCIE_VGAN_R RP4 1
H47 AU36 AD43 2 0X2
C/BE2# PETN7 CLKOUT_PEG_A_N CLK_PCIE_VGAP_R CLK_PCIE_VGAN 25
G34
C/BE3# NV_WE#_CK0
AV11 AV36
PETP7 CLKOUT_PEG_A_P
AD45 3 4
CLK_PCIE_VGAP 25 Output To MXM
PCI_PIRQA# NV_WE#_CK1
BF5 Note: CLK_PCIE_DMI#_R
G38 BG34 AN4 RP5 1 2 0X2
PIRQA# PCIE port7/8 may not be available on all PCH sku PERN8 CLKOUT_DMI_N

PEG
PCI_PIRQB# CLK_PCIE_DMI_R CLK_PCIE_DMI# 13
H51
PIRQB#
BJ34
PERP8 CLKOUT_DMI_P
AN2 3 4
CLK_PCIE_DMI 13 Output To CPU
PCI_PIRQC# B37 H18 (HM55 support 6port only) BG36
PCI_PIRQD# PIRQC# USBP0N USBP0- 31 PETN8
A44
PIRQD# USBP0P
J18 USBP0+ 31 Rear-USB BJ36
PETP8
A18 AT1 DPCLK_PCH#_R RP14 1 2 0X2
PCI_REQ0# USBP1N USBP1- 31 CLKOUT_DP_N / CLKOUT_BCLK1_N DPCLK_PCH_R DPCLK_PCH# 10
F51
REQ0# USBP1P
C18 USBP1+ 31 Rear-USB CLKOUT_DP_P / CLKOUT_BCLK1_P
AT3 3 4
DPCLK_PCH 10 Output To CPU
PCI_REQ1# A46 N20 AK48
dGPU_SELECT# REQ1# / GPIO50 USBP2N USBP2- 31 CLKOUT_PCIE0N
B45
REQ2# / GPIO52 USBP2P
P20 USBP2+ 31 Side-USB AK47
CLKOUT_PCIE0P

From CLK BUFFER


PCI_REQ3# M53 J20 AW24
C REQ3# / GPIO54 USBP3N USBP3- 31 CLK_PCIE_REQ0# CLKIN_DMI_N CLK_BUF_PCIE_3GPLLN 9 C
USBP3P
L20 USBP3+ 31 Side-USB P9
PCIECLKRQ0# / GPIO73 CLKIN_DMI_P
BA24 CLK_BUF_PCIE_3GPLLP 9
PCI_GNT0# F48 F20 EHCI1
20 PCI_GNT0# PCI_GNT1# GNT0# USBP4N USBP4- 35
20 PCI_GNT1#
K45
GNT1# / GPIO51 USBP4P
G20 USBP4+ 35 Camera Mini WLAN + BT
F36 A20 CLK_PCH_SRC3N_R AM43 AP3
PCI_GNT3# GNT2# / GPIO53 USBP5N USBP5- 30 30 CLK_PCH_SRC3N CLK_PCH_SRC3P_R AM45 CLKOUT_PCIE1N CLKIN_BCLK_N CLK_BUF_BCLKN 9
20 PCI_GNT3#
H53
GNT3# / GPIO55 USBP5P
C20 USBP5+ 30 MiniWLAN 30 CLK_PCH_SRC3P CLKOUT_PCIE1P CLKIN_BCLK_P
AP1 CLK_BUF_BCLKP 9
M22 USBP6-
USBP6N TP23
PCI_PIRQE# B41 N22 USBP6+ CLK_PCIE_REQ3# U4
PIRQE# / GPIO2 USBP6P TP20 30 PCIECLKRQ3# PCIECLKRQ1# / GPIO18
PCI_PIRQF# K53 B21 USBP7- F18
PIRQF# / GPIO3 USBP7N TP53 CLKIN_DOT_96N CLK_BUF_DREFCLKN 9
PCI_PIRQG# A36 D21 USBP7+ Mini TV E18
PIRQG# / GPIO4 USBP7P TP51 CLKIN_DOT_96P CLK_BUF_DREFCLKP 9
PCI_PIRQH# A48 H22 CLK_PCH_SRC1N_R AM47 Intel does not recommend
PIRQH# / GPIO5 USBP8N USBP8- 31 30 CLK_PCH_SRC1N CLK_PCH_SRC1P_RAM48 CLKOUT_PCIE2N leave XTAL25_IN signal as No
USBP8P
J22 USBP8+ 31 Rear-USB 30 CLK_PCH_SRC1P CLKOUT_PCIE2P
USB

K6 E22 AH13 Connect for reliability


PCIRST# USBP9N USBP9- 31 CLK_PCIE_REQ1#_R CLKIN_SATA_N / CKSSCD_N CLK_BUF_DREFSSCLKN 9 concerns.
USBP9P
F22 USBP9+ 31 Dongle 30 PCIECLKRQ1# N4
PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P
AH12 CLK_BUF_DREFSSCLKP 9
PCI_SERR# E44 A22 XTAL25_IN should be pulled to
PCI_PERR# SERR# USBP10N USBP10- 31 GND via a 0-Ω resistor by
E50
PERR# USBP10P
C22 USBP10+ 31 BT LAN
G24 EHCI2 CLK_PCH_SRC5N_R AH42 P41 default.
USBP11N USBP11- 31 33 CLK_PCIE_LOMN CLK_PCH_SRC5P_R CLKOUT_PCIE3N REFCLK14IN CLK_ICH_14M 9
H24 Rear-USB AH41 0_J_4
PCI_IRDY# USBP11P USBP11+ 31 33 CLK_PCIE_LOMP CLKOUT_PCIE3P
A42 L24 C447
PCI_PAR IRDY# USBP12N USBP12- 30 CLK_PCIE_LAN_REQ#_R A8 CLK_PCI_FB
H44
PAR USBP12P
M24 USBP12+ 30 Mini TV 33 CLK_PCIE_LAN_REQ# PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK
J42

2
TP25 PCI_DEVSEL# USBP13-
F46 A24 TP26
PCI_FRAME# DEVSEL# USBP13N USBP13+ Y5
C46 C24 TP27
FRAME# USBP13P XTAL25_IN R409
AM51 AH51 *25MHz
PCI_PLOCK# CLKOUT_PCIE4N XTAL25_IN XTAL25_OUT *1M_J_4
D49 AM53 AH53

1
PLOCK# USB_BIAS CLKOUT_PCIE4P XTAL25_OUT
B25
PCI_STOP# USBRBIAS# CLK_PCIE_REQ4#_R
D41 R470 T16 M9 AF38 XCLK_RCOMP R144 90.9_F_4 +1.05V C446
PCI_TRDY# STOP# 22.6_F_4 PCIECLKRQ4# / GPIO26 XCLK_RCOMP *18P/50V_4
C48 D25
TRDY# USBRBIAS
Card Reader
TP22 ICH_PME# M7 CLK_PCH_SRC2N_R AJ50 T45 CLK_FLEX0 T9
PME# USB_OC0# 28 CLK_PCH_SRC2N CLK_PCH_SRC2P_R CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
OC0# / GPIO59
N16 AJ52
CLKOUT_PCIE5P
No stuff XTAL25_IN and XTAL25_OUT circuitry
PCI_PLTRST# USB_OC1# 28 CLK_PCH_SRC2P
D5 J16 until integrated CG becomes PCH POR.
PLTRST# OC1# / GPIO40 USB_OC2# T13 CLK_PCIE_REQ2#_R CLK_FLEX1 T11
F16 H6 P43

Clock Flex
R455 22_J_4 CLK_LPC_DEBUG_C OC2# / GPIO41 USB_OC3# PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65
N52 L16
30 CLK_LPC_DEBUG CLK_PCI_PCCARD CLKOUT_PCI0 OC3# / GPIO42 USB_OC4#
T19 P53 E14
R178 22_J_4 CLK_PCI_775_C CLKOUT_PCI1 OC4# / GPIO43 USB_OC5# CLK_FLEX2 T12
P46 G16 AK53 T42
36 CLK_PCI_775 CLK_PCI_FB R452 22_J_4 CLK_PCI_FB_C CLKOUT_PCI2 OC5# / GPIO9 USB_OC6# CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
P51 F12 AK51
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7# CLKOUT_PEG_B_P
P48 T15
B CLKOUT_PCI4 OC7# / GPIO14 PEG_B_CLKREQ# B
P13 N50 CLK_FLEX3 T20
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
IbexPeak-M_R1P0
IbexPeak-M_R1P0
PCIECLKRQ{0,3,4,5,6,7}# should have a 10-k pull-up to +V3.3A.
PCIECLKRQ{1,2} should have a
10-k pull-up to +3.3S
Support PCIe 2.0

PEG_A_CLKRQ# PD for FreeRun, due GPU not support.


PCI/USBOC# Pull-up CLK_REQ/Strap Pin
PLTRST# A16 swap override Strap/Top-Block
+3V_S5 +3V_S5
Swap Override jumper SMBus/Pull-up
RP19 Low = A16 swap
TP68 USB_OC7# 6 5 R201 10K_J_4 CLK_PCIE_REQ0# Low to enable clock request override/Top-Block
TP69 USB_OC6# 7 4 USB_OC0# TP72 R437 10K_J_4 CLK_PCIE_REQ3# R440 *10K_J_4 PCI_GNT3# +3V_S5
USB_OC5# USB_OC1# CLK_PCIE_REQ4#_R
Swap Override enabled
TP70 8 3 TP73 R150 10K_J_4
TP71 USB_OC4# 9 2 USB_OC2# TP74 R217 10K_J_4 PEG_B_CLKREQ# R218 *10K_J_4 High = Default R462 10K_J_4 RSV_SMBALERT#
Add Buffers as needed for 10 1 USB_OC3# TP75 R200 *10K_J_4 CLK_PCIE_LAN_REQ#_R R197 10K_J_4 R216 10K_J_4 RSV_SML0ALERT#
+3V_S5 +3V_S5 R457 *10K_J_4 PEG_CLKREQ#_R R416 10K_J_4 RSV_SML1ALERT#
Loading and fanout concerns. ICH_SMBCLK
8.2K_10P8R Boot BIOS Strap R214 2.2K_J_4
R211 2.2K_J_4 ICH_SMBDATA
GNT0# GNT1# Boot BIOS Location R199 2.2K_J_4 SMB_CLK_ME0
C221 R212 2.2K_J_4 SMB_DATA_ME0
+3V 0 0 LPC R204 2.2K_J_4 SMB_CLK_ME1
0.1U/10V/X7R_4 RP10 R225 2.2K_J_4 SMB_DATA_ME1
PCI_REQ0# 6 5 0 1 Reserved (NAND)
5

PCI_PIRQB# 7 4 PCI_PIRQH#
PCI_PLTRST# 2 PCI_REQ3# 8 3 PCI_TRDY# 1 0 PCI
4 PCI_PIRQD# 9 2 PCI_FRAME# R179 10K_J_4 CLK_PCIE_REQ2#_R
PLTRST# 10,22,28,30,33 PCI_REQ1# +3V 1 1 SPI
1 +3V 10 1
A A
U11 R208 8.2K_10P8R R441 10K_J_4 CLK_PCIE_REQ1#_R R449 *10K_J_4
3

TC7SH08FU Danbury Technology Enabled


100K_J_4 +3V Low to enable clock request R454 10K_J_4 PEG_CLKREQ#_R
+3V High = Enable
RP9 NV_ALE
PCI_PLOCK# 6 5 Low = Disable
PCI_SERR# 7 4 PCI_PERR# R472 10K_J_4 dGPU_SELECT#
PCI_DEVSEL# 8 3 PCI_PIRQC# R473 8.2K_J_4 PCI_PIRQE#
PCI_STOP# 9 2 PCI_IRDY# R459 8.2K_J_4 PCI_PIRQF# DMI Termination Voltage
+3V 10 1 PCI_PIRQA# R474 8.2K_J_4 PCI_PIRQG# Quanta Computer Inc.
Set to Vcc when LOW
8.2K_10P8R NV_CLE PROJECT :ZN2
Set to Vcc/2 when HIGH
Size Document Number Rev
A
PCH (PCIE/USB/CLK/NV)
Date: Tuesday, March 16, 2010 Sheet 21 of 49
5 4 3 2 1
5 4 3 2 1

IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)


GPU RST#
22
+3V

C203 *0.1U/10V/X7R_4

5
1 PLTRST# 10,21,28,30,33
25 GPU_RST# 4
2 dGPU_HOLD_RST#
D U18F D

3
U19 R421
TP78 BMBUSY# Y3 AH45 TP_PCH_PCIE6N TP14 *TC7SH08FU *100K_J_4
BMBUSY# / GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P AH46 TP_PCH_PCIE6P TP12
SIO_EXT_SMI# C38
36 SIO_EXT_SMI# TACH1 / GPIO1
To EC
SIO_EXT_SCI# D37
36 SIO_EXT_SCI# TACH2 / GPIO6
AF48 TP_PCH_PCIE7N TP15
CLKOUT_PCIE7N

MISC
change board_id0 to GPIO7 at 6/1 BOARD_ID0 J32 AF47 TP_PCH_PCIE7P TP13
TACH3 / GPIO7 CLKOUT_PCIE7P
RSV_GPIO8 F10
20 RSV_GPIO8 GPIO8 R425 0_J_4
36 SWI# K9 U2 SIO_A20GATE 36
LAN_PHY_PWR_CTRL / GPIO12 A20GATE
CR_WAKE# T7
20 CR_WAKE# GPIO15
TP79 dGPU_HOLD_RST# AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLKN 10
Output To CPU
F38 AM1
25 dGPU_PWROK TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLKP 10
GPIO22 Y7 BG10 PCH_PECI_R R365
SCLOCK / GPIO22 PECI H_PECI 10,36

GPIO
*0_J_4
TP80 H10 GPIO24 RCIN# T1 SIO_RCIN# 36
AB12 BE10
28 CR_CPPE# GPIO27 PROCPWRGD H_PWRGOOD 10 GPIO Pull-up/Pull-down

CPU
TP_PCH_GPIO28 V13 BD10 PCH_THRMTRIP#_R R93 56_F_4
32 WRITE_EDID_ROM GPIO28 THRMTRIP# PCH_THERMTRIP# 10
STP_PCI# M11 R94 56_F_4 +1.1V_VTT +3V_S5
STP_PCI# / GPIO34
C TP16 V6 SATACLKREQ# / GPIO35 C

TP81 dGPU_PWR_EN# AB7 BA22 TP1_PCH TP10 TP_PCH_GPIO28 R175 10K_J_4


dGPU_PWR_EN# should be stable SATA2GP / GPIO36 TP1 CLR_BIOS_DATA R453 10K_J_4
before dGPU_VRON enable dGPU_PRSNT# AB13 AW22 TP2_PCH TP11 CLR_PASSWD R456 10K_J_4
10,25,36 dGPU_PRSNT# SATA3GP / GPIO37 TP2 GPIO57 R190 *10K_J_4
GPIO38 V3 BB22 SWI# R203 *10K_J_4
SLOAD / GPIO38 TP3
P3 AY45 +3V
36 WP# SDATAOUT0 / GPIO39 TP4
H3 AY46 SIO_EXT_SMI# R478 10K_J_4
29 CLR_BIOS_DATA PCIECLKRQ6# / GPIO45 TP5 SIO_EXT_SCI# R479 10K_J_4
29 CLR_PASSWD F1 AV43
PCIECLKRQ7# / GPIO46 TP6 dGPU_PWR_EN# R134 10K_J_4
SV_SET_UP AB6 AV45
SDATAOUT1 / GPIO48 TP7 remove GPIO7 PU at 6/1
TP82 SATA5GP AA4 AF13
SATA5GP / GPIO49 TP8 +3V
GPIO57 F8 M18
R406 GPIO57 TP9 SIO_RCIN# R428 10K_J_4
21,37 SML1ALERT# *0_J_4 SIO_A20GATE R426 10K_J_4
TP10 N18
EC suggestion use GPIO49 for FAN control dGPU_HOLD_RST# R415 *10K_J_4
A4 AJ24 SATA5GP R410 10K_J_4
VSS_NCTF_1 TP11 GPIO22 R139 10K_J_4
A49
NCTF

VSS_NCTF_2
RSVD

SATA5GP / GPIO49 / TEMP_ALERT# is used to A5 AK41 8/5:Default Pull High dGPU_PRSNT# R130 10K_J_4
VSS_NCTF_3 TP12
A50
alert for EC when CPU or Graph/Memory A52
VSS_NCTF_4
AK42 STP_PCI# R202 10K_J_4
VSS_NCTF_5 TP13
controllers' temperature go out of limit. A53
VSS_NCTF_6
B2 M32 GPIO38 R423 10K_J_4
So connecting GPIO49 to EC and avoid this B4
VSS_NCTF_7 TP14
pin to be used for other purpose VSS_NCTF_8 BMBUSY# R420 8.2K_J_4
B B52 N32 B
VSS_NCTF_9 TP15
B53
VSS_NCTF_10 SV_SET_UP R133 10K_J_4
BE1 M30
VSS_NCTF_11 TP16
BE53
VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
BF53 SV_SET_UP 1-X High = Strong (Default)
VSS_NCTF_14
BH1 H12
VSS_NCTF_15 TP18
BH2 VSS_NCTF_16
BH52 AA23
VSS_NCTF_17 TP19 GPIO57 stuff PD and not stuff PU for Intel suggestion at 6/1
BH53
VSS_NCTF_18
BJ1 AB45
VSS_NCTF_19 NC_1 GPIO57 R191 10K_J_4
BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
BJ49
VSS_NCTF_22
BJ5 AB42
VSS_NCTF_23 NC_3
BJ50 VSS_NCTF_24
BJ52 AB41
VSS_NCTF_25 NC_4 R210 *10K_J_4 BOARD_ID0 R224 10K_J_4
BJ53 VSS_NCTF_26 +3V_S5
D1 VSS_NCTF_27 NC_5 T39
D2
VSS_NCTF_28
D53 VSS_NCTF_29
E1 P6 TP_INT3_3V
VSS_NCTF_30 INIT3_3V# TP17
E53
VSS_NCTF_31
C10
TP24
Integrated Clock Chip Enable
IbexPeak-M_R1P0
High = Discrete
BOARD_ID0
Low = SW
High = Disable
A RSV_GPIO8 A
Low = Enable

Quanta Computer Inc.


PROJECT :ZN2
Size Document Number Rev
A
PCH (GPIO/CPU)
Date: Tuesday, March 16, 2010 Sheet 22 of 49
5 4 3 2 1
5 4 3 2 1

IBEX PEAK-M (POWER)


23
VCCACLK= 52mA(15mils) U18J POWER
VCCIO = 3.062A(150mils)
R135 0_J_8 +1.05V_VCCCORE_ICHAB24
U18G POWER +VCCA_DAC_1_2
VCCADAC= 69mA(15mils)
L37
+1.05V L10
C189
*10uh_8 +V1.1LAN_VCCA_CLK
*10U/6.3V/X5R_6
AP51
VCCACLK[1] VCCIO[5]
V24 +1.05V
+1.05V AE50 +3V V26
R129 0_J_8 VCCCORE[1] VCCADAC[1] BKP1608HS181T_6_1.5A C192 *1U/6.3V_4 VCCIO[6] C186 1U/10V_4
AB26 AP53 Y24
VCCCORE[2] VCCACLK[2] VCCIO[7]
AB28 AE52 Y26
C179 1U/10V_4 VCCCORE[3] VCCADAC[2] C448 C456 C454 VCCIO[8]
VCCCORE(+1.05V) = 1.432A(80mils) AD26
VCCCORE[4]
VCCLAN = 320mA(30mils) VCCSUS3_3 = 0.163A(20mils)

CRT
AD28 AF53 +1.05V R149 +1.05V_VCCAUX AF23 V28 +3V_S5_VCCPUSB R209 +3V_S5
D C182 10U/6.3V_6 VCCCORE[5] VSSA_DAC[1] 0.01U/25V_4 10U/6.3V_6 0.1U/16V_4 *0_F_6 VCCLAN[1] VCCSUS3_3[1] 0_F_6 D
AF26 U28
VCCCORE[6] VCCSUS3_3[2]

VCC CORE
AF28 AF51 If integrated LAN is not used: AF24 U26 C212 C209 C197
VCCCORE[7] VSSA_DAC[2] Recommend to connect LAN_RST# to GND via an R156 VCCLAN[2] VCCSUS3_3[3]
AF30 VCCALVDS= 1mA U24
VCCCORE[8] R147 8.2-k to 10-k pull-down resistor. VCCSUS3_3[4] 0.022U/16V_4 0.1U/16V_4
AF31 +3V P28
VCCCORE[9] 0_J_4 Connect the VccLAN pins on PCH directly to TP_PCH_VCCDSW VCCSUS3_3[5] 0.1U/16V_4
AH26 Y20 P26
VCCCORE[10] GND DCPSUSBYP VCCSUS3_3[6]
AH28 N28
VCCCORE[11] R145 C175 C191 VCCSUS3_3[7]
AH30 N26
VCCCORE[12] *0_J_4 0.1U/16V_4 0_F_6 VCCSUS3_3[8]
AH31 AH38 AD38 M28
VCCCORE[13] VCCALVDS 0.1U/16V_4 VCCME[1] VCCSUS3_3[9]
AJ30 M26
VCCCORE[14] VCCSUS3_3[10]
AJ31 AH39 AD39 L28

USB
VCCCORE[15] VSSA_LVDS VCCME[2] VCCSUS3_3[11]
L26
VCCSUS3_3[12]
VCCTX_LVDS= 59mA(15mils) AD41
VCCME[3] VCCSUS3_3[13]
J28
AP43 VCCTX_LVDS L9 +1.8V J26
VCCTX_LVDS[1] 0.1uH_8 VCCSUS3_3[14]
AP45 AF43 H28
VCCTX_LVDS[2] C170 C165 C168 VCCME[4] VCCSUS3_3[15]
AT46 H26

LVDS
R143 +1.05V_PCH_VCCDPLL_EXP VCCTX_LVDS[3] R137 VCCSUS3_3[16]
+1.05V AK24 AT45 VCCME(+1.05V) = 1.849A(100mils) AF41 G28
0_F_6 VCCIO[24] VCCTX_LVDS[4] 0.01U/25V_4 0.1U/16V_4 10U/6.3V_6 *0_J_4 VCCME[5] VCCSUS3_3[17]
G26
R162 +1.05V_VCCEPW VCCSUS3_3[18]
+1.05V AF42 F28
L32 *1uH_6 +V1.1LAN_VCCAPLL_EXP 0_J_8 VCCME[6] VCCSUS3_3[19]
40mA(15mils) +1.05V BJ24
VCCAPLLEXP VCCSUS3_3[20]
F26
AB34 R163 C200 22U/6.3V_8 V39 E28
C403 *10U/6.3V/X5R_6 VCC3_3[2] 0_J_8 VCCME[7] VCCSUS3_3[21]

Clock and Miscellaneous


E26
C201 22U/6.3V_8 VCCSUS3_3[22]
AN20
VCCIO[25] VCC3_3[3]
AB35 VCC3_3 = 357mA(30mils) V41
VCCME[8] VCCSUS3_3[23]
C28
AN22 C26

HVCMOS
VCCIO[26] +3V_VCC_GIO R164 C198 1U/10V_4 VCCSUS3_3[24]
AN23 AD35 +3V V42 B27
VCCIO[27] VCC3_3[4] 0_F_6 VCCME[9] VCCSUS3_3[25]
AN24 A28
VCCIO[28] C195 C187 1U/10V_4 VCCSUS3_3[26]
AN26 Y39 A26
VCCIO[29] VCCME[10] VCCSUS3_3[27]
VCCIO = 3.062A(150mils) AN28
VCCIO[30]
+1.05V BJ26 0.1U/16V_4 Y41 U23
VCCIO[31] VCCME[11] VCCSUS3_3[28]
BJ28
VCCIO[32]
AT26 Y42 V23 +1.05V
VCCIO[33] VCCME[12] VCCIO[56]
AT28 V5REF_SUS< 1mA
VCCIO[34] R229 100_F_4
AU26 F24 +5V_S5
C C159 1U/10V_4 VCCIO[35] V5REF_SUS C
AU28 VCCVRM= 196mA(15mils)
VCCIO[36] +VCCRTCEXT C230 D15 RB500V-40
AV26 V9 +3V_S5
C194 1U/10V_4 VCCIO[37] +VCCVRM R96 C174 0.1U/16V_4 DCPRTC 1U/16V_6
AV28 AT24 +V1.5S_1.8S
VCCIO[38] VCCVRM[2] 0_F_6
AW26 V5REF< 1mA
C193 1U/10V_4 VCCIO[39] R194 100_F_4
AW28 K49 +5V
VCCIO[40] V5REF

DMI
BA26 AT16 +VCCDM R112 0_J_4 +1.1V_VTT VCCDMI= 61mA(15mils) +V1.5S_1.8S AU24

PCI/GPIO/LPC
C196 1U/10V_4 VCCIO[41] VCCDMI[1] VCCVRM[3] D43 RB500V-40
BA28 +3V
VCCIO[42] R111 *0_J_4 C213
BB26 AU16 +1.05V J38
C204 10U/6.3V_6 VCCIO[43] VCCDMI[2] VCC3_3[8] 1U/16V_6
BB28 BB51
VCCIO[44] C152 +V1.1LAN_VCCA_A_DPL VCCADPLLA[1]
BC26
VCCIO[45]
68mA(15mils) BB53
VCCADPLLA[2] VCC3_3[9]
L38
PCI E*

BC28
VCCIO[46] 1U/10V_4 +3V_VCCPPCI R177
BD26 M36 +3V
VCCIO[47] +V1.1LAN_VCCA_B_DPL VCC3_3[10] 0_F_6
BD28
VCCIO[48]
69mA(15mils) BD51
VCCADPLLB[1]
BE26 AM16 BD53 N36 VCC3_3 = 0.357A(30mils)
VCCIO[49] VCCPNAND[1] VCCADPLLB[2] VCC3_3[11]
BE28
VCCIO[50] VCCPNAND[2]
AK16 VCCPNAND= 156mA(15mils)
BG26 AK20 +1.05V AH23 P36 C208
VCCIO[51] VCCPNAND[3] VCCPNAND R109 VCCIO[21] VCC3_3[12] 0.1U/16V_4
BG28 AK19 +1.8V AJ35
VCCIO[52] VCCPNAND[4] 0_J_8 VCCIO[22]
BH27
VCCIO[53] VCCPNAND[5]
AK15 VCCIO = 3.062A(150mils) AH35
VCCIO[23] VCC3_3[13]
U35
AK13 C172 C180 1U/10V_4
VCCPNAND[6] C185 1U/10V_4
VRM enable by strap pin GPIO27 AN30
VCCIO[54] VCCPNAND[7]
AM12 AF34
VCCIO[2]
NAND / SPI

AN31 AM13 0.1U/16V_4 C188 1U/10V_4 AD13 +3V


which supply clean 1.05V for VCCIO[55] VCCPNAND[8]
AM15 AH34
VCC3_3[14]
[VCCACLK,VCCAPLLEXP,VCCFDIPLL,VCCSATAPLL] VCCPNAND[9] VCCIO[3] C184
+3V AN35 AF32 0.1U/16V_4 31mA(15mils)
VCC3_3[1] VCCIO[4]
AK3
C167 0.1U/16V_4 +VCCSST VCCSATAPLL[1] +V1.1LAN_VCCAPLL L36 *10uh_8
V12 AK1 +1.05V
DCPSST VCCSATAPLL[2]
37mA(15mils) +V1.5S_1.8S AT22
VCCVRM[1]
VCCME3_3= 85mA(15mils) C444 C445
+1.05V L33 *1uH_6 +V1.1LAN_VCCAPLL_FDI BJ18 AM8 *1U/6.3V_4 *10U/6.3V/X5R_6
VCCFDIPLL VCCME3_3[1] +3V_VCCME_SPI R105 +V1.1LAN_INT_VCCSUS
VCCME3_3[2]
AM9 +3V Y22
DCPSUS
VCCIO = 3.062A(150mils)
FDI

+1.05V AM23 AP11 0_F_6 C202 0.1U/16V_4 AH22 +1.05V


C404 VCCIO[1] VCCME3_3[3] C158 VCCIO[9]
AP9
B *10U/6.3V/X5R_6 VCCME3_3[4] B
0.1U/16V_4 P18 AT20 +V1.5S_1.8S C205
VCCSUS3_3[29] VCCVRM[4] 1U/10V_4
VCCSUS3_3 = 163mA(20mils)
IbexPeak-M_R1P0 +3V_S5 R205 +3V_S5_VCCPSUS U19

SATA
VCCSUS3_3[30]

PCI/GPIO/LPC
0_F_6 AH19
C216 0.1U/16V_4 VCCIO[10]
U20
VCCSUS3_3[31]
AD20
VCCIO[11]
U22
VCCSUS3_3[32]
AF22
VCCIO[12]
VCC3_3 = 0.357A(30mils) VCCIO[13]
AD19
+3V R146 +3V_VCCPCORE V15 AF20
0_F_6 VCC3_3[5] VCCIO[14]
VCCVRM=196mA(15mils) HDA_SYNC (PCH strap pin) VCCIO[15]
AF19
C199 V16 AH20
R95 VCC3_3[6] VCCIO[16]
+1.8V +V1.5S_1.8S Internal weak pull-down
0_F_6 VCCVRM=>+1.8V (default) 0.1U/16V_4 Y16 AB19
C164 C162 VCC3_3[7] VCCIO[17]
external pull-up AB20
VCCIO[18]
AB22
0.1U/16V_4 0.1U/16V_4 VCCVRM=>+1.5V VCCIO[19]
V_CPU_IO >1mA(15mils) AD22
R361 +VTT_VCCPCPU VCCIO[20]
+1.1V_VTT AT18
V_CPU_IO[1]
VCCME = 1.849A(100mils)
0_F_6 AA34 +1.05V_VCCEPW

CPU
C402 4.7U/10V_8 VCCME[13]
Y34
C110 0.1U/16V_4 VCCME[14]
AU18 Y35
C160 0.1U/16V_4 V_CPU_IO[2] VCCME[15]
AA35
VCCME[16]
VCCRTC= 2mA(15mils)

RTC
+VCCRTC A12 L30 +V3.3A_1.5A_HDA_IO R171 +3V_S5
VCCRTC VCCSUSHDA

HDA
0_J_4
+1.05V L29 10uh_8 +V1.1LAN_VCCA_A_DPL C459 C457 VCCSUSHDA= 6mA(15mils)
IbexPeak-M_R1P0 C206
C406 + C420 0.1U/16V_4 0.1U/16V_4 1U/10V_4
220U/2.5V_3528 1U/10V_4
A A

L30 10uh_8 +V1.1LAN_VCCA_B_DPL

C407 + C419
220U/2.5V_3528 1U/10V_4

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
PCH (POWER)
Date: Tuesday, March 16, 2010 Sheet 23 of 49
5 4 3 2 1
5 4 3 2 1

24
IBEX PEAK-M (GND)
U18I
U18H AY7 H49
VSS[159] VSS[259]
AB16 VSS[0] B11 VSS[160] VSS[260] H5
B15 VSS[161] VSS[261] J24
D AA19 VSS[1] VSS[80] AK30 B19 VSS[162] VSS[262] K11 D
AA20 VSS[2] VSS[81] AK31 B23 VSS[163] VSS[263] K43
AA22 VSS[3] VSS[82] AK32 B31 VSS[164] VSS[264] K47
AM19 VSS[4] VSS[83] AK34 B35 VSS[165] VSS[265] K7
AA24 VSS[5] VSS[84] AK35 B39 VSS[166] VSS[266] L14
AA26 VSS[6] VSS[85] AK38 B43 VSS[167] VSS[267] L18
AA28 VSS[7] VSS[86] AK43 B47 VSS[168] VSS[268] L2
AA30 VSS[8] VSS[87] AK46 B7 VSS[169] VSS[269] L22
AA31 VSS[9] VSS[88] AK49 BG12 VSS[170] VSS[270] L32
AA32 VSS[10] VSS[89] AK5 BB12 VSS[171] VSS[271] L36
AB11 VSS[11] VSS[90] AK8 BB16 VSS[172] VSS[272] L40
AB15 VSS[12] VSS[91] AL2 BB20 VSS[173] VSS[273] L52
AB23 VSS[13] VSS[92] AL52 BB24 VSS[174] VSS[274] M12
AB30 VSS[14] VSS[93] AM11 BB30 VSS[175] VSS[275] M16
AB31 VSS[15] VSS[94] BB44 BB34 VSS[176] VSS[276] M20
AB32 VSS[16] VSS[95] AD24 BB38 VSS[177] VSS[277] N38
AB39 VSS[17] VSS[96] AM20 BB42 VSS[178] VSS[278] M34
AB43 VSS[18] VSS[97] AM22 BB49 VSS[179] VSS[279] M38
AB47 VSS[19] VSS[98] AM24 BB5 VSS[180] VSS[280] M42
AB5 VSS[20] VSS[99] AM26 BC10 VSS[181] VSS[281] M46
AB8 VSS[21] VSS[100] AM28 BC14 VSS[182] VSS[282] M49
AC2 VSS[22] VSS[101] BA42 BC18 VSS[183] VSS[283] M5
AC52 VSS[23] VSS[102] AM30 BC2 VSS[184] VSS[284] M8
AD11 VSS[24] VSS[103] AM31 BC22 VSS[185] VSS[285] N24
AD12 VSS[25] VSS[104] AM32 BC32 VSS[186] VSS[286] P11
AD16 VSS[26] VSS[105] AM34 BC36 VSS[187] VSS[287] AD15
AD23 VSS[27] VSS[106] AM35 BC40 VSS[188] VSS[288] P22
AD30 VSS[28] VSS[107] AM38 BC44 VSS[189] VSS[289] P30
AD31 VSS[29] VSS[108] AM39 BC52 VSS[190] VSS[290] P32
AD32 VSS[30] VSS[109] AM42 BH9 VSS[191] VSS[291] P34
AD34 VSS[31] VSS[110] AU20 BD48 VSS[192] VSS[292] P42
AU22 VSS[32] VSS[111] AM46 BD49 VSS[193] VSS[293] P45
C C
AD42 VSS[33] VSS[112] AV22 BD5 VSS[194] VSS[294] P47
AD46 VSS[34] VSS[113] AM49 BE12 VSS[195] VSS[295] R2
AD49 VSS[35] VSS[114] AM7 BE16 VSS[196] VSS[296] R52
AD7 VSS[36] VSS[115] AA50 BE20 VSS[197] VSS[297] T12
AE2 VSS[37] VSS[116] BB10 BE24 VSS[198] VSS[298] T41
AE4 VSS[38] VSS[117] AN32 BE30 VSS[199] VSS[299] T46
AF12 VSS[39] VSS[118] AN50 BE34 VSS[200] VSS[300] T49
Y13 VSS[40] VSS[119] AN52 BE38 VSS[201] VSS[301] T5
AH49 VSS[41] VSS[120] AP12 BE42 VSS[202] VSS[302] T8
AU4 VSS[42] VSS[121] AP42 BE46 VSS[203] VSS[303] U30
AF35 VSS[43] VSS[122] AP46 BE48 VSS[204] VSS[304] U31
AP13 VSS[44] VSS[123] AP49 BE50 VSS[205] VSS[305] U32
AN34 VSS[45] VSS[124] AP5 BE6 VSS[206] VSS[306] U34
AF45 VSS[46] VSS[125] AP8 BE8 VSS[207] VSS[307] P38
AF46 VSS[47] VSS[126] AR2 BF3 VSS[208] VSS[308] V11
AF49 VSS[48] VSS[127] AR52 BF49 VSS[209] VSS[309] P16
AF5 VSS[49] VSS[128] AT11 BF51 VSS[210] VSS[310] V19
AF8 VSS[50] VSS[129] BA12 BG18 VSS[211] VSS[311] V20
AG2 VSS[51] VSS[130] AH48 BG24 VSS[212] VSS[312] V22
AG52 VSS[52] VSS[131] AT32 BG4 VSS[213] VSS[313] V30
AH11 VSS[53] VSS[132] AT36 BG50 VSS[214] VSS[314] V31
AH15 VSS[54] VSS[133] AT41 BH11 VSS[215] VSS[315] V32
AH16 VSS[55] VSS[134] AT47 BH15 VSS[216] VSS[316] V34
AH24 VSS[56] VSS[135] AT7 BH19 VSS[217] VSS[317] V35
AH32 VSS[57] VSS[136] AV12 BH23 VSS[218] VSS[318] V38
AV18 VSS[58] VSS[137] AV16 BH31 VSS[219] VSS[319] V43
AH43 VSS[59] VSS[138] AV20 BH35 VSS[220] VSS[320] V45
AH47 VSS[60] VSS[139] AV24 BH39 VSS[221] VSS[321] V46
AH7 VSS[61] VSS[140] AV30 BH43 VSS[222] VSS[322] V47
AJ19 VSS[62] VSS[141] AV34 BH47 VSS[223] VSS[323] V49
AJ2 VSS[63] VSS[142] AV38 BH7 VSS[224] VSS[324] V5
B AJ20 AV42 C12 V7 B
VSS[64] VSS[143] VSS[225] VSS[325]
AJ22 VSS[65] VSS[144] AV46 C50 VSS[226] VSS[326] V8
AJ23 VSS[66] VSS[145] AV49 D51 VSS[227] VSS[327] W2
AJ26 VSS[67] VSS[146] AV5 E12 VSS[228] VSS[328] W52
AJ28 VSS[68] VSS[147] AV8 E16 VSS[229] VSS[329] Y11
AJ32 VSS[69] VSS[148] AW14 E20 VSS[230] VSS[330] Y12
AJ34 VSS[70] VSS[149] AW18 E24 VSS[231] VSS[331] Y15
AT5 VSS[71] VSS[150] AW2 E30 VSS[232] VSS[332] Y19
AJ4 VSS[72] VSS[151] BF9 E34 VSS[233] VSS[333] Y23
AK12 VSS[73] VSS[152] AW32 E38 VSS[234] VSS[334] Y28
AM41 VSS[74] VSS[153] AW36 E42 VSS[235] VSS[335] Y30
AN19 VSS[75] VSS[154] AW40 E46 VSS[236] VSS[336] Y31
AK26 VSS[76] VSS[155] AW52 E48 VSS[237] VSS[337] Y32
AK22 VSS[77] VSS[156] AY11 E6 VSS[238] VSS[338] Y38
AK23 VSS[78] VSS[157] AY43 E8 VSS[239] VSS[339] Y43
AK28 VSS[79] VSS[158] AY47 F49 VSS[240] VSS[340] Y46
F5 VSS[241] VSS[341] P49
IbexPeak-M_R1P0 G10 Y5
VSS[242] VSS[342]
G14 VSS[243] VSS[343] Y6
G18 VSS[244] VSS[344] Y8
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 VSS[247] VSS[347] AD51
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
H30 VSS[255] VSS[355] AK45
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

IbexPeak-M_R1P0
Quanta Computer Inc.
PROJECT :ZN2
Size Document Number Rev
A
PCH (GND)
Date: Tuesday, March 16, 2010 Sheet 24 of 49
5 4 3 2 1
5 4 3 2 1

MXM Module 25
6/25 Change CN22 pin define and footprint at C test.
At 11/21
update MXM footprint to mxm-mm70-314-310b1-1-270p

VIN_MXM 7~20V CN14B

VIN_MXM
CN14A
Check Footprint and P/N LVDS_MXM_UCLK# IV@0X2 1 2 RN6 LVDS1_CLK2- 169
LVDS_UCLK# DP_A_AUX#
277
LVDS_MXM_UCLK 3 4 LVDS1_CLK2+ 171 279
LVDS_UCLK DP_A_AUX LVDS_MXM_UTX0# IV@0X2 1 RN17 LVDS1_A4-
2
E1 E2 LVDS1_A4- 193 253 LVDS_MXM_UTX0 3 4 LVDS1_A4+
PWR_SRC PWR_SRC LVDS1_A5- LVDS_UTX0# DP_A_L0# LVDS_MXM_UTX1# IV@0X2 1 RN18 LVDS1_A5-
E3 E4 187 259 2
PWR_SRC PWR_SRC LVDS_UTX1# DP_A_L1#

Upper-CH

DP-A
E5 E6 LVDS1_A6- 181 265 LVDS_MXM_UTX1 3 4 LVDS1_A5+
10Amp E7
PWR_SRC PWR_SRC
E8 LVDS1_A7- 175
LVDS_UTX2# DP_A_L2#
271
PWR_SRC PWR_SRC LVDS_UTX3# DP_A_L3#
E9
PWR_SRC PWR_SRC
E10 MXM3.0 n-Vidia AMD LVDS_MXM_UTX2# IV@0X2 1 RN8 LVDS1_A6-
E11 E12 2
PWR_SRC PWR_SRC LVDS1_A4+ LVDS_MXM_UTX2 LVDS1_A6+
E13
PWR_SRC PWR_SRC
E14 LVDS LVDS LVDS/Int. DP 195
LVDS_UTX0 DP_A_L0
255 3 4
D E15 E16 LVDS1_A5+ 189 261 LVDS_MXM_UTX3# IV@0X2 1 2 RN7 LVDS1_A7- D
PWR_SRC PWR_SRC LVDS1_A6+ LVDS_UTX1 DP_A_L1 LVDS_MXM_UTX3 LVDS1_A7+
E17
PWR_SRC PWR_SRC
E18 DP_D N/A X 183
LVDS_UTX2 DP_A_L2
267 3 4
LVDS1_A7+ 177 273
LVDS_UTX3 DP_A_L3

LVDS
GND
E20 dGPU_PRSNT# Sku DP_A HDMI HDMI
E22 276
GND LVDS_MXM_LCLK# IV@0X2 1 RN16 LVDS1_CLK1- DP_A_HPD
E19
GND GND
E24 Low MXM DP_C Ext. DP/DVI Ext. DP/DVI 2 176
LVDS_LCLK#
E21 E26 LVDS_MXM_LCLK 3 4 LVDS1_CLK1+ 178
GND GND LVDS_LCLK LVDS_MXM_LTX0# IV@0X2 1 RN5 LVDS1_A0-
E23
GND GND
E28 High WO/ MXM DP_B N/A N/A DP_B_AUX#
270 2
E25 E30 LVDS1_A0- 200 272 LVDS_MXM_LTX0 3 4 LVDS1_A0+
GND GND LVDS1_A1- LVDS_LTX0# DP_B_AUX LVDS_MXM_LTX1# IV@0X2 1 RN4 LVDS1_A1-
E27 E32 194 2
GND GND LVDS_LTX1#

Lower-CH
E29 E34 LVDS1_A2- 188 246 LVDS_MXM_LTX1 3 4 LVDS1_A1+
GND GND LVDS1_A3- LVDS_LTX2# DP_B_L0#

DP-B
E31 E36 182 252
GND GND LVDS_LTX3# DP_B_L1#
E33 258
GND DP_B_L2# LVDS_MXM_LTX2# IV@0X2 1 RN14 LVDS1_A2-
E35 2 dGPU_PRSNT# 10,22,36 264 2
GND PRSNT_R# R174 *10K_J_4 LVDS1_A0+ DP_B_L3# LVDS_MXM_LTX2 LVDS1_A2+
281 +3V_MXM 202 3 4
PRSNT_L# LVDS1_A1+ LVDS_LTX0 LVDS_MXM_LTX3# IV@0X2 1 RN15 LVDS1_A3-
196 2
+5V_MXM R180 *0_J_4 LVDS1_A2+ LVDS_LTX1 LVDS_MXM_LTX3 LVDS1_A3+
1
5VRUN PEX_STD_SW#
19 PEX_Swing adjust 190
LVDS_LTX2 DP_B_L0
248 3 4
3 LVDS1_A3+ 184 254
2.5Amp 5
5VRUN
156 R395 *10K_J_4 LVDS_LTX3 DP_B_L1
260
5VRUN PEX_RST# GPU_RST# 22 +3V_MXM DP_B_L2
7 154 PEG_CLKREQ# 21 23 266
5VRUN 1, 3, 5, 7, 9 = 5VRUNPEX_CLK_REQ# 32 MXM_LVDS_PWREN LVDS_PWREN DP_B_L3

Display Port
9
5VRUN These capacitors have to 32 MXM_LVDS_BLON
25
LVDS_BLEN
153 TP18 27 274
+3V_MXM PEX_REFCLK#
155
CLK_PCIE_VGAN 21 be put near to MXM 3.0. LVDS_BRIGHT_PWM DP_B_HPD
1Amp PEX_REFCLK CLK_PCIE_VGAP 21
33
19,32 LCD_DAT LVDS_DDC_DAT
278 19,32 LCD_CLK 35 223
3V3RUN278, 280 = 3V3RUN LVDS_DDC_CLK DP_C_AUX#
280 225
3V3RUN EXRXN0 0.1U/16V/X7R_4 C90 PEG_RXN0 DP_C_AUX
147
C60 C54 C53 PEX_RX0# EXRXN1 0.1U/16V/X7R_4 C95 PEG_RXN1 PEG_RXN0 13
141 PEG_RXN1 13 199
PEX_RX1# EXRXN2 0.1U/16V/X7R_4 C100 PEG_RXN2 MXM_CRT_DAT DP_C_L0#
11 135 PEG_RXN2 13 27 MXM_CRT_DAT 158 205
10U/10V_8
1U/6.3V_41U/6.3V_4 GND PEX_RX2# EXRXN3 0.1U/16V/X7R_4 C108 PEG_RXN3 MXM_CRT_CLK CRT_DDC_DAT DP_C_L1#
13 121 160 211
GND 11,13, 15, 17 = GND PEX_RX3# EXRXN4 0.1U/16V/X7R_4 C113 PEG_RXN4 PEG_RXN3 13 27 MXM_CRT_CLK CRT_DDC_CLK DP_C_L2#
15 115 217
GND PEX_RX4# EXRXN5 0.1U/16V/X7R_4 C117 PEG_RXN5 PEG_RXN4 13 MXM_V_SYNC DP_C_L3#
17 109 162
GND PEX_RX5# EXRXN6 0.1U/16V/X7R_4 C125 PEG_RXN6 PEG_RXN5 13 27 MXM_V_SYNC MXM_H_SYNC VGA_VSYNC
103 164

DP-C
PEX_RX6# PEG_RXN6 13 27 MXM_H_SYNC VGA_HSYNC

CRT
97 EXRXN7 0.1U/16V/X7R_4 C131 PEG_RXN7 201
PEX_RX7# EXRXN8 0.1U/16V/X7R_4 C135 PEG_RXN8 PEG_RXN7 13 MXM_Red DP_C_L0
36 91 168 207
GND PEX_RX8# EXRXN9 0.1U/16V/X7R_4 C140 PEG_RXN9 PEG_RXN8 13 27 MXM_Red VGA_RED DP_C_L1
37 85 213
GND PEX_RX9# EXRXN10 0.1U/16V/X7R_4 C144 PEG_RXN10 PEG_RXN9 13 MXM_Green DP_C_L2
46 79 170 219
GND PEX_RX10# EXRXN11 0.1U/16V/X7R_4 C149 PEG_RXN11 PEG_RXN10 13 27 MXM_Green VGA_GREEN DP_C_L3
7/28: add 47
GND PEX_RX11#
73 PEG_RXN11 13
52 67 EXRXN12 0.1U/16V/X7R_4 C154 PEG_RXN12 MXM_Blue 172 234
decoupling GND PEX_RX12# EXRXN13 0.1U/16V/X7R_4 C163 PEG_RXN13 PEG_RXN12 13 27 MXM_Blue VGA_BLUE DP_C_HPD
53 61
capacitors for GND PEX_RX13# EXRXN14 0.1U/16V/X7R_4 C173 PEG_RXN14 PEG_RXN13 13
58 55
GND PEX_RX14# EXRXN15 0.1U/16V/X7R_4 C181 PEG_RXN15 PEG_RXN14 13 R186 10K_J_4
AMD 59
GND PEX_RX15#
49
PEG_RXN15 13 +3V_MXM DP_D_AUX#
230
recommendation 64
GND
7/28: pull-up resistor for 4
WAKE# DP_D_AUX
232
65 AMD recommendation. 22 dGPU_PWROK 6
GND PWR_GOOD
70 206
GND (AMD:10K ohm pull-up resistor) DP_D_L0#

PM
71 149 EXRXP0 0.1U/16V/X7R_4 C87 PEG_RXP0 MXMPWR_EN_R 8 212
GND PEX_RX0 EXRXP1 0.1U/16V/X7R_4 C92 PEG_RXP1 PEG_RXP0 13 PWR_EN DP_D_L1#
76 143 218
GND PEX_RX1 EXRXP2 0.1U/16V/X7R_4 C98 PEG_RXP2 PEG_RXP1 13 MXM_ACIN DP_D_L2#

DP-D
C 77 137 PEG_RXP2 13 18 224 C
GND PEX_RX2 EXRXP3 0.1U/16V/X7R_4 C106 PEG_RXP3 PWR_LEVEL DP_D_L3#
82 123 PEG_RXP3 13 21
GND PEX_RX3 EXRXP4 0.1U/16V/X7R_4 C111 PEG_RXP4 Main_VGA_DIS#
83 117
GND PEX_RX4 EXRXP5 0.1U/16V/X7R_4 C115 PEG_RXP5 PEG_RXP4 13
88 111 208
GND PEX_RX5 EXRXP6 0.1U/16V/X7R_4 C119 PEG_RXP6 PEG_RXP5 13 R172 10K_J_4 DP_D_L0
89 105 +3V_MXM 214
GND PEX_RX6 PEG_RXP6 13 DP_D_L1

THERM
94 99 EXRXP7 0.1U/16V/X7R_4 C126 PEG_RXP7 20 220
GND PEX_RX7 EXRXP8 0.1U/16V/X7R_4 C133 PEG_RXP8 PEG_RXP7 13 36 VGA_THERM# TH_OVERT# DP_D_L2
95 93 PEG_RXP8 13 22 226
GND PEX_RX8 EXRXP9 0.1U/16V/X7R_4 C136 PEG_RXP9 R166 10K_J_4 TH_ALERT# DP_D_L3
100 87 36 VGA_ALT# +3V_MXM 24
GND PEX_RX9 EXRXP10 0.1U/16V/X7R_4 C142 PEG_RXP10 PEG_RXP9 13 FAN_PWM
101 81 236
GND PEX_RX10 EXRXP11 0.1U/16V/X7R_4 C147 PEG_RXP11 PEG_RXP10 13 DP_D_HPD
106 75 36 MXM_SMDATA12 32
GND PEX_RX11 EXRXP12 0.1U/16V/X7R_4 C153 PEG_RXP12 PEG_RXP11 13 SMB_DAT
107 69 PEG_RXP12 13 36 MXM_SMCLK12 34 29
GND PEX_RX12 EXRXP13 0.1U/16V/X7R_4 C156 PEG_RXP13 SMB_CLK HDMI_CEC
112 63 PEG_RXP13 13 31
GND PEX_RX13 EXRXP14 0.1U/16V/X7R_4 C169 PEG_RXP14 DVI_HPD
113 57
GND PEX_RX14 EXRXP15 0.1U/16V/X7R_4 C177 PEG_RXP15 PEG_RXP14 13
118 51 126 159
GND PEX_RX15 PEG_RXP15 13 KEY RSVD
119 127 161
GND KEY RSVD
124 128 163
GND KEY RSVD
125 129 165
GND KEY RSVD
133 130 167
GND KEY RSVD
134 131 227
GND KEY RSVD
139 132 229
GND EXTXN0 0.1U/16V/X7R_4 C83 PEG_TXN0 KEY RSVD
140 148 PEG_TXN0 13 231
GND PEX_TX0# EXTXN1 0.1U/16V/X7R_4 C88 PEG_TXN1 RSVD
145 142 PEG_TXN1 13 38 233
GND PEX_TX1# EXTXN2 0.1U/16V/X7R_4 C94 PEG_TXN2 OEM RSVD
146 136 PEG_TXN2 13 39 235
GND PEX_TX2# EXTXN3 0.1U/16V/X7R_4 C99 PEG_TXN3 OEM RSVD
151 120 PEG_TXN3 13 40 237
GND PEX_TX3# EXTXN4 0.1U/16V/X7R_4 C107 PEG_TXN4 OEM RSVD
152 114 PEG_TXN4 13 41 238
GND PEX_TX4# EXTXN5 0.1U/16V/X7R_4 C112 PEG_TXN5 OEM RSVD
157 108 PEG_TXN5 13 42 239
GND PEX_TX5# EXTXN6 0.1U/16V/X7R_4 C116 PEG_TXN6 OEM RSVD
166 102 PEG_TXN6 13 43 240
GND PEX_TX6# EXTXN7 0.1U/16V/X7R_4 C124 PEG_TXN7 OEM RSVD
173 96 PEG_TXN7 13 44 241
GND PEX_TX7# EXTXN8 0.1U/16V/X7R_4 C132 PEG_TXN8 T6 OEM RSVD
174 90 PEG_TXN8 13 45 242
GND PEX_TX8# EXTXN9 0.1U/16V/X7R_4 C137 PEG_TXN9 OEM RSVD
179 84 PEG_TXN9 13 243
GND PEX_TX9# EXTXN10 0.1U/16V/X7R_4 C143 PEG_TXN10 RSVD
180 78 PEG_TXN10 13 10 245
GND PEX_TX10# EXTXN11 0.1U/16V/X7R_4 C150 PEG_TXN11 RSVD RSVD
185 72 PEG_TXN11 13 12 247
GND PEX_TX11# EXTXN12 0.1U/16V/X7R_4 C161 PEG_TXN12 RSVD RSVD
186 66 PEG_TXN12 13 14 249
GND PEX_TX12# EXTXN13 0.1U/16V/X7R_4 C166 PEG_TXN13 RSVD RSVD
191 60 PEG_TXN13 13 16
GND PEX_TX13# EXTXN14 0.1U/16V/X7R_4 C176 PEG_TXN14 RSVD
192 54 PEG_TXN14 13
GND PEX_TX14# EXTXN15 0.1U/16V/X7R_4 C183 PEG_TXN15 MXM3_2.0 CONNECTOR
197 48 PEG_TXN15 13
GND PEX_TX15#
198
GND
203
GND
204
GND EXTXP0 0.1U/16V/X7R_4 C82 PEG_TXP0
209 150 PEG_TXP0 13
GND PEX_TX0 EXTXP1 0.1U/16V/X7R_4 C84 PEG_TXP1
210 144 PEG_TXP1 13
GND PEX_TX1 EXTXP2 0.1U/16V/X7R_4 C91 PEG_TXP2
215 138 PEG_TXP2 13
GND PEX_TX2 EXTXP3 0.1U/16V/X7R_4 C96 PEG_TXP3
216 122
221
GND
GND
PEX_TX3
PEX_TX4
116 EXTXP4
EXTXP5
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C101
C109
PEG_TXP4
PEG_TXP5
PEG_TXP3
PEG_TXP4
13
13 MXM VIN Power switch
222 110 PEG_TXP5 13
GND PEX_TX5 EXTXP6 0.1U/16V/X7R_4 C114 PEG_TXP6
228 104 PEG_TXP6 13
GND PEX_TX6 EXTXP7 0.1U/16V/X7R_4 C118 PEG_TXP7
244 98 PEG_TXP7 13 10Amp
GND PEX_TX7 EXTXP8 0.1U/16V/X7R_4 C127 PEG_TXP8 MXM_12V VIN_MXM
B 250 92 PEG_TXP8 13 B
GND PEX_TX8 EXTXP9 0.1U/16V/X7R_4 C134 PEG_TXP9
251 86 PEG_TXP9 13
GND PEX_TX9 EXTXP10 0.1U/16V/X7R_4 C141 PEG_TXP10 80ohm/5A
256 80 PEG_TXP10 13
GND PEX_TX10 EXTXP11 0.1U/16V/X7R_4 C148 PEG_TXP11 L14 HI0805R800R-00_8
257 74 PEG_TXP11 13
GND PEX_TX11 EXTXP12 0.1U/16V/X7R_4 C155 PEG_TXP12
262 68 PEG_TXP12 13
GND PEX_TX12 EXTXP13 0.1U/16V/X7R_4 C157 PEG_TXP13 L15 HI0805R800R-00_8
263 62 PEG_TXP13 13
GND PEX_TX13 EXTXP14 0.1U/16V/X7R_4 C171 PEG_TXP14
268 56 PEG_TXP14 13
GND PEX_TX14 EXTXP15 0.1U/16V/X7R_4 C178 PEG_TXP15 L16 HI0805R800R-00_8
269 50 PEG_TXP15 13
GND PEX_TX15
275
GND
26
GPIO0
GPIO1
28 These capacitors have to be put near to LGA1156. MXM 3V/5V Power switch
30
GPIO2

MXM3_2.0 CONNECTOR

+3V_MXM

To low power status mode


1 : FULL POWER
+3V To EC +3V

1Amp
L5 HI0805R800R-00_8

0 : LOW POWER
At 11/14 Add it +5V_MXM
+3V_S5 +3V_S5
5

1 +5V L11 HI0805R800R-00_8


MXMPWR_EN 36
MXMPWR_EN_R 4
2 R193
R182 R181 0_J_4
+3V_MXM 2.5Amp
3

U10 C215
10K_J_4 10K_J_4 TC7SH08FU
D13
*0.1U/10V/X5R_4
MXM_LVDS_CONNECT LCDVCC
MXM_ACIN 2 1 MXM_PWR_LEVEL# 36

RB500V-40

CON1
29 30
27 28
LVDS_MXM_LTX1# 25 26 LVDS_MXM_LTX2
LVDS_MXM_LTX1 23 24 LVDS_MXM_LTX2#
21 22
LVDS_MXM_LTX0# 19 20 LVDS_MXM_LTX3
LVDS_MXM_LTX0 17 18 LVDS_MXM_LTX3# +5V_MXM
A 15 16 A
LVDS_MXM_UCLK# LVDS_MXM_LCLK
LVDS_MXM_UCLK 13 14 LVDS_MXM_LCLK#
11 12
LVDS_MXM_UTX3# 9 10 LVDS_MXM_UTX0 C220 C217 C214 C211 C210
LVDS_MXM_UTX3 7 8 LVDS_MXM_UTX0#
LVDS_MXM_UTX2# 5 6 LVDS_MXM_UTX1 4.7U/25V_8 1U/10V_4 1U/10V_4 .1U/16V/Y5V_4.1U/16V/Y5V_4
LVDS_MXM_UTX2 3 4 LVDS_MXM_UTX1#
1 2 VIN_MXM
LCD_CON30

87216-300x-30p-ldv

C235 C229 C231 C226 C223 C225 C240

10U/25V_1206 4.7U/25V_8 1u/25V_6 *1U/25V_6 .1U/25V/X5R_4.1U/25V/X5R_4*5.6u/25V_1206


LVDS PIN Swap Quanta Computer Inc.
PROJECT : ZN2
Size Document Number Rev
A
MXM 3.0
Date: Tuesday, March 16, 2010 Sheet 25 of 49
5 4 3 2 1
5 4 3 2 1

+5V

HPOUT_R
Demodulation Filter
Place close to Codec 26
AL5
HPOUT_L
AC9 AC12 +5V *TI201209U220/0805 +5VA
0.1U/10V/X5R_4 10U/6.3V_6

3
IN OUT
4 Vset =1.25V
MIC1-VREFO-L
AMP_GND AR10 *0_F_6 2
GND Vout =Vset[1+AR(1,2)/AR(2,GND)]
Place next to pin 39
MIC1-VREFO-R 1 5 AR18 29.4K_F_4
SHDN SET
+5V MIC1-VREFO-L AU1
MAX8863SEUK+T AR19
D +5VA D
AC14 2nd Source G913 10K_F_4 AC15 AC17 AC20 AC19
AR5 *0_F_6 AC3 *10U/6.3V/X5R_6 0.1U/10V/X5R_4 10U/25V_1206 0.1U/10V/X5R_4 0.1U/10V/X5R_4 0.1U/10V/X5R_4
AR32 0_J_4
AC34 + Place next to pin 27
AC8 AC11
0.1U/10V/X5R_4 10U/6.3V_6 2.2U/6.3V_6
AC26
10U/6.3V_6
AC35 AC28 +5VA
AMP_GND 0.1U/10V/X5R_4
+
Place next to pin 46 2.2U/6.3V_6

AC21
AU5

36

35

34

33

32

31

30

29

28

27

26

25
AC23
0.1U/10V/X5R_4

CBP

CPVEE

HP-OUT-L

MIC2-VREFO

MIC1-VREFO-L

AVSS1

AVDD1
CBN

HP-OUT-R

CPVREF

MIC1-VREFO-R

VREF
10U/6.3V_6
L_SPK+ AL6 8.2UH

AC38
Spilt by DGND 37 24
AVSS2 LINE1-R LINEOUT_R 27 *1000P/50V/X7R_6
+5VA 38 23 AC36 Speaker OUT
AVDD2 LINE1-L LINEOUT_L 27 Place next to pin 25 AC39
39 22 MICIN-R 1U/16V/X7R/1206 ACN4
+5V PVDD1 MIC1-R AMP_GND *1000P/50V/X7R_6
AC7 AC6 L_SPK+ 40 21 MICIN-L Internal SPK_L+
SPK-L+ MIC1-L L_SPK- 1
10U/6.3V_6 0.1U/10V/X5R_4 AL7 8.2UH
2 Internal SPK_L-
L_SPK- 41 20 R_SPK- AL8 8.2UH Internal SPK_R-
SPK-L- MONO-OUT 3
4 Internal SPK_R+
AR23 20K_F_4
42 PVSS1 (Vista Premium Version) JDREF 19
AC40
Place next to pin 38 43 18
PVSS2 Sense-B *1000P/50V/X7R_6 AC37
R_SPK- 44 17
SPK-R- MIC2-R 1U/16V/X7R/1206
AMP_GND R_SPK+ 45 16 AC41
SPK-R+ MIC2-L AMP_GND
+5V 46 15 *1000P/50V/X7R_6
PVDD2 LINE2-R R_SPK+ AL9 8.2UH
GPIO0/DMIC-DATA

C EAPD#1 C
GPIO1/DMIC-CLK

47 14
27 EAPD#1 SPDIFO2/EAPD LINE2-L
SPDIF OUT AC33 48 13 SENSE# AR24 39.2K_F_4HPSENSE#
SDATA-OUT

T21 SPDIFO Sense A


*0.1U/10V/X5R_4
SDATA-IN

DVDD-IO

PCBEEP
RESET#
BIT-CLK

EAPD# 49 AR26 10K_F_4


DVDD1

DVSS2

PGND LINEOUT_JD# 27
SYNC

R510 *0_J_4
PD#

DIGITAL AR25 20K_F_4 MICSENSE#

AMP_GND ALC269
1

10

11

12

ANALOG MIC1-VREFO-R
C476 R504 10K_F_4
PC_BEEP
SPKR 20
1U/10V_6 MIC1-VREFO-L
+3V +1.5V
R505
C475 1K_J_4
DMIC_CLK AC31 0.1U/10V/X5R_4
0.1U/10V/X5R_4 AC32 AR4 AR7
C7 10U/6.3V_6 R506 4.7K_F_4 4.7K_F_4
*0_J_8

*10P/50V_4
MIC-IN Jack
ACZ_SDIN

Place next to pin 1


ACZ_BITCLK_R

R509 0_J_4 +AZA_VDD 6 ACN2


35 DMIC_DAT +3V
4.7U/6.3V_6 AL1 BK1608HM241-T 1
DMIC_CLK R508 0_J_4 AC24 MICIN-L AC1 MICIN-L1AR3 1K_F_4 MICIN-L2 MICIN-L3 2
35 DMIC_CLK
AL2 BK1608HM241-T
AC25 MICIN-R MICIN-R1AR6 1K_F_4 MICIN-R2 MICIN-R3 3
PD# PCH_AZ_CODEC_RST# 20
0.1U/10V/X5R_4 10U/6.3V_6 AC4 4.7U/6.3V_6 4
0V : Power down Class D SPK amplifer PCH_AZ_CODEC_SYNC 20 5
3.3V : Power up Class D SPK amplifer MICSENSE# 7
AC29 10p/50V_4 AR30 22_J_4 8 MIC_JACK
PCH_AZ_CODEC_SDIN0 20

*PESD5V0U1BB

*PESD5V0U1BB
AC5 AC2

1
220P/50V/X7R_4
PCH_AZ_CODEC_SDOUT 20
Place next to pin 9 Max. 100mVrms input for Mic-IN 220P/50V/X7R_4 D28 D26
AR8 0_F_6 AR34 0_F_6 AR2 0_F_6 AR31 22_J_4
PCH_AZ_CODEC_BITCLK 20
AC30

2
10p/50V_4
B AR13 0_F_6 B
AR16 0_F_6 AR1 0_F_6
AR15 *0_F_6
AR33 0_F_6

AMP_GND
AMP_GND AMP_GND
digital_ground
Headphone-OUT
Tied at one point only under the
ALC269 or near the ALC269 Analog_ground 6 ACN3
BK1608HM241-T 1
HPOUT_L AR12 75_F_4 HPOUT_L1_L AL3 HPOUT_L2 2
HPOUT_R AR14 75_F_4 HPOUT_R1_L AL4 BK1608HM241-T HPOUT_R2 3
4
5
HPSENSE# 7
de-pop sound circuit 8
AC10 AC13 Headphone_JACK

*PESD5V0U1BB

*PESD5V0U1BB
AR17 *0_J_4

1
+3V

1000P/50V/X7R_4

1000P/50V/X7R_4
AD2

AR20 10_J_4 +3VPCU D30 D31

SDM10K45-7-F

2
5

AU2A AU2B AU4


5

36 EC_AMP_MUTE# 1
AR21 1M_J_4 1 6 3 4 2 4 PD# 27
20 PCH_AZ_CODEC_RST#
4 EAPD# 2
1
AC18 7WZ14 7WZ14 AU3 NL17SZ32DFT2G
3

10U/6.3V_6
3

TC7SH08FU(F)
A A

AC16
*1000P/50V/X7R_4

Vender suggest (Realtek)

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
1A
AUDIO CODEC AL269
Date: Tuesday, March 16, 2010 Sheet 26 of 49
5 4 3 2 1
5 4 3 2 1

27
HPOUT_L1

+3VPCU
HPOUT_R1

AR28 PD_MUTE
22K_F_4

3
AR29 10K_J_4 2 AQ1

3
R500
MMBT3906 R501 1K_F_4 2 30K_F_4
AD3

1
1
1SS355
D 26 PD# 2 AR27 2SD1781KPT D

1
Q24
MMBT3906 AC22

3
AQ2 22U/6.3V_8 220K_J_4
AC27

3
26 EAPD#1 *0.1U/10V/X5R_4
R503 1K_F_4 2 R502
AD4 1SS355 30K_F_4
+3VPCU 2SD1781KPT

1
Q25

L20 MNB-160808-0600A-N2Q 5 ACN1


26 LINEOUT_L LINEOUT_L HPOUT_L1 4
C276 47U/6.3V_1206 R246 75_J_6 L19 1
MNB-160808-0600A-N2Q
26 LINEOUT_R LINEOUT_R HPOUT_R1 3
C274 47U/6.3V_1206 R244 75_J_6 2
CN AUDIO JACK 5P H15 Green
26 LINEOUT_JD#

C277 C275
Normal Open Type

*BC00SM24Z00

*BC00SM24Z00
Green Type

1
1000P/50V/X7R_6
1000P/50V/X7R_6
D23 D25

2
C C

Reserve to CRT
19 INT_CRT_RED INT_CRT_RED

19 INT_CRT_GRE INT_CRT_GRE
+5V

19 INT_CRT_BLU INT_CRT_BLU

C66

C67

C61
CN6
R51 R55 R42 R53 R57 R49 6
11
150_J_6 150_J_6 150_J_6 150_J_6 150_J_6 150_J_6 1
12P/50V_4

12P/50V_4

12P/50V_4
7 16
B 12 17 B
Change value to 150 Change value to 150 2
4 3 INT_CRT_DDCDAT 6/30 6/30 8
25 MXM_CRT_DAT
25 MXM_CRT_CLK 2 1 INT_CRT_DDCCLK 13
RN2 *0X2_4 +5V
4 3 CRT_HSYNC_L
Place near to PCH. 3
9
25 MXM_H_SYNC
25 MXM_V_SYNC 2 1 CRT_VSYNC_L 14
RN3 *0X2_4 4

1
25 MXM_Red R50 *0/J_4 INT_CRT_RED 10
D36 D35 D38 D37 15
R54 *0/J_4 INT_CRT_GRE 3 DA204U 3 DA204U 3 DA204U 3 DA204U 5
25 MXM_Green

25 MXM_Blue R41 *0/J_4 INT_CRT_BLU 2

2
*DFDB15FR029

+5V
19 INT_CRT_DDCDAT R18 33_F_4 DDCDATA_L1

C55
0.1U/10V/X5R_4 19 INT_CRT_DDCCLK R17 33_F_4 DDCCLK_L1
5

U2
AHCT1G125DCH L3
19 INT_HSYNC 2 4 CRT_HSYNC_L R32 33_F_4 CRT_HSYNC_L1
27nH

L2
CRT_VSYNC_L R20 33_F_4 CRT_VSYNC_L1
27nH

R19
1K_J_6 C49 C48 C52 C51 C50
5

*220P/X7R_6 *220P/X7R_6 47P/50V_6 47P/50V_6 0.1U/10V/X5R_4


A A

19 INT_VSYNC 2 4
U1
AHCT1G125DCH

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
1A
Line Out/CRT
Date: Tuesday, March 16, 2010 Sheet 27 of 49
5 4 3 2 1
A B C D E

CARD READER SD/MS_3V

R407 10K_J_4 SD_WP#/XD_WP


6/29
+3V
CARDREADER POWER 28
R394 10K_J_4 MS_BS/SD_CMD/XD_WE
+3V Q17 SD/MS_3V
R371 1K_F_4 XD_R/B *AO3409
SD/MS_3V
R375 200K_F_4XD_READ +3V R207 1 3
150_F_4 +5V
R372 200K_F_4XD_ADD_L
R393 10K_J_4 XD_C_L C453 C398 C139 C422

2
2
10U/6.3V_8 .1U/10V/X5R_4 .1U/10V/X5R_4 .1U/10V/X5R_4
R368 4.7K_J_4 SD_CD#/XD_CD# LED2 MC_PWR_CTRL_0# R358 *10K_F_4
4 LED17-21VGC-TR8 4
SD/MS_3V
LED17-21VGC-TR8
MS_CD_CLK/XD_CD_R R408 22_J_4 MS_CD_CLK/XD_CD
R364 0_J_8

1
+3V
C438 CARD_LED
CARD POWER RESERVED for JMicron -- after
R363 4.7K_J_4 MS_CD# programming can out-put VCC3
*22P/50V_4 throught MC_PWR_CTRL_0# signal
+3V

C430 .1U/10V/X5R_4
MS_CD# D40 1N4148

C411 .1U/10V/X5R_4
SD_CD#/XD_CD# D41 1N4148
XD_CD# 6 IN 1 CONN
C400 .1U/10V/X5R_4 L1394_TPB0-_R R381 0_J_4
Reserve for EMI
L1394_TPB0+_R R384 0_J_4
C429 10U/6.3V_8
L1394_TPA0-_R R387 0_J_4 CN15
1 XD-GND1 GND 43
L1394_TPA0+_R XD_CD# R429 33_J_4 2
XD_R/B R430 33_J_4 XD-CD# 33_J_4 R360 SD_WP#/XD_WP
3 42
TPBIAS0 +3V XD_READ R431 33_J_4 XD-R/B SD-WP
4 XD-RE SD-GND1 41
+1.8V_CARD MS_CD_CLK/XD_CD R432 33_J_4 5 40 *10K_J_4 R451
XD-CE SD-CD# +3V
XD_C_L R433 33_J_4 6 39
C433 10U/6.3V_8 XD_ADD_L R434 33_J_4 XD-CLE SD-GND2 MS_D2/SD_D2/XD_D2 SD_CD#/XD_CD#
7 38

XD_READ
MS_BS/SD_CMD/XD_WE R435 33_J_4 XD-ALE SD-D2 MS_D1/SD_D1/XD_D1
8 XD-WE SD-D1 37

XD_D4

XD_D5

XD_D6

XD_D7
C425 .1U/10V/X5R_4 SD_WP#/XD_WP R436 33_J_4 9 36 MS_D0/SD_D0/XD_D0
XD-WP SD-D0
10 35
C435 .1U/10V/X5R_4 R389 MS_D0/SD_D0/XD_D0 R88 33_J_4 XD-GND2 SD-GND MS_CD_CLK/XD_CD
11 XD-D0 SD-CLK 34
*12K_F_4 MS_D1/SD_D1/XD_D1 R89 33_J_4 12 33
SD/MS_3V XD-D1 SD_VCC SD/MS_3V
C432 1000P/50V_4 MS_D2/SD_D2/XD_D2 R85 33_J_4 13 32
MS_D3/SD_D3/XD_D3 R86 33_J_4 XD-D2 SD-GND3 MS_BS/SD_CMD/XD_WE
14 31
C412 *0.1U/10V/X5R_4 XD_D4 R81 33_J_4 XD-D3 SD-CMD MS_D3/SD_D3/XD_D3
3
15 XD-D4 SD-D3 30 3
XD_D5 R82 33_J_4 16 29
C423 *10U/6.3V_8 XD_D6 R77 33_J_4 XD-D5 MS-GND2
U17 17 28
36

35

34

33

32

31

30

29

28

27

26

25
XD-D6 MS-VCC SD/MS_3V
XD_D7 R78 33_J_4 18 27 MS_CD_CLK/XD_CD
R418 XD-D7 MS-SCLK MS/SD_DAT3 33_J_4 R120 MS_D3/SD_D3/XD_D3
19 26
TPBIAS_1

TPA1P

TPB1P

TAV33

MDIO8

MDIO9

MDIO10

MDIO11

MDIO12
TREXT

TPA1N

TPB1N SD/MS_3V XD-VCC MS-P-D3 *10K_J_4 R117


*10K_F_4 20 25 +3V
MS_BS/SD_CMD/XD_WE R100 33_J_4 MS-GND1 MS-INS MS_DAT2 33_J_4 R116 MS_D2/SD_D2/XD_D2
21 MS-BS MS-P-D2 24
MS_D1/SD_D1/XD_D1 R103 MS_DAT1
33_J_4 MS/SD_DAT0 33_J_4 R107 MS_D0/SD_D0/XD_D0 MS_CD#
Reserve for JMB385 +1.8V_CARD 37 24 R374 0_J_4
22
44
MS-D1 MS-SDIO
23
45
DV18 TCPS T18 SD/MS_3V Con-GND1 Con-GND2
JMB380CLK+ 38 23 XD_R/B TAI TWUN 6 IN 1 PUSH TYPE
TXIN MDIO13 SD/MS_3V

D3E_GPIO#
JMB380CLK- 39 22 XD_ADD_L
R397 TXOUT MDIO14 +3V C442
XD_C_L 40 21 CARD_LED C443 2.2U/6.3V_6
MDIO7 JMB385 CR_LEDN
*1M_F_4 SD_WP#/XD_WP 41 20 +3V 10U/6.3V_6
MDIO6 DV33
MS_CD_CLK/XD_CD_R 42 19 D42 CLOSE CONN
MDIO5 DV33
Y4 1SS355
MS_BS/SD_CMD/XD_WE 43 18 +1.8V_CARD R362 R369
MDIO4 DV18 4.7K_J_4 4.7K_J_4
*24.576MHz 50ppm 10pF +3V 44 17 MC_PWR_CTRL_0#
C440 C441 DV33 CR1_PCTLN
MS_D3/SD_D3/XD_D3 45 16 SD_CD#/XD_CD#
*22P/50V/4 *22P/50V/4 MDIO3 CR1_CD0N/WAKEN
MS_D2/SD_D2/XD_D2

MS_D1/SD_D1/XD_D1
46

47
MDIO2 CR1_CD1N 15

14 CR1_CD2N R359 *0_J_4 XD_CD#


MS_CD#
1394
MDIO1 NC +3V
MS_D0/SD_D0/XD_D0 48 13
MDIO0 CPPEN
APCLKN

APREXT
APCLKP

49 TPBIAS0 C439 *EV@0.33u/10V_4


APGND
APVDD

APRXN
XRSTN

APRXP

APTXN

APTXP
XTEST

EPAD
APV18

R97
*10K_J_4 TO SB
*22_J_4
1

10

11

12

2
CR_CPPE# 22 R388 R386 L12 2

1
R98 1 2
Q6 1 2
4 3
4 3
R377

*2N7002E-LF *EV@56.2/F_4 *EV@56.2/F_4


2 *1394@CL-2M2012-121JT
10,21,22,30,33 PLTRST#
CN18
5
L1394_TPA0+_R RN25 2 1 *0X2_4 L1394_TPA0+ L1394_TPB0- 1
As close as L1394_TPA0-_R 4 3 L1394_TPA0- L1394_TPA0- 3
3
8.2K_F_4

L1394_TPA0+ 4
possible to JMB380 L1394_TPB0+ 2 6
+1.8V_CARD

+1.8V_CARD

21 CLK_PCH_SRC2N
L1394_TPB0-_R RN26 3 4 *0X2_4 L1394_TPB0- *EV@C13141-10405-L
21 CLK_PCH_SRC2P
L1394_TPB0+_R 1 2 L1394_TPB0+

21 PCIE_TXP5
R380 R383 L13 GND1
21 PCIE_TXN5
C409 .1U/10V/X5R_4 PCIE_RXN5_C 1 2
21 PCIE_RXN5 C408 .1U/10V/X5R_4 PCIE_RXP5_C *EV@56.2/F_4 *EV@56.2/F_4 1 2 R226 0_J_8
4 3
21 PCIE_RXP5 4 3
1394_COM *1394@CL-2M2012-121JT
GND1
R54 (pin7 APREXT) C434 These 1394 signals are high speed
R379
8.2K for JM380B *EV@220p/25V_4
differential pairs and must be kept equal
12K for JM380C *EV@4.99K/F_4 length with a differential impedance (Zo)
of 110ohms.

L1394_TPA0+ L1394_TPB0+

L1394_TPA0- L1394_TPB0-
1 1
+3V +3V

2
D1

D2

D1

D2
GND

GND
VCC

VCC
*SR05 *SR05
D14 D16
4

1
Quanta Computer Inc.
PROJECT : ZN2
Size Document Number Rev
1A
JMB380
Date: Tuesday, March 16, 2010 Sheet 28 of 49
A B C D E
5 4 3 2 1

VIN VIN VIN VIN


VIN_CPU VIN_CPU
VIN VIN
29
C495 C496 C498 C499 C500 C497 C501 C502

*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4

D
SATA HDD(3.5") +3V
+1.5V_SUS +1.1V_VTT +VCC_CORE V_AXG V_AXG +VCC_CORE +3V +5V
D

SATA HDD CONNECT R92


150_F_4
+3V +3V +5V +5V VIN +3V +3V +3V

CN11
GND3 7

2
6 C504 C505 C506 C507 C508 C509 C510 C515
RXP SATA_TXP0 20
5 LED3
RXN SATA_TXN0 20
4 0.01U/25V_4 C105 *LED12-21SYGC-Green *0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
GND2 SATA_RX#0_R
TXN 3
0.01U/25V_4 C104 SATA_RXN0 20
TXP 2
1 SATA_RX0_R

1
GND1 SATA_RXP0 20 +5V +5V
CON44A_0
sata-c12712-10704-l-7p-r

+1.5V_SUS +1.1V_VTT +1.5V_SUS V_AXG +5V +5V +5V


HDD_12V 20,30 SATA_ACT#
+5V

C C
C511 C512 C513 C514 C516 C517 C518

*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
*0.1U/25V/X5R_4
1

F4 F5
3A 3A
RC1206 RC1206
+3V +3V_S5 MXM_12V
2

CN22

1
2
3
4 + FOR EMI DEMAND
+ C255 C273
10U/6.3V_6 10U/6.3V_6 C269
C262

100U/16V_R6_24
100U/16V_R6_24
B B

SATA ODD CONNECTOR ODD_CONN


JP3

CLR_BIOS_DATA 1 2 CN19
22 CLR_BIOS_DATA CLR_PASSWD +5V
3 4 12
22 CLR_PASSWD
5 6 F3 11
30 EJECT_R#
7 8 10
1 2 5VSATA_ODD
9
CONN RCPT 4x2 C241 0.01U/25V_4 8
3A SATA_RX#1_R 7
RC1206 1K_J_4 20 SATA_RXN1 6
C242 0.01U/25V_4
R232 SATA_RX1_R 5
20 SATA_RXP1 4
C228 C232 C224
20 SATA_TXN1 3
0.1U/25V/X5R_4 10U/6.3V_6 100U/6.3V/3528 20 SATA_TXP1 2
1

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
1A
SATA HDD/ODD
Date: Tuesday, March 16, 2010 Sheet 29 of 49
5 4 3 2 1
1 2 3 4 5 6 7 8

+1.5V
For wirlesss Lan card/Bluetooth TO POWER BUTTON & LED LIGHT& IR 30
C246 C247 C248 CN20
51 52 0_J_8 R235 +3V +5VPCU
.1U/10V/X5R_4
.1U/10V/X5R_4
.1U/10V/X5R_4 Reserved +3.3V +5V_S5_USB CN29
49 Reserved GND 50
47 48 +1.5V *0_J_8 R233 PWR_3VMINIC1
Debug(PCIRST#) +1.5V
45 Debug(PCICLK) LED_W PAN# 46 1
+3V R228 0_J_8 43 44 2
GND LED_W LAN# R234 *10K_J_4 +3VPCU
41 +3.3Vaux LED_W W AN# 42 36 PWRLED1# 3
PWR_3VMINIC1 R231 *0_J_8 MINI3V_WLAN 39 40 4
+3V +3.3Vaux GND USBP5+ 36 PWRLED0#
A
37 GND USB_D+ 38 USBP5+ 21 36 Ir_LED_ON# 5 A
35 36 USBP5- SATALED_R 6
GND USB_D- USBP5- 21
PCIE_TXP1 33 34 7
21 PCIE_TXP1 PETp0 GND 36 BL_DW#
PCIE_TXN1 31 32 8
21 PCIE_TXN1 PETn0 SMB_DATA CLK_SDATA 9,17,18,32,37 36 BL_UP#
C251 C250 C249 29 30 R251 9
GND SMB_CLK CLK_SCLK 9,17,18,32,37 36 EJECT#
C237 0.1U/10V/X7R_4 27 28 +1.5V *100_J_4 10
GND +1.5V 36 NBSWON#
.1U/10V/X5R_4
.1U/10V/X5R_4
.1U/10V/X5R_4 21 PCIE_RXP1 PCIE_RXP1 PCIE_RXP1_WLAN 25 26 11
PCIE_RXN1 PCIE_RXN1_WLAN PERp0 GND MINI3V_WLAN RX1B
21 PCIE_RXN1 23 PERn0 +3.3Vaux 24 12
C238 0.1U/10V/X7R_4 21 22 PLTRST# CIR_RX0 13
GND PERST# PLTRST# 10,21,22,28,33 36 CIR_RX0
CLK_LPC_DEBUG 19 20 R485 4.7K_J_4 14
PCIRST# Reserved W _DISABLE#
36 PCIRST# 17 Reserved GND 18 IR Receiver
7/8
15 16 Learing Receiver in Pwer_IR_board
GND Reserved LPC_LAD0 20,36
CLK_PCH_SRC3P 13 14
21 CLK_PCH_SRC3P REFCLK+ Reserved LPC_LAD1 20,36
CLK_PCH_SRC3N 11 12
21 CLK_PCH_SRC3N REFCLK- Reserved LPC_LAD2 20,36
9 GND Reserved 10 LPC_LAD3 20,36
21 PCIECLKRQ3# 7 8 R140 *0_J_4
CLKREQ# Reserved LPC_LFRAME# 20,36 29 EJECT_R#
5 Reserved +1.5V 6 +1.5V
Q9 3 4

GND

GND
WLAN_WAKE# Reserved GND
19,33 PCIE_WAKE# 3 1 1 W AKE# +3.3V 2
*2N7002E-LF
C15706-190A1-L +5V
FOR EMI

53

54
+3VPCU
IR Blaster
2
R230 *10K_J_4
+3VPCU C282 0.1U/25V/X5R_4 +3VPCU
C283 0.1U/25V/X5R_4 NBSWON# R245 D24
4.7K_J_4 1SS355
C285 0.1U/25V/X5R_4 BL_UP# CN24
R243 100_F_4 5
B +1.5V +3V C286 0.1U/25V/X5R_4 BL_DW# 4 B
C426 36 CIR_TX1
1
0.1U/25V/X5R_4 C284 0.1U/25V/X5R_4 EJECT# CIR_ED1 R247 1K_F_4 3
36 CIR_ED1
2
C190 C233 C207 C234 C236 C239

.1U/10V/X5R_4
.1U/10V/X5R_4
.1U/10V/X5R_4.1U/10V/X5R_4
.1U/10V/X5R_4
.1U/10V/X5R_4
For TV MODULE CARD IR Blaster

+5V

CN17
51 52 0_J_8 R136 +3V +3V +5V
R443 *0_J_8 Reserved +3.3V R114 R99
+3V_S5 49 Reserved GND 50
47 48 +1.5V *0_J_8 R141 PWR_3VMINIC1 R113
R422 *0_J_8 Debug(PCIRST#) +1.5V 1.8K_F_4 1.8K_F_4
PWR_3VMINIC1 45 Debug(PCICLK) LED_W PAN# 46 100K_F_4
43 44 U7A R101
GND LED_W LAN#

2
+3V R442 0_J_8 MINI3V_TV 41 42 R157 *10K_J_4 U8 C130 .1U/10V/X5R_4CIR@10K_4
+3.3Vaux LED_W W AN# R108
39 +3.3Vaux GND 40 3 - 1 5
37 38 USBP12+ 1K_J_4 4 2
GND USB_D+ USBP12+ 21
35 36 USBP12- 1 + 3 4
GND USB_D- USBP12- 21 CIR_RX1 36
PCIE_TXP2 33 34
21 PCIE_TXP2 PETp0 GND

2
PCIE_TXN2 31 32 G1214TAU NL17SZ14DFT2G
21 PCIE_TXN2 CLK_SDATA 9,17,18,32,37

5
PETn0 SMB_DATA R115
29 GND SMB_CLK 30 CLK_SCLK 9,17,18,32,37
C218 0.1U/10V/X7R_4 27 28 +1.5V 12K_J_6
PCIE_RXP2 PCIE_RXP2_TV GND +1.5V
21 PCIE_RXP2 25 PERp0 GND 26
21 PCIE_RXN2 PCIE_RXN2 PCIE_RXN2_TV 23 24 MINI3V_TV

1
C219 0.1U/10V/X7R_4 PERn0 +3.3Vaux PLTRST# +5V
21 GND PERST# 22 R102
CLK_LPC_DEBUG 19 20 R192 4.7K_J_4
21 CLK_LPC_DEBUG NC W _DISABLE#
BC_CD# 17 18
AUX1/DETECT GND

3
C151 0.01U/16V_4 R106
C C
15 16 RX1B 2 Q7
CLK_PCH_SRC1P GND NC BC_RST# 18K_F_4 100K_F_4
21 CLK_PCH_SRC1P 13 REFCLK+ BCAS_RST 14
CLK_PCH_SRC1N BC_CLK MMBT3904
21 CLK_PCH_SRC1N 11 12

1
REFCLK- BCAS_CLK BC_DATA
9 GND BCAS_DATA 10
21 PCIECLKRQ1# 7 8 BC_PWR R125
*2N7002E-LF CLKREQ# BCAS_PW R
5 AUX2/NC +1.5V 6 +1.5V 100_F_4
Q8 3 4 C227
GND

GND

WLAN_WAKE# COEX1 GND .1U/10V/X5R_4


19,33 PCIE_WAKE# 3 1 1 W AKE# +3.3V 2
C15706-190A1-L
53

54
2

R227 *10K_J_4 +3V


+3VPCU

R253
+3VPCU Q20
*SI3433BVD 4A 2.2K_J_4
6 L38
B-CAS CONN

2
4 5 PWR_3VMINIC1
2
1 *MNB-201209-0030 SATALED_R 3 1 SATA_ACT# 20,29
CN10
3

R447 Q10
R414 220_J_6 10 2N7002K
3

470K_J_4 C455 9 BC_CD#


0.01U/50V_6 12 8 BC_C8
T5
11 7 BC_DATA R252 *0_F_6
1 6
5
D Q22 PWR_3VMINIC1 4 BC_C4 D
T4
R419 *ME2N7002E 3 BC_CLK
47K_J_4 2 BC_RST#
2

1 BC_PWR BC_PWR
3

40MIL
1

C451 C450 C449 C452 B-CAS connector C97


36 SLP_MINI# 1
.1U/10V/X5R_4
.1U/10V/X5R_4
.1U/10V/X5R_4
4.7U/10V_6
.1U/10V/X5R_4 Quanta Computer Inc.
2

Q21
*ME2N7002E PROJECT : ZN2
BC_PWR From TV card Size Document Number Rev
2

1A
Close to CN23 MINI PCIE(WLAN/TV/IR)
Date: Tuesday, March 16, 2010 Sheet 30 of 49
1 2 3 4 5 6 7 8
5 4 3 2 1

Rear USB

+5V_S5_USB
40 mils 1
F11
2 USBVCC0
+5V_S5_USB
40 mils 1

POLY_SWITCH
F12
2 USBVCC1 31
POLY_SWITCH

USB USBVCC0 F13


WCM2012-110 F10
40 mils USBVCC11
L40 USBVCC0 1
40 mils 40 mils 1 2 USBVCC8
+5V_S5_USB 1 2
+5V_S5_USB

PESD5V0U1BB
1 2 USB0_FB# 2 POLY_SWITCH
21 USBP0-

1
D D
3 4 USB0_FB 3 POLY_SWITCH

100U/10V/7343
21 USBP0+
4

*100U/10V/7343
5 C481 D51

*PESD5V0U1BB

*PESD5V0U1BB

C477

C483
4 3 6 0.1U/25V/X5R_4

1
2 1

EGA-0402
RN30 *0X2_4

2
1
D48 D47

EGA-0402
CN28
RV10 RV9

2
F8 F9
40 mils 1 2 USBVCC2
40 mils 1 2 USBVCC3
+5V_S5_USB +5V_S5_USB
POLY_SWITCH POLY_SWITCH

USBVCC2
USB USBVCC1
WCM2012-110 40 mils
L42 40 mils

PESD5V0U1BB
USBVCC1 1

1
PESD5V0U1BB
1 2 USB1_FB# 2

100U/10V/7343
21 USBP1-

1
3 4 USB1_FB 3

100U/10V/7343

*100U/10V/7343
21 USBP1+
4 WCM2012-110 CN21 C245 D17

*100U/10V/7343
*PESD5V0U1BB

*PESD5V0U1BB
C491 D59 L17

C469

C466
1 5 1 V GND 4 0.1U/25V/X5R_4

1
USB2_FB

C493

C489
4 3 6 0.1U/25V/X5R_4 21 USBP2+ 1 2 3 D+GND 5
2 1 21 USBP2- 3 4 6

2
GND
1

RN32 *0X2_4 D54 D53 USB2_FB#


EGA-0402

2 7

2
D- GND

*AZ2015-01H_ESD

*AZ2015-01H_ESD
RV14

EGA-0402
C CN32 2 1 GND 8 VCC C

1
RV13 4 3
RV4 D18 SIDE_USB
2

1
RN27 *0X2_4 D19 DATA+
2

EGA-0402
RV3

EGA-0402
2

2
DATA-

2
GND
USB USBVCC8 USBVCC3
WCM2012-110
L41 USBVCC8 1
40 mils

PESD5V0U1BB
1 2 USB8_FB# 2
21 USBP8-

PESD5V0U1BB
3 4 USB8_FB 3

100U/10V/7343

100U/10V/7343
21 USBP8+

1
4

*100U/10V/7343

*100U/10V/7343
*PESD5V0U1BB

*PESD5V0U1BB

5 C484 D52 WCM2012-110 CN23 C268


1

C478

C482

C265

C472
4 3 6 0.1U/25V/X5R_4 L18 1 4 0.1U/25V/X5R_4 D20
USB3_FB V GND
2 1 21 USBP3+ 3 4 3 D+GND 5
1

RN31 *0X2_4 D50 D49


EGA-0402

1 2 6

2
21 USBP3- GND
1

USB3_FB#
EGA-0402

RV12 CN27 2 7

2
RV11 D22 D21 D- GND
GND 8

*AZ2015-01H_ESD

*AZ2015-01H_ESD
4 3
2

1
2 1 RV6 SIDE_USB
2

1
RN28 *0X2_4

EGA-0402

EGA-0402
RV5
B B

2
2

2
USB USBVCC11
WCM2012-110
L43 USBVCC11 1
40 mils
PESD5V0U1BB
1 2 USB11_FB# 2
21 USBP11-

1
3 4 USB11_FB 3
21 USBP11+
4
100U/10V/7343

5 C492 D60
*100U/10V/7343
*PESD5V0U1BB
*PESD5V0U1BB

4 3 6 0.1U/25V/X5R_4 Buletooth
1

C490

C494

2 1
1

EGA-0402

RN33 F7
2
1

EGA-0402

*0X2_4 RV16 D56 D55 CN31 1 2 +5V_S5_USB


RV15 USBVCC6

100U/10V/7343

0.1U/25V/X5R_4
POLY_SWITCH
2

C399

C401
2

F6 BT USB
40 mils 1 2 USBVCC9 1 D61 2
+5V_S5_USB

100U/10V/7343
POLY_SWITCH PESD5V0U1BB 1 *WCM2012-110

C287
2
USB 3 USB10_FB 4 3 USBP10+ 21
WCM2012-110 4 USB10_FB# 2 1 USBP10- 21
L24 1 5

1
USB9_FB# BT_ON L8

EGA-0402

EGA-0402
A
21 USBP9- 1 2 2 6 A
3 4 USB9_FB 3 2 1
21 USBP9+
4 4 3
1

1
EGA-0402

EGA-0402
5 CN12 RV1 RV2 0X2_4

2
2 1 6 RN24
4 3 RV7 RV8
RN29 *0X2_4 Quanta Computer Inc.
2

CN30
R84 *100K_F_4 BT_ON
+5V_S5 PROJECT : ZN2
Size Document Number Rev
A
ON BOARD USB
Date: Tuesday, March 16, 2010 Sheet 31 of 49
5 4 3 2 1
5 4 3 2 1

EEPROM IIC Selection


BACKLIGHT CONTROL
CN35
PANEL EDID DATA 32

3
+5V

EEPROM_SCL 1 +3V +3V WRITE_EDID_ROM


2 2
+3V EEPROM_SDA
3
4 Address:A8/A9

1
*EDID CONNECTOR Q23
85205-04xx-4p-l DTC144EU C467 0.1U/10V/X5R_4
R486 +3V +3V
R69 10K_F_4 U21
+5V 8 1
10K_F_4 VCC A0
D 7 WC# A1 2 D
+3V C70 0.1U/25V/X5R_4 G1 6 3
SCL A3

1
WRITE_EDID_ROM 5 4
C465 SDA GND R481 R482
U20

5
*SHORT_PAD 4.7K_F_4 4.7K_F_4
D3 1 2 1SS355 2 0.22u/6.3V/X5R_4
16 VCC 8 24LC02
19,36 PWROK_EC

2
DISPON GND
4
BLON 1
U5 2
19,25 LCD_CLK IA0
TC7SH08FU 5 4 EEPROM_SCL
19,25 LCD_DAT

3
IB0 YA
11 IC0

2
14 7 EEPROM_SDA
C69 0.1U/25V/X5R_4 C71 ID0 YB
+3V

C461

C464
*1000P/50V_4 9,17,18,30,37 CLK_SCLK 3 9

1
IA1 YC

1
6
9,17,18,30,37 CLK_SDATA IB1 EMI
5

AD1 SDM10K45-7-F 10 12
IC1 YD
2 13

2
ID1

1000P/16V_4

1000P/16V_4
R64 0_J_4 4 BLON
19 INT_LVDS_BLON
1
U6 WRITE_EDID_ROM 1 15
22 WRITE_EDID_ROM S OE
TC7SH08FU
3

SN74CBT3257CPWR

R65 0_J_4
25 MXM_LVDS_BLON
+3V

R483 *2.2K_J_4 R516 2.2K_J_4


C C

PANEL VCC CONTROL


+5V
+5V LCDVCC Discharge panel power
LCDVCC
Q3
F1 2A LCDVCC
R44 C58 0.1U/25V/X5R_4 6 1 1 2 R48 R35
0_J_4 IN OUT 169_F_4
25 MXM_LVDS_PWREN 20K_F_4
4 2 RC1206
R46 IN GND
R47

3
0_J_4 DIGON_R 3 5 C65 C64 C62
19 INT_LVDS_PWREN ON/OFF GND
10U/6.3V_6 0.1U/25V/X5R_4 Q5 0.1U/25V/X5R_4
0_J_4 ME2N7002E
AAT4280IGU-1-T1 2
Q4

3
R43 DTC144EU
*10K_F_4
R45 DIGON_R 2

1
1
*10K_F_4
C63
3300P/50V_4

2
B B

TO INVERTER CONNECT LCD PANEL CONNECTOR


LCDVCC

CN9 F2
1 VIN_LCD 0_J_8 CN7
VIN
2 29 30
3 27 28
4 25 26
5 DISPON C80 C77 C93 C89 TXLOUT#1 TXLOUT2
19 TXLOUT#1 23 24 TXLOUT2 19
6 VADJ-1 10U/25V_1206 0.1U/25V/X5R_4 0.1U/25V/X5R_4 10U/25V_1206 TXLOUT1 TXLOUT#2
19 TXLOUT1 21 22 TXLOUT#2 19
7 19 20
8 TXLOUT#0 TXLOUT3
19 TXLOUT#0 17 18 TXLOUT3 19
9 TXLOUT0 TXLOUT#3
19 TXLOUT0 15 16 TXLOUT#3 19
10 L7 0_J_4 TXUCLK# TXLCLK
ADJ 36 19 TXUCLK# 13 14 TXLCLK 19
TXUCLK TXLCLK#
19 TXUCLK 11 12 TXLCLK# 19
2

C74 TXUOUT#7 9 10 TXUOUT4


INV CONNECTOR 19 TXUOUT#7 7 8 TXUOUT4 19
*1000P/50V_4 TXUOUT7 TXUOUT#4
19 TXUOUT7 TXUOUT#4 19
1

TXUOUT#6 5 6 TXUOUT5
A
PWM CONTROL 19
19
TXUOUT#6
TXUOUT6
TXUOUT6 3
1
4
2
TXUOUT#5
TXUOUT5 19
TXUOUT#5 19 A

LVDS CONNECTOR

87216-300x-30p-ldv

LVDS PIN Swap


Quanta Computer Inc.
PROJECT : ZN2
Size Document Number Rev
A
LCD PANEL/INVERTER
Date: Tuesday, March 16, 2010 Sheet 32 of 49
5 4 3 2 1
A B C D E

LAN Power LANVCC

3V_LAN
C471 C474
R496
R494 *1K_J_4
LANVCC
33
.1U/10V/X5R_4 22U/6.3V_8 0_J_8Width>40
mil
Trace<200 mil U22
EECS 1 8 C470
R495 *0_J_8 LED1/EESK CS VCC
2 SK DC 7
4 LED2/EEDI 3 6 *0.1U/16V/Y5V_4 4
R241 LED3/EEDO DI ORG
4 DO GND 5

6/22 *AT93C46A(3.3V)
R491 XTAL25
2.49K_F_4 Y2
0_J_8 XTAL25_1 1 2 R493 3.6K_F_6 LANVCC

CTRL15/VDD33
WIDE TRACE CTRL12A
XTAL25_R
25MHZ

CTRL12/VDD
CTRL12/VDD

LANVCC

LANVCC
DVDD12
1.2V source C260 C263

RSET

LED0
LANVCC
27P/50V_4 27P/50V_4

LED0 D57 1 2 1SS355 LAN_ACT# 34


Width>60 mil EC-A-01
U13 LED1/EESK D58 1 2 *1SS355

48
47
46
45
44
43
42
41
40
39
38
37
Trace<200 mil LAN_LINK# 34
Vender suggest R514 0_J_6

VCTRL12A/SROUT12
GND
RSET
VCTR12DVDDSR
NC/VDDSR
NC/ENSWREG
CKTAL2
CKTAL1
NC/AVDD33
NC/LV_PLL
LED0
VDD33
L39
CTRL12A EVDD12_R LED3/EEDO R239 0_J_6
4.7uH LAN_LINK1# 34

3 +3V 3
C473 C267 LANVCC 1 36 DVDD12
AVDD33 DVDD12 LED1/EESK
34 LAN0_MDI0+ 2 MDIP0 LED1/EESK 35
22U/6.3V_8 .1U/10V/X5R_4 34 LAN0_MDI0- 3 34 LED2/EEDI
DVDD12 MDIN0 LED2/EEDI LED3/EEDO
4 NC/FB12 LED3/EEDO 33
34 LAN0_MDI1+ 5 32 EECS
MDIP1 EECS GND R492
34 LAN0_MDI1- 6 MDIN1 GND 31
GND 7 RTL8111DL 30 DVDD12 1K_J_4
R497 GND DVDD12 LANVCC
34 LAN0_MDI2+ 8 NC/MDIP2 VDD33 29
EVDD12_R 0_J_8 EVDD12 34 LAN0_MDI2- 9 NC/MDIN2 ISOLATEB 28 ISOLATEB
DVDD12 10 27 LAN_REST#
C264 C261 DVDD12/AVDD12 PERSTB
34 LAN0_MDI3+ 11 NC/MDIP3 LANW AKEB 26 PCIE_WAKE# 19,30
34 LAN0_MDI3- 12 NC/MDIN3 CLKREQB 25 CLK_PCIE_LAN_REQ# 21
1U/6.3V_4 1U/6.3V_4 R236

NC/SMDATA
REFCLK_N
REFCLK_P

NC/SMCLK
DVDD12

EVDD12
15K_J_4

HSON
EGND
HSOP
R242

HSIN
HSIP
GND
0_J_8 LANVCC

U12

13
14
15
16
17
18
19
20
21
22
23
24

5
DVDD12 R238 *10K_F_4 LANVCC
2
C272 C271 C266 C253 C254 LAN_REST# 4

EVDD12
DVDD12
PLTRST# 10,21,22,28,30

GND

GND
2 1 2
*0.1U/10V/X5R_4 .1U/10V/X5R_4 .1U/10V/X5R_4 .1U/10V/X5R_4 .1U/10V/X5R_4
TC7SH08FU

3
+3VPCU
C257 0.1U/10V/X7R_4
21 PCIE_TXP3 PCIE_RXN3_CC258 0.1U/10V/X7R_4
PCIE_RXP3_C PCIE_RXN3 21
21 PCIE_TXN3 PCIE_RXP3 21 R237 *0_J_4
LANVCC
CLK_PCIE_LOMN 21

2
CLK_PCIE_LOMP 21
C259 C256 C270 C252 PR201

1
.1U/10V/X5R_4 .1U/10V/X5R_4 .1U/10V/X5R_4 .1U/10V/X5R_4 100K_J_6
PQ50

1
AO3413
2

3
C329
36 LAN_PWRON 2
DVDD12

3
1U/6.3V_6
1 1
*0_J_8 CTRL12/VDD PQ51
DTC144EUA-7-F

1
R499 3V_LAN
Quanta Computer Inc.
LANVCC 0_J_8 CTRL12/VDD PROJECT : ZN2
Size Document Number Rev
R498 1A
LAN(RTL8111DL)
Date: Tuesday, March 16, 2010 Sheet 33 of 49
A B C D E
5 4 3 2 1

34
LAN Transformer & EOS CONN to RJ45
D D

RJ45
C488 *1500P/50V_6

C487 *1500P/50V_6

CN26
LAN_ACT# R513 510_J_6 L3 13
33 LAN_ACT# Y-
L4 14
LANVCC Y+
R10 10
33 LAN0_MDI3- NC/3-
R9 9
33 LAN0_MDI3+ NC/3+
R8 8
C 33 LAN0_MDI2- NC/2- C

R7 7
33 LAN0_MDI2+ NC/2+
C479 1500P/3KV_1808 TCT1 R6 6 NC/6
TCT2 R5 5
C480 1500P/3KV_1808 NC/5
R4 4
33 LAN0_MDI1- RX-/1-
NC1 18
R3 3
33 LAN0_MDI1+ RX+/1+
NC 17
R2 2
33 LAN0_MDI0- TX-/0-
GND 16
R1 1
33 LAN0_MDI0+ TX+/0+
GND 15
33 LAN_LINK# LAN_LINK# R511 510_J_6 GLED- L1111
R512 LAN_LINK1#
*0_J_6 L1212 G-
LANVCC G+
33 LAN_LINK1#
C486 C485 RJ45-CONN
*1500P/50V_6 *1500P/50V_6

B B

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
1A
LAN Transformer & RJ45
Date: Tuesday, March 16, 2010 Sheet 34 of 49
5 4 3 2 1
5 4 3 2 1

2nd FAN CONN SYSTEM FAN CONN


35
+5V

VSET 3~1V Vout=4*Vset HDD_12V

2
VSET = 3V ; VO = 12V
VSET = 1V ; VO = 4V R1

2
3.3K_F_4
+5V VSET 3~1V Vout=4*Vset R90
FOR EMI
D D
C1 VSET = 3V ; VO = 12V 3.3K_F_4
CN1

1
2.2u/25V_8 MXM_FAN_SENSE VSET = 1V ; VO = 4V
6 1

1
GND GND HDD_12V CPU_FAN_SENSE
5 GND 12V 2
3 MXM_FAN_SENSE R2 C85
SENSE CN13

2
4 0_J_4 2.2u/25V_8
CONTROL MXM_FAN_CTRL 36
6 1 R87
GND GND 15K_F_4
53048-0410 5 GND 12V 2
C2 MXM_FAN_TACH 3 CPU_FAN_SENSE
53398-0410-4P-L *10U/25V_1206 MXM_FAN_TACH 36 SENSE
4

1
CONTROL CPU_FAN_CTRL 36

2
DFHD04MR103 CPU_FAN_TACH
R5 CPU_FAN_TACH 36
53048-0410

2
6.2K_F_4 C86
53398-0410-4P-L *10U/25V_1206 R79
DFHD04MR103 6.2K_F_4

1
+5V_S5
close to conn TO WEB CAM MODULE
C
PS2 KEYBOARD& PS2 MOUSE C

2
*PESD5V0U1BB

*PESD5V0U1BB
D29 D27
C4 1 2 *10P/50V_4 USB4_FB

R248 R249
FOR EMI C3 1 2 *10P/50V_4 USB4_FB#
*4.7K_J_4 *4.7K_J_4

1
CN25 L21
*BLM18PG181SN1D_6 C6 2 1 22P/50V/4 DMIC_CLK
1 TPCLK2 36
2 C5 0.1U/25V/X5R_4 CCD_VCC
3 TPDATA2 36
4
+5V_S5 7 5 L23 *BLM18PG181SN1D_6
close to conn

1
8 6 C279 C281 RN1 2 1 0X2_4
4 3 change BOM value
2

2
*PESD5V0U1BB

*PESD5V0U1BB

*220P/X7R_4 *220P/X7R_4

2
D33 D32 *PS2 CN2
*90ohm,400mA L1
2 1 USB4_FB 1
+5V_S5 21 USBP4+
R254 R255 4 3 USB4_FB# 2
21 USBP4-
*4.7K_J_4 *4.7K_J_4 CCD_VCC 3
1

CN33 R4 Bead 4
26 DMIC_CLK
L25 *BLM18PG181SN1D_6 R3 Bead 5
26 DMIC_DAT
1 L22 6
TPCLK1 36
B 2 1 2 B
3 TPDATA1 36 R403 and R392 (0 ohm)are changed to bead for EMI damand.
4 *POLY_SWITCH
7 5 L27 *BLM18PG181SN1D_6
1

8 6 C289 C291 C278 C280


*0.1U/10V/X7R_4 *0.1U/10V/X7R_4
*220P/X7R_4 *220P/X7R_4
2

*PS2
+5V_S5_USB +3V_S5
+5V_S5 CAMERA POWER CONTROL
FOR EMI CHANGE CAP 1:DATA 1:DATA
R257 R259
6 5 2:NC 6 5 2:NC 0_J_8 *0_J_8 CCD_VCC
L26 3:GND 3:GND R258
1 2
4 4:VCC 4 4:VCC
*POLY_SWITCH 3 5:CLK 3 5:CLK Q11
C290 C288 2 1 6:NC 2 1 6:NC *AO3403 0_J_8 C292 10U/10V/X5R_8

+
*0.1U/10V/X7R_4 *0.1U/10V/X7R_4
1 3 C293 1000P/50V/X7R_4

C294 0.1U/25V/X5R_4

2
A A
CCD_POWER_ON# 36

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
FAN/Webcam/PS2
Date: Tuesday, March 16, 2010 Sheet 35 of 49
5 4 3 2 1
5 4 3 2 1

EC Layout Note:
Place all capacitors close to IT8512.
EC_3AVCC L4 BK1608HS121-T +3VPCU
+3VPCU 36
3VPCU_EC +3VPCU C57 C59 EC_3VSTBY L6 BK1608HS121-T +3VPCU
C72 .1U/10V/X5R_4
1000P/50V/X7R_4 .1U/10V/X5R_4

L28 0_J_4 H_PECI R63 *4.7K_J_4 +3VPCU


C389 C392 C391 C390 C393 C388
BL_UP# 30
CIR_ED1 HWPG R68 *10K_F_4 MXM_SMCLK12 R347 4.7K_J_4
CIR_ED1 30
0.1U/25V/X5R_4 0.1U/25V/X5R_4 0.1U/25V/X5R_4 MXM_SMDATA12R348 4.7K_J_4
0.1U/25V/X5R_4 0.1U/25V/X5R_4 0.1U/25V/X5R_4 S5_Power_ON 46 NBSWON# R67 10K_J_4
MXM_PWR_LEVEL# 25 LPCPD# R72 *10K_J_4
HWPG MXMPWR_EN 25 SWI# R80 10K_J_4
EC_AMP_MUTE# 26
D SUSC# 19 D
C395 R353
CLK_PCI_775

+VCCRTC
SUSON 42,46 THERM_CLK_EC R61 4.7K_J_4
*10P/50V_4 *22_J_4 ICH_RSMRST# 19 THERM_DAT_EC R62 4.7K_J_4 +3V
+3V 3VPCU_EC VRON 44
PWROK_EC 19,32 EJECT# R74 10K_J_4
MAINON 39,42,43,45,46 BL_UP# R38 10K_J_4
CIR_TX1 30 BL_DW# R66 10K_J_4
CIR_RX1 30
PWRLED CCD_POWER_ON# R39 *10K_J_4
PWRLED 39
C78
ICH_PWRBTN#
.1U/10V/X5R_4 HWPG

114
121

127

107
SUSC#

11
26
50
92

74

84
83
82

56
57
33
19
20

99
98
97
96
95
94
93
3
C56
10 110 C81 C73

KSO16/GPC3
KSO17/GPC5
GINT/GPD5
L80HLAT/GPE0
L80LLAT/GPE7

GPG1/ID7
GPH6/ID6
GPH5/ID5
GPH4/ID4
GPH3/ID3
GPH2/ID2/BADDR1
GPH1/ID1/BADDR0
VCC

AVCC

GPE1/ISAD
VBAT
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY

VSTBY

GPE3/ISCLK
GPE2/ISAS

GPH0/ID0/SHBM
20,30 LPC_LAD0 LAD0 SMCLK0/GPB3 MXM_SMCLK12 25
9 111 *39P/50V/4
20,30 LPC_LAD1 LAD1 SMDAT0/GPB4 MXM_SMDATA12 25

SM BUS
8 115 *39P/50V/4 *39P/50V/4
20,30 LPC_LAD2 LAD2 SMCLK1/GPC1 THERM_CLK_EC 37
20,30 LPC_LAD3 7 116 THERM_DAT_EC 37
R75 10K_J_4 LID# LAD3 SMDAT1/GPC2 H_PECI
+3VPCU 22 117 H_PECI 10,22
CLK_PCI_775 LPCRST#/WUI4/GPD2 SMCLK2/GPF6
21 CLK_PCI_775 13 118 BL_DW# 30
LPCCLK SMDAT2/GPF7 +3V
20,30 LPC_LFRAME# 6
LFRAME#
85 TPCLK1 35
LPCPD# PS2CLK0/GPF0
17 86
LPCPD#/WUI6/GPE6 PS2DAT0/GPF1
PS2CLK1/GPF2
87
TPDATA1
TPCLK2
35
35
R71 HWPG

PS/2
22 SIO_A20GATE
126
GA20/GPB5 GPIO PS2DAT1/GPF3
88 TPDATA2 35
D2 BAS316 5 89 DNBSWON#
20 IRQ_SERIRQ SERIRQ PS2CLK2/GPF4 ICH_PWRBTN# 19
15 90 D1 BAS316 10K_J_4
22 SIO_EXT_SMI# ECSMI#/GPD4 PS2DAT2/GPF5 VGA_THERM# 25
D9 BAS316 23 LPC R36 0_J_4 HWPG
22 SIO_EXT_SCI# PCURST# D6 BAS316 ECSCI#/GPD3
14
D5 BAS316 WRST# R37 *0_J_4 D4 BAS316
4 VGA_ALT# 25 42 HWPG_1.5V
22 SIO_RCIN# SENSOR OUT KBRST#/GPB6
16
D10 BAS316 PWUREQ#/GPC7 R70
Reserve PWM0/GPA0
24
ADJ 32
*20K_F_4
R83 *10K_J_4 25 D8 *BAS316

C
30 CIR_RX0
CIR_RX0 119
123
GPC0/CRX
GPB2/CTX CIR
IT8512 PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
28
29
30
R152 0_J_4 PWRLED0#
EJECT#
PWRLED1#
30
30
30
CPU_FAN_CTRL 35
41 VAXG_PWRGD

10,43 CPU_VTT_PG
D11 BAS316
C
T3 31 D12 BAS316
PWM5/GPA5 SWI# 22 45 +1.05V_PG
+3V 32 D7 BAS316 CPU_VTT_PG 10,43
PWM6/GPA6 MXM_FAN_CTRL 35
PWM PWM7/GPA7
34
Ir_LED_ON# 30
1.1V leavel
R565 47 R350 0_J_4
TACH0/GPD6 CPU_FAN_TACH 35
48 R349 0_J_4
*150_F_4
Reserve TACH1/GPD7 MXM_FAN_TACH 35 8Mbit , SPI
120
2

+3VPCU TMR0/WUI2/GPC4 SLP_MINI# 30 +3VPCU


124
LED5 +3V TMR1/WUI3/GPC6 LAN_PWRON 33
*LED17-21VGC-TR8 CN8
R352
470K_J_4 1 125 NBSWON# 30
PWRSW/GPE4
2 18 SUSB# 19
1

SENSOR OUT RI1#/WUI0/GPD0 R73 10K_J_4 R33


3 WAKE UP RI2#/WUI1/GPD1
21 3VPCU_EC
PCURST# 10K_J_4 R60
35 -PCUHOLD 10K_J_4
WUI5/GPE5
112
C394 RING#/PWRFAIL#/LPCRST#/GPB7 U3
0.1U/25V/X5R_4 1.5VSUS = EAD1.5 8512_SCE# 1 8
+12V = EAD12 * 6 8512_SCK R59 47_J_4 8512_SCK_R CE# VDD
109 dGPU_PRSNT# 10,22,25 6
TXD/GPB1 8512_SI R58 47_J_4 8512_SI_R SCK C68
UART RXD/GPB0
108 CLKRUN# 19 5
SI
8512_SO R34 15_J_4 8512_SO_R 2 7
SO HOLD# .1U/10V/X5R_4
66 3 4
R56 10K_J_4 ADC0/GPI0 WP# VSS
106 67 ADP-ID 39
FLRST#/WUI7/GPG0/TM ADC1/GPI1

1
8512_SCK 105 68 W25X80
FLCLK/SCK ADC2/GPI2 PCIRST# 30 *MMBT3906
104 69 22 WP# 2
8512_SO FLAD3/GPG6 ADC3/GPI3 SW1 Q15
103
FLAD2/SO FLASH ADC4/GPI4
70
8512_SI 102 71

3
8512_SCE# FLAD1/SI ADC5/GPI5 NBSWON#
101 72 1 3
R52 *100K_J_4 FLAD0/SCE# ADC6/GPI6
100
FLFRAME#/GPG2 A/D D/A ADC7/GPI7
73 2 4

MY0 36 *SW_1-4P
MY1 KSO0/PD0
37
MY2 KSO1/PD1
38
MY3 KSO2/PD2
39 76
B
MY4 KSO3/PD3 DAC0/GPJ0 PCH_ACIN 19 B
Note 1 : Since all GPIO belong to VSTBY power domain, and 40
KSO4/PD4 KBMX DAC1/GPJ1
77
MY5 41 78
there are some special considerations below: KSO5/PD5 DAC2/GPJ2 CCD_POWER_ON# 35
MY6 42 79
(1) If it is output to external VCC derived power domain MY7 43
KSO6/PD6 DAC3/GPJ3
80 T1
circuit, this signal should be isolated by a diode such as MY8 KSO7/PD7 DAC4/GPJ4 T2
44 81
MY9 KSO8/ACK# DAC5/GPJ5
KBRST# and GA20. 45
KSO9/BUSY
MY10 46
(2) If it is input from external VCC derived power domain MY11 KSO10/PE PMUX1 *0_J_6 R76
51 2 ICH_SUSCLK 19
KSI3/SLIN#

circuit, this external circuit must consider not to float the KSO11/ERR# CK32KE
KSI1/AFD#
KSI0/STB#

KSI2/INIT#

MY12 52 CLOCK 128 PMUX2


GPIO input. MY13 KSO12/SLCT CK32K
53
KSO13
AVSS

Note 2 : MY14 54 +3VPCU


KSI4
KSI5
KSI6
KSI7

VSS
VSS
VSS
VSS
VSS
VSS
VSS

MY15 KSO14
(1) Each input pin should be driven or pulled. 55 Y1
KSO15 220Px4 CP6 *88502-2401-24P-L
RP3
(2) Each output-drain output pin should be pulled. MX5 MY3
IT8512 U4 1 4 7 8 10 1
58
59
60
61
62
63
64
65

1
12
27
49
91
113
122

75

Layout Note: 2 3 5 6 MX4 MY4 9 2 MY2


24
24 MX2
Place R471,R498,R534 within 500 mils from SPI AJ085120F05 3 4 MY15 MY5 8 3 MY1 23 MX4
1

1
23
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

1 2 MY10 MY6 7 4 MY0 22 MX1


Flash.Place R567 within 500mils from R534; C75 32.768KHZ C76 MY7 22 MX7
6 5 21
R520 within 500mils from R498 and R570 within 12P/50V_4 12P/50V_4 21 MX3
20
2

2
500mils from R471. 220Px4 CP5 20 MX0
10KX8 19
MY0 19 MX6
7 8 18
MX0 18 MX5
5 6 RP2 17
MX6 MY11 17 MY4
3 4 10 1 16
C79 R354 MY8 MX0 MY10 16 MY1
1 2 9 2 15
*0_J_4 MY12 MY9 15 MY3
Layout Note: 8 3
14
14
.1U/10V/X5R_4 32.768kHz clock lines: MY13 7 4 MY8 13 MY5
220Px4 CP4 MY14 13 MY6
6 5 12
a. If possible, please avoid using any through-hole. 7 8 MX7 12
11 MY7
b. Please make the trace length short, and the trace width wide enough. MY13 11 MY8
5 6 10KX8 10
MX1 10 MY9
c. The spacing to the closest neighbor should be wide enough. 3 4
9
9
1 2 MX3 RP1 8 MY10
+3VPCU MX3 8 MY14
10 1 7
MX6 MY15 7 MY11
9 2 6
220Px4 CP3 MX5 MX2 6 MY2
8 3 5
MY12 MX4 MX1 5 MY0
7 8 7 4 4
MY11 MX7 4 MY12
5 6 6 5 3
1

MY3 3 MY13
3 4 2
MX2 2 MY15
A 1 2 10KX8 1 A
NBSWON# Q16 1
30 NBSWON# 2
DTA124EU CON2
220Px4 CP2
7 8 MY6
3

-PCUHOLD 5 6 MY14
19 SUSB#
D39 BAS316 3 4 MY9
1 2 MY2

R351 220Px4 CP1

100K_J_4
7 8 MY4
MY1
Quanta Computer Inc.
5 6
3 4 MY5
1 2 MY7 PROJECT : ZN2
Size Document Number Rev
A
EC ITE 8512N/FLASH
Date: Tuesday, March 16, 2010 Sheet 36 of 49
5 4 3 2 1
1 2 3 4 5 6 7 8

CPU XDP Connector 37


bsh-060-01-l-d-60p-ldv
XDP0 - CPU bsh-060-01-l-d-60p-ldv
+1.1V_VTT

A +1.1V_VTT +1.1V_VTT A

Change to NI_T_BY ICE

CN34
1 1 2 2
CPU_TDI R263 51_F_4 3 4
10 XDP_CPU_PREQ_N 3 4
10 XDP_CPU_PRDY_N 5 5 6 6
7 8
CPU_TMS R264 51_F_4 7 8
9 10
9 10
CPU HAS INTEGRATED 11
11 12
12
13 14
CPU_TDO R261 51_F_4 TCK/TMS/TDI TERMINATION. 15
13 14
16
+1.1V_VTT 15 16
17 18
17 18
19 20
19 20
21 22
CPU_TCK0 R271 51_F_4 21 22
23 24
23 24
25 26
R265 25 26
27 27 28 28
CPU_TRST_N R262 51_F_4 29 30
1.3K_F_4 29 30
XDP_PFRST_N 31 31 32 32
33 33 34 34
35 36
35 36
37 37 38 38
R266 *0_J_4 XDP_PWRGD 39 40
10 XDP_CPU_PWRGD 39 40 XDP_CPU_BCLK_P 10
R267 0_J_4 41 42
10 XDP_PFRST_N 41 42 XDP_CPU_BCLK_N 10
43 43 44 44
45 46 XDP_RESET1# 1K_F_4 R260
10 XDP_CPU_PWRGD 45 46 CPU_RESET_OUT_N 10
47 47 48 48 SYS_RST_N 10,19
49 50
R268 0_J_4 XDP0_SMBDAT 49 50 CPU_TDO
9,17,18,30,32 CLK_SDATA 51 52 CPU_TDO 10
R269 0_J_4 XDP0_SMBCLK 51 52 CPU_TRST_N
B 9,17,18,30,32 CLK_SCLK 53 53 54 54 CPU_TRST_N 10 B
55 56 CPU_TDI
CPU_TCK0 R270 0_J_4 55 56 CPU_TMS CPU_TDI 10
10 CPU_TCK0 57 57 58 58 CPU_TMS 10
59 60
59 60
C295 *CN XDP SMD 60P(P0.5,H3.25)
*DFHS60FS717

*1U/6.3V_4

CAD NOTE:
PLACE TDO TERMINATION NEAR XDP CONNECTOR
PLACE TCK/TDI/TMS END TERMINATION NEAR CPU

PCH XDP Connector

C C

+3V

C355
R323 1_6
Ambient U14
0.1u/10V_4

36 THERM_CLK_EC 8 1
SMCLK VCC
7 2 C26
36 THERM_DAT_EC SMDATA DXP
+3V R322 10K_4
SML1ALERT# R324 0_4 6 3 2200p/50V_4
21,22 SML1ALERT# -ALT DXN

1
MMBT3906
5 4 2
GND -OVT Q2
<check list> ADM1032ARMZ-2R +3V

3
Layout Note:Routing 10:10 mils and away MSOP8-4_9-65 10K_4 R319
from noise source with ground gard

D D

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
A
XDP
Date: Tuesday, March 16, 2010 Sheet 37 of 49
1 2 3 4 5 6 7 8
5 4 3 2 1

38

D D

Coaxil conn WLAN TV MXM


H21 H22 H16 H18 H17 H13
H23 H19

1
1

1
*h-c276d118p2 *h-c276d118p2 *h-c276d118p2 *h-c276d118p2 *H-C236D122P2 *H-C236D122P2
*h-c315d315n *h-c315d315n

CPU frame CPU fan


H6 H7 H10 H9 H8

1
*H-C276D138P2 *H-C276D138P2 *H-C276D138P2

1
*h-c276d169p2 *h-c276d169p2
C C

Board screw holes


H2 H20 H15 H24 H14 H26 H3
1

1
*h-c276d138p2 *h-c276d138p2 *h-c276d138p2 *h-c276d138p2 *h-c276d138p2 *h-c276d138p2 *h-c276d138p2

GND SHAPE for EMI in DDR3

H25 H27 H1
B
Delete B
1

*h-c276d165p2 *h-c276d138p2 *h-c276d165p2 H28

CPU socket
H4 H12 H5 H11

1
*spad-re348x756np
1

*H-C250D185PT *H-C250D185PT *H-C250D185PT *H-C250D185PT

Need discuss with ME/EMI

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
Screw Hole 1A

Date: Tuesday, March 16, 2010 Sheet 38 of 49


5 4 3 2 1
5 4 3 2 1

RAMP
ADP AC_IN & HDD12V PR239 *22R/J_1206

PQ43
*MMBT2907A

39
PR229
SOT23_3P
*62/F_6
INRUSH_PASS_THRU_E1 1 3

PQ82
*MMBT2907A

2
PR228
SOT23_3P
*62/F_6
INRUSH_PASS_THRU_E2 1 3

LED4

2
PL18
D 2 1 D
HI0805R800R-10/0805 PR243
PL17 VA *LED17-21VGC-TR8 *6.8K/F_6
dcjk-2dc1003-000313-6p-v PQ63
FDD6685 VIN
POWER_JACK HI0805R800R-10/0805
PL16
5 19V_DC_SOURCE VA 3 4
4 HI0805R800R-10/0805
3
6
PC115 PR104 PR94 PC92
RAMP

1
1
PC116 PC118 PC117
PJ1 0.1U/25V_6 200K/F_6 200K/F_6 0.1U/25V/X7R_6
1
2

0.1U/25V_6 2200P/50V_6 0.1U/25V_6 PD9


*P4SMAJ20A
15VPCU

2
PQ67
*MMBT2907A
SOT23_3P
RAMP PR227
200K/F_6
PR93 PC89
DC-IN JACK 1 3 820K/F_6 0.1U/25V_6

+3VPCU

2
INRUSH_B
PD6
PR245 PR241
*RB500V-40/UMD2
*100K/F_4 *2K/F_6
PR106

ADP-ID 36
*10K/F_6

PR232 EN3V5V
EN3V5V 40
PR230 PR233 1
13K/F_6 *13K/F_6 *100K/F_6
PC119 PD5
RAMP *PDZ3.3B VA

3
0.1U/25V/X7R_6
*MMBT3904
2
2

C PQ65 C

1
PR69
4.7K_F_6
Adapter Support ( Adapter ID ) PC212
Rid with no MXM stuffing: 64.9K Recommand use 150W adapter. PR231
RAMP

2
*3.3K/F_6 *0.1U/25V/X7R_6
Rid with MXM stuff: 49.9K Recommand use 180W adapter. LED1
LED17-21VGC-TR8
LED17-21VGC-TR8

3 1
PQ23
PWRLED 1
36 PWRLED *ME2N7002E PR66
0_J_8
PR68

2
*100K_F_4

VIN

+3VPCU +5V_S5 PL12

FBMJ3216HS480NT_1206

PD7

1
B PC198

2200P/50V_6
PC197

0.1U/50V/X7R_6
PC196

*10U/25V_1206
+ PC98

100U/25V_R6
RAMP B

RB500V-40/UMD2

2
5
6
7
8
2

PC191
PC194 PR211 PC195
PR212
*0.1U/16V/X7R_4 *10K_J_6 1U/16V_6 4
1_J_6 0.22U/25V/X5R_6 PQ53
MAX:4.4A
1

AO4468 OCP: 6A
2

+5V_S5 PU13
6

PR213
10 1
VCC

10K_J_6 MXM_12V
3
2
1

PG BST
7 3 12VCC
1

COMP/EN UG PL19
PR208 0_J_8
PR200 PR202 PC192
2 12VCC HDD_12V HDD_12V
3.3K_F_4 LX
PDGND

1000P/50V/X7R_4
3.3K_F_4 10UH/MSCDRI-1040-4.4A
GND

VOS

8 FB LG 4
5
6
7
8

PC190 NCP1589A PR205


11

2.2_J_8
0.22U/10V/X5R_4
2

4 PQ52 PC188 PC187 + PC96 + PC97


3

PR203
3

FDS6690AS 0.1U/50V/X7R_6 10U/25V_1206 100U/16V_R6_24 100U/16V_R6_24


PC193 10K_F_6
2

36,42,43,45,46 MAINON 2 1 PC189


1

0.022U/16V_4 PR209 PR210


2200P/50V_6
3
2
1

332_F_4 4.75K_F_4
PR204 PR206
RAMP
1

PQ48 PQ49
PR207
2

332_F_4 4.75K_F_4
DTC144EUA-7-F ME2N7002E 51.1_F_4

Iocth = (Iocset * Rocset) / Rds(on)


A FDS6690AS Rds(on) = 15 m ohm A

Iocset = 10 uA
Rocset(R266) = 10 k ohm
Iocth = (10 uA * 10 k) / 15 m ohm = 6.667A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
AC in & HDD12V 1A

Date: Tuesday, March 16, 2010 Sheet 39 of 49


5 4 3 2 1
A B C D E F G H

SYSTEM POWER +3V_VPCU/+5V_VPCU/+5V/+3V/+5V_S5/+3V_S5 40


VIN Place these CAPs Place these CAPs
close to FETs close to FETs
PL15

1 5VL 1
FBMJ3216HS480NT_1206
PD8
PR218 PR219

10U/25V_1206
10U/25V_1206
10U/25V_1206

10U/25V_1206
1 2

2200P/50V_4

2200P/50V_4
2

2
0.1U/25V/X5R_4

0.1U/25V/X5R_4

0.1U/25V/X5R_4
+ PC111 PR98
1K_F_4 150K_F_4

PC114

PC209

PC208
*10_F_4

PC199
UDZ5V6B-7-F

8206ON_LDO

PC202

PC201
PC200
*27U/25V_R6_40

PC206
PC205
1

1
2
PC107

1
0.1U/25V/X5R_4 PC103

1
1U/6.3V_4

2
1
5VL PR101 +3VPCU +/- 5%

5
6
7
8
PC106
*0.1U/10V/X5R_41
*0.1U/10V/X5R_4
0_J_4 Countinue current:5.1A

2
+2VREF 4
PC102 Peak current:6A

2
8
7
6
5
PC109 PQ55
+5VPCU +/- 5% 4.7U/6.3V_6 OCP minimum 7.5A

1
.1U/10V/X5R_4 AO4496
Countinue current:4.9A 4 PR99 +3VPCU

8
7
6
5
4
3
2
1
Peak current :6A 0_J_4 PL13

3
2
1
REF
LDOREFIN

IN
N.C

VCC
TON
LDO

ONLDO
5.2UH/CHOKE-MSCDRI-104R
OCP minimum :7.5A

2
PQ62 +3.3V_ALWP
+5VPCU PR217

2
AO4496 182K_F_4
PL14 9 32

1
2
3
2 PR222 BYP REFIN2 2
10 OUT1 ILIM2 31 1 2 PR102

5
6
7
8

2
3.8UH/CHOKE-MSCDRI-104R 270K_F_4 5V_FB1 11 PU6 30 3V_FB2
FB1 OUT2 0_J_4
1 2 12 29 PR216 *2.2_J_8 PR214
PGOOD1 ILIM1 RT8206B SKIP PGOOD2
TP33 13 28 TP32

1
PGOOD1 PGOOD2
2

8
7
6
5
EN3V5V 14 27 EN3V5V 4 0_J_4 PC99 + PC101
ON1 ON2
2

PR221 5V_DH 15 26 3V_DH

1
5V_LX DH1 DH2 3V_LX
PR225 16 25 PC104 .1U/10V/X5R_4 330U/6.3V_R6_16
*2.2_J_8 LX1 LX2
4 37
330U/6.3V_R6_16

*0_J_4 PAD
.1U/10V/X5R_4

+
4.7U/6.3V_6

36 *1500P/50V_4
1

PAD

AGND
PGND
BST1

BST2
39 PQ57

VDD
PAD
PAD
PAD
PAD

PAD
PAD
1

PAD

2
DL1

DL2
N.C
40
PC112
PC108

3
2
1
PC113

PAD AO4712

2
PC203 PR215
PC110 PC100
*1500P/50V_4
RAMP

38
35
34
33
17
18
19
20
21
22
23
24

42
41
0.1U/25V/X5R_4 0.1U/25V/X5R_4 *0_J_4
PQ58
1
2
3

1
2

AO4712

RAMP PR223
0_J_4
Rds(on) 17m ohm
1
PR103
2 5V_BST1 3V_BST2 1
PR100

2_J_6
2
Rds(on) 17m ohm
2_J_6
5V_DL 3V_DL
1

5VL
5VL

PR97
MAIND 1 2
EN3V5V 39
+5VPCU 100K_F_4

2
4

1
PR220 PC105
5 PQ56
+5V 3 6 *0_J_4 1U/6.3V_4

2
3 2 7 +3VPCU AO4468 3

1
120mils 1 8
8 1
7 2 +3V
PQ60 6 3
AO4468 5
PR96 0_J_4
10 SYS_SHDN#

4
S5_PWRON 0_J_4 PR224
Iocp = (Vtrip / Rds_on) + (Iripple / 2) = (Vtrip/Rds_on) + (1/(2 * L * f) * (Vin - Vout)*Vout / Vin) MAIND 42,46
*22P/50V_4 PC204
PQ54
AO4712 MOSFET Rds_on = 15 m ohm ~ 18 m ohm 3VPCU Operate Frequence by 500kHz AO6402A
4

+5V_S5 5
5VPCU Operate Frequence by 400kHz Rtrip = 182 K ohm 6
5 4 +3V_S5
3 6 2

160mils
2
1
7
8
Rtrip = 270 K ohm Vtrip = 182 K ohm * 5/10 = 91 mV 1

3
PQ59 Vtrip = 270 K ohm * 5/10 = 135 mV PL8 = 5.2 uH Iocp_3VPCU = 6.06 ~ 5.05 A
AO4468
SUSD 0_J_4 PR226 PL8 = 3.8 uH Iocp_5VPCU = 9 ~ 7.5 A
46 SUSD
*22P/50V_4 PC207
S5_PWRON 46
4

4 5 4
+5V_S5_USB
3 6
2 7
160mils 1 8

PQ61
AO4468
Quanta Computer Inc.
PROJECT : ZN2
Size Document Number Rev
1A
+5V_VPCU/+3V_VPCU (RT8206B)
Date: Tuesday, March 16, 2010 Sheet 40 of 49
A B C D E F G H
5 4 3 2 1

V_AXG 41
PL10
VIN
FBMJ3216HS480NT_1206

1
10U/25V_1206

100U/25V_R6
2200P/50V_4

0.1U/25V/X5R_4

0.1U/25V/X5R_4
2

2
D + D

PC58

PC59

PC57
PC61

PC60
PQ20

1
4 AOL1448
V_AXG

1
2
3
+5V_S5 +5V_S5
RAMP
PL11 V_AXG_1
0.45UH/PCMB-1045-25A
+3VPCU

PR55
4.7_F_4
PR48 PQ21 PQ22

560U/2.5V_R6_16

560U/2.5V_R6_16

560U/2.5V_R6_16
PC70

2.2_J_6
10K_F_4 AOL1718 AOL1718

PR57
1U/10V_6 PR63 JP1

PC62

PC63

PC64
PC67 + + + PC179
36 VAXG_PWRGD VAXG_PWRGD 7.5K_F_4 0_F_4
1 18 1U/10V_6
PGOOD VCC
10 GFX_VR_EN 17 EN .1U/10V/X5R_4
GFXVID7 32 19 4 4

2200P/50V_6
GFXVID6 VID7 PVCC
25
GFXVID5 VID6 V_AXG_BOOT
26 22

1
2
3

1
2
3
VID5 BOOT PC75

PC77
GFXVID4 27 PC65
V_AXG GFXVID3 VID4
GFXVID2
28
29
VID3
23
0.1U/50V/X7R_6
V_AXG_UGATE
20A
GFXVID1 VID2 UGATE V_AXG_PHASE
30 VID1 PHASE 24
C GFXVID0 V_AXG_LGATE .1U/10V/X5R_4 C
31
VID0 LGATE
21 OCP:26A
PR65
16 V_AXG_ISEN_P
100_J_4 ISEN1+
15
ISEN1-
12
VSEN V_AXG_ISEN_N
10 VCCGT_SENSE_P PC74 PR62 PC76
PC78
14 0.01U/25V_4 41.2K_F_4 For Lynnfield CPU.
ISENNO .1U/10V/X5R_4
*0.001U/50V_4
10 VCCGT_SENSE_N
11
RGND PR59 PC73
OCSET 13
PR64 680_F_4 1000P/50V_4
PR61 1.6K_F_4
+5V_S5 100_J_4
20
NC
PR53
V_AXG_OFS 5 10 V_AXG_VDIFF
OFS VDIFF
PR58 4.7K_F_4 PC72 PR60 1K_F_4
*84.5K_F_4 V_AXG_REF 4 8
REF DVC
PR52 9 V_AXG_FB 8200P/25V_4
V_AXG_FS FB
3 FS
7 V_AXG_COMP PC71 330P/50V_6
*80.6K_F_4 V_AXG_SS COMP
2
SS
6 V_AXG__APA
APA
33
PR50 PR49 GND PC69 1000P/16V_4
PR51 PC66
18K_F_4 80.6K_F_4 0.01U/16V_4 80.6K_F_4
PU4 PC68
B B
ISL6314CRZ PR56 5.1K_F_4 0.01U/16V_4
PR54 1K_F_4

GFXVID7
10 G_VID7
GFXVID6
10 G_VID6
GFXVID5
10 G_VID5
GFXVID4
10 G_VID4
GFXVID3
10 G_VID3
GFXVID2
10 G_VID2
GFXVID1
10 G_VID1
GFXVID0
1K_F_4
*1K_F_4

*1K_F_4

*1K_F_4

*1K_F_4

*1K_F_4

*1K_F_4

*1K_F_4

A A
PR191

PR184

PR186

PR185

PR187

PR188

PR189

PR190

Quanta Computer Inc(QCI).


211, Wen Hwa 2nd Rd., Kuei Shan,
Tao Yuan 33377, Taiwan
Tel : +886-3-327-2345
Title
ZN2
Size Document Number Rev
Custom A01
V_AXG(GFX)
Date: Tuesday, March 16, 2010 Sheet 41 of 49
5 4 3 2 1
5 4 3 2 1

DDR3_1.5V(TPS51116)
42

D VIN D

PL2
PC135 10U/6.3V_6
FBMJ3216HS480NT_1206
1.5VSUS_1

PC39 PC38 PC211 PC24 PC29 PC28


PR18 0_F_6 PC15 0.1U/25V/X7R_6
51116_BST 0.1U/25V/X5R_4 2200P/50V_4 10U/25V_1206 10U/25V_1206 10U/25V_1206 0.1U/25V/X7R_6
SMDDR_VTERM

5
51116_DH
PC134 PC130
51116_LX 4
10U/6.3V_6 10U/6.3V_6
51116_DL

1
2
3
PQ7
AOL1448 Continue current 20 A +1.5V_SUS
PL4

25

24

23

22

21

20

19
CHOKE COIL 0.88UH,20%20A(PCMC104T-R88MN)
1.5VSUS_1

LL

DRVL
VTT

VBST
GND

VLDOIN

DRVH
1 VTTGND PGND 18
PR149

5
2 17 +5VPCU PC37
C VTTSNS CS_GND 2.2_J_6 + PC27 + PC210 C
PR116
3 16
GND TPS51116RGE or CS

0.1U/25V/X7R_6
4 4 560U/2.5V_R6_16 *560U/2.5V_R6_16
DIS_MODE 6.81K_F_4
TP1 4 MODE RT8207GQW V5IN 15
5.1_F_6
*0_F_6 PR115

1
2
3

1
2
3
SMDDR_VREF PR3 VTREF 51116_V5FILT PQ6 PQ64
1 5 14
VTTREF V5FILT PC140
51116_V5FILT AOL1718 *AOL1718
6 13
COMP PGOOD

1
VDDQSNS PC122 PC123 2200P/50V_4
VDDQSET 1U/6.3V_4 1U/6.3V_4
PC9

2
NC

NC
0.033U/50V_6 S3

S5
7

10

11

12
PR12 100K_F_6
PU7 +3VPCU
TPS51116RGE
HWPG_1.5V 36

PR7 620K_F_4
VIN

PR110 0_J_4
1.5VSUS_1
SUSON 36,46

AOL1718 Rdson * 2 = 3.4 ~ 4.3 m Ohms

1
PC121
1.5VSUS Operate Frequence by 400kHz
1

R256 *1U/6.3V_4
PC120 PR109 0_J_4 2 Rtrip = 6.81 k ohm Vtrip = 6.81 k * 10 uA = 68.1 mV
B 100P/50V/NPO_6 10K_F_4 B

PR108 *0_J_4
PL26 = 0.88 uH
2

S3_1.5V
MAINON 36,39,43,45,46 Iocp_1.5VSUS = 22 ~ 21.98 A
PR1 *0_J_4
VDDQSET +5VPCU
Iocp_1.5VSUS_worst_case = 24.54 ~ 16.1 A
1

PR107
VDDQSET
10K_F_4 GND = 2.5V Iocp = (Vtrip / Rds_on) + (Iripple / 2) = (Vtrip/Rds_on) + (1/(2 * L * f) * (Vin - Vout)*Vout / Vin)
5V = 1.8V
2

R = 1.5~3V
MAIND
PR114 *0_J_4 MAIND 40,46
DIS_MODE

+1.5V +1.5V_SUS

3
PR111 0_J_4
1.5VSUS_1 1A 1
2
4 5
6

PQ4
PC25
AO6402A
PR118 short
A 0.1U/25V/X7R_6 A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
DDR3 1.5V(TPS51116) 1A

Date: Tuesday, March 16, 2010 Sheet 42 of 49


5 4 3 2 1
5 4 3 2 1

CPU_VTT(1.1V) 43

VIN
D D

PL3

FBMJ3216HS480NT_1206

10U/25V_1206

10U/25V_1206
5

2200P/50V_6

100U/25V_R6
100U/25V_R6
0.1U/25V/X7R_6

0.1U/25V/X5R_4
2
+ +

PC35
PC21
PC31

PC34

PC33

PC22
PC32
4

1
1
2
3
PQ5 RAMP 1.1V 30A +1.1V_VTT

AOL1448 PL1
CPU_VTT_1.1V_1
+3VPCU +5V_S5 +5V_S5
CHOKE 0.23U(40A,+-20%,SIHH1170-R23M-R29)

PR27 PR19
4.7K_J_4 4.7_F_4 PQ3 PQ2

10,36 CPU_VTT_PG AOL1718 AOL1718

560U/2.5V_R6_14

560U/2.5V_R6_14
5

560U/2.5V_R6_14

560U/2.5V_R6_14
2.2_J_6
PR10
C + + + + C

PR23

0.1U/25V/X7R_6
PC18 10K_F_4
1U/10V_6 4 4
PC23
CPU_VTT_PG_R 1 18

PC11
PR16

PC30

PC12

PC19

PC10
1K_F_6

2200P/50V_6
PGOOD VCC 1U/10V_6
17 OCP:36A

1
2
3

1
2
3
36,39,42,45,46 MAINON EN
32 19
PR29 VID7 PVCC

PC16
10K_J_4 25
+3VPCU VID6
26 22 CPU_VTT_BOOT
VID: 01010010 (1.1000V) VID5 BOOT
27 VID4
28 PC26 0.1U/50V/X7R_6
10 VTT_SELECT_VID3 VID3
29 23 CPU_VTT_UGATE PC3
CPU_VTT_1.1V_1 VID2 UGATE CPU_VTT_PHASE 0.1U/16V/X7R_4
30 24
VID1 PHASE CPU_VTT_LGATE
31 21

PR6
PR141
1K_J_4
VID0 LGATE

ISEN1+ 16
15
CPU_VTT_1.1V_1 RAMP
100_J_4 ISEN1- CPU_VTT_ISEN_N
12 VSEN
PC8 PR8 PC124
PC7
10 VSENSE_DIE_CPU0_VTT_P 0.01U/25V_4 80.6K_F_4 0.1U/16V/X7R_4
14
0.001U/50V_4 ISENNO
10 VSENSE_DIE_CPU0_VTT_N
11 PR117 3K_F_4
RGND
13
OCSET
PR5 PR4 PC2
+5V_S5
100_J_4 20 1.5K_F_4 4700P/25V_4
NC
PR135
CPU_VTT_OFS 5 10 CPU_VTT_VDIFF
OFS VDIFF
B *100K_F_4 PR14 4.7K_F_4 PR11 1K_F_4 B
CPU_VTT_REF 4 8
REF DVC
CPU_VTT_FB PC5 8200P/25V_4
PR24 9
CPU_VTT_FS FB
3
FS CPU_VTT_COMP
7
80.6K_F_4 CPU_VTT_SS COMP
2
SS PC14
6 CPU_VTT_APA 330P/50V_6
APA
33
GND PC17 1000P/16V_4
PR133 PR138 PC20 PR25
*18K_F_4 *80.6K_F_4 0.01U/16V_4 80.6K_F_4 PU1
ISL6314CRZ PR21 5.1K_F_4 PR15 PC6
3.9K_F_4 0.01U/16V_4

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
CPU_VTT_1.1V 1A

Date: Tuesday, March 16, 2010 Sheet 43 of 49


5 4 3 2 1
5 4 3 2 1

44
CPU_CORE(NCP5392)

D +1.1V_VTT
+5V_S5 VIN_CPU
12VCC +5V_S5
RAMP VIN_CPU D

PD1
PR157

2
CPU_BST1 PC151 PC150 PC147 PC148 PC149
PR39 PR165 2.2_J_6
RB500V-40/UMD2 PC146 2200P/50V_4 0.1U/25V/X5R_4
10U/25V_1206 10U/25V_1206 10U/25V_1206
PR164

1
5
2.2_J_6 150K_F_4
0.1U/25V/X7R_6
2.2_J_6 PU2

1
0_J_8
CPU_12VMON 4 8
PR31
CPU_DH1 4 PQ8
RAMP

BST
VCC DRVH PL5
PR30 10K_J_4
AOL1448 0.36UH/PCMC135T-R36MF-41A

1
2
3
7 CPU_SW1

PGND
PC154 SWN
PR161 PR163 PC155 PR158 2

5
IN
0.1U/25V/X7R_6 3 5
*1K_F_4 2.2U/6.3V_6 OD DRVL
2K_F_4 10K_F_4 PR32 PR155

6
2.2_J_6 PC152 NCP5359A CPU_DL1 4 4 2.2_J_8
1U/16V_6 PR22 PR20
PQ9 0_J_4 0_J_4

1
2
3

1
2
3
PQ10
PC158 PC145 PU8 PC153
AOL1718 AOL1718 2200P/50V_6
*0.1U/16V/X7R_4 0.1U/16V/X7R_4 NCP5392TMNR2G

35

34
6X6 QFN
VR_READY 39 CS1

VCC

12VMON
9,19 VR_READY VR_RDY
1 29 CPU_DRVON CS1N
36 VRON ENABLE DRVON
VID0 2 30 CPU_PWM1
10
10
10
H_VID0
H_VID1
H_VID2
VID1
VID2
VID3
3
4
5
VID0
VID1
VID2
G1
CS1N
CS1
21
22
CS1N
12VCC +5V_S5
RAMP VIN_CPU
10 H_VID3 VID3 PR140 PR137 *100K_F_4 PC136
VID4 6
10 H_VID4 VID4 2.32K_F_4 PC137 *0.1U/16V/X7R_4 PD2
VID5 7 CS1 PR170
10 H_VID5

2
VID6 VID5 CPU_BST2 PC161 PC162 PC164 PC163 PC165
8
10
10
H_VID6
H_VID7
VID7 9
VID6
31 CPU_PWM2
0.22U/25V/X7R_6
PR166 2.2_J_6
OCP = 150A Fsw = 280KHz
VID7 G2 CS2N RB500V-40/UMD2 2200P/50V_4 0.1U/25V/X5R_4
10U/25V_1206 10U/25V_1206 10U/25V_1206
10 VCCP_PSI_N 37 23 PC166

1
5
PSI CS2N 2.2_J_6 0.8375V~1.6V/75A
15 24 0.1U/25V/X7R_6
PR120 PC132 DIFFOUT CS2 PR145 PU9
PR144 *100K_F_4 PC138

1
PC127 VR_COMP 16 2.32K_F_4 PR169 0_J_8 PQ13
4.12K_F_4 COMP CS2 PC139 *0.1U/16V/X7R_4
4 8 CPU_DH2 4
RAMP +VCC_CORE

BST
PR130 75_F_4 330P/50V_4 VCC DRVH
2200P/50V_4 AOL1448 PL6
C PC128 0.22U/25V/X7R_6 PR33 10K_J_4 C
0.36UH/PCMC135T-R36MF-41A

1
2
3
PR112 PR131 1K_F_4 32 CPU_PWM3 7 CPU_SW2

PGND
22P/50V_4 VR_VFB G3 CS3N SWN
+5VPCU 17 25 2

5
VFB CS3N IN
26 3 5

560U/2.5V_R6_14

560U/2.5V_R6_14

560U/2.5V_R6_14
560U/2.5V_R6_14
*100K_F_4 CS3 PR150 OD DRVL
18 PR148 *100K_F_4 PC141
VDRP 2.32K_F_4 PR167 PR168
PR122 2.94K_F_4

6
PR113 CS3 PC142 *0.1U/16V/X7R_4 2.2_J_6 PC159 NCP5359A CPU_DL2 4 2.2_J_8

22P/50V_4
4 + + + +
*100K_F_4

PC133
Place close PR125 634_F_4 PR34 PR35

PC36
PC45

PC44
1U/16V_6

PC40
0.22U/25V/X7R_6
to inductor PR26 PR128 PQ11 0_J_4 0_J_4

1
2
3

1
2
3
33 CPU_PWM4 PQ12
10K/NTC_J_6 G4 PC160
1K_F_4 27 CS4N AOL1718 AOL1718
+VCC_CORE CS4N 2200P/50V_6
PR123 634_F_4 19 28
VDFB CS4 PR154
PR132 PR153 *100K_F_4 PC143
20 2.32K_F_4
CSSUM CS4 PC144 *0.1U/16V/X7R_4 CS2 OS-CON
PR124 1K_F_4 715_F_4
CS2N
PR121 0.22U/25V/X7R_6
100_J_4 PC157
0.01U/16V_4
36

13
DAC
40 VR_HOT
12VCC +5V_S5
RAMP VIN_CPU

10 VCC_SENSE VSP VR_HOT VR_HOT 10


PD3 RAMP

2
PC131
ROSC

AGND
IMON

PR162 *10K_J_4 PR171 PC168 PC169 PC171 PC172 PC170


ILIM

*0.01U/16V_4 14 38 CPU_BST3
10 VSS_SENSE VSN NTC +3V
2200P/50V_4 0.1U/25V/X5R_4
10U/25V_1206 10U/25V_1206 10U/25V_1206

1
RB500V-40/UMD2 2.2_J_6
PR119 PC129 PC126 PC167
12
11

10

41

5
PR172
100_J_4 *0.1U/16V/X7R_4 *0.1U/16V/X7R_4 0.1U/25V/X7R_6
2.2_J_6 PU3

1
CPU_NTC PR159 *15K_F_4 PR41 0_J_8 PQ14
+5V_S5
4 8 CPU_DH3 4
RAMP

BST
VCC DRVH PL8
PR129 PR38 10K_J_4 AOL1448
0.36UH/PCMC135T-R36MF-41A

1
2
3
IMON 26.7K_F_4 CPU_SW3
10 H_ISENSE PR160 7

PGND
PC156 SWN
2

5
PR127 330_J_4 IN

560U/2.5V_R6_14

560U/2.5V_R6_14

560U/2.5V_R6_14
560U/2.5V_R6_14
The H_ISENSE do not connection *0_J_4 3
OD DRVL
5
PC125 Fsw= 280Khz *0.1U/16V/X7R_4
PR42 PR40
1U/16V_6

6
OCP = 120A PR126 2.2_J_6 PC173 NCP5359A CPU_DL3 4 4 2.2_J_8 + + + +
1U/16V_6 PR37 PR36

PC42
PC50

PC41
PC54
10.5K_F_4 PR152
>300us FILTER PQ16 PQ15 0_J_4 0_J_4

1
2
3

1
2
3
PC43
*10K/NTC_J_6 AOL1718 AOL1718 2200P/50V_6
B B

CS3
PR156 short CS3N

Place 12VCC +5V_S5


RAMP VIN_CPU

close to PD4
hottest PR44

2
CPU_BST4 PC175 PC176 PC177 PC178 PC174
MOSFET 2.2_J_6
+5VPCU RB500V-40/UMD2 2200P/50V_4 0.1U/25V/X5R_4
10U/25V_1206 10U/25V_1206 10U/25V_1206
PC53

1
5
PR43
0.1U/25V/X7R_6
2.2_J_6 PU10

RAMP

1
PR2 PR175 0_J_8
PR9 49.9K_F_4 4 8 CPU_DH4 4 PQ19
RAMP

BST
VR_VFB VCC DRVH PL9
9.09K_F_4 PR176 10K_J_4 AOL1448 0.36UH/PCMC135T-R36MF-41A

1
2
3
PC1 7 CPU_SW4

PGND
3

SWN
PQ1 2

5
150P/50V_4 IN
2 3 5
PR174 *0_F_6 OD DRVL
3 phase PR173 PR45
MMBT3904
option
1

6
2.2_J_6 PC52 NCP5359A CPU_DL4 4 4 2.2_J_8
VR_COMP 1U/16V_6 PR46 PR47
PR13 PC13 PQ17 0_J_4 0_J_4

1
2
3

1
2
3
PC4 PQ18 PC56
1K_F_4 0.1U/16V/X7R_4 PR17 0.033U/50V_6 AOL1718 AOL1718 2200P/50V_6
33K_F_4

CS4
CS4N

VIN VIN_CPU

PL7

A 1.5UH A

PC47 PC46 PC48 + PC49 + PC51 + PC55

0.1U/25V/X7R_6 0.1U/25V/X7R_6 10U/25V_1206 27U/25V/6R/45m 27U/25V/6R/45m 27U/25V/6R/45m

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
1A
CPU_CORE(VCC_CORE)
Date: Tuesday, March 16, 2010 Sheet 44 of 49
5 4 3 2 1
5 4 3 2 1

1.05V_PCH, 1.05V_ME, 1.8V_SRF


45
D D

VIN +1.5V_SUS

+5VPCU 3VREF
PU11 G914D
+5VPCU 3VREF
RAMP PC186 PC93 + PC91 1 IN VOUT 5
0.01U/25V_4 0.1U/25V/X7R_6
330U/2.5V_R6_16
3 SD BYP 4

G
PR194 PR196 PC181 PC182

2
6.8K_F_6 40.2K_F_6 1U/10V_6 PC180 1U/10V_6

5
0.1U/25V/X7R_6

8
3 +
1 4 PQ42 4 PQ41
2 -
PU12A AOL1448 AOL1448

1
2
3

1
2
3
4
LM358A
3

3
36,39,42,43,46 MAINON
PR195 1K_F_6
2 2
PR197

19.1K_F_6
PC183

0.1U/25V/X7R_6
PC185
RAMP PR95 For PCH
1K_J_6 1.05V_PCH
PQ46 PQ47
47P/50V/NPO_4
1

1
DDTC144EU DDTC144EU
C
6A C
1.05V_PCH +1.05V 1.05V
PR199 0_F_6
2.22A
change Footprint
RAMP PC184 PC95 + PC90 PC94

100P/50V/NPO_6 0.1U/25V/X7R_6 330U/2.5V_R6_16 0.01U/25V_4

+5V_S5 RAMP +5V_S5

B B
+3V_S5
PR72
PU5
PC79 100K_J_4 PR192
RT9025-25PSP
0.1U/50V/X7R_6
+1.8V +5V_S5
4 VPP PGOOD 1
PR70 1K_F_6 10K_F_4
EN_DTV1.8V 2 6 PR193
36,39,42,43,46 MAINON VEN VO
1.05V_PCH
+3V_S5 3 VIN 1.0A
8 PR67 +1.05V_PG
ADJ

GND +1.05V_PG 36
9 GND NC 5

3
43.2K_F_6 10K_F_4
1K_F_4
7

PC82 PC85 PC81


0.8V 1
PC84 PC83 PC80 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6
Ranper

3
PR198 PQ45
*0.1U/50V/X7R_6 10U/6.3V_6 0.1U/50V/X7R_6 PR71 2
PQ44

2
34K_F_6 TR NPN MMBT3904 40V 0.2A

1
ME2N7002E
Change Footprint

RAMP
Vout =0.8(1+R1/R2) =1.8V
A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
1A
1.05V_PCH, 1.05V_ME,1.8V
Date: Tuesday, March 16, 2010 Sheet 45 of 49
5 4 3 2 1
5 4 3 2 1

Discharge

46
D D

VIN +5V +3V +1.1V_VTT +1.5V +1.05V +1.8V V_AXG 15VPCU

PR80 PR73 PR74 PR75 PR76 PR77 PR78 PR79


22_J_8 22_J_8 22_J_8 22_J_8 22_J_8 22_J_8 22_J_8 PR82
1M_J_6
470K_J_6

MAING
MAIND 40,42

3
3

3
PQ25 PQ26 PQ27 PQ28 PQ29 PQ30 PQ31
MAINON 2 PR81 1 1 1 1 1 1 1 PQ32
36,39,42,43,45 MAINON PC86
ME2N7002E ME2N7002E ME2N7002E ME2N7002E ME2N7002E ME2N7002E ME2N7002E 1
PQ24 1M_J_6 ME2N7002E
*0.01U/50V_6
DTC144EUA-7-F
1

2
C C

VIN +5V_S5 +3V_S5 15VPCU

PR84 PR85 PR86 PR89


1M_J_6 22_J_8 22_J_8 1M_J_6

S5_PWRON S5_PWRON 40
3

3
3

PR83 PQ33 PQ34 PQ35


36 S5_Power_ON 2 1 1 1 PC88
1M_J_6 ME2N7002E ME2N7002E ME2N7002E
PQ40 *0.01U/50V_6
DTC144EUA-7-F
1

2
B B

VIN SMDDR_VTERM +1.5V_SUS 15VPCU

PR87 PR88 PR92


PR91
1M_J_6 22_J_8 22_J_8 1M_J_6

SUS_S3
SUSD
SUSD 40
3

2 PR90 PQ37 PQ38 PQ39


36,42 SUSON
1 1 1
PQ36 1M_J_6 ME2N7002E ME2N7002E ME2N7002E PC87

DTC144EUA-7-F *0.01U/50V_6
1

A A

Quanta Computer Inc.


PROJECT : ZN2
Size Document Number Rev
Discharge Circuit 1A

Date: Tuesday, March 16, 2010 Sheet 46 of 49


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DATE ZN2 Schematic file ZN2 Board file Revision

D
DATE Schematic Change Description D

10.Oct.2009 1. Add +3V pull up trace to CPU_SEL (page 09)


10.Oct.2009 2. Add the VTT_Select circuit as EL5 does. (page 10)
10.Oct.2009 3. Change the off page symbol of FDI Sync and Int as output from PCH to Processor. (Page 19)
10.Oct.2009 4. Populate the series resistance with ICH_PWRBTN# to EC. (Page 19)
10.Oct.2009 5. Add the CLKRUN# net from EC to ICH. (Page 36)
10.Oct.2009 6. Change the off page symbol of PMSYNC as the output type from PCH. (Page 19)
10.Oct.2009 7. Add the test point for L_BKLTCTL (Page 19)
10.Oct.2009 8. Correct the connection of the following net names: PWROK_EC, MXM_LVDS_BLON, MXM_LVDS_PWREN, (Page 32)
10.Oct.2009 9. Correct the connection of LCD_CLK and LCD_DAT. (Page 19)
10.Oct.2009 10. Remove the nets of CRT function and HDMI audio on MXM (Page 25)
C C
11.Oct.2009 11. Remove the redudant enable for unused port and add the switch IC for DP dual mode. (Page 19)
11.Oct.2009 12. Add the capacitors for SATA transmitor. (Page 20)
11.Oct.2009 13. Add GPIO WRITE_EDID_ROM for L10 EDID update (Page 22)
11.Oct.2009 14. Remove the HDMI audio from PCH to MXM (Page 20)
11.Oct.2009 15. Reserve the GPIO CR_CPPE# of PCH. (Page 22)
11.Oct.2009 16. Add the function for CLR_BIOS_DATA and CLR_PASSWD. (Page 22)
11.Oct.2009 17. Correct the symbol of CLR_BIOS_DATA and CLR_PASSWD. (Page 29)
11.Oct.2009 18. Correct the STAT capacitors of ODD to receiver. (Page 29)
11.Oct.2009 19. Use 5V_PCU and +5V_S5 to CN21. (Page 30)
11.Oct.2009 20. Reserve the GPIO control of CCD_POWER_ON#. (Page 36)
11.Oct.2009 21. Delete CRT debug from MXM. (Page 25)
B B

12.Oct.2009 22. Correct the power net for 3VPCU and 5VPCU. (Page 30, 26, 27, 36)
12.Oct.2009 23. Correct the connection of M_A_DQ46 and M_A_DQ47. (Page 17)
12.Oct.2009 24. Correct the net name to VR_HOT. (Page 10)
12.Oct.2009 25. Change the net name of USB4_FB and USB4_FB#. (Page 35)
12.Oct.2009 26. Change the net name of DDR3 VTT to DDR_VTERM. (Page 17, 18) ==> no change~!!!
12.Oct.2009 27. Reserve the resistnaces for CK0 and CK1 pairs of CHA and CHB. (Page 17, 18)
12.Oct.2009 28. Change the MXM_12V on MXM page. (Page 25)
27.Nov.2009 29. Change net VR_ready Pull High(Page 9)
27.Nov.2009 30. Delete MXM to VGA port circuit(Page 25/27)
27.Nov.2009 31. Change ACN4 to right angle typy(Page26)
A 27.Nov.2009 32. Delete CN16 XDP connect (Page37) A

27.Nov.2009 33. Swap USB2, USB3, USB10, differential signal(Page31)


27.Nov.2009 34. Delete all JP connection
27.Nov.2009 35. CN14 LCD_Clk & LCD_Data swap(Page25) Quanta Computer Inc.
PROJECT : ZN2
27.Nov.2009 36. CLK_LPC_DEBUG net change to CN17 pin19(Page30) Size Document Number Rev
1A
CHANGE LIST
27.Nov.2009 37. PEG_CLKREQ#_R pull low,Change R457 resistor to R454(Page21) Date: Tuesday, March 16, 2010 Sheet 47 of 49
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5 4 3 2 1

DATE ZN2 Schematic file ZN2 Board file Revision

D
DATE Schematic Change Description D

27.Nov.2009 38. Change ACin Soft start Function and add Adaptor ID to identify Function and disable ID to identify and delete Short Pad JP5, JP6 (Page 39)
27.Nov.2009 39. Delete Short Pad PJP7, PJP8, PJP9, PJP10, PJP11, PJP12 (Page 40)
27.Nov.2009 40. Delete short Pad PJP4, PJP5 and Place up PR190 for V_AXG initial setting Voltage Place up PR48 for V_AXG PG Pull high (Page 41)
27.Nov.2009 41. Change PR116 Value to 6.81K ohm and PL4 Value to 0.88uH and add Location PC210, PC211, PQ64 and delete Short Pad PJP1 (Page 42)
27.Nov.2009 42. Delete Short Pad PJP2, PJP3 (Page 43)
27.Nov.2009 43. Change CPU core Value PR132, PR122, PR140, PR145, PR150, PR154 (Page 44)
27.Nov.2009 44. Delete Short Pad PJP6 (Page 45)
27.Nov.2009 45. Place up PQ27, PQ28, PQ29, PQ30, PQ31, PQ38, PR88 (Page 46)
29.Nov.2009 46. MOVE EC circuit (PAGE 36)'s LED indicate circuit to (Page 39) ACin circuit
2.Dec.2009 47. Connect GFX_VR_EN to dGPU_PRSNT# (Page 10)
C C
2.Dec.2009 48. Add RC circuit for SRTC_RST# (Page 20)
2.Dec.2009 49. Change CLK_PCIE_DMI# differential pair RP15 to L44/L45 (Page 21)
2.Dec.2009 50. Change C328 to 330uF and Delete C329,C335,C336,C343,C344(Page 14)
2.Dec.2009 51. Remove R174 10Kohm(Page 25)
2.Dec.2009 52. Remove R389 , place R374 to 0 ohm, 1394 component, Change U17 to JMB385 (Page 28)
2.Dec.2009 53. Change CN11 to right angle type(Page 29)
2.Dec.2009 54. Place the SATA_ACT circuit component(Page 30)
2.Dec.2009 55. Remove the hall sensor component and add LED5(Page 36)
2.Dec.2009 56. Add SW1 (Page 36)
7.Dec.2009 57. Reverse HDD connect pin (Page 29)
26.Jan.2010 58. Change Write_EDID_ROM to GPIO28 (Page 22)
B B

26.Jan.2010 59. Reserve MXM to CRT function (Page 25/27)


26.Jan.2010 60. Reserve R395 for PEG_CLKREQ pull high (Page 25)
26.Jan.2010 61. Change C274/C276 to 47u (Page 27)
26.Jan.2010 62. Change CN29 Pin2 power to +5V_S5_USB (Page 30)
26.Jan.2010 63. Change F7/F8/F9 power to +5V_S5_USB (Page 31)
26.Jan.2010 64. Change C447,C483,C493,C489,C478,C482,C490,C494,,C287,C399,C265,C472,C469,C466 to 100u/7343 type (Page 31)
26.Jan.2010 65. Add D61 (Page 31)
26.Jan.2010 66. Reserve R232 for Write_EDID_ROM pull low function (Page 32)
26.Jan.2010 67. Add C329 for Lan loss solution (Page 33)
26.Jan.2010 68. CN29 Pin15/16 floating (Page 34)
A 26.Jan.2010 69. Change R257 power to +5V_S5_USB (Page 35) A

26.Jan.2010 70. Reserve R63 (Page 36)


26.Jan.2010 71. Add ADP-ID to EC ADC1 (Page 36/39)
26.Jan.2010 72. Change Screw H23,H19,H2,H4,H5,H11,H28 (Page 38) Quanta Computer Inc.
PROJECT : ZN2
26.Jan.2010 73. Change ACin Adaptor ID to identify Function circuit and add delay time for EN3V5V enable circuit(Page 39) Size Document Number Rev
1A
CHANGE LIST
Date: Tuesday, March 16, 2010 Sheet 48 of 49
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4. Nat name Description : 5. Board Stack up Description


Voltage Rails
VIN Primary DC system power supply PCB Layers
D
+5VPCU 5.0V always on power rail by LATCH or ACIN Layer 1 Component Side, Microstrip signal Layer D
+3VPCU 3.3V always on power rail by LATCH or ACIN
+5V_S5 5.0V always on power rail by DCON Layer 2 Ground Plane
+3V_S5 3.3V always on power rail by DCON Layer 3 Stripline Layer(High Speed)
+5V_S5_USB 5.0V power rail by SUSD Layer 4 Normal Signal / Ground 1 Plane
+3V 3.3V switched power rail by MAIND Layer 5 Power Plane
+5V 5.0V switched power rail by MAIND
Layer 6 Solder Side,Microstrip signal Layer
+VCC_CORE Core Voltage for CPU
CPU_VTT_1.1V 1.1V power rail for AGTL+ termination/Core for GMCH by MAINON
Layers : 6 Depth 1.6mm Impence 55 ohms +/- 10%
1.05V_PCH 1.05V power rail for PCH Core Power by MAINON
+1.8V 1.8V power rail for CPU PLL/DMI;PCIE;DDRII DLLs Single End Impedance Differential Impedance for Microstrip Differential Impedance for Stripline
Host Clock 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15%
for VRM/NVRAM by MAINON
SRC Clock 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15%
+1.5V 1.5V power rail for MiniPCI by MAIND Host Bus 55 ohm +/- 15%
DDR2 CLK 42 ohm +/- 15% 70 ohm +/- 20% 70 ohm +/- 20%
+1.5V_SUS 1.5V power rail for DDRIII by SUSON DDR2 Strobe 55 ohm +/- 15% 85 ohm +/- 20%
DDR2 Bus 55 ohm +/- 15%
C SMDDR_VTERM 0.75V DDRIII Termination Voltage by MAINON DMI Bus 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15% C

PCIE Bus 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15%
Part Naming Conventions SATA 95 ohm +/- 15% 100 ohm +/- 15%
SDVO 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15%
C = Capacitor LVDS 100 ohm +/- 15% 100 ohm +/- 15%
CN = Connector USB 90 ohm +/- 15% 90 ohm +/- 15%
D = Diode IEEE1394 110 ohm +/- 15% 110 ohm +/- 15%
F = Fuse Lan 50 ohm +/- 15%
L = Inductor
Q = Transistor
R = Resistor
RP = Resistor Pack
U = Arbitrary Logic Device
Y = Crystal and Osc

Net Name Suffix


# = Active Low signal
B B

A A

Quanta Computer Inc(QCI).


211, Wen Hwa 2nd Rd., Kuei Shan,
Tao Yuan 33377, Taiwan Confidential
Tel : +886-3-327-2345
Title
ZN2

Size Document Number Rev


C ZN6C A02

Date: Tuesday, March 16, 2010 Sheet 49 of 49


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