CS8382- Digital Systems Lab Dept of ECE 2018-19

RAJALAKSHMI INSTITUTE OF TECHNOLOGY

Kuthambakkam - Chennai

ANNA UNIVERSITY OF TECHNOLOGY

2017 REGULATION

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

CS8382- Digital Systems Laboratory

(II B.E III Semester Batch 2017)

Manual prepared by
Ms.K.Jayamani, AP(SS)/ECE
Ms.R.Aruna Jayashree, AP/ECE
Ms.V.Subashini, AP/ECE
Mr.A.Karunakaran, AP/ECE
Mr.U.Maheswaran, AP/ECE
Ms.C.Malarvizhi, AP(SS)/ECE

Rajalakshmi Institute of Technology

 Vision of the Department
To empower the students with high quality technical education in the
field of Computer Science and Engineering to face the challenges of
modern computing industry and research for the positive contributions to
the society.

Mission of the Department

• To produce globally competent and highly employable professionals, who
will be innovative in solving real world problems.
• To train the students with high ethical values to serve the society efficiently
in their profession.
• To promote research activities the students and faculty members that could
fortify industry academic community connections.
PROGRAM EDUCATIONAL OBJECTIVES (PEOs):
1.To enable graduates to pursue higher education and research, or have a
successful career in industries associated with Computer Science and
Engineering, or as entrepreneurs.
2. To ensure that graduates will have the ability and attitude to adapt to
emerging technological changes.
PROGRAM OUTCOMES POs:
Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science,
engineering fundamentals and an engineering specialization to the solution of
complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and
analyze complex engineering problems reaching substantiated conclusions
using first principles of mathematics, natural sciences, and engineering
sciences.
3. Design/development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified
needs with appropriate consideration for the public health and safety, and the
cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based
knowledge and research methods including design of experiments, analysis
and interpretation of data, and synthesis of the information to provide valid
conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and
modeling to complex engineering activities with an understanding of the
limitations.
6. The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate
the knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a
member or leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering
activities with the engineering community and with society at large, such as,
being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear
instructions.
11. Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply these
to one‘s own work, as a member and leader in a team, to manage projects and
in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and
ability to engage in independent and life-long learning in the broadest context
of technological change.
PROGRAM SPECIFIC OBJECTIVES (PSOs)
1. To analyze, design and develop computing solutions by applying
foundational concepts of Computer Science and Engineering.
2. To apply software engineering principles and practices for developing
quality software for scientific and business applications.
3. To adapt to emerging Information and Communication Technologies (ICT)
to innovate ideas and solutions to existing/novel problems.

CS8382 DIGITAL SYSTEMS LABORATORY L T P C 0 0 4 2

OBJECTIVES:
• To understand the various basic logic gates
• To design and implement the various combinational circuits
• To design and implement combinational circuits using MSI devices.
• To design and implement sequential circuits
• To understand and code with HDL programming

OUTCOMES:
Upon Completion of the course, the students will be able to:
• Implement simplified combinational circuits using basic logic gates
• Implement combinational circuits using MSI devices
• Implement sequential circuits like registers and counters
• Simulate combinational and sequential circuits using HDL
 CO-PO MAPPING

CO PO PO PO PO PO PO PO PO PO PO PO 11 PO
1 2 3 4 5 6 7 8 9 10 12
CO1: Implement
simplified
combinational 3 3 3 3 1 2 2 1 2 2 2 1
circuits using basic
logic gates
CO2: Implement
combinational
3 3 3 3 2 2 2 1 2 2 2 1
circuits using MSI
devices.
CO3: Implement
sequential circuits
3 3 3 3 2 2 2 1 2 2 2 1
like registers and
counters
CO4: Simulate
combinational and
sequential circuits 3 3 3 3 2 2 2 1 2 2 2 1
using HDL

CO PSO 1 PSO 2 PSO 3

CO1: Implement simplified combinational circuits using
basic logic gates 3 2 1

CO2: Implement combinational circuits using MSI

devices. 2 3 2

CO3: Implement sequential circuits like registers and

3 3 2
counters
CO4: Simulate combinational and sequential circuits
using HDL
3 3 2
 SYLLABUS

CS 8382 DIGITAL SYSTEMS LABORATORY

1. Verification of Boolean theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for
arbitrary functions, code converters, etc.
3. Design and implementation of Half/Full Adder and Subtractor.
4. Design and implementation of combinational circuits using MSI devices:
• 4-bit binary adder / subtractor
• Parity generator / checker
• Magnitude comparator
• Application using multiplexers
5. Design and implement shift-registers.
6. Design and implement synchronous counters.
7. Design and implement asynchronous counters.
8. Coding combinational circuits using HDL.
9. Coding sequential circuits using HDL.
10. Design and implementation of a simple digital system (Mini Project).
 LIST OF EXPERIMENTS

1. Study and verification of logic gates.

2. Study and verification of Boolean theorems using basic gates.
3. Design and implementation of adders and subtractors using logic gates
and using IC 7483.
4. Design and implementation of code converters using logic gates.
5. Design and implementation of an arbitrary function using logic gates.
6. Design and implementation of 8-bit magnitude comparator using IC
7485.
7. Design and implementation of 4-bit, 16-bit odd/even parity checker/
generator using IC 74180.
8. Implementation of Full adder using multiplexer.
9. Implementation of SISO, SIPO, PISO and PIPO shift registers using
flip-flops.
10.Construction and verification of 4-bit Johnson counter.
11. Design and implementation of 3-bit synchronous up/down counter.
12.Design and implementation of Mod-10/Mod-12 ripple counter.
13.HDL programs for combinational and sequential circuits.
 Introduction

There are 3 hours allocated to a laboratory session in Digital Electronics. It is a

necessary part of the course at which attendance is compulsory.

Here are some guidelines to help you perform the experiments and to submit the reports:

1. Read all instructions carefully and carry them all out.

2. Ask a demonstrator if you are unsure of anything.

3. Record actual results (comment on them if they are unexpected!)

4. Write up full and suitable conclusions for each experiment.

5. If you have any doubt about the safety of any procedure, contact the
demonstrator beforehand.

The Breadboard

The breadboard consists of two terminal strips and two bus strips (often broken in the
centre). Each bus strip has two rows of contacts. Each of the two rows of contacts are a
node. That is, each contact along a row on a bus strip is connected together (inside the
breadboard). Bus strips are used primarily for power supply connections, but are also
used for any node requiring a large number of connections. Each terminal strip has 60
rows and 5 columns of contacts on each side of the centre gap. Each row of 5 contacts is
a node.

You will build your circuits on the terminal strips by inserting the leads of circuit
components into the contact receptacles and making connections with 22-26 gauge wire.
There are wire cutter/strippers and a spool of wire in the lab. It is a good practice to wire
+5V and 0V power supply connections to separate bus strips.
 The breadboard. The lines indicate connected holes.

The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs
(Integrated circuits) used during the experiments. Incorrect connection of power to the
ICs could result in them exploding or becoming very hot - with the possible serious
injury occurring to the people working on the experiment! Ensure that the power
supply polarity and all components and connections are correct before switching on
power.

Building the Circuit

Throughout these experiments we will use TTL chips to build circuits. The steps for
wiring a circuit should be completed in the order described below:

1. Turn the power (Trainer Kit) off before you build anything!
2. Make sure the power is off before you build anything!
3. Connect the +5V and ground (GND) leads of the power supply to the power and
ground bus strips on your breadboard.
4. Plug the chips you will be using into the breadboard. Point all the chips in the
same direction with pin 1 at the upper-left corner. (Pin 1 is often identified by a
dot or a notch next to it on the chip package)
5. Connect +5V and GND pins of each chip to the power and ground bus strips on
 the breadboard.
6. Select a connection on your schematic and place a piece of hook-up wire between
corresponding pins of the chips on your breadboard. It is better to make the short
connections before the longer ones. Mark each connection on your schematic as
you go, so as not to try to make the same connection again at a later stage.
7. Get one of your group members to check the connections, before you turn the
power on.
8. If an error is made and is not spotted before you turn the power on. Turn the
power off immediately before you begin to rewire the circuit.
9. At the end of the laboratory session, collect you hook-up wires, chips and all
equipment and return them to the demonstrator.
10. Tidy the area that you were working in and leave it in the same condition as it was
before you started.

Common Causes of Problems

1. Not connecting the ground and/or power pins for all chips.
2. Not turning on the power supply before checking the operation of the circuit.
3. Leaving out wires.
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates
6. Modifying the circuit with the power on.

In all experiments, you will be expected to obtain all instruments, leads, components at
the start of the experiment and return them to their proper place after you have finished
the experiment. Please inform the demonstrator or technician if you locate faulty
equipment. If you damage a chip, inform a demonstrator, don't put it back in the box of
chips for somebody else to use.
Digital ICs Pin Diagrams

NAND Gate

NOR Gate
NOT Gate

OR Gate
 AND Gate

Ex - OR Gate
Expt. No: Date:
STUDY AND VERIFICATION OF LOGIC GATES
1.a

AIM:
To study various logic gates and to verify the truth table.

COMPONENTS / EQUIPMENTS REQUIRED:

S. No. Components / Equipments Specification Quantity

1. Digital IC trainer kit --- 1
2. AND Gate IC7408 1
3. OR Gate IC7432 1
4. NOT Gate IC7404 1
5. NAND Gate IC7400 1
6. NOR Gate IC7402 1
7. Ex-Or Gate IC7486 1
8. Connecting Wires --- Sufficient Numbers

THEORY:

AND gate: The AND gate is a digital logic gate that implements logical
conjunction - it behaves according to the truth table given. A HIGH output (1) results
only if both the inputs to the AND gate are HIGH (1). If neither or only one input to
the AND gate is HIGH, a LOW output results. In another sense, the function of AND
effectively finds the minimum between two binary digits.

OR gate : The OR gate is a digital logic gate that implements logical

disjunction - it behaves according to the truth table to the right. A HIGH output (1)
results if one or both the inputs to the gate are HIGH (1). If neither input is HIGH,
a LOW output (0) results. In another sense, the function of OR effectively finds the
maximum between two binary digits.

NOT gate: In digital logic, an inverter or NOT gate is a logic gate which
implements logical negation. The truth table is shown. This represents perfect switching
behavior, which is the defining assumption in Digital electronics. In practice, actual
devices have electrical characteristics that must be carefully considered when designing
inverters. In fact, the non-ideal transition region behavior of a CMOS inverter makes it
useful in analog electronics as a class A amplifier.

NAND gate: The Negated AND, NO AND or NAND gate is the opposite of the
digital AND gate, and behaves in a manner that corresponds to the opposite of AND
gate, as shown in the truth table. A LOW output results only if both the inputs to the
gate are HIGH. If one or both inputs are LOW, a HIGH output results. The NAND
gate is a universal gate in the sense that any boolean function can be implemented by
NAND gates. NAND gates can also be made with more than two inputs, yielding an
output of LOW if all of the inputs are HIGH, and an output of HIGH if any of the
inputs is LOW.

NOR gate : The NOR gate is a digital logic gate that implements logical
NOR - it behaves according to the truth table to the right. A HIGH output (1) results
if both the inputs to the gate are LOW (0). If one or both input is HIGH (1), a
LOW output (0) results. NOR is the result of the negation of the OR operator. NOR
is a functionally complete operation—combinations of NOR gates can be combined
to generate any other logical function. By contrast, the OR operator is monotonic
as it can only change LOW to HIGH but not vice versa.

EX- OR gate: The XOR gate (sometimes EOR gate) is a digital logic gate
that implements an exclusive disjunction; that is, it behaves according to the truth table
shown on the right. A true output (1) results if one, and only one, of the inputs to the
gate is true (1). If both inputs are false (0) and both are true (1), a false output (0)
results. A way to remember XOR is "one or the other but not both.

LOGIC DIARGAM:

AND Gate: OR Gate:

Logic Diagram: Truth Table: Logic Diagram Truth Table:

A B Y=AB
A B Y=A+B
 NOT Gate: NAND Gate:

Logic Diagram: Truth Table: Logic Diagram Truth Table:

Y=
A B
A Y=A’ (AB)’

NOR Gate: Ex-OR Gate:

Logic Diagram: Truth Table: Logic Diagram Truth

Table:
Y= A B
A B
(A+B)’

PROCEDURE:

1. Give the connections as per the pin diagram (AND gate).

2. Switch on the trainer kit.
3. Apply the binary inputs at the appropriate terminal and observe
the corresponding output.
4. Verify the truth table.
5. Repeat the above procedure for other (OR, NOT, NAND, NOR and Ex-Or)
gates.

INFERENCE AND CONCLUSION:

REVIEW
QUESTIONS
1. What are the universal gates?
2. Switches arranged in series act like what type of logic gate?
3. Switches arranged in parallel act like what type of logic gate?
4. Write the Boolean expression for neither NAND, NOR, XNOR gate.
5. Which logic gate might be called any (or) all gate.
Expt. No: VERIFICATION OF BOOLEAN THEOREMS Date:
2 USING LOGIC GATES

AIM:

To study and verify the truth table of basic logic gates NOT, AND, OR, NAND,
NOR and EX-OR and to verify the Boolean theorems.

COMPONENTS / EQUIPMENTS REQUIRED:

S.No. Name of the apparatus Range Quantity

1 Digital Trainer kit
2 NOT gate IC7404 1
3 AND gate IC7408 1
4 OR gate IC7432 1
5 EX-OR gate IC7486 1
6 NAND gate IC7400 1
7 NOR gate IC7402 1
8 Connecting wires

THEORY:

In Boolean algebra three basic logic operations are available. They are OR, AND,
NOT. These logic gates are digital circuits constructed from diodes, transistors, and
resistors connected in such a way that the circuit output is the result of a basic logic
operation (OR, AND, NOT) performed on the inputs.

Truth table: A truth table is a means for describing how a logic circuit's output
depends on the logic levels present at the circuit's inputs

DeMorgan's Theorem:

DeMorgan's theorems are extremely useful in simplifying expressions in which a

product or sum of variables is inverted. The two theorems are:

(A+B)' = A'.B'

(A.B)' = A' +B'

Commutative Law:
 A.B = B.A
A+B = B+A

Associative Law:
A. (B.C) = (A.B). C

Commutative Law: A.B = B.A

Associative Law: A. (B.C) = (A.B). C

DeMorgans Law (A+B)’ = A’. B’

Observations:

Commutative Law:

A B A.B B.A
 Associative Law:

A B C A(BC) (AB)C

DeMorgans Law:

A B (A+B)’ A’.B’

INFERENCE AND CONCLUSION:

VIVA QUESTIONS:
1. Obtain AND gate using only NAND gates.
2. What are universal gates?
3. State Demorgans theorem:
4. Implement OR gate using only NAND gate:
5. Write the truth table for EX-OR gate:
6. What is a logic gate?
7. State the consensus theorem in Boolean algebra:
8. What are don’t care conditions?
9. What is the the need for Quine Mccluskey method ?
10. What are minterm and maxterm?
Expt. No: IMPLEMENTATION OF BOOLEAN FUNCTIONS - Date:
3.a ADDERS AND SUBTRACTORS

AIM:
To design and verify the adders and subtractors using logic gate.

COMPONENTS / EQUIPMENTS REQUIRED:

S. No Components / Equipments Specifications Quantity

1. Digital IC trainer --- 1
2. NOT, AND, OR, Ex-OR Gate IC 7404,7408,7432,7486 Each one
3. Connecting wires --- Sufficient numbers
THEORY:

Half Adder:
The half adder is an example of a simple, functional digital circuit built from two
logic gates. The half adder adds to one-bit binary numbers (AB). The output is the sum of
the two bits (S) and the carry (C). Note how the same two inputs are directed to two
different gates. The inputs to the XOR gate are also the inputs to the AND gate. The
input "wires" to the XOR gate are tied to the input wires of the AND gate; thus, when
voltage is applied to the A input of the XOR gate, the A input to the AND gate receives
the same voltage. Select an input combination from the pull-down selector and view the
resulting output.
The logic circuit for the addition of two one bit numbers is referred to as a half
adder. Here A and B are the two inputs and S (sum) and C (carry) are two outputs. The
two outputs, the sum and carry equations are carried from the truth table of addition of
two numbers.
They are S =ĀB+AB,
C = AB.

Full Adder:
A half adder has only two inputs and there s no provision to add a carry coming
from the lower order bits when multi bit additions performed. For this purpose, a third
input terminal is added and this circuit is used to add An, Bn and Cn-1 where An and Bn
are the nth order bits of the numbers A and B respectively and Cn-1 is the carry
generated from the addition of (n-1) th order bits. This circuit is referred to as full
adder. The sum and carry equations are carried from the truth table of addition of three
numbers.
They are S=A B C,
C = AB + BC + CA.
 Half Subtractor:
A logic circuit for the subtractor of B(subtrahend) from A (minuend) where A and
B are 1bit numbers is referred to as a half subtractor. The two outputs, the difference
(D) and borrow (B) equations are carried from the truth table of subtraction of two
numbers.
They are
Difference = AB + AB,
Borrow = AB .

Full subtractor:
Just like a full adder circuit, full subtractor circuit performs multiple subtraction
wherein borrow from the previous bit position may also be there. A full subtractor will
have three inputs, An (minuend), Bn (subtrahend) and Cn-1 (borrow from previous stage) and
two outputs Dn (difference) and Cn (borrow). The difference and carry equations carried
out from the truth table of subtraction.
Diff.(D) = A B C,
Borrow = AB+A C+ B
C.

Truth Table for Half Adder

A B Sum Carry

K-map simplification for Half Adder

K-Map for SUM: K-Map for CARRY:

SUM = CARRY =
 LOGIC DIAGRAM OF HALF ADDER:

BLOCK SCHEMATIC OF HALF ADDER:

A S =A B
Half Adder

B C = AB

Truth Table for Full Adder

A B C SUM CARRY
 K-Map for SUM:

SUM =

K-Map for CARRY:

CARRY =

LOGIC DIAGRAM OF FULL ADDER

BLOCK DIAGRAM OF FULL ADDER

An
Sn = (An Bn ) Cn-1
Full Adder
Bn
Cn-1 Cn = Cn-1 ( An Bn) +AnBn
 Truth Table for Half Subtractor

A B DIFFERENCE BORROW

K-Map for DIFFERENCE:

DIFFERENCE =

K-Map for BORROW:

BORROW =

LOGIC DIAGRAM FOR HALF SUBTRACTOR

 BLOCK SCHEMATIC OF HALF SUBTRACTOR:

A D =A B

Half subtractor
B C = AB

Truth Table for Full Subtractor

A B C BORROW DIFFERENCE

K-Map for Difference:

Difference =
 K-Map for Borrow:

Borrow =

LOGIC DIAGRAM FOR FULL SUBTRACTOR

BLOCK SCHEMATIC OF FULL SUBTRACTOR

An
Full Dn = (An Bn ) Cn-1

Bn subtractor
Cn-1 Cn = Cn-1 (An Bn) + AnBn
 PROCEDURE:
1. Give the connections as per the circuit diagram (Half Adder).
2. Switch on the trainer kit.
3. Apply the binary inputs at the appropriate terminal and observe the
corresponding output.
4. Verify the truth table and repeat the above procedure for other circuits.

INFERENCE AND CONCLUSION:

REVIEW QUESTIONS:
1. What is the sum of binary number 1010+0100?
2. Parallel adders are logic circuits.
3. What is the IC number of 4 bit binary adder?
4. Find the 1’s complement of 10101010.
5. Subtract using 2’s complement 110102 – 011002.
6. Why NAND & NOR gates are called Universal gates?
7. Realize the EX-OR gates using minimum number of NAND gates?
8. Realize the AND gate using NOR gate.
9. Realize OR gate using NAND gate.
10. Built the truth table forF=A'BC + ABC + AB'C + A'B'C'
11. What is the need for K Map?
Expt. No: DESIGN AND IMPLEMENTATION OF 4 BIT Date:
3.b BINARY ADDER / SUBTRACTOR USING IC 7483

AIM:
To study the 4 bit binary adder/subtractor using IC7483.

COMPONENTS / EQUIPMENTS REQUIRED:

S.No. Name of the apparatus Specifications Quantity

1 Digital Trainer kit - 1
2 OR gate IC 7432 1
3 AND gate IC 7408 1
4 Binary Adder / Subtractor IC 7483 2
5 Connecting wires - some

THEORY:
The full adder/sub tractors are capable of adding/subtracting only two single digit
binary numbers along with a carry input. But in practice we need to add/subtract binary
numbers, which are much longer than just one bit. To add/subtract two n-bit binary
numbers we need to use the n-bit parallel subtractor/adder.

Binary adder:

IC type 7483 is a 4-bit binary parallel adder/subtractor .The two 4-bit input binary
numbers are A1 through A4 and B1 through B4. The sum is obtained from S1 through
S4. C0 is the input carry and C4 the output carry. Test the 4-bit binary adder 7483 by
connecting the power supply and ground terminals. Then connect the four A inputs to a
fixed binary numbers such as 1001 and the B inputs and the input carry to five toggle
switches. The five outputs are applied to indicator lamps. Perform the addition of a few
binary numbers and check that the output sum and output carry give the proper values.
Show that when the input carry is equal to 1, it adds 1 to the output sum.

Binary subtractor:

The subtraction of two binary numbers can be done by taking the 2’s complement of
the subtrahend and adding it to the minuend. The 2’s complement can be obtained by
taking the 1’s complement and adding. To perform A-B, we complement the four bits of
B, add them to the four bits of A, and add 1 through the input carry. The four XOR gates
complement the bits of B when the mode select M=1(because x  0  x ) and leave the
bits of B unchanged when M=0(because x  0  x ) .Thus , when the mode select M is
equal to 1, the input carry C0 is equal 1 and the sum output is A plus the 2’s
complement of B. when M is equal to 0, the input carry is equal to 0 and the sum
generates A+B.

Functional symbol for IC 7483:

Operand1 Operand2

B3 B2 B1 B0 A3 A2 A1 A0

4 bit IC 7483
C C

O
Pin Diagram of IC7483:
Circuit Diagram for 4-bit Binary adder/subtractor:
4-BIT BINARY ADDER:

4-BIT BINARY SUBTRACTOR

PROCEDURE:
1. Give the connections as per the circuit diagram (Half Adder).
2. Switch on the trainer kit.
3. Apply the binary inputs at the appropriate terminal and observe the
corresponding output.
4. Verify the truth table and repeat the above procedure for other circuits.

INFERENCE AND CONCLUSION:

Expt. No. DESIGN AND IMPLEMENTATION OF Date:
4 CODE CONVERTERS

AIM:
To design and verify the truth table of the following code converters
1. Binary to Gray converter
2. Gray to Binary converter &
3. BCD to Excess3 &
4. Excess3 to BCD.

COMPONENTS / EQUIPMENTS REQUIRED:

Quantity
S. No. Components / Equipments Specifications
1. Digital IC trainer --- 1
2. NOT, AND, OR, Ex-OR Gate IC7404,7408,7432,7486 1
3. Connecting wires Sufficient numbers

THEORY:

Binary to GRAY Converter:

By representing the ten decimal digits with a four bit Gray code, we have
another form of BCD code. The Gray code however can be extended to any number of
bits and conversion between binary code and Gray code is sometimes useful. The
following rules apply for conversion:
1. The MSB in the Gray code is the same as the corresponding bit in the binary
number.
2. Going from left to right, add each adjacent pair of binary bits to get the next
Gray code bit. Disregard carries.

GRAY to Binary Converter:

To convert from Gray code to binary code, A similar method is used, at there
are some differences. The following rules apply:
1. The MSB in the binary code is the same as the corresponding digit in the Gray code
2. Add each binary digit generated to the gray digit in the next adjacent position
Disregard carries.
TRUTH TABLE FOR BINARY TO GRAY CODE CONVERTER:
| Binary input | Gray code output
B3 B2 B1 B0 G3 G2 G1 G0

K-Map for G3:

K-Map for G2:

K-Map for G1:

K-Map for G0:

 Binary to GRAY

TRUTH TABLE FOR GRAY CODE TO BINARY CONVERTOR:

| Gray Code | Binary Code

G3 G2 G1 G0 B3 B2 B1 B0
K-Map for B3:

K-Map for B2:

K-Map for B1:

K-Map for B0:

 GRAY to Binary

TRUTH TABLE FOR BCD TO EXCESS-3 CONVERTOR:

| BCD input | Excess – 3 output
|
B3 B2 B1 B0 G3 G2 G1 G0
K-Map for E3:

K-Map for E2:

K-Map for E1:

K-Map for E0:

 LOGIC DIAGRAM:

BCD TO EXCESS-3 CONVERTOR

TRUTH TABLE FOR EXCESS-3 TO BCD CONVERTOR:

| Excess – 3 Input | BCD Output |

B3 B2 B1 B0 G3 G2 G1 G0
 K-Map for A:

K-Map for B:

K-Map for C:
 K-Map for D:

LOGIC DIAGRAM:

EXCESS-3 TO BCD CONVERTOR

PROCEDURE:

Procedure:
1. Connections are given as per the circuit diagram (Binary to GRAY).
2. Switch on the power supply.
3. Verify the truth table given for different inputs.
4. Repeat the above procedures for other converters.

INFERENCE AND CONCLUSION:

REVIEW QUESTIONS:
Viva Voce Questions:
1. State some examples of weighted codes.
2. Convert Gray code to binary: 11010101.
3. What is the significance of gray code?
4. Express the following decimals number into excess 3.(i)124 (ii) 7621
5. What is the use of parity bit?
Expt. No: IMPLEMENTATION OF AN ARBITRARY Date:
5. FUNCTIONS USING LOGIC GATES

AIM:
To Implement the given Arbitrary Functions by using logic gates.

COMPONENTS / EQUIPMENTS REQUIRED:

S.No. Name of the apparatus Specifications Quantity

1 Digital Trainer kit - 1
2 NOR gate IC 7402 2
3 AND gate IC 7408 2
4 NOT gate IC 7404 1
5 Ex-OR gate IC 7486 1
6 Connecting wires - some

Given Arbitrary Functions are

(A=B) = A1 A0 B1 B0  A1 A0 B1 B0  A1 A0 B1 B0  A0 A1 B0 B1
A<B = A A B  A B  A B
1 0 0 1 1 0 1
A>B = B0
A0 B1 B0  A1 A0 B0  A1 Truth Table:
B1

Inputs Outputs
A1 A0 B1 B0 A<B A=B A>B
 Circuit Diagram:

PROCEDURE:

1. Connections are given as per in the circuit diagram.

2. Inputs are given through the logic switches.
3. Outputs are noted and verified with truth table.

INFERENCE AND CONCLUSION:

Expt. No: DESIGN AND IMPLEMENTATION OF 8 BIT - Date:
6 MAGNITUDE COMPARATOR USING MSI DEVICES

AIM:
To design and implement 8 – bit magnitude comparator using IC 7485.

COMPONENTS / EQUIPMENTS REQUIRED:

S.No: COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE COMPARATOR IC 7485 2
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

THEORY:
The comparison of two numbers is an operator that determine one number is
greater than, less than (or) equal to the other number. A magnitude comparator is a
combinational circuit that compares two numbers A and B and determine their relative
magnitude. The outcome of the comparator is specified by three binary variables that
indicate whether A>B, A=B (or) A<B.
A = A3 A2 A1 A0
B = B3 B2 B1 B0
The equality of the two numbers and B is displayed in a
combinational circuit designated by the symbol (A=B).
 This indicates A greater than B, then inspect the relative magnitude
of pairs of significant digits starting from most significant position. A is 0
and that of B is 0.

We have A<B, the sequential comparison can be expanded as

A>B = A3B 31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01

A<B = A31B3 + X3A2 1B2 + X3X2A1 1B1 + X3X2X1A01B0

The same circuit can be used to compare the relative magnitude of two
BCD digits.
Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)

   
x3 x2 x1 x0
PIN DIAGRAM FOR IC 7485:

LOGIC DIAGRAM:

8 BIT MAGNITUDE COMPARATOR:

 TRUTH TABLE FOR 8 BIT MAGNITUDE COMPARATOR:

A B A>B A=B A<B

0000 0000 0000 0000 0 1 0
0001 0001 0000 0000 1 0 0
0000 0000 0001 0001 0 0 1

PROCEDURE:

1. Connections are given as per in the circuit diagram.

2. Inputs are given through the logic switches.
3. Outputs are noted and verified with truth table.

INFERENCE AND CONCLUSION:

VIVA QUESTIONS:

1. What is a comparator?

2. What are the various applications of a comparator?

Expt. No: DESIGN AND IMPLEMENTATION OF 16-BIT ODD / Date:
7 EVEN PARITY GENERATOR & CHECKER

AIM:
To design and implement 16 bit odd/even parity checker generator using IC 74180.

COMPONENTS / EQUIPMENTS REQUIRED:

S.No COMPONENT SPECIFICATION QTY.

1. NOT GATE IC 7404 1
2. PARITY GENERATOR/CHECKER IC IC 74180 2
3. IC TRAINER KIT - 1
4. PATCH CORDS - 30

THEORY:
A parity bit is used for detecting errors during transmission of binary information. A
parity bit is an extra bit included with a binary message to make the number is either
even or odd. The message including the parity bit is transmitted and then checked at the
receiver ends for errors. An error is detected if the checked parity bit doesn’t
correspond to the one transmitted.
The circuit that generates the parity bit in the transmitter is called a ‘parity generator’
and the circuit that checks the parity in the receiver is called a ‘parity checker’.
In even parity, the added parity bit will make the total number is even amount.
In odd parity, the added parity bit will make the total number is odd amount. The parity
checker circuit checks for possible errors in the transmission. If the information is
passed in even parity, then the bits required must have an even number of 1’s. An error
occur during transmission, if the received bits have an odd number of 1’s indicating that
one bit has changed in value during transmission.
LOGIC DIAGRAM:
16 BIT ODD/EVEN PARITY CHECKER

TRUTH TABLE FOR 16 BIT ODD/EVEN PARITY CHECKER :

I7 I6 I5 I4 I3 I2 I1 I0 I7’I6’I5’I4’I3’I2’11’ I0’ Active ∑E ∑O

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1

LOGIC DIAGRAM:
16 BIT ODD/EVEN PARITY GENERATOR
TRUTH TABLE 16 BIT ODD/EVEN PARITY GENERATOR:

I7 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0 Active ∑E ∑O
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0

PIN DIAGRAM FOR IC 74180:

FUNCTION TABLE:
INPUTS OUTPUTS
Number of High PE PO ∑E ∑O
Data
Inputs (I0 – I7)
EVEN 1 0 1 0
ODD 1 0 0 1
EVEN 0 1 0 1
ODD 0 1 1 0
X 1 1 0 0
X 0 0 1 1
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Switch on the power supply.
3. Verify the truth table given for different inputs.
4. Repeat the above procedures for even parity checker.

INFERENCE AND CONCLUSION:

REVIEW QUESTIONS:
1. What is parity generator?
2. What is the need for error checking?
3. Name the methods used to check the error?
4. What is even parity?
5. What is odd parity?
 Date:
Expt. No. IMPLEMENTATION OF FULL ADDER USING
MULTIPLEXER
8

AIM:
To design and construct full adder circuit and verify the truth table using
multiplexers.

COMPONENTS / EQUIPMENTS REQUIRED:

S.No. COMPONENT SPECIFICATION QTY.
1. MUX IC IC 74151 2
2. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 32

THEORY:-
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a single output
line. The selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input line and n selection lines whose bit combination determine
which input is selected.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time
but a half adder cannot do so. In full adder sum output will be taken from X-OR Gate,
carry output will be taken from OR Gate.
LOGIC DIAGRAM FOR SUM BIT OF FULL ADDER USING 4:1
MULTIPLEXER:

LOGIC DIAGRAM FOR CARRY BIT OF FULL ADDER USING 4:1

MULTIPLEXER:
 PROCEDURE:
1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.

3. Observe the output and verify the truth table.

INFERENCE AND CONCLUSION:

VIVA QUESTIONS:

1. What is a multiplexer?
2. What are the applications of multiplexer?
3. What is the difference between multiplexer & demultiplexer?
4. In 2n: 1 multiplexer how many selection lines are used?
5. Draw a 2 to 1 multiplexer circuit
6. Draw a 1 to 2 demultiplexer circuit.
Expt. No: IMPLEMENTATION OF SISO, SIPO, PISO AND PIPO Date:
9 SHIFT REGISTERS

AIM:
To implement the 4 bit shift register using flip flops and to study the operations in
the following modes.
(i) Serial in serial out (ii)
Serial in parallel out (iii)
Parallel in parallel out (iv)
Parallel in serial out

COMPONENTS / EQUIPMENTS REQUIRED:

S.No. Name of the apparatus Range Quantity

1 Digital Trainer kit 1
2 D Flip Flop IC 7474 2
3 Connecting wires some

THEORY:

SHIFT REGISTER:
A register is a device capable of storing a bit. The data can be serial or parallel. The
register can convert a data from serial to parallel and vice versa shifting then digits to
left and right is the important aspect for arithmetic operations,

A register capable of shifting its binary information either to the right or to the left is
called a shift register. An N bit shift register consists of N flip-flops and the gates that
control the shift operation. A shift register can be used in four different configurations
depending upon the way in which the data are entered into and taken out of it. These
four configurations are:
❑ Serial-input, Serial-output
❑ Parallel-input, Serial-output
❑ Serial-input, parallel-output
❑ Parallel-output, parallel-output

The serial input is a single line going to the input of the leftmost flip-flop of the
register. The serial output is a single line from the output of the rightmost flip-flop of
the register, so that the bits stored in the register can come out through this line one at a
time.

The parallel output consists of N lines, one for each of the flip-flops in the register,
so the information stored in the register can be inspected through these lines all at once.
Serial in Serial out:
Serial in Parallel Out:

Parallel In Parallel Out

PARALLEL IN SERIAL OUT

 TRUTH TABLE FOR PISO SHIFT REGISTER:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

PROCEDURE:
1. The flip-flop is connected using connecting wires as shown in the circuit.
2. The flip flop are then reset to zero internally with the help of reset to set inputs.
3. The bits are shifted in by giving suitable clock input.
4. Thus the truth table is then verified.

INFERENCE AND CONCLUSION:

Expt. No: DESIGN AND IMPLEMENTATION OF 4 BIT Date:
10 SYNCHRONOUS JOHNSON COUNTER

AIM:
To design and implementation of 4-bit synchronous Johnson counter using D flip flop.

COMPONENTS / EQUIPMENTS REQUIRED:

S.No. Name of the apparatus Range Quantity

1 Digital Trainer kit 1
2 D Flip Flop IC 7474 2
3 Connecting wires some

THEORY:

The Johnson counter, also known as the twisted-ring counter, is exactly the same
as the ring counter except that the inverted output of the last flip-flop is connected to the
input of the first flip-flop.

The Johnson counter works in the following way: Take the initial state of the
counter to be 000. On the first clock pulse, the inverse of the last flip-flop will be fed
into the first flip-flop, producing the state 100. On the second clock pulse, since the last
flip-flop is still at level 0, another 1 will be fed into the first flip-flop, giving the state
110. On the third clock pulse, the state 111 is produced. On the fourth clock pulse, the
inverse of the last flip-flop, now a 0, will be shifted to the first flip-flop, giving the state
011. On the fifth and sixth clock pulse, using the same reasoning, we will get the states
001 and 000, which is the initial state again. Hence, this Johnson counter has six distinct
states: 000, 100, 110, 111, 011 and 001, and the sequence is repeated so long as there is
input pulse. Thus this is a MOD-6 Johnson counter.

A Johnson counters represent a middle ground between ring counters and binary
counters. A Johnson counter requires fewer flip-flops than a ring counter but generally
more than a binary counter; it has more decoding circuitry than a ring counter but less
than a binary counter.
Circuit Diagram:

4-bit Synchronous Johnson Counter

Truth Table:-
PROCEDURE: -

1. Connections are made as per circuit diagram.

2. Clock pulses are applied one by one at the clock I/P and the O/P is observed at QA,
QB & QC for IC 7476.

3. Verify the Truth table

INFERENCE AND CONCLUSION:

VIVA QUESTIONS:

1. What is the difference between Register & counter?

2. What is Johnson Counter?
3. What is ring counter?
4. Which flip flop is used in counters?
5. What is D flip flop? Draw its truth table.
6. What is T flip flop? Draw its truth table.
7. What is a register?
8. What are the applications of shift register?
9. Which flip flop is used in shift register?
10. What is a universal shift register?
Expt. No. DESIGN AND IMPLEMENTATION OF Date:
11. SYNCHRONOUS COUNTER

AIM:
To construct and verify the synchronous up/down counters.

COMPONENTS / EQUIPMENTS REQUIRED:

S. No. Components / Equipments Specification Quantity

1. Digital IC trainer kit JK ---- 1
2. Flip-Flop, AND Gate IC 7473,7408 2,1
3. Connecting wires ---- Sufficient Nos

THEORY:

Synchronous Counter
Clock input is applied simultaneously to all flip-flops. The output of the first FLIP-
FLOP is connected to the input of second FLIP-FLOP and so on.
Design of synchronous counter
Step 1: Find the number of flip-flops required. For an n-bit counter, n- flip-flops
is required. Step 2: Write the count sequence in tabular form.
Step 3: Determine the flip-flop inputs, which must be present for the desired next
State from the present state using excitation table of flip-flops.
Step 4: Prepare K-map for each flip-flop input in terms of flip-flop output as
input
Variables. Simplify the K-map and obtain the minimized expressions.
Step 5: Connect the circuit using the flip-flops.

CIRCUIT DIAGRAM: Design of 3-bit synchronous up:

Design of 3-bit synchronous down counter:

Pin Diagram

Truth Table:
3 Bit Synchronous DOWN
3 Bit Synchronous UP Counter
Counter
Clock Q2 Q1 Q0 Clock Q2 Q1 Q0
0 0 0 0 0 1 1 1
1 0 0 1 1 1 1 0
2 0 1 0 2 1 0 1
3 0 1 1 3 1 0 0
4 1 0 0 4 0 1 1
5 1 0 1 5 0 1 0
6 1 1 0 6 0 0 1
7 1 1 1 7 0 0 0
 PROCEDURE:
1. The connections are made as per the circuit diagram.
2. Switch on the power supply.
3. The input is given at the appropriate terminal and corresponding output
is observed and truth table is verified.

INFERENCE AND CONCLUSION:

REVIEW QUESTIONS
1. Name any four flip-flop used to construct the counter.
2. Draw the basic block diagram of a practical 4-bit counter.
3. What is MOD 5 counter?
4. What is the need for counters?
5. Give some practical applications of counters.
Expt. No. DESIGN AND IMPLEMENTATION OF Date:
12. ASYNCHRONOUS COUNTER

AIM:
To construct and verify the asynchronous counters.

COMPONENTS / EQUIPMENTS REQUIRED:

S. No. Components / Equipments Specification Quantity

1. Digital IC trainer kit ----- 1
2. JK Flip-Flop IC 7473 2
3. NAND, AND Gate IC 7400, 7408 Each 1
4. Connecting wires --- Sufficient

THEORY:
It is a sequential circuit made of FLIP-FLOP’s. The output of the first FLIP-
FLOP is connected to the clock input of second FLIP-FLOP and so on. A maximum of
4 FLIP-FLOP can count from 0-15.

CIRCUIT DIAGRAM: ASYNCHRONOUS COUNTER: - MOD 16 COUNTER

MOD 12 COUNTERS:

MOD 10 COUNTERS

Truth Table:
MOD 16 Counter
Clock Q0 Q1 Q2 Q3
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
CS8382- Digital Systems Lab Dept of ECE 2018-19

4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0
MOD 12 Counter
Clock Q0 Q1 Q2 Q3
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 0 0 0 0

MOD 10 Counter
Clock Q0 Q1 Q2 Q3
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0

Rajalakshmi Institute of Technology

 PROCEDURE:

1. The connections are made as per the circuit diagram.

2. Switch on the power supply.
3. The input is given at the appropriate terminal and corresponding output is
observed and truth table is verified.

INFERENCE AND CONCLUSION:

REVIEW QUESTIONS:
1. Name any four flip-flop used to construct the counter.
2. Draw the basic block diagram of a practical 4-bit counter.
3. What is MOD 5 counter?
4. What is the need for counters?
5. Give some practical applications of counters.

Rajalakshmi Institute of Technology

Expt. No. HDL CODING FOR COMBINATIONAL AND Date:
13 SEQUENTIAL CIRCUITS

Aim:
To write an HDL program for combinational and sequential circuits.

COMPONENTS / EQUIPMENTS REQUIRED:

1. PC
2. VHDL simulation Software

Program:

HALF ADDER:-

FULL ADDER:-
HALF SUBTRACTOR:-

FULL SUBTRACTOR:-
4:1 MULTIPLEXER:-
1:4 DEMULTIPLEXER:-
SERIAL IN SERIAL OUT:
SERIAL IN PARALLEL OUT:
PARALLEL IN SERIAL OUT:
PARALLEL IN PARALLEL OUT:
INFERENCE AND CONCLUSION:

VIVA QUESTIONS:

1. What is HDL?
2. What is logic simulation?
3. What is logic synthesis?
4. What is UDP?
5. What is Gate level modeling?
6. What is Dataflow modeling?
7. What is Behavioral modeling?
 Appendix

Useful IC Pin details

7400(NAND)

7402(NOR)
 7404(NOT)

7408(AND)

7411(3-i/p AND)
 7432(OR)

7486(EX-OR)
CS8382- Digital Systems Lab Dept of ECE 2018-19

Rajalakshmi Institute of Technology

CS8382- Digital Systems Lab Dept of ECE 2018-19

7410(3-i/p NAND)

7420(4-i/p NAND)

Rajalakshmi Institute of Technology

CS8382- Digital Systems Lab Dept of ECE 2018-19

Rajalakshmi Institute of Technology