sumador completo de 4 bits,

library ieee;
use ieee.std_logic_1164.all;

entity sumador4bit is
port(As: in std_logic_vector(3 downt 0);
Bs: in std_logic_vector(3 downt 0);
Cis: in std_logic;
Ss: out std_logic _vector(3 downt 0);
Cos: out std_logic);
end sumador4bit;

architecture s4bit of sumador4bit is

Signal Co_s0, Co_s1, Co_s2: std_logic;
Component sumador is
port(A: in std_logic;
B: in std_logic;
Ci: in std_logic;
S: out std_logic;
Co: out std_logic);
end Component;

Begin
SO: sumador port map( As(0), Bs(0), Cis, Ss(0), Co_s0);
S1: sumador port map( As(1), Bs(1), Co_s0, Ss(1), Co_s1);
S2: sumador port map( As(2), Bs(2), Co_s1, Ss(2), Co_s2);
S3: sumador port map( As(3), Bs(3), Co_s2, Ss(3), Cos);
end s4bit;