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S9KEA128P80M48SF0
KEA128 Sub-Family Data
Sheet
Supports the following:
S9KEAZ64AMLK(R),
S9KEAZ128AMLK(R),
S9KEAZ64AVLK(R),
S9KEAZ128AVLK(R),
S9KEAZ64ACLK(R),
S9KEAZ128ACLK(R),
S9KEAZ64AMLH(R),
S9KEAZ128AMLH(R),
S9KEAZ64AVLH(R),
S9KEAZ128AVLH(R),
S9KEAZ64ACLH(R) and
S9KEAZ128ACLH(R)
Key features • System peripherals
– Power management module (PMC) with three power
• Operating characteristics
modes: Run, Wait, Stop
– Voltage range: 2.7 to 5.5 V
– Low-voltage detection (LVD) with reset or interrupt,
– Flash write voltage range: 2.7 to 5.5 V
selectable trip points
– Temperature range (ambient): -40 to 125°C
– Watchdog with independent clock source (WDOG)
• Performance – Programmable cyclic redundancy check module
– Up to 48 MHz ARM® Cortex-M0+ core (CRC)
– Single cycle 32-bit x 32-bit multiplier – Serial wire debug interface (SWD)
– Single cycle I/O access port – Aliased SRAM bitband region (BIT-BAND)
– Bit manipulation engine (BME)
• Memories and memory interfaces
– Up to 128 KB flash • Security and integrity modules
– Up to 16 KB RAM – 80-bit unique identification (ID) number per chip
• Clocks • Human-machine interface
– Oscillator (OSC) - supports 32.768 kHz crystal or 4 – Up to 71 general-purpose input/output (GPIO)
MHz to 24 MHz crystal or ceramic resonator; choice – Two 32-bit keyboard interrupt modules (KBI)
of low power or high gain oscillators – External interrupt (IRQ)
– Internal clock source (ICS) - internal FLL with
• Analog modules
internal or external reference, 37.5 kHz pre-trimmed
– One up to 16-channel 12-bit SAR ADC, operation in
internal reference for 48 MHz system clock
Stop mode, optional hardware trigger (ADC)
– Internal 1 kHz low-power oscillator (LPO)
– Two analog comparators containing a 6-bit DAC
and programmable reference input (ACMP)
1 Ordering parts
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q B KEA A C FFF M T PP N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field Description Values
Q Qualification status • S = Automotive qualified
• P = Prequalification
B Memory type • 9 = Flash
KEA Kinetis Auto family • KEA
A Key attribute • Z = M0+ core
• F = M4 W/ DSP & FPU
• C= M4 W/ AP + FPU
C CAN availability • N = CAN not available
• (Blank) = CAN available
2.4 Example
This is an example part number:
S9KEAZ128AMLK
3 Ratings
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78D, IC Latch-up Test. The test produced the following results:
• Test was performed at 125 °C case temperature (Class II).
• I/O pins pass +100/-100 mA I-test with IDD current limit at 400 mA (VDD collapsed during positive injection).
• I/O pins pass +50/-100 mA I-test with IDD current limit at 1000 mA for VDD.
• Supply groups pass 1.5 Vccmax.
• RESET_B pin was only tested with negative I-test due to product conditioning requirement.
4 General
4.1.1 DC characteristics
This section includes information about power supply requirements and I/O pin
characteristics.
Table 2. DC characteristics
Symbol Descriptions Min Typical1 Max Unit
— Operating voltage — 2.7 — 5.5 V
VOH Output All I/O pins, except PTA2 5 V, Iload = –5 mA VDD – 0.8 — — V
high and PTA3, standard-drive 3 V, Iload = –2.5 mA VDD – 0.8 — — V
voltage strength
High current drive pins, 5 V, Iload = –20 mA VDD – 0.8 — — V
high-drive strength2 3 V, Iload = –10 mA VDD – 0.8 — — V
IOHT Output Max total IOH for all ports 5V — — –100 mA
high 3V — — –60
current
VOL Output All I/O pins, standard-drive 5 V, Iload = 5 mA — — 0.8 V
low strength 3 V, Iload = 2.5 mA — — 0.8 V
voltage
High current drive pins, 5 V, Iload =20 mA — — 0.8 V
high-drive strength2 3 V, Iload = 10 mA — — 0.8 V
IOLT Output Max total IOL for all ports 5V — — 100 mA
low 3V — — 60
current
VIH Input high All digital inputs 4.5≤VDD<5.5 V 0.65 × VDD — — V
voltage 2.7≤VDD<4.5 V 0.70 × VDD — —
VIL Input low All digital inputs 4.5≤VDD<5.5 V — — 0.35 × V
voltage VDD
2.7≤VDD<4.5 V — — 0.30 ×
VDD
Vhys Input All digital inputs — 0.06 × VDD — — mV
hysteresis
|IIn| Input Per pin (pins in high VIN = VDD or VSS — 0.1 1 µA
leakage impedance input mode)
current
VDD-VOH(V)
IOH(mA)
VDD-VOH(V)
IOH(mA)
VDD-VOH(V)
IOH(mA)
VDD-VOH(V)
IOH(mA)
VOL(V)
IOL(mA)
Figure 5. Typical VOL Vs. IOL (standard drive strength) (VDD = 5 V)
VOL(V)
IOL(mA)
VOL(V)
IOL(mA)
VOL(V)
IOL(mA)
Switching specifications
Table 5. Control timing (continued)
Num Rating Symbol Min Typical1 Max Unit
5 Reset low drive trstdrv 34 × tcyc — — ns
6 IRQ pulse width Asynchronous path2 tILIH 100 — — ns
Synchronous path3 tIHIL 1.5 × tcyc — — ns
7 Keyboard interrupt pulse Asynchronous path2 tILIH 100 — — ns
width Synchronous path tIHIL 1.5 × tcyc — — ns
8 Port rise and fall time - — tRise — 10.2 — ns
Normal drive strength (load tFall — 9.5 — ns
= 50 pF)4
Port rise and fall time - high — tRise — 5.4 — ns
drive strength (load = 50 tFall — 4.6 — ns
pF)4
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
3. This is the minimum pulse width that is guaranteed to pass through the pin synchronization
circuitry.
Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
4. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 125 °C.
textrst
RESET_b pin
KBIPx
IRQ/KBIPx
tILIH
Thermal specifications
tTCLK
tclkh
TCLK
tclkl
FTMCHn
FTMCHn
tICPW
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.
J2
J3 J3
SWD_CLK (input)
J4 J4
SWD_CLK
J9 J10
J11
J12
SWD_DIO
J11
Table 9. OSC and ICS specifications (temperature range = -40 to 125 °C ambient) (continued)
Num Characteristic Symbol Min Typical1 Max Unit
16 MHz — 0 — kΩ
6 Crystal start-up Low range, low power tCSTL — 1000 — ms
time low range = Low range, high gain — 800 — ms
32.768 kHz
crystal; High High range, low power tCSTH — 3 — ms
range = 20 MHz High range, high gain — 1.5 — ms
crystal4,5
7 Internal reference start-up time tIRST — 20 50 µs
8 Internal reference clock (IRC) frequency trim fint_t 31.25 — 39.0625 kHz
range
9 Internal T = 125 °C, VDD = 5 V fint_ft — 37.5 — kHz
reference clock
frequency,
factory trimmed,
10 DCO output FLL reference = fint_t, flo, or fdco 40 — 50 MHz
frequency range fhi/RDIV
11 Factory trimmed T = 125 °C, VDD = 5 V Δfint_ft -0.8 — 0.8 %
internal oscillator
accuracy
12 Deviation of IRC Over temperature range from Δfint_t -1 — 0.8 %
over temperature -40 °C to 125°C
when trimmed at
T = 25 °C, VDD =
5V
13 Frequency Over temperature range from Δfdco_ft -2.3 — 0.8 %
accuracy of DCO -40 °C to 125°C
output using
factory trim value
14 FLL acquisition time4,6 tAcquire — — 2 ms
15 Long term jitter of DCO output clock (averaged CJitter — 0.02 0.2 %fdco
over 2 ms interval)7
OSC
EXTAL XTAL
RS
RF
Crystal or Resonator
C1
C2
Program and erase operations do not require any special power sources other than the
normal VDD supply. For more detailed information about program/erase operations, see
the Flash Memory Module section in the reference manual.
5.4 Analog
1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT z ADIN
Pad SIMPLIFIED
ZAS leakage CHANNEL SELECT
due to CIRCUIT ADC SAR
R AS input R ADIN ENGINE
protection
v ADIN
C AS
v AS
R ADIN
INPUT PIN
R ADIN
INPUT PIN
R ADIN
Table 12. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Characteristic Conditions Symbol Min Typ1 Max Unit
ADC asynchronous High speed (ADLPC = fADACK 2 3.3 5 MHz
clock source 0)
Low power (ADLPC = 1.25 2 3.3
1)
Conversion time Short sample tADC — 20 — ADCK cycles
(including sample time) (ADLSMP = 0)
Long sample — 40 —
(ADLSMP = 1)
Sample time Short sample tADS — 3.5 — ADCK cycles
(ADLSMP = 0)
Long sample — 23.5 —
(ADLSMP = 1)
Total unadjusted Error2 12-bit mode ETUE — ±5.0 — LSB3
10-bit mode — ±1.5 —
8-bit mode — ±0.8 —
Differential Non- 12-bit mode DNL — ±1.5 — LSB3
Liniarity 10-bit mode — ±0.4 —
8-bit mode — ±0.15 —
Integral Non-Linearity 12-bit mode INL — ±1.5 — LSB3
10-bit mode — ±0.4 —
8-bit mode — ±0.15 —
Zero-scale error4 12-bit mode EZS — ±1.0 — LSB3
10-bit mode — ±0.2 —
8-bit mode — ±0.35 —
Full-scale error5 12-bit mode EFS — ±2.5 — LSB3
10-bit mode — ±0.3 —
8-bit mode — ±0.25 —
Quantization error ≤12 bit modes EQ — — ±0.5 LSB3
Input leakage error6 all modes EIL IIn x RAS mV
Temp sensor slope -40 °C–25 °C m — 3.266 — mV/°C
25 °C–125 °C — 3.638 —
Temp sensor voltage 25 °C VTEMP25 — 1.396 — V
1. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. Includes quantization
3. 1 LSB = (VREFH - VREFL)/2N
4. VADIN = VSSA
5. VADIN = VDDA
6. IIn = leakage current (refer to DC characteristics)
SS1
(OUTPUT)
3 2 10 11 4
SPSCK 5
(CPOL=0)
(OUTPUT) 5
10 11
SPSCK
(CPOL=1)
(OUTPUT)
6 7
MISO
MSB IN2 BIT 6 . . . 1 LSB IN
(INPUT)
8 9
MOSI
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
SS1
(OUTPUT)
2
3 10 11 4
SPSCK
(CPOL=0)
(OUTPUT)
5 5 10 11
SPSCK
(CPOL=1)
(OUTPUT)
6 7
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN
8 9
MOSI
(OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA
SS
(INPUT)
2 12 13 4
SPSCK
(CPOL=0)
(INPUT)
3 5 5
SPSCK 12 13
(CPOL=1)
(INPUT)
9
8 10 11 11
6 7
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
SS
(INPUT)
2 4
3 12 13
SPSCK
(CPOL=0)
(INPUT)
5 5 12 13
SPSCK
(CPOL=1)
(INPUT)
10 11 9
MISO see
SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT
(OUTPUT) note
8 6 7
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
5.5.2 MSCAN
Table 16. MSCAN wake-up pulse characteristics
Parameter Symbol Min Typ Max Unit
MSCAN wakeup dominant pulse filtered tWUP - - 1.5 µs
MSCAN wakeup dominant pulse pass tWUP 5 - - µs
6 Dimensions
7 Pinout
8 Revision History
The following table provides a revision history for this document.
Table 17. Revision History
Rev. No. Date Substantial Changes
Rev. 1 11 March 2014 Initial Release
Rev. 2 18 June 2014 • Parameter Classification section is
removed.
• Classification column is removed
from all the tables in the
document.
• New section added - Supply
current characteristics.
Rev. 3 18 July 2014 • Added supported part numbers.
• ESD handling ratings section is
updated.
• Figures in DC characteristics
section are updated.
• Specs updated in following tables:
• Table 9.
Rev. 4 03 Sept 2014 • Data Sheet type changed to
"Technical Data".