A B C D E

1 INDEX
2 CPU (SOCKET 7)
3 CLOCK GENERATOR
4
4 MTXC HOST INTERFACE 4

5 MTXC SYSTEM INTERFACE

6 CACHE 1
7 CACHE 2
8 DIMM 1
9 DIMM 2
10 SYSTEM BIOS, TSOP
11 PIIX4 1
12 PIIX4 2
3 13 IDE INTERFACE 3

14 ULTRA IO CONTROLLER
15 PARALLEL PORT
16 KB, FLOPPY, & COM PORTS
17 USB PORT INTERFACE
18 FAN & FRONT PANEL CONNECTORS
19 POWER SUPPLY
20 PCI SLOTS #1 & #2
21 PCI SLOTS #3 & #4
2 2
22 ISA SLOT #1
23 ISA SLOT #2
24 ISA SLOT #3
25 PULL-UP RESISTORS
26 DECOUPLING CAPS
27 CPU VOLTAGE REGULATORS
28 APPENDIX: SYSTEM BIOS, DIP
29 APPENDIX: COAST MODULE

1 1
Intel Corporation
Title
TX DESKTOP INDEX
Size Document Number Rev
2.1

Date: Thursday, December 19, 1996 Sheet 1 of 29

A B C D E
 1 2 3 4 5 6 7 8

CPUVCORE

4,6 HD[63..0] HA[31:3] 4,6

AN11
AN13
AN15
AN17

AN19
AJ11
AG1
AA1

AC1

AE1

AN9
A11

A13

A15

A17

E15

W1
G1

Q1
A7

A9

B2

N1

S1

U1

Y1
J1

L1
U14
HD0 K34 AL35 HA3

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE
VCORE

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE
VCORE
VCORE
VCORE
VCORE

VCORE
G35 D0 A3 AM34
HD1 D1 A4 HA4
HD2 J35 AK32 HA5
G33 D2 A5 AN33
A HD3 D3 A6 HA6 A
HD4 F36 AL33 HA7
F34 D4 A7 AM32
HD5 D5 A8 HA8
HD6 E35 AK30 HA9
E33 D6 A9 AN31
HD7 D7 A10 HA10
HD8 D34 AL31 HA11
C37 D8 A11 AL29
HD9 D9 A12 HA12
HD10 C35 AK28 HA13
B36 D10 A13 AL27
HD11 D11 A14 HA14
HD12 D32 AK26 HA15
B34 D12 A15 AL25
HD13 D13 A16 HA16
HD14 C33 AK24 HA17
A35 D14 A17 AL23
HD15 D15 A18 HA18
HD16 B32 AK22 HA19
C31 D16 A19 AL21
HD17 D17 A20 HA20
HD18 A33 AF34 HA21
D28 D18 A21 AH36
HD19 D19 A22 HA22
HD20 B30 AE33 HA23
C29 D20 A23 AG35
HD21 HA24

P54C/P55
A31 D21 A24 AJ35
HD22 D22 A25 HA25
HD23 D26 AH34 HA26
C27 D23 A26 AG33
HD24 D24 A27 HA27
HD25 C23 AK36 HA28
D24 D25 A28 AK34
HD26 D26 A29 HA29
HD27 C21 AM36 HA30
D22 D27 A30 AJ33
HD28 D28 A31 HA31
HD29 C19
D20 D29 AM2
HD30 D30 ADSC# HADSC# 6
HD31 C17
D31
HD32 C15 AL9 HBE#0

SOCKET 7
D16 D32 BE0# AK10
HD33 HBE#1
C13 D33 BE1# AL11
HD34 HBE#2
D14 D34 BE2# AK12
HD35 HBE#3
C11 D35 BE3# AL13
HD36 HBE#4
D12 D36 BE4# AK14
HD37 HBE#5
C9 D37 BE5# AL15
HD38 HBE#6
D10 D38 BE6# AK16
HD39 HBE#7
D8 D39 BE7#
HD40 D40
B HD41 A5 B
D41 HBE#[7:0] 4,6
HD42 E9 Q5
CPUVIO D42 FERR# HFERR# 12
HD43 B4 AJ1
D6 D43 BREQ AL5
HD44 D44 HITM# HHITM# 4
HD45 C5 AK6
8 RP20-1 1 E7 D45 HIT# AF4
HA20M# HD46
C3 D46 PCHK# CPUVIO
4.7K HD47 D47
HD48 D4 AJ3
6 RP32-33 E5 D48 HLDA AK2 8 RP21-1 1
HSMI# HD49 HAP
D2 D49 AP AH4 4.7K
4.7K HD50 D50 LOCK# HLOCK# 4
HD51 F4 AE5
8 RP35-11 E3 D51 APCHK# AC5
HIGNNE# HD52
G5 D52 PRDY AG5
4.7K HD53 D53 PCD
HD54 E1 AL3
8 RP32-11 G3 D54 PWT U3
HINTR HD55
H4 D55 CACHE# HCACHE# 4
4.7K HD56 D56
HD57 J3 AJ5
7 RP32-22 J5 D57 ADS# AK4 HADS# 4
HNMI HD58 HD/C# 4
K4 D58 D/C# AM6
4.7K HD59 D59 W/R# HW/R# 4,6
HD60 L5 T4
D60 M/IO HM/IO# 4
HSTPCLK# 5 RP35-44 HD61 L3
M4 D61
4.7K HD62 D62
HD63 N3 AL17
R53 D63 SCYC Y35 6 RP35-3 3
HRESET HFRCMC#
FRCMC# P4 4.7K
330 IERR# AG3 HSMIACT# 4
R55 SMIACT#
HINIT
5V_SUPPLY: AN1,AN3 Q3
330 PM0/BP0
4 RP43-4 5 HDP0 D36 R4
3 RP43-36 DP0 PM1/BP1
4.7K HDP1 D30
DP1 CPU_IO_VCC: A19,A21,A23,A25,A27,A29,AA37,AC37 BP2
S3
4.7K 2 RP43-27 HDP2 C25 S5 ** THIS TABLE IS FOR JUMPER
DP2 BP3 CONFIGURATION BELOW.
1 RP43-1 8 4.7K HDP3 D18
DP3 AE37,AG37,AJ19,AJ29,AN21,AN23,AN25
4.7K 4 RP38-4 5 HDP4 C7 M34
3 RP38-36 DP4 TCK
4.7K HDP5 F6
DP5 AN27,AN29,E21,E27,E37,G37,J37,L33 TDO
N33
4.7K 2 RP38-2 7 HDP6 F2 N35 BUS/CORE
1 RP38-18 DP6 TDI BF1 BF0 FREQUENCY RATIO
4.7K HDP7 N5
DP7 L37,N37,Q37,S37,T34,U33,U37,W37,Y37 TMS
P34
4.7K Q33
AK18 TRST#
C 3 HCLKCPU CLK CPU_CORE_VCC: A7,A9,A11,A13,A15,A17,AA1,AC1,AE1,AG1 C
0 0 2/5
Z4 AJ11,AN9,AN11,AN13,AN15,AN17,AN19,B2 H34
4 HBOFF# BOFF# PICCLK
AK8 J33
12 HA20M# A20# PICD0
12 HINTR
AD34 E15,G1,J1,L1,N1,Q1,S1,U1,W1,Y1 L35 0 1 1/3
AC33 INTR PICD1
12 HNMI NMI
AA35
12 HIGNNE# IGNNE#
W5 GND: A3,AB2,AB36,AB4,AD2,AD36,AF2,AF36,AH2 AC3 1 0 1/2
4 HKEN# 2 RP21-2 7 AN7 KEN# PHITM# AA3
HFLUSH#
V4 FLUSH# PHIT# AD4 CPUVIO
4 HAHOLD 4.7K AJ7,AJ9,AJ13,AJ17,AJ21,AJ25,AJ27,AJ31
AM4 AHOLD PBGNT# AE3 1 1 2/3
4 HEADS# EADS# PBREQ#
X4 AJ37,AL37,AM8,AM10,AM12,AM1 4,AM16,AM18
4 HBRDY# BRDY#
12 HRESET
AK20
RESET BF0
Y33 HBF0
U5
INV AM20,AM22,AM24,AM26,AM 28,AM30,AN37,B6 BF1
X34 HBF1
Y5
4 HNA# 3 RP21-3 6 AL7 NA# AE35
HBUSCHK# B8,B10,B12,B14,B16,B18,B20,B22,B24,B26
2 RP20-2 7 HWB/WT# AA5 BUSCHK# U/O# JB1
4.7K
AA33 WB/WT# Q35
4.7K B28,E11,E13,E19,E23,E29,E31,H2,H36,K2
12 HINIT AB34 INIT CPUTYP 2 1
R58 12 HSMI# SMI# 4 3
HHOLD AC35 K36,M2,M36,P2,P36,R2,R36,T2,T36,U35,V2 AH32
2 RP35-2 7 HPEN# Z34 R/S# UPVRM# 6 5
330 PEN#
4.7K V34 V36,W3,X2,X36,Z2,Z36 AL1
12 HSTPCLK# STOPCLK# VCC2DET VCC2DET 27 JB3
R61 AB4
W3 HOLD
HEWBE#
EWBE#
330 R39 HBRDYC# Y3
BRDYC#
330

P55C_0

D D

This drawing contains information

which has not been verified for Intel Corporation
manufacturing an end user product Title
Intel is not responsible for the TX DESKTOP P54C/P55
misuse of this information. Size Document Number Rev
2.1
Date: Thursday, December 19, 1996 Sheet 2 of 29
1 2 3 4 5 6 7 8
 A B C D E

CLKVCC3A C232

C242 0.1UF

C225 0.1UF

4
C220 22UF 4

If IMISC652 is used: C217 0.1UF

Install R163 C226 0.1UF

0.1UF
Do Not Install R98 C231
0.1UF
C223
+3_3V
C227 0.1UF
L13
CLKVCC3A C216 0.1UF
1 2

+
R98 47UF
12 OSCPIIX4 FBS01L
33

R100 OSCIOR
14 OSCUIO

46
40

48
25

15
21
28
34
33

7
HCLKCPUR 2 R105 1

VDDQ2
VDDQ2

VDD
VDD
VDDQ3
VDDQ3
VDDQ3
VDDQ3
VDDQ3
HCLKMTXC 5
R102 OSCR 33
22,23,24 OSC
33
2
1 REF0 42
R163 OSCPIIX4R REF1 CPUCLK0
47 41 R108 33
CPU3_3 CPUCLK1 HCLKCPU 2
33 39
4 CPUCLK2 38 R111
XTAL1 HCLKSRAM1R 33 HCLKSRAM1 6
5 XTAL_IN CPUCLK3
3 XTAL2 3
XTAL_OUT 36 HCLKDIMM5R R131 22 HCLKDIMM5 9
6 SDRAM0 35 R122
Y3 HCLKDIMM1R 22 HCLKDIMM1 8
18 MODE SDRAM1 33 R121
HCLKDIMM2R 22 HCLKDIMM2 8
+3_3V SEL_66/60 SDRAM2 32 22
HCLKDIMM3R R125 HCLKDIMM3 8
C214 C215 19 SDRAM3 30
14.318MHz SMBDPU HCLKDIMM4R R129 22 HCLKDIMM4 9
20 SDATA SDRAM4 29
10pf HCLKDIMM6R R133 22 HCLKDIMM6 9
10pf 8,9,12 SMBCLK SDCLK SDRAM5
R45 22 8 PCLKPIIXR R101 47
48/24_MHZ PCICLK_F PCLKPIIX4 12
J18 10K 23 9
3 48/24_MHZ PCICLK0 11 R104 1 2 33
PCLK0R PCLK0 20
2 26 PCICLK1 12 R109 1 2 33
CLKSEL0 HCLKDIMM7R PCLK1R PCLK1 20
1 27 PCI_STP#/SDRAM7 PCICLK2 13 R110 1 2 33
HCLKDIMM0R PCLK2R PCLK2 21
CPU_STP#/SDRAM6PCICLK3 14 R120 1 2 33
PCLK3R PCLK3 21
45 PCICLK4 16 R124 1 2 47
JMP_3P HCLK 66MHz 60MHz IOAPIC0 PCICLK5
PCLKMTXCR PCLKMTXC 5
44
PWR_DWN#
J18 1-2 2-3 U18
HCLKDIMM0R R114 22
IMISC671A HCLKDIMM0 8

R130 CLK48MR R132 22

12 CLK48M HCLKDIMM7 9
22

2 R128 1
8,9,12 SMBDATA SMBDPU
0
2 2

NOTE: Install w/ 671 Device

Do not Install w/ 652 Device

1 1

This drawing contains information

which has not been verified for SYSTEM CLOCKS Title
Intel Corporation

manufacturing an end user product TX DESKTOP SYSTEM CLOCKS

Intel is not responsible for the
Size Document Number Rev
misuse of this information.
2.1
Date: Thursday, December 19, 1996 Sheet 3 of 29
A B C D E
 A B C D E

HD[63..0]
HD[63..0] 2,6
4 4
HA[3..31]
2,6 HA[31..3]

U13A

CPUVIO V11 Y1
HA3 A3 HD0 HD0
HA4 Y11 Y3 HD1
U8 A4 HD1 Y2
HA5 A5 HD2 HD2
HA6 T11 Y4 HD3
Y8 A6 HD3 W1
HA7 A7 HD4 HD4
HA8 V8 W2 HD5
V7 A8 HD5 V1
HA9 A9 HD6 HD6
R49 22K HA10 Y7 R1 HD7
W7 A10 HD7 U1
HA11 A11 HD8 HD8
HA12 U7 W3 HD9
Y6 A12 HD9 V3
HA13 A13 HD10 HD10
HA14 V6 W4 HD11
W6 A14 HD11 T1
HA26 HA15 HD12
U6 A15 HD12 V4
HA16 A16 HD13 HD13
HA17 Y5 U3 HD14
W5 A17 HD14 V2
HA18 A18 HD15 HD15
CPUVIO
2-3 1-2
HA19
HA20
HA21
V5
U5
V9
A19
A20
A21
MTXC HD16
HD17
HD18
U4
T2
U2
HD16
HD17
HD18
HA22 U10 R3 HD19
60 MHz 66 MHz A22 HD19
HA23 U9 T4 HD20
A23 HD20
J17
1
HA24
HA25
W10
W9
V10
A24
A25
PART 1 OF 2 HD21
HD22
R2
T3
P1
HD21
HD22
HA26 HD23
3 2
3 MTXCCLKSEL R46
HA27
HA27
HA28
Y9
Y10
A26
A27
A28
HOST HD23
HD24
HD25
R4
P3
HD24
HD25
3

JMP_3P 4.7K HA29

HA30
U11
W11
W8
A29
A30
INTERFACE HD26
HD27
P2
N1
P4
HD26
HD27
HA31 A31 HD28 HD28
N3 HD29
HBE#[7..0] HD29 N2
2,6 HBE#[7..0] HD30 HD30
N4 HD31
HD31 M3
HD32 HD32
HBE#0 K2 M2 HD33
K3 BE0# HD33 K1
HBE#1 BE1# HD34 HD34
HBE#2 K4 M4 HD35
L1 BE2# HD35 J2
HBE#3 HD36
L2 BE3# HD36 J1
HBE#4 HD37
L3 BE4# HD37 J4
HBE#5 HD38
L4 BE5# HD38 H1
HBE#6 HD39
M1 BE6# HD39 H2
HBE#7 HD40
BE7# HD40 G2
HD41 HD41
J3 HD42
HD42 G4
HD43 HD43
T5 H4 HD44
2 HADS# ADS# HD44
2 HBRDY# M5 G1 HD45
N5 BRDY# HD45 H3
2 HNA# NA# HD46 HD46
L5 F2 HD47
2 HAHOLD AHOLD HD47
R5 F1 HD48
2 HEADS# EADS# HD48
P5 G3 HD49
2 HBOFF# BOFF# HD49
T8 F4 HD50
2 HHITM# HITM# HD50
H5 F3 HD51
2 HM/IO# M/IO# HD51
G5 E1 HD52
2 HLOCK# HLOCK# HD52
J5 E4 HD53
2 HCACHE# CACHE# HD53
K5 E2 HD54
2 2 HKEN# KEN#/INV HD54 2
T10 D1 HD55
2 HSMIACT# T9 SMIACT# HD55 E3
2,6 HW/R# W/R# HD56 HD56
T7 D3 HD57
2 HD/C# D/C# HD57 D2
HD58 HD58
C1 HD59
HD59 C2
HD60 HD60
C3 HD61
HD61 B1
HD62 HD62
A1 HD63
HD63

MTXC

1 1

This drawing contains information Intel Corporation

which has not been verified for Title
manufacturing an end user product TX DESKTOP MTXC MICRO CONTROLLER
Intel is not responsible for h
te
Size Document Number Rev
misuse of this information. 2.1

Date: Thursday, December 19, 1996 Sheet 4 of 29

A B C D E
 A B C D E

5VREF
+3_3V +3_3V +3_3V
+3_3V C273
8,9 MD[0..63] 0.1uF

R15

E12
P15

E14

R16
N16

P16
F15

F14
T13

L16
AD[31..0] 11,20,21

G6
R7
R6
F6

F5
U13B

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

VCC_CPU
VCC_CPU
VCC_CPU
VCC_CPU

VCC
VCC

VCC5REF

VCCPSUS
VCCPSUS

VCCSUS
MD0 H17 A15 AD0
J16 MD0 AD0 A14
MD1 MD1 AD1 AD1
4 MD2 J17 B13 AD2 4
L17 MD2 AD2 A13
MD3 MD3 AD3 AD3
MD4 H18 C12 AD4
H19 MD4 AD4 B12
MD5 MD5 AD5 AD5
MD6 L20 A12 AD6
K19 MD6 AD6 C11
MD7 MD7 AD7 AD7
MD8 F18 A11 AD8
D20 MD8 AD8 C10 +3_3V +5V
MD9 MD9 AD9 AD9
MD10 C19 B10 AD10
MD11
MD12
R20
B18
B16
MD10
MD11
MD12
MTXC AD10
AD11
AD12
A10
C9
B9
AD11
AD12 1
D3
3
R73

MD13 MD13 AD13 AD13 1K

MD14 B15 A9 AD14
E13 MD14 AD14 C8 2 + C167
MD15 MD15 AD15 AD15
MD16 H16 C7 AD16
H20 MD16 AD16 B7 1uF
MD17 MD17 AD17 AD17 BAT54C
MD18 G18 A7 AD18
F20 MD18 AD18 C6
MD19 MD19 AD19 AD19
MD20 M19 B6 AD20
MD20 AD20 5VREF
MD21
MD22
MD23
N19
M20
J20
MD21
MD22
PART 2 OF 2 AD21
AD22
A6
C5
B5
AD21
AD22
AD23
5VREF 12

MD23 AD23
MD24
MD25
MD26
E19
E17
D18
MD24
MD25
PCI,DRAM,CACHE AD24
AD25
D6
C4
B4
AD24
AD25
AD26
A19 MD26 AD26 A4
MD27 MD27 AD27 AD27
MD28 C17 B3 AD28
A17 MD28 AD28 A3
MD29 MD29 AD29 AD29
MD30 D16 B2 AD30
B14 MD30 AD30 A2
MD31 MD31 AD31 AD31 MRAS#[3..0] 8,9
MD32 G17
3 F17 MD32 Y20 3
MD33 MRAS#0
K17 MD33 RAS#0 P18
MD34 MRAS#1
G16 MD34 RAS#1 R17
MD35 MRAS#2 MRAS#R[5..4] 8,9
G19 MD35 RAS#2 N17
MD36 MRAS#3 MCAS#[7..0] 8,9
L18 MD36 RAS#3 V19 RP34
MD37 MRAS#R4
L19 MD37 RAS#4 M16 5 4
MD38 MRAS#R5 MCAS#5
K18 MD38 RAS#5 6 3
MD39 MD39 MCAS#0
MD40 F19 7 2 MCAS#2
E18 MD40 U18 8 1
MD41 MCAS0#R MCAS#1
C20 MD41 CAS#0 W20
MD42 MCAS1#R
A20 MD42 CAS#1 V20
MD43 MCAS2#R 10
MD43 CAS#2 RP29
MD44 D17
MD44 CAS#3
T17 MCAS3#R
MD45 C16
MD45 CAS#4
T19 MCAS4#R 5 4 MCAS#6
MD46 D15
MD46 CAS#5
U19 MCAS5#R 6 3 MCAS#3
MD47 C14
MD47 CAS#6
P17 MCAS6#R 7 2 MCAS#4
MD48 F16
MD48 CAS#7
T18 MCAS7#R 8 1 MCAS#7
MD49 E16
MD49 10 MAA0 8
MD50 G20
MD50 MAA1 8
MD51 N20 V15 MAR0 8 RP71-1 1 MAA0
MD51 MA0 MA[11..2] 8,9
MD52 J18 V16 MAR1 5 RP69-4 4 10 MAA1
M17 MD52 MA1 Y17 6 RP71-3 3
MD53 MD53 MA2
MAR2 10 MA2
MD54 K20 T14 MAR3 2 R107 1 10 MA3
J19 MD54 MA3 U15 2 R113 1
MD55 MD55 MA4
MAR4 10 MA4
MD56 E20 Y16 MAR5 7 RP71-2 2 10 MA5
D19 MD56 MA5 W18 7 RP69-22
MD57 MD57 MA6
MAR6 10 MA6
MD58 B20 Y18 MAR7 5 RP71-4 4 10 MA7
B19 MD58 MA7 W19 6 RP69-3 3
MD59 MD59 MA8
MAR8 10 MA8
MD60 A18 U17 MAR9 5 RP72-4 4 10 MA9
B17 MD60 MA9 U16 6 RP72-3 3 MA10
MD61 MAR10 10
C18 MD61 MA10 Y19 8 RP69-11 MA11
MD62 MAR11 10
C15 MD62 MA11 10
2
MD63 MD63 2
U20 MABR0 7 RP72-22
CKE MAB0 9
W16 MABR1 8 RP72-11
CKEB 10 MAB1 9
11,20,21 C/BE0# C/BE0# B11 V17
C/BE#0 KRQAK 10 KRQAK 6
11,20,21 C/BE1# C/BE1# B8 N18 MSRASA#R 1 R159 2 MSRASA# 8
A8 C/BE#1 SRASA# P19 10 1 R157 2
11,20,21 C/BE2# C/BE2# MSCASA#R MSCASA# 8
C/BE#2 SCASA#
11,20,21 C/BE3# C/BE3# A5 P20 MSRASB#R 1 R158 2 10
MSRASB# 9
C/BE#3 SRASB# M18 10 1 R156 2
MSCASB#R MSCASB# 9
E6 SCASB# 10
11,20,21,25 FRAME# FRAME#
E9 W12
11,20,21,25 DEVSEL# DEVSEL# CADV# CADV# 6
E7 U12
11,20,21,25 IRDY# IRDY# CADS# CADS# 6
11,20,21,25 TRDY# E8 W13
TRDY# CCS# CCS# 6
E11 V12
11,20,21,25 STOP# STOP# COE# COE# 6
E5 V13
20,21,25 PLOCK# LOCK# GWE# CGWE# 6
Y12
BWE# CBWE# 6
11,20,25 PREQ0# D7 Y13
REQ#0 TWE# CTWE# 6
11,20,25 PREQ1# D9 R18 MWEA#R 1 R48 2
REQ#1 MWEA# 10 MWEA# 8
D11 V18 MWEB#R 1 R47 2
11,21,25 PREQ2# REQ#2 MWEB# 10 MWEB# 9 CTAG[7..0] 6
D13
+3_3V 11,21,25 PREQ3# REQ#3 U14
TIO0 CTAG0
20,25 PGNT0# D8 Y14 CTAG1
D10 GNT#0 TIO1 V14
20,25 PGNT1# GNT#1 TIO2 CTAG2
21,25 PGNT2# D12 T12 CTAG3
D14 GNT#2 TIO3 W15
21,25 PGNT3# GNT#3 TIO4 CTAG4
R75 Y15 CTAG5
D4 TIO5 U13
1K 11,25 PHOLD# PHOLD# GND: E15,J9,J10,J11,J12,K9,K10,K11,K12, TIO6 CTAG6
D5 W14 CTAG7
11,25 PHLDA# PHOLDA# TIO7
A16 T20
11,20,21,25 PAR PAR L9,L10,L11,L12,M9,M10,M11,M12,T6,T16 SUSCLK SUSCLK 12
C13 K16
11,20,21 CLKRUN# CLKRUN# HCLKIN HCLKMTXC 3 +3_3V
R19
SUS_STAT# SUSTAT1# 12
1
E10 1
PCLKIN W17 PCLKMTXC 3 R65
TESTIN#
TEST# T15
RST# PCIRST# 6,11,20,21 10K

MTXC
This drawing contains information
which has not been verified for Intel Corporation
manufacturing an end user product Title
Intel is not responsible for the TX DESKTOP MTXC MICRO CONTROLLER
misuse of this information. Size Document Number Rev
2.1
Date: Thursday, December 19, 1996 Sheet 5 of 29
A B C D E
 1 2 3 4 5 6 7 8

NOTE: PIN 16, 38, 39, 42, 43 & 66 are no

connects for PB SRAM
2,4 HD[63..0]

2,4 HA[31..3]

2,4 HBE#[7..0]

5 CCS#
A HA18 A

2
5 COE#
R112
5 CADV#
0
2 HADSC#

1
5 CADS#

5 CBWE# STUFF FOR 512K

5 CGWE#

U17 U16
HA3 37 52 HD32 HA3 37 52 HD0
HA4 36 A0 DQ1 53 HD33 HA4 36 A0 DQ1 53 HD1
HA5 35 A1 DQ2 56 HD34 HA5 35 A1 DQ2 56 HD2
HA6 34 A2 DQ3 57 HD35 HA6 34 A2 DQ3 57 HD3
A3 DQ4 A3 DQ4
HA7 33 58 HD36 HA7 33 58 HD4
HA8 32 A4 DQ5 59 HD37 HA8 32 A4 DQ5 59 HD5
HA9 100 A5 DQ6 62 HD38 HA9 100 A5 DQ6 62 HD6
HA10 99 A6 DQ7 63 HD39 HA10 99 A6 DQ7 63 HD7
HA11 82 A7 DQ8 68 HD40 HA11 82 A7 DQ8 68 HD8
A8 DQ9 A8 DQ9
HA12 81 69 HD41 HA12 81 69 HD9
HA13 44 A9 DQ10 72 HD42 HA13 44 A9 DQ10 72 HD10
HA14 45 A10 DQ11 73 HD43 HA14 45 A10 DQ11 73 HD11
HA15 46 A11 DQ12 74 HD44 HA15 46 A11 DQ12 74 HD12
HA16 47 A12 DQ13 75 HD45 HA16 47 A12 DQ13 75 HD13
A13 DQ14 A13 DQ14
HA17 48 78 HD46 HA17 48 78 HD14
49 A14 DQ15 79 HD47 49 A14 DQ15 79 HD15
XA18 XA18
A15 DQ16 2 HD48 A15 DQ16 2 HD16
B DQ17 DQ17 B
HBE#4 93 3 HD49 HBE#0 93 3 HD17
94 BWE1# DQ18 6 HD50 94 BWE1# DQ18 6 HD18
HBE#5 HBE#1
BWE2# DQ19 BWE2# DQ19
HBE#6 95 7 HD51 HBE#2 95 7 HD19
96 BWE3# DQ20 8 HD52 96 BWE3# DQ20 8 HD20
HBE#7 HBE#3
BWE4# DQ21 9 HD53 BWE4# DQ21 9 HD21
DQ22 12 HD54 DQ22 12 HD22
89 DQ23 13 HD55 89 DQ23 13 HD23
3 HCLKSRAM1 HCLKSRAM1
CLK DQ24 CLK DQ24
18 HD56 18 HD24
+3_3V DQ25 19 HD57 DQ25 19 HD25
98 DQ26 22 HD58 98 DQ26 22 HD26
R82 97 CE# DQ27 23 HD59 97 CE# DQ27 23 HD27
CRPU1
86 CE2 DQ28 24 HD60 86 CE2 DQ28 24 HD28
10k OE# DQ29 OE# DQ29
83 25 HD61 83 25 HD29
84 ADV# DQ30 28 HD62 84 ADV# DQ30 28 HD30
85 ADSP# DQ31 29 HD63 85 ADSP# DQ31 29 HD31
ADSC# DQ32 ADSC# DQ32

87 16 VDD1A 87 16 VDD1B
BWE# VDD1 66 BWE# VDD1 66
VDD2A VDD2B
88 VDD2 88 VDD2
GWE# 51 GWE# 51
38 NC 80 38 NC 80
PCIRST#D PCIRST#C
39 NC NC 1 +3_3V 39 NC NC 1
HW/R#D HW/R#C
LNF1D 42 NC NC 30 42 NC NC 30
RNF1C
NC NC NC NC
92 14 CRPU2 2 RP67-27 92 14 CRPU2
31 CE3# FT- 43 31 CE3# FT- 43 RNF2C
LNF2D 10K
LBO# NC 64 LBO# NC 64 CZZ
ZZ CZZ 12 ZZ
1 RP67-18
C 10K C

CBURST_SEQ2 **Optional
CRPD3 +5V
PBSRAM 64KX32 CTAG[7:0] 5 PBSRAM 64KX32
DRAM CACHE
CPUVIO
VDD1B 1 R92 2
U12

1
HA13 10 11 CTAG0 0
HA14 9 A0 DQ1 12 R97
CTAG1
HA15 8 A1 DQ2 13 VDD2B 1 R94 2
CTAG2 220
1 R56 2 HA28 HA17 7 A2 DQ3 15 CTAG3 0
HA7 6 A3 DQ4 16
4.7K CTAG4
A4 DQ5
HA5 5 17 CTAG5

2
R57 A5 DQ6
1 2 HA29 HA12 4 18 CTAG6 C207 C200
HA10 3 A6 DQ7 19 C204 C209
4.7K CTAG7
HA9 25 A7 DQ8
0.01uF 0.01uF 3.3uF 1uF
1 R54 2 HA30 HA8 24 A8 **Optional +5V

1
A9
4.7K HA16 21
A10 DRAM CACHE
HA6 23
1 R60 2 HA31 HA11 2 A11 1 R93 2
VDD1A
HA18 1 R43 2 26 A12 1 R80 2 HW/R#D
4.7K CA18 0
1 A13 2,4 HW/R#
CACHE SIZE INSTALL 0 A14 R95 0
VDD2A 1 2
2 R87 1 HW/R#C
0
27
0 R64 R60 5 CTWE# WE# 0 +3_3V

2
20 C205 C208
CE# C201 C202
0.01uF R78
R60 R56 2 R52 1 HA30 22 0.01uF 3.3uF 1uF RNF2C 1 R89 2 LNF2D 2 1
256K OE#
1

1
4.7K 1K 10K
R57 R52 R59 1
SRAM32KX8
+3_3V
2 HA31
D
R59 R54 D
1

4.7K R86
*NOTE: 1 2 PCIRST#D
512K R53 R55 R64
5,11,20,21 PCIRST#
0
R43 is for 512K
R43 Cache only.
10K
2 R85 1 PCIRST#C
CPUVIO
This drawing contains information 0
2

which has not been verified for 2 R91 1 1 R79 2 LNF1D Intel Corporation
5 KRQAK
manufacturing an end user product 0 Title
10K
Intel is not responsible for the 2 R88 1 RNF1C TX DESKTOP CACHE 1
misuse of this information. Size Document Number Rev
0
2.1

Date: Thursday, December 19, 1996 Sheet 6 of 29

1 2 3 4 5 6 7 8
 A B C D E

4 4

3 3

THIS PAGE INTENTIONALY LEFT BLANK

2 2

1 1

Intel Corporation
Title
CACHE 2
Size Document Number Rev
2.1
Date: Thursday, December 19, 1996 Sheet 7 of 29
A B C D E
 A B C D E

5,9 MD[63..0]
+3_3V

4 4

102
110
124

146

133
143
157
168
18
26
40
41
90

62

49
59
73
84
6
MD0 2 55 MD16

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

NC
NC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
MD1 DQ0 DQ16
3
DQ1 DQ17
56 MD17
MD2 4 57 MD18
DQ2 DQ18
MD3 5
DQ3 DQ19
58 MD19
MD4 7 60 MD20
DQ4 DQ20
MD5 8
DQ5 DQ21
65 MD21
MD6 9 66 MD22
MD7 10 DQ6 DQ22 67 MD23
DQ7 DQ23
MD8 11 69 MD32
DQ8 DQ24
MD9 13 70 MD33
MD10 14 DQ9 DQ25 71 MD34
MD11 15 DQ10 DQ26 72 MD35
DQ11 DQ27
MD12 16 74 MD36
DQ12 DQ28
MD13 17
DQ13 DQ29
75 MD37
MD14 19
DQ14 DQ30
76 MD38
MD15 20 77 MD39
DQ15 DQ31
MD40 86 139 MD56
87 DQ32 DQ48 140
MD41 MD57
88 DQ33 DQ49 141
MD42 MD58
89 DQ34 DQ50 142
MD43 MD59
91 DQ35 DQ51 144
MD44 MD60
92 DQ36 DQ52 149
MD45 MD61
93 DQ37 DQ53 150
MD46 MD62
94 DQ38 DQ54 151
MD47 MD63
3 DQ39 DQ55 3
MD48 95 153 MD24
97 DQ40 DQ56 154
MD49 MD25
98 DQ41 DQ57 155
MD50 MD26
99 DQ42 DQ58 156
MD51 MD27
100 DQ43 DQ59 158
MD52 MD28
DQ44 DQ60
MD53
MD54
MD55
101
103
104
DQ45
DQ46
DQ47
DQ61
DQ62
DQ63
159
160
161
MD29
MD30
MD31 DIMM 0 (BANK 0)
5 MAA0 33 79 NC: 62,146
MAA0 HCLKDIMM1 3
5 MAA1 117 A0 CK2 163
MAA1 HCLKDIMM0 3
5,9 MA[11..2] 34 A1 CK3 80 +3_3V: 6,18,26,40,41,49,59,73
MA2
118 A2 NC 164
MA3
35 A3 NC 81 84,90,102,110,124,133
MA4
119 A4 NC 61
MA5
36 A5 NC 134 143,157,168
MA6
120 A6 NC 135
MA7
37 A7 NC 136 GND: 1,12,23,31,32,43,44,54,64
MA8 MPAR7A +3_3V
121 A8 NC 137
MA9 MPAR3A
38 A9 NC 147 68,78,85,96,107,116,127,138
MA10
5,9 MRAS#R[5..4] 122 A10 NC 63
MA11
2 R62 1 39 BA0 CKE1 21 148,152,162
MRAS#R4 MRAS4A# MPAR0A
10 2 R67 1 123 BA1 NC 50
MRAS#R5 MRAS5A#
126 A11 NC 51
10
A12 NC 52
NC MPAR2A
22 53
MPAR1A NC NC MPAR4A
24 145
25 NC RFU
105 NC 165
MPAR5A 106 NC SA0 166
2 MPAR6A 108 NC SA1 167 2
109 NC SA2
5,9 MCAS#[7..0] NC 82
SDA SMBDATA 3,9,12
MCAS#0 28 83
DQMB0 SCL SMBCLK 3,9,12 MRAS#[3..0] 5,9
MCAS#1 29
46 DQMB1 30
MCAS#2 MRAS#0
47 DQMB2 /S0 114
MCAS#4 MRAS#1
112 DQMB3 /S1 45
MCAS#5 U5
113 DQMB4 /S2 129
MCAS#6
130 DQMB5 /S3 27
MCAS#7 MWEA# +3_3V
131 DQMB6 DIMM REV A /WE0 111
MCAS#3 MSCASA# 5
DQMB7 /CAS 115
/RAS MSRASA# 5
48 128
5 MWEA# DU CKE0 132 MPDED0#
42 A13
3 HCLKDIMM3 CK0 125
CK1 HCLKDIMM2 3
R50
44 100
DU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

31
DU
1
12
23
32
43
54
64
68
78
85
96
107
116
127
138
148
152
162

1 1

This drawing contains information

which has not been verified for Intel Corporation
manufacturing an end user product Title
Intel is not responsible for the TX DESKTOP DIMM 0
misuse of this information. Size Document Number Rev
2.1
Date: Thursday, December 19, 1996 Sheet 8 of 29
A B C D E
 A B C D E

5,8 MD[63..0]
+3_3V

4 4

102
110
124

146

133
143
157
168
18
26
40
41
90

62

49
59
73
84
6
MD0 2 55 MD16

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

NC
NC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
3 DQ0 DQ16 56
MD1 DQ1 DQ17 MD17
MD2 4 57 MD18
5 DQ2 DQ18 58
MD3 DQ3 DQ19 MD19
MD4 7 60 MD20
8 DQ4 DQ20 65
MD5 DQ5 DQ21 MD21
MD6 9 66 MD22
10 DQ6 DQ22 67
MD7 DQ7 DQ23 MD23
MD8 11 69 MD32
13 DQ8 DQ24 70
MD9 DQ9 DQ25
MD33
MD10 14 71 MD34
15 DQ10 DQ26 72
MD11 DQ11 DQ27
MD35

DIMM 1
MD12 16 74 MD36
17 DQ12 DQ28 75
MD13 DQ13 DQ29
MD37
MD14 19 76 MD38
20 DQ14 DQ30 77 (BANK 1)
MD15 DQ15 DQ31
MD39

MD40 86 139 MD56

87 DQ32 DQ48 140 NC: 62,146
MD41 MD57
88 DQ33 DQ49 141
MD42 MD58
89 DQ34 DQ50 142 +3_3V: 6,18,26,40,41,49,59,73
MD43 MD59
91 DQ35 DQ51 144
MD44 MD60
92 DQ36 DQ52 149 84,90,102,110,124,133
MD45 MD61
93 DQ37 DQ53 150
MD46 MD62
94 DQ38 DQ54 151 143,157,168
MD47 MD63
3 DQ39 DQ55 3
MD48 95 153 MD24 GND: 1,12,23,31,32,43,44,54,64
97 DQ40 DQ56 154
MD49 MD25
98 DQ41 DQ57 155 68,78,85,96,107,116,127,138
MD50 MD26
99 DQ42 DQ58 156
MD51 MD27
100 DQ43 DQ59 158 148,152,162
MD52 MD28
101 DQ44 DQ60 159
MD53 MD29
103 DQ45 DQ61 160
MD54 MD30
104 DQ46 DQ62 161
MD55 MD31
DQ47 DQ63
5 MAB0 33 79
MAB0 HCLKDIMM6 3
5 MAB1 117 A0 CK2 163
5,8 MA[11..2] MAB1 HCLKDIMM7 3
34 A1 CK3 80
MA2
118 A2 NC 164
MA3
35 A3 NC 81
MA4
119 A4 NC 61
MA5
36 A5 NC 134
MA6
120 A6 NC 135
MA7
37 A7 NC 136 +3_3V
MA8 MPAR7B
121 A8 NC 137
5,8 MRAS#R[5..4] MA9 MPAR3B
38 A9 NC 147
MA10
122 A10 NC 63
MA11
2 R63 1 39 BA0 CKE1 21
MRAS#R4 MRAS4B# MPAR0B
10 2 R66 1 123 BA1 NC 50
MRAS#R5 MRAS5B#
126 A11 NC 51
10 A12 NC 52
NC MPAR2B
22 53
MPAR1B NC NC MPAR4B
24 145
25 NC RFU +3_3V
105 NC 165
MPAR5B 106 NC SA0 166
2 MPAR6B 108 NC SA1 167 2
109 NC SA2
5,8 MCAS#[7..0] NC 82 SMBDATA 3,8,12
SDA MRAS#[3..0] 5,8
MCAS#0 28 83
DQMB0 SCL SMBCLK 3,8,12
MCAS#1 29
46 DQMB1 30
MCAS#2 MRAS#2
47 DQMB2 /S0 114
MCAS#4 MRAS#3
112 DQMB3 /S1 45
MCAS#5 U6
113 DQMB4 /S2 129
MCAS#6
DQMB5 /S3
MCAS#7 130 27 MWEB#
131 DQMB6 DIMM REV A /WE0 111 +3_3V
MCAS#3 MSCASB# 5
DQMB7 /CAS 115
/RAS MSRASB# 5
48 128
5 MWEB# DU CKE0 132 MPDED1#
42 A13
3 HCLKDIMM4 CK0 125
CK1 HCLKDIMM5 3
44
DU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
31 GND
DU
1
12
23
32
43
54
64
68
78
85
96
107
116
127
138
148
152
162

R51
100

1 1

This drawing contains information Intel Corporation

which has not been verified for Title
manufacturing an end user product TX DESKTOP DIMM 1
Intel is not responsible for h
te
Size Document Number Rev
misuse of this information.
2.1
Date: Thursday, December 19, 1996 Sheet 9 of 29
A B C D E
 A B C D E

J11
MODE POS.
NORMAL 2-3
RECOVERY 1-2
Note: The X denotes a don’t care.
MODE J7 J6
4 4
J1 Program Device 1-2 1-2
SA16/17 3
+5V Plug -N- Play 2-3 1-2
U2C 2
14 Non-Plug-N-Play X 2-3
5 6 SA16/17# 1
7 Not Used 2-3 2-3
+5V
74HCT14
+12V +5V
INSTALL
J7
SA16 IF +12V
Install for BX R3
1M FLASH 1 R2 2 SA16 FL5VPU R9
8.2K

3
0 8.2K J6
1
INSTALL R1
1 2 SA17 FL_VPP 2
SA17 IF
0 C1
2M FLASH FL_PNPPU 3
C2 0.1uF
0.1uF

BIOSMSB
11,14,22,23,24,25 SA[19..0] Install for BC R4
3 0 3
U1
U3 2 13 XD0
40 25 3 A16 DQ0 14
XD0 SA15 XD1
1 A17 DQ0 26 29 A15 DQ1 15
SA16 XD1 SA14 XD2
2 A16 DQ1 27 28 A14 DQ2 17
SA15 XD2 SA13 XD3
3 A15 DQ2 28 4 A13 DQ3 18
SA14 XD3 SA12 XD4
4 A14 DQ3 32 25 A12 DQ4 19
SA13 XD4 SA11 XD5
5 A13 DQ4 33 23 A11 DQ5 20
SA12 XD5 SA10 XD6
6 A12 DQ5 34 26 A10 DQ6 21
SA11 XD6 SA9 XD7
36 A11 DQ6 35 27 A9 DQ7
SA10 XD7 SA8
7 A10 DQ7 5 A8 +5V
SA9 +5V SA7
8 A9 12 6 A7
SA8 SA6
14 A8 DU 30 7 A6 32
SA7 SA5
15 A7 VCC 31 8 A5 VCC 16
SA6 SA4
16 A6 VCC 23 9 A4 GND
SA5 SA3
17 A5 GND 39 10 A3
SA4 SA2
18 A4 GND 13 11 A2
SA3 SA1
19 A3 NC 29 +5V 12 A1
SA2 SA0
20 A2 NC 37 A0
SA1
21 A1 NC 38
SA0
A0 NC C19 31
9 24 WE#
WE# 0.1uF OE#
24 22
22 OE# 30 CE# 1
10 CE# 11 RP# VPP
PWD# VPP
P28F001BX-T
E28F002BC-T
2 2

11,22,23,24,25 MEMW#
11,22,23,24,25 MEMR#
FL2MPU
OPTIONAL 2MB FLASH
12 ROMCS#

14 XD[7..0]

1 1

Intel Corporation
Title
TX DESKTOP FLASH BIOS

Size Document Number Rev

2.1

Date: Thursday, December 19, 1996 Sheet 10 of 29

A B C D E
 A B C D E

5,20,21 AD[31..0]

DDS[15..0] 13

U15A
AD0 B10
AD0 DDS0
E15 DDS0
AD1 A10
AD1 DDS1
B15 DDS1
AD2 D9
AD2 DDS2
D14 DDS2
AD3 C9
AD3 DDS3
C14 DDS3
AD4 B9
AD4 DDS4
A14 DDS4
AD5 A9
AD5 DDS5
C13 DDS5
4 AD6 D8
AD6 DDS6
A13 DDS6 4
AD7 E8 C12 DDS7
AD8 B8 AD7
AD8
IDE DDS7
DDS8
D12 DDS8
AD9 A8 B13 DDS9
AD10 D7 AD9 SIGNALS DDS9 D13 DDS10
AD10 DDS10
AD11 C7
AD11 DDS11
B14 DDS11
AD12 B7
AD12 DDS12
E14 DDS12
AD13 A7
AD13 DDS13
A15 DDS13
AD14 D6
AD14 DDS14
C15 DDS14
AD15 E6
AD15 DDS15
D15 DDS15
AD16 E4
AD16
AD17 C4
AD17 CS3S#
C18
IDECS13# 13
AD18 AD18 B4
AD18 CS3P#
H16
IDECS03# 13
AD19 A4
AD19 CS1S#
B18
IDECS11# 13
AD20 D3
AD20 CS1P#
H17
IDECS01# 13
AD21 E3
AD21 SA[19..0] 10,14,22,23,24,25
AD22 C3
AD22
AD23 B3
AD23 SA0
U11 SA0
AD24 E2
AD24 SA1
T11 SA1
AD25 C2
AD25 SA2
W11 SA2
AD26 B2
AD26 SA3
Y11 SA3
AD27 A2
AD27 SA4
T10 SA4
AD28 D1
AD28
PCI BUS SA5
W10 SA5
AD29 E1 U9 SA6
AD30 C1 AD29 INTERFACE SA6 V9 SA7
AD30 SA7
AD31 B1
AD31 SA8
Y9 SA8
T8 SA9
SA9 W8
SA10 SA10
C8 U7 SA11
5,20,21 C/BE0# C/BE#0 SA11
C6 V7 SA12
5,20,21 C/BE1# C/BE#1 SA12
R72 220 D4 Y7 SA13
5,20,21 C/BE2# C/BE#2 SA13
D2 V6 SA14
3 5,20,21 C/BE3# C/BE#3 SA14 3
Y6 SA15
5,20,21,25 DEVSEL#
5,20,21 CLKRUN#
C10
E5
A5
CLOCKRUN#
DEVSEL#
PIIX4 SA15
SA16
SA17
T5
W5
U4
SA16
SA17
5,20,21,25 FRAME# FRAME# SA18 SA18
PXIDSEL A3 V4 SA19
B5 IDSEL SA19
5,20,21,25 IRDY# IRDY# SD[15..0] 14,22,23,24,25
5,20,21,25 PAR B6
A1 PAR V3
5,6,20,21 PCIRST# PCIRST# SD0 SD0
5,25 PHOLD# B12 W3 SD1
PHOLD# SD1
5,25 PHLDA#
A12
A6 PHOLDA# ISA/EIO SD2
U2
T2
SD2
SD3
20,21,25 SERR#
5,20,21,25 STOP#
D5 SERR#
STOP#
SIGNALS SD3
SD4
W2 SD4
5,20,21,25 TRDY# C5 Y2 SD5
TRDY# SD5 T1
SD6 SD6
E10 V1 SD7
5,20,25 PREQ0# REQ0# SD7
A11 W16 SD8
5,20,25 PREQ1# REQ1# SD8
B11 T16 SD9
5,21,25 PREQ2# REQ2# SD9
C11 Y17 SD10
5,21,25 PREQ3# REQ3# SD10 V17 SD11
C17 SD11 Y18
13 DAS0 DAS0 SD12 SD12
B17 W18 SD13
13 DAS1 DAS1 SD13
13 DAS2 A18 Y19 SD14
G19 DAS2 SD14 W19
13 IDEDACK0# PDDACK# SD15 SD15 LA[23..17] 22,23,24,25
A17
13 IDEDACK1# SDDACK#
F18
13 IDEDRQ0 A16 PDREQ# Y15
13 IDEDRQ1 SDREQ# GPO1/LA17 LA17
F17 T14 LA18
13 IDEIOR0# PDIOR# GPO2/LA18
F16 W14 LA19
13 IDEIOW0# PDIOW# GPO3/LA19
G20 U13 LA20
13 IDEIORDY0 PIORDY GPO4/LA20
C16 V13 LA21
13 IDEIOR1# SDIOR# GPO5/LA21
B16 Y13 LA22
13 IDEIOW1# D16 SDIOW# GPO6/LA22 T12
13 IDEIORDY1 SIORDY GPO7/LA23 LA23
2 G16 2
13 DAP0 G18 DAP0 Y12
13 DAP1 DAP1 MEMCS16# MEMCS16# 22,23,24,25
13 DAP2
G17
DAP2
IDE MEMR#
V15
MEMR# 10,22,23,24,25
U15
13 DDP[15..0] SIGNALS MEMW# W4
MEMW# 10,22,23,24,25
SMEMR# 22,23,24,25
SMEMR#
DDP0 F20
DDP0
DDP1 E18
DDP1 SMEMW#
U3
SMEMW# 22,23,24,25 R76
DDP2 E20
DDP2 SYSCLK
T7 SYSCLKR SYSCLK 22,23,24
DDP3 D18
DDP3 GPO0/BALE
U10
BALE 22,23,24,25 33
DDP4 D20
DDP4 GPI0/IOCHK#
Y1
IOCHK# 22,23,24,25
DDP5 C20
DDP5
DDP6 B20
DDP6 REFRESH#
W7
REFRESH# 22,23,24,25
DDP7 A20
DDP7 IOCS16#
V12
IOCS16# 22,23,24,25
DDP8 A19
DDP8 ZEROWS#
Y3
ZEROWS# 22,23,24,25
DDP9 B19
DDP9
DDP10 C19
DDP10 SBHE#
W12 SBHE# 22,23,24,25
DDP11 D19
DDP11 RSTDRV
W1
RSTISA 14,22,23,24
DDP12 D17
DDP12 IOR#
Y5
IOR# 14,22,23,24,25
DDP13 E19
DDP13 IOW#
T4
IOW# 14,22,23,24,25
DDP14 E17
DDP14 IOCHRDY
T3
IOCHRDY 14,22,23,24,25
DDP15 F19
DDP15 AEN
Y4
AEN 14,22,23,24

PIIX4

+5V
U2A
14
1 2
IDERST# 13
7

1 74HCT14 1

This drawing contains information Intel Corporation

which has not been verified for Title
manufacturing an end user product TX DESKTOP PIIX4 (SOUTHBRIDGE)
Intel is not responsible for the Size Document Number Rev
misuse of this information.
2.1
Date: Thursday, December 19, 1996 Sheet 11 of 29
A B C D E
 A B C D E

+3_3V SB3V

E11

R15

E12
E16

P15

R16
N16
F15

F14
G6
R6

E9

R7

K5
F6

F5

T6
U15B
4 U14 F1 4

VCC
VCC
VCC
VCC
VCC

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

VCCSUS
VCCSUS
VCCUSB
14,22,23,24 DACK0# DACK0# USBP1+ USBP1+R 17
14,22,23,24 DACK1# W6 H2
DACK1# USBP1- USBP1-R 17
14,22,23,24 DACK2# Y10 G2
DACK2# USBP0+ USBP0+R 17
14,22,23,24 DACK3# V5 H3
USBP0-R 17
22,23,24 DACK5# T15 DACK3#
DACK5#
USB USBP0-
OC0
J1
USBOC0# 17
22,23,24 DACK6# V16 J2
DACK6# OC1 USBOC1# 17
22,23,24 DACK7# W17 STB5V
DACK7#
14,22,23,24,25 DRQ0 W15 V20 EXTSMI
U6 DREQ0 EXTSMI# W20 U20A
14,22,23,24,25 DRQ1 DREQ1 SUSA#
14,22,23,24,25 DRQ2 V2 V19 14
U5 DREQ2 GPO15/SUSB# U18 1 2
14,22,23,24,25 DRQ3 PS-ON PS_ON# 19
Y16 DREQ3 GPO16/SUSC# 7
22,23,24,25 DRQ5 DREQ5
U16 R1
+3_3V 22,23,24,25 DRQ6 U17 DREQ6 GPO17/CPU_STP# R2 C238
22,23,24,25 DRQ7 DREQ7 GPO18/PCI_STP# 74HCT14
K16 0.01UF
GPO19/ZZ CZZ 6
1 RP42-1 8 PIIXREQA# M1 T17
RP42-2 REQA#/GPI2 GPO20/SUS_STAT1# SUSTAT1# 5
2 7 10K PIIXREQB# N2 T18
REQB#/GPI3 GPO21/SUS_STAT2#
10K 3 RP42-3 6 PIIXREQC# P3
REQC#/GPI4
POWER GPI8/HCT#
H19 PIIXTHRM#
10K U19 PIIXBATLO#
N1 MGMT. GPI9/BATLOW# M17
RSMRST# 19
P2 GNTA#/GPO9 RSMRST# U20
GNTB#/GPO10 PWRBT# PWRBT# 18
P4 P16 PIIXLID
GNTC#/GPO11 GPI10/LID T20
SMBDATA SMBDATA 3,8,9
V10 R19
14,22,23,24 T/C TC SMBCLK SMBCLK 3,8,9
J17 N17 PIIXAMBAL#
H18 APICACK#/GPO12 DMA/IRQ GPI11/SMBALERT# P18 PIIX_RI# +3_3V
APICCS#/GPO13 GPI12/RI#A PIIX_RI# 14
4 RP55-4 5 PIIXAPICRQ# K18
APICREQ#/GPI5 SIGNALS SB3V
10K

H20
3 J20 IRQ0/GPO14 2 RP62-27 R115 U22 3
14,25 IRQ1 IRQ1
14,22,23,24,25 IRQ3 T9 8.2K
IRQ3 8.2K
14,22,23,24,25 IRQ4 W9 7 3
U8 IRQ4 A0 OS
14,22,23,24,25 IRQ5 IRQ5
14,22,23,24,25 IRQ6 V8 6
Y8 IRQ6 A1
14,22,23,24,25 IRQ7 IRQ7
14,25 IRQ8 Y20 THPU 5
U1 IRQ8/GPI6 J16 A2
14,22,23,24,25 IRQ9 IRQ9 VREF 5VREF 5
U12 +3_3V +3_3V
14,22,23,24,25 IRQ10
14,22,23,24,25 IRQ11
14,22,23,24,25 IRQ12
W13
T13
IRQ10
IRQ11
IRQ12
PIIX4 C193
1
SDA
+3_3V V14 0.1UF 2 8
13,14,22,23,24,25 IRQ14 Y14 IRQ14 P19 5 RP66-4 4 SCL VCC
PIIX_GPI1
13,14,22,23,24,25 IRQ15 IRQ15 GPI1 L2 8.2K 5 RP70-4 4
PIIXGPI13
3 RP55-3 6 J19 GPI13 J3 6 RP68-3 3
PIIXSIRQ PIIXGPI14 8.2K LM75
R3 SERIRQ/GPI7 GPI14 L5 6 RP70-3 3
10K 20,21,25 PIRQ0# PIIXGPI15 8.2K
R4 PIRQA# GPI15 K3 7 RP70-2 2
20,21,25 PIRQ1# PIIXGPI16 8.2K
P5 PIRQB# GPI16 K4 8 RP70-1 1
PIIXGPI17 8.2K
20,21,25
20,21,25
PIRQ2#
PIRQ3#
G1 PIRQC#
PIRQD#
GPI17
GPI18
H1 PIIXGPI18 5 RP68-4 4 8.2K THERMAL DEVICES
RP68-2
K20
GPO/GPI/GPIO/SCAN GPI19
H4
H5
PIIXGPI19
PIIXGPI20
8.2K
2 RP66-2 7
7
8.2K
2
DO NOT STUFF
M19 SLP# GPI20 G3 8 RP68-1 1
2 HRESET PIIXGPI21 8.2K
K19 CPURST GPI21
2 HFERR# 8.2K
L17 FERR#
2 HIGNNE# IGNNE#
L18
SB3V 2 HINIT
2 HINTR
L19 INIT
INTR
CPU
P1
14 A20GATE
L20 A20GATE# INTERFACE
2 HNMI P20 NMI SB3V +3_3V
2 HSMI# J18 SMI#
2 HSTPCLK# STPCLK#
R77 14 KBRESET# N20 G4
2 RCIN# GPO0 FAN-ON 18 R81 2
M20 T19 SMBCLK
1K 2 HA20M# M18 A20M# GPO8 G5
19 PWROK PWROK GPO27 PIIXGPO27 8.2K
K17 F2
18 SPKR SPKR GPO28 PIIXGPO28
PIIXTEST# V18 F3 PIIXTHRM# 1 RP66-1 8
R17 TEST# GPO29 F4
PIIXCONF1
PIIXCONF2 R18 CONFIG1 SYSTEM/TEST GPO30 PIIXGPO30 8.2K
CONFIG2 4 RP62-4 5
EXTSMI
DO NOT STUFF 14 XOE# M4
8.2K
M3 XOE#/GPO23 2 RP58-2 7
14 XDIR# PIIX_RI#
M2 XDIR#/GPO22
10 ROMCS# BIOSCS# 8.2K
L1 J4
R83
K2 RTCALE/GPO25 X-BUS N/C N18 PIIXLID 3 RP58-3 6
K1 RTCCS#/GPO24 N/C N3
KBCCS#/GPO26 N/C 8.2K
1M M16
RTCX2 R20 N/C M5 PIIXAMBAL# 1 RP58-1 8
RTCX2 GND: N/C
2 1 RTCX1 N19 R5 8.2K
L16 RTCX1 D10,E7,E13,J9,J10,J11,J12,K9,K10,K11,K12, N/C
Y2 14,19 VBAT3V VBAT L9,L10,L11,L12,M9,M10,M11,M12 3 RP62-3 6
PIIXBATLO#
C196 32.768KHz C197 P17
5 SUSCLK SUSCLK 8.2K
L3 N4
3 CLK48M 48Mhz VSSUSB: MCCS#
22pF 22pF V11 PIIXCONF1 1 RP62-1 8
3 OSCPIIX4 OSC J5
D11 L4 8.2K
3 PCLKPIIX4 PCICLK PCS0#
PROG CHIP SEL. PCS1#
N5
PIIXPCS1
PIIXCONF2 4 RP58-4 5
PIIX4 8.2K
C256

0.1uF
1 1

Intel Corporation
This drawing contains information Title
which has not been verified for TX DESKTOP PIIX4 (SOUTH BRIDGE)
manufacturing an end user product
Size Document Number Rev
Intel is not responsible for h
te
2.1
misuse of this information.
Date: Thursday, December 19, 1996 Sheet 12 of 29
A B C D E
 A B C D E

IDE CONNECTORS
11 DDP[15..0]

PRIMARY IDE CONNECTOR

R154 IDERSTP#R
11 IDERST#
4
33 J21 4

1
3 RP57-36 1 2 7 RP57-22
DDP7 DDP7R DDP8R DDP8
1 RP61-18 33 3 4 33 5 RP57-4 4
R90 DDP6 DDP6R DDP9R DDP9
33 3 RP61-36 5 6 7 RP61-2 2
DDP5 DDP5R DDP10R 33 DDP10
5.6K 3 RP65-36 7 8 33 7 RP65-2 2
+5V DDP4 33 DDP4R DDP11R DDP11
33 1 RP65-18 9 10 5 RP61-4 4 33
DDP3 DDP3R DDP12R DDP12
2 RP60-27 11 12 8 RP60-1 1
33 DDP2R DDP13R 33

2
DDP2 13 14 DDP13
DDP1 33 4 RP65-45 DDP1R DDP14R 8 RP64-1 1 33 DDP14
2 RP64-2 7 15 16 5 RP60-4 4
+5V DDP0 33 DDP0R DDP15R 33 DDP15
R151 33 17 18 33
3 RP60-36 19 20
1K IDEDRQ0R
11 IDEDRQ0 1 RP59-1 8 33 21 22
11 IDEIOW0# IDEIOW0#R
2 RP59-27 23 24
11 IDEIOR0# 33 IDEIOR0#R
R141 R150 33 25 26 IDESELA
11 IDEIORDY0 IDEIORDY0R

1
4 RP59-4 5 27 28
10K 47 11 IDEDACK0# IDEDACK0#R
33 R147 IDEIRQ0R 29 30
IRQ14 R149
12,14,22,23,24,25 IRQ14 3 RP63-3 6 31 32
11 DAP1 47 DAP1R
33 3 RP59-3 6 33 34 8 RP63-1 1 470
11 DAP0 DAP0R DAP2R DAP2 11
4 RP63-4 5 33 35 36
11 IDECS01# IDECS01#R 33
37 38
33

2
18 HD_ACTA# 39 40
HEADER 20X2 IDECS03#R 7 RP63-2 2
IDECS03# 11
33

3 3

11 DDS[15..0]

SECONDARY IDE CONNECTOR

IDERST# R155 IDERSTS#R
33 J20
RP50-2
2

1 RP50-1 8 1 2 7 2
DDS7 DDS7R DDS8R DDS8
3 RP50-3 6 33 3 4 33 5 RP50-4 4
R84 DDS6 DDS6R DDS9R DDS9
33 2RP51-2 7 5 6 8RP51-1 1 33
5.6K DDS5 DDS5R DDS10R DDS10
4RP51-4 5 33 7 8 7RP52-2 2
+5V DDS4 DDS4R DDS11R 33 DDS11
33 4RP52-4 5 9 10 6 RP51-3 3 33
DDS3 DDS3R DDS12R DDS12
1RP52-1 8 11 12 7 RP53-2 2
33 DDS2R DDS13R 33
1

DDS2 13 14 DDS13
DDS1 33 3RP53-3 6 DDS1R DDS14R 5 RP53-4 4 33 DDS14
3RP52-3 6 33 15 16 33 8 RP53-11
+5V DDS0 DDS0R DDS15R DDS15
R153 33 17 18
2 33 2

1 RP57-1 8 19 20
1K 11 IDEDRQ1 IDEDRQ1R
1 RP54-1 8 33 21 22
11 IDEIOW1# IDEIOW1#R
33 2RP54-2 7 23 24
11 IDEIOR1# IDEIOR1#R
R140 R152 33 25 26 IDESELB
IDEIORDY1R

1
11 IDEIORDY1 3 RP54-3 6 27 28
10K 47 11 IDEDACK1# IDEDACK1#R
33 IDEIRQ1R 29 30
IRQ15 R96 R148
12,14,22,23,24,25 IRQ15 4 RP54-4 5 47 31 32
11 DAS1 DAS1R
33 1 RP56-1 8 33 34 7 RP56-2 2 470
11 DAS0 DAS0R DAS2R DAS2 11
3 RP56-3 6 35 36
33 IDECS11#R 33
11 IDECS11# 33 37 38

2
18 HD_ACTB# 39 40
HEADER 20X2 IDECS13#R 5 RP56-4 4
IDECS13# 11
33

1 1

Intel Corporation
This drawing contains information
Title
which has not been verified for
manufacturing an end user product TX DESKTOP IDE CONNECTORS
Intel is not responsible for the Size Document Number Rev
misuse of this information. 2.1

Date: Thursday, December 19, 1996 Sheet 13 of 29

A B C D E
 1 2 3 4 5 6 7 8

ULTRA IO

A A
+5V
Install only when RTC in UIO is used.

125
101

139
60
21
R42 U10
12,19 VBAT3V 121 37
0 UIOBAT
VBAT 14CLK01

VCC
VCC
VCC
VCC
VCC
UIOXTAL 1 122 38
124 XTAL1 14CLK02 39
UIOXTAL 2
22 XTAL2 14CLK03
3 OSCUIO 14CLOCKI
68 36
11,22,23,24,25 IOR# 69 IOR# 16CLK 35
C257 11,22,23,24,25 IOW# 70 IOW# 24CLK
Y1 11,22,23,24 AEN
2

2 1 0.1uF 80 AEN 14
11,22,23,24,25 SD[15..0] 11,22,23,24 RSTISA RSTDRV INDEX# INDEX# 16
R40 90 9
11,22,23,24,25 IOCHRDY IOCHRDY DIR# DIR# 16
1M 32.768KHz 10
72 STEP# 11 STEP# 16 Install for 935 only.
SD0 WDATA# 16
73 SD0 WDATA# 12
SD1 WGATE# 16
74 SD1 WGATE# 15 2 R16 1
SD2
1

SD2 TRK0# TRK0# 16

SD3 75 16
SD3 WPT# WPT# 16 1K
C78 C85 SD4 76 17 RDATA# 16
77 SD4 RDATA# 13 2 R17 1
22pF 22pF SD5 SIDE1# 16
78 SD5 SIDE1# 18
12,22,23,24,25 DRQ[7..0] SD6 DSKCHG# 16 1K
79 SD6 DSKCHG# 4
SD7
SD7 MTR0# 7 MOTEA# 16
89 MTR1# 6 MOTEB# 16
12,22,23,24 T/C TC DRVSEL0# DRVSA# 16 R18
5 2 1
DRVSEL1# DRVSB# 16 IRR3/MODE 18
DRQ0 82 2 0
84 DRQ0 DRVDEN0 3 REDWC# 16
OSCUIO DRQ1
86 DRQ1 DRVDEN1 20 DRATE0 16
DRQ2 MEDID0 Install for 935FR only.
88 DRQ2 MEDID0 19
DRQ3 MEDID1
DRQ3 MEDID1
81
12,22,23,24 DACK0# DACK0
C37 83 138 PD0R
22pF 12,22,23,24 DACK1# DACK1 PD0 PD0R 15
85 137 PD1R
12,22,23,24 DACK2# DACK2 PD1 PD1R 15
87 136 PD2R
12,22,23,24 DACK3# DACK3 PD2 PD2R 15
135 PD3R
PD3 PD3R 15
B 12,25 IRQ1 IRQ1 67 134 PD4R B
IRQ1 PD4 PD4R 15
+5V 12,22,23,24,25 IRQ3 IRQ3 66 133 PD5R
IRQ3 PD5 PD5R 15
12,22,23,24,25 IRQ4 IRQ4 65 132 PD6R
IRQ4 PD6 PD6R 15
12,22,23,24,25 IRQ5 IRQ5 64 131 PD7R
U19A IRQ5 PD7 PD7R 15
12,22,23,24,25 IRQ6 IRQ6 63
14 62 IRQ6 140
12,22,23,24,25 IRQ7 IRQ7 SLIN#R 15 INSTALL FOR 370 CONFIG.
R25 2 1 61 IRQ7 SLIN# 141
UIOIRQ8 UIOIRQ8B INIT#R 15
12,25 IRQ8 7 59 IRQ8/IRQ8# INIT# 143 2 R24 1
0 12,22,23,24,25 IRQ9 IRQ9 +5V
58 IRQ9 AFD# 144 AFD#R 15
12,22,23,24,25 IRQ10 IRQ10 10K
57 IRQ10 STB# 128 STB#R 15
12,22,23,24,25 IRQ11 IRQ11
Install only when RTC 7407
IRQ12 56 IRQ11 BUSY 129 BUSY 15
12,22,23,24,25 IRQ12 IRQ12 ACK# ACK# 15
in UIO is used. 12,13,22,23,24,25 IRQ14 IRQ14 55
IRQ14 PE
127
PE 15
INSTALL FOR 3F0 CONFIG.
IRQ15 54 126 2 R23 1
12,13,22,23,24,25 IRQ15 IRQ15 SLCT SLCT 15
10,11,22,23,24,25 SA[19..0] 142
ERR# ERR# 15 1K
SA0 41
42 SA0 145
SA1 RX0 16
43 SA1 RXD1 146
SA2 TX0 16
44 SA2 TXD1 148
SA3 RTS0# 16
45 SA3 RTS1# 149
SA4 CTS0# 16
46 SA4 CTS1# 150
SA5
47 SA5 DTR1# 147 DTR0# 16
SA6
48 SA6 DSR1# 152 DSR0# 16
SA7
49 SA7 DCD1# 151 DCD0# 16
SA8
50 SA8 RI1# RI0# 16
SA9
51 SA9 155 +5V
SA10 RX1 16
52 SA10 RXD2 156
SA11
53 SA11 TXD2 158 TX1 16 U19B
SA12
27 SA12/CS RTS2# 159 RTS1# 16 14
SA13
28 SA13/HDCS2# CTS2# 160 CTS1# 16 3 4 2 R123 1
SA14 PIIX_RI#R
+5V 29 SA14/HDCS3# DTR2# 157 DTR1# 16 7 PIIX_RI# 12
+5V SA15 0
SA15/IDE2_IRQ DSR2# 154 DSR1# 16
4 RP42-4 5 26 DCD2# 153 DCD1# 16
IDE1_IRQ 7407
23 IDE1_IRQ RI2# RI1# 16
10K IDE1_OE#
R160 24
10K 25 HDCS0# 96 IRTX 18
RP23 30 HDCS1# GP10/IRQIN 97
PWRLED1
5 4 31 IOROP# GP11/IRQIN 98
IOWOP# GP12/IRRX IRRX 18 R41
6 3 99
C
7 2 R14 34 GP13/IRTX 100 PWRLED# 18 C
UIOBUT# 0
8 1 1K 33 IDE_A0 GP14/RS 102 +5V
32 IDE_A1 GP15/WS 103 1 R166 2
IDE_A2 GP16/JOYRS Install for 935 only.
4.7K Install for 935FR only. 104
10K
92 GP17/JSWS 105
16 KBCLK# KCLK GP20/IDE2_OE KBRESET# 12
16 KBDAT# 91 106
94 KDAT GP21/EEDIN 107 KBLOCK# 18 R15
16 MSCLK# PWRLED1
93 MSCLK GP22/EDOUT 108
16 MSDAT# MSDAT GP23/EECLK 0
109
111 GP24/EEEN 110
XD0 Install for 935FR only.
112 RD0 GP25/8024_P21 A20GATE 12
XD1
113 RD1 +5V
XD2
114 RD2 2 R164 1
XD3 +5V: 21,60,101,125,139
115 RD3
XD4 10K
RD4
XD5 116
RD5
GND: 1,8,40,71,95,123,130
XD6 117
118 RD6
XD7
RD7
119
10 XD[7..0] 12 XOE# ROMCS#
120
12 XDIR# ROMOE#
FDC37C93X

D D

This drawing contains information

which has not been verified for Intel Corporation
manufacturing an end user product Title
Intel is not responsible for the TX DESKTOP ULTRA I/O
misuse of this information. Size Document Number Rev
2.1

Date: Thursday, December 19, 1996 Sheet 14 of 29

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

A A

14 PD0R PD0R 1 RP12-18 PD0

33
14 PD1R PD1R 2 RP12-27 PD1
33
14 PD2R PD2R 3 RP12-36 PD2
33
B PD3R 4 RP12-45 PD3 B
14 PD3R
33
14 PD4R PD4R 1 RP15-18 PD4
33
14 PD5R PD5R 2 RP15-27 PD5
33
14 PD6R PD6R 3 RP15-36 PD6
33
14 PD7R PD7R 4 RP15-45 PD7
33

+5V +5V
8

6
RP18-4 1K

RP18-2 1K

RP4-1 1K

RP4-3 1K

RP3-1 1K

RP2-4 1K

RP1-4 1K

RP1-2 1K

RP2-2 1K

RP4-4 1K

RP4-2 1K

RP18-1 1K

RP18-3 1K

RP1-3 1K

RP2-3 1K
RP2-1 1K

RP1-1 1K
1

3
J3
1 RP10-1 8 STB# PD0
14 STB#R 33 1 2
PD1 PD2
C 3 4 C
PD3 PD4
5 6
PD5 PD6
7 8
PD7 ACK#
9 10 ACK# 14
PE
14 BUSY 11 12 7RP10-2 2 PE 14
AFD#
14 SLCT 13 14 33 6RP10-3 3 AFD#R 14
INIT#
14 ERR# 4 RP10-4 5 15 16 33 INIT#R 14
SLIN#
14 SLIN#R 33 17 18
19 20

180pF CP5-2
180pF CP5-1

180pF CP5-3

180pF CP1-4

180pF CP2-2

180pF CP4-4

180pF CP4-2

180pF CP1-3

180pF CP2-3
180pF CP2-1

180pF CP1-1

180pF CP2-4

180pF CP1-2

180pF CP5-4
180pF CP4-1

180pF CP3-1
180pF CP4-3

21 22
1

3
23 24
25
26
27
8

6
D-SUB 25

PARALLEL PORT CONNECTOR

D D

This drawing contains information

which has not been verified for Intel Corporation
manufacturing an end user product Title
Intel is not responsible for h
te TX DESKTOP PARALLEL HEADER
misuse of this information. Size Document Number Rev
2.1
Date: Thursday, December 19, 1996 Sheet 15 of 29
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+12V

C45
0.1UF
+5V COM PORT 0
A A
U8
1 20 J5-1
2 VCC+ VCC 19
SP_DCD0 DCD0# 14
3 RA RY 18
SP_RXD0 RX0 14
4 RA RY 17 1
SP_DSR0 DSR0# 14 SP_DCD0
5 RA RY 16 6
SP_DTR0 DTR0# 14 SP_DSR0
6 DY DA 15 2
SP_TXD0 TX0 14 SP_RXD0
7 DY DA 14 7
SP_CTS0 CTS0# 14 SP_RTS0
8 RA RY 13 3
SP_RTS0 RTS0# 14 SP_TXD0
9 DY DA 12 8
SP_RI0 RI0# 14 SP_CTS0
10 RA RY 11 4
SP_DTR0
VCC- GND 9 SP_RI0
GD75232SOP 5
-12V

4
CP6-2 CP7-2 CP8-2 CP9-2 CP9-4 CP8-4 CP7-4 CP6-4
DB9_DUL
100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF

19

20
7

5
+12V

C21

0.1UF
+5V
COM PORT 1
U4
1 20 J5-2
2 VCC+ VCC 19
SP_DCD1 DCD1# 14
3 RA RY 18
SP_RXD1 RX1 14
4 RA RY 17 10
SP_DSR1 DSR1# 14 SP_DCD1
5 RA RY 16 15
SP_DTR1 DTR1# 14 SP_DSR1
B 6 DY DA 15 11 B
SP_TXD1 TX1 14 SP_RXD1
7 DY DA 14 16
SP_CTS1 CTS1# 14 SP_RTS1
8 RA RY 13 12
SP_RTS1 RTS1# 14 SP_TXD1
9 DY DA 12 17
SP_RI1 RI1# 14 SP_CTS1
10 RA RY 11 13
SP_DTR1
VCC- GND 18 SP_RI1
GD75232SOP 14
-12V

3
CP6-1 CP7-1 CP8-1 CP9-1 CP9-3 CP8-3 CP7-3 CP6-3
DB9_DUL
100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF

21

22
8

6
+5V

F3
1.0 AMP

+5V
KB5V

1
2

RP6-4 RP6-3 RP6-2 RP6-1

R19
L6 1K 1K 1K 1K 1K
FBHS04B
FLOPPY CONNECTOR

8
C C
1

J4
J19
2 L9 1 1
KBDAT_FB#
14 KBDAT# FBHS01K 2 14 DSKCHG# 34 33
14 SIDE1# 32 31
3 14 RDATA#
4 30 29
L7 KB5V_FB 14 WPT#
2 1 5 28 27
14 KBCLK# KBCLK_FB# 14 TRK0#
FBHS01K 6 26 25
14 WGATE# 24 23
L10 14 WDATA# 22 21
2 1 MSDAT_FB# 7
14 MSDAT# FBHS01K 8 17 14 STEP# 20 19
KBF1
9 16 14 DIR# 18 17
10 15 14 MOTEB# 16 15
L8 1 14 DRVSA# 14 13
14 MSCLK# 2 MSCLK_FB# 11 14
12 13 14 DRVSB# 12 11
FBHS01K
14 MOTEA# 10 9
14 INDEX# 8 7
470pf 470pf 470pf 470pf 470pf DIM6_DUL
C14 C16 C13 C15 C24 14 DRATE0 6 5
4 3
14 REDWC# 2 1
1

HEADER 17X2
KBF2 L11
FBHS01K
2

L12
2

FBHS04B
1

D D

Intel Corporation
Title
TX DESKTOP COM_PORT
Size Document Number Rev
2.1
Date: Thursday, December 19, 1996 Sheet 16 of 29
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+5V
L4
F1
USBVFB0 2 1 USBV0

1.0 AMP FBHS04B

1
C20 + C8
R11 0.1uF
150uF
470K

2 2
A A

12 USBOC0#
R12

C29 560K
0.001uF

1
J2-1

USBV0 1
VCC 9
R68 S
2 1 USBP0- 2
12 USBP0-R DATA-
33
2 R70 1 USBP0+ 3
12 USBP0+R DATA+ 10
33 S
USBG0 4
GND

1
USB_CON_0.0

1
R8
C159 C162 R5
15K
15K
50pf 50pf

1
2
L1

2
B B
C3 FBHS04B
0.1uF

2
+5V

F2 L5
USBVFB1 2 1 USBV1

1.0 AMP FBHS04B

1
C10 +
R10 150uF C9
470K 0.1uF

2 2

12 USBOC1#
R13
C30
0.001uF 560K
1

C C

J2-2

USBV1 5
VCC 11
S USBGND
2 R69 1 USBP1- 6
12 USBP1-R DATA-
33 R71 1
12 USBP1+R 2 USBP1+ 7
DATA+ 12
33 S
USBG1 8
1

GND
C160 R7
1

1
50pF 15K USB_CON_0.0
C163 R6
1

50pF 15K
L3
2

FBHS01L
C7 L2
2

0.1uF FBHS04B

2
2

D D

USB PORT INTERFACE

This drawing contains information Intel Corporation
which has not been verified for Title
manufacturing an end user product TX DESKTOP UNIVERSAL SERIAL BUS (USB)
Intel is not responsible for the
Size Document Number Rev
misuse of this information. 2.1

Date: Thursday, December 19, 1996 Sheet 17 of 29

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

A A

SB3V

R119
4.7K
STB5V
STB5V

U21B U20D
14 14
4 3 POWER-ON# 8 9 POWER-ON
12 PWRBT# 7 7

7407 74HCT14

R144
+12V
510K
B B

R20
+5V STB5V
4.7k
U2B U21A
P-CHANNEL

1
14 14 Q1A
3 4 FAN-ON# 1 2 FAN-ONV 2
12 FAN-ON
7 7
MOSFET
Si9933DY
74HCT14 7407

8
7
+5V
J23

FAN-CON
14 IRRX 1
14 IRTX 2
3
FAN CONNECTOR
J15
14 IRR3/MODE 4
5
6
1 7
2 12,19,25 SB3V 8
+5V 9
JP2 10
R143 11
HDLED
12
C 220 13 C
HARDDRV
14
15
16
14 PWRLED# 17
R142 18
PLED
19
220 20
14 KBLOCK# 21
22
23
24
HARDDRV SPK4
1 R137 2 25
SPK3
26
68
CON26
SPK2 1 R139 2
+5V +5V 68
U19F U19E +5V
14 14 R127 BZ1
13 12 10 11 1 2 SPK1 Q5 C249
13 HD_ACTA# HD_ACTB# 13 12 SPKR 2N3904
7 7 0.1uF 2
2.2K
1
7407 7407
BUZZER

D D

This drawing contains information Intel Corporation

which has not been verified for Title
manufacturing an end user product TX_DESKTOP FAN & FRONT PANEL CONNECTORS
Intel is not responsible for h
te
Size Document Number Rev
misuse of this information. 2.1

Date: Thursday, December 19, 1996 Sheet 18 of 29

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

DO NOT REPRODUCE

A A

+5V

+3_3V +12V

5
+5V
RP26-4
10K STB5V
J16 STB5V
1 2 U20C U20B

4
3 4 14 14
5 6 1 R116 2 5 6 3 4
PWRGD1 PWRGD2 PWROK# PWROK5V
7 8 7 7
STB5V 9 10 100
11 12
13 14 PS_ON# 12 74HCT14 74HCT14

2
15 16
17 18 R117
19 20
8.2K
C229

1
.01uF
B -5V B
PWROK 12

1
-12V
1

R145 R118
56 8.2K

2
SB3V
2

D4
1 3
VBAT3V 12,14
3

VBAT 2 R161 1 VBATRA 2

+ C230 D5
1K
C234 10UF MMBZ5226BL BAT54C
.1UF
1

1
4
3 BT1
BAT_G
2
J22 1 BATTERY
3

HEADER 4

EXTERNAL BATTERY
C C

STB5V STB5V

U20E U20F
14 14 R103
R99 11 10 13 12 2 1
RSMRST#0 RSMRST#1 RSMRST#2
7 7 RSMRST# 12
22K
8.2K
C192
74HCT14 74HCT14
1UF

2
R106
8.2K

1
D D

Intel Corporation
Title
TX DESKTOP POWER SUPPLY
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR Size Document Number Rev
MANUFACTURING AN END USER PRODUCT. 2.1
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION. Date: Thursday, December 19, 1996 Sheet 19 of 29
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

PCI SLOTS #1 & #2

PCI CONNECTOR #1 PCI CONNECTOR #2

+3_3V +3_3V
A A

+12V +5V+3_3V +12V +5V+3_3V

+5V +5V

-12V -12V

J11 J12
B1 A1 B1 A1
B2 B1 A1 A2 B2 B1 A1 A2
B3 B2 A2 A3 B3 B2 A2 A3
B4 B3 A3 A4 B4 B3 A3 A4
B5 B4 A4 A5 B5 B4 A4 A5
12,21,25 PIRQ1# B5 A5 12,21,25 PIRQ2# B5 A5
B6 A6 B6 A6
12,21,25 PIRQ3# B6 A6 PIRQ0# 12,21,25 12,21,25 PIRQ0# B6 A6 PIRQ1# 12,21,25
B7 A7 B7 A7
B7 A7 PIRQ2# 12,21,25 B7 A7 PIRQ3# 12,21,25
B8 A8 B8 A8
C56 0.1UF B9 B8 A8 A9 C57 0.1UF B9 B8 A8 A9
PCIA0 B9 A9 CLKRUN# 5,11,21 PCIB0 B9 A9 CLKRUN# 5,11,21
B10 A10 B10 A10
B11 B10 A10 A11 B11 B10 A10 A11
C60 PCIA1 C61 PCIB1
B12 B11 A11 A12 B12 B11 A11 A12
0.1UF 0.1UF
B13 B12 A12 A13 B13 B12 A12 A13
B14 B13 A13 A14 B14 B13 A13 A14
B15 B14 A14 A15 B15 B14 A14 A15
B15 A15 PCIRST# 5,6,11,21 B15 A15 PCIRST# 5,6,11,21
B16 A16 B16 A16
3 PCLK0 B16 A16 3 PCLK1 B16 A16
B17 A17 B17 A17
B17 A17 PGNT0# 5,25 B17 A17 PGNT1# 5,25
B18 A18 B18 A18
5,11,25 PREQ0# B18 A18 5,11,25 PREQ1# B18 A18
B19 A19 B19 A19
B20 B19 A19 A20 AD30 B20 B19 A19 A20 AD30
AD31 AD31
B21 B20 A20 A21 B21 B20 A20 A21
AD29 AD29
B22 B21 A21 A22 AD28 B22 B21 A21 A22 AD28
B22 A22 B22 A22
AD27 B23 A23 AD26 AD27 B23 A23 AD26
B B24 B23 A23 A24 B24 B23 A23 A24 B
AD25 AD25
B24 A24 B24 A24 R33
B25
B25 A25
A25 AD24 B25
B25 A25
A25 AD24
5,11,21 C/BE3#
B26 A26 PCIA2 2 1
5,11,21 C/BE3#
B26 A26 PCIB2 1 2 AD29
B27 B26 A26 A27 B27 B26 A26 A27
AD23 R32 220 AD23 220
B27 A27 B27 A27
B28
B28 A28
A28 AD22 B28
B28 A28
A28 AD22
AD21 B29 A29 AD20 AD21 B29 A29 AD20
B30 B29 A29 A30 B30 B29 A29 A30
AD19 AD19
B30 A30 B30 A30
B31 A31 AD18 B31 A31 AD18
B32 B31 A31 A32 AD16 B32 B31 A31 A32 AD16
AD17 AD17
B33 B32 A32 A33 B33 B32 A32 A33
5,11,21 C/BE2# B33 A33 5,11,21 C/BE2# B33 A33
B34 A34 B34 A34
B34 A34 FRAME# 5,11,21,25 B34 A34 FRAME# 5,11,21,25
B35 A35 B35 A35
5,11,21,25 IRDY# B35 A35 5,11,21,25 IRDY# B35 A35
B36 A36 B36 A36
B36 A36 TRDY# 5,11,21,25 B36 A36 TRDY# 5,11,21,25
5,11,21,25 DEVSEL# B37 A37 B37 A37
B37 A37 5,11,21,25 DEVSEL# B37 A37
B38 A38 B38 A38
B38 A38 STOP# 5,11,21,25 B38 A38 STOP# 5,11,21,25
B39 A39 B39 A39
5,21,25 PLOCK# B39 A39 5,21,25 PLOCK# B39 A39
B40 A40 B40 A40
21,25 PERR# B40 A40 SDONE 21,25 21,25 PERR# B40 A40 SDONE 21,25
B41 A41 B41 A41
B41 A41 SBO# 21,25 B41 A41 SBO# 21,25
11,21,25 SERR# B42 A42 11,21,25 SERR# B42 A42
B43 B42 A42 A43 B43 B42 A42 A43
B43 A43 PAR 5,11,21,25 B43 A43 PAR 5,11,21,25
5,11,21 C/BE1#
B44 A44 AD15 5,11,21 C/BE1#
B44 A44 AD15
B45 B44 A44 A45 B45 B44 A44 A45
AD14 AD14
B45 A45 B45 A45
B46
B46 A46
A46 AD13 B46
B46 A46
A46 AD13
AD12 B47
B47 A47
A47 AD11 AD12 B47
B47 A47
A47 AD11
AD10 B48 A48 AD10 B48 A48
B48 A48 B48 A48
B49
B49 A49
A49 AD9 B49
B49 A49
A49 AD9

AD8 B52 A52 AD8 B52 A52

B52 A52 C/BE0# 5,11,21 B52 A52 C/BE0# 5,11,21
AD7 B53 A53 AD7 B53 A53
B54 B53 A53 A54 AD6 B54 B53 A53 A54 AD6
C
B55 B54 A54 A55 AD4 B55 B54 A54 A55 AD4 C
AD5 AD5
B56 B55 A55 A56 B56 B55 A55 A56
AD3 AD3
B56 A56 B56 A56
B57
B57 A57
A57 AD2 B57
B57 A57
A57 AD2
AD1 B58 A58 AD0 AD1 B58 A58 AD0
B59 B58 A58 A59 B59 B58 A58 A59
B60 B59 A59 A60 B60 B59 A59 A60
25 ACK64S0# B60 A60 REQ64S0# 25 25 ACK64S1# B60 A60 REQ64S1# 25
B61 A61 B61 A61
B62 B61 A61 A62 B62 B61 A61 A62
B62 A62 B62 A62
PCI CONNECTOR PCI CONNECTOR

5,11,21 AD[31..0]

D D

This drawing contains information Intel Corporation

which has not been verified for Title
manufacturing an end user product TX DESKTOP PCI SLOTS 1 & 2
Intel is not responsible for the
Size Document Number Rev
misuse of this information. 2.1

Date: Thursday, December 19, 1996 Sheet 20 of 29

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

PCI SLOTS #3 & #4

PCI CONNECTOR #3 PCI CONNECTOR #4
A A

+3_3V +3_3V

+12V +5V+3_3V +12V +5V+3_3V

+5V +5V

-12V -12V

J13 J14
B1 A1 B1 A1
B2 B1 A1 A2 B2 B1 A1 A2
B3 B2 A2 A3 B3 B2 A2 A3
B4 B3 A3 A4 B4 B3 A3 A4
B5 B4 A4 A5 B5 B4 A4 A5
12,20,25 PIRQ3# B5 A5 12,20,25 PIRQ0# B5 A5
12,20,25 PIRQ1# B6 A6 B6 A6
B6 A6 PIRQ2# 12,20,25 12,20,25 PIRQ2# B6 A6 PIRQ3# 12,20,25
B7 A7 B7 A7
B7 A7 PIRQ0# 12,20,25 B7 A7 PIRQ1# 12,20,25
B8 A8 B8 A8
C58 0.1UF B9 B8 A8 A9 C59 0.1UF B9 B8 A8 A9
PCIC0 B9 A9 CLKRUN# 5,11,20 PCID0 B9 A9 CLKRUN# 5,11,20
B10 A10 B10 A10
B11 B10 A10 A11 B11 B10 A10 A11
C62 PCIC1 C63 PCID1
B12 B11 A11 A12 B12 B11 A11 A12
0.1UF 0.1UF
B13 B12 A12 A13 B13 B12 A12 A13
B14 B13 A13 A14 B14 B13 A13 A14
B15 B14 A14 A15 B15 B14 A14 A15
B15 A15 PCIRST# 5,6,11,20 B15 A15 PCIRST# 5,6,11,20
B16 A16 B16 A16
3 PCLK2 B16 A16 3 PCLK3 B16 A16
B17 A17 B17 A17
B17 A17 PGNT2# 5,25 B17 A17 PGNT3# 5,25
B18 A18 B18 A18
5,11,25 PREQ2# B18 A18 5,11,25 PREQ3# B18 A18
B19 A19 B19 A19
B19 A19 B19 A19
B AD31 B20
B20 A20
A20 AD30 AD31 B20
B20 A20
A20 AD30 B
AD29 B21 A21 AD29 B21 A21
B21 A21 B21 A21
B22
B22 A22
A22 AD28 B22
B22 A22
A22 AD28
AD27 B23
B23 A23
A23 AD26 AD27 B23
B23 A23
A23 AD26
AD25 B24 A24 AD25 B24 A24
B24 A24 R34 B24 A24 R38
B25
B25 A25
A25 AD24 B25
B25 A25
A25 AD24
5,11,20 C/BE3#
B26
B26 A26
A26 PCIC2 1 2
5,11,20 C/BE3#
B26
B26 A26
A26 PCID2 1 2 AD31
AD23 B27 A27 AD23 B27 A27
B27 A27 220 B27 A27 220
B28
B28 A28
A28 AD22 B28
B28 A28
A28 AD22
AD21 B29 A29 AD20 AD21 B29 A29 AD20
B30 B29 A29 A30 B30 B29 A29 A30
AD19 AD19
B30 A30 B30 A30
B31
B31 A31
A31 AD18 B31
B31 A31
A31 AD18
AD17 B32 A32 AD16 AD17 B32 A32 AD16
B33 B32 A32 A33 B33 B32 A32 A33
5,11,20 C/BE2# B33 A33 5,11,20 C/BE2# B33 A33
B34 A34 B34 A34
B34 A34 FRAME# 5,11,20,25 B34 A34 FRAME# 5,11,20,25
B35 A35 B35 A35
5,11,20,25 IRDY# B35 A35 5,11,20,25 IRDY# B35 A35
B36 A36 B36 A36
B36 A36 TRDY# 5,11,20,25 B36 A36 TRDY# 5,11,20,25
B37 A37 B37 A37
5,11,20,25 DEVSEL# B38 B37 A37 A38 5,11,20,25 DEVSEL# B38 B37 A37 A38
B38 A38 STOP# 5,11,20,25 B38 A38 STOP# 5,11,20,25
B39 A39 B39 A39
5,20,25 PLOCK# B39 A39 5,20,25 PLOCK# B39 A39
B40 A40 B40 A40
20,25 PERR# B40 A40 SDONE 20,25 20,25 PERR# B40 A40 SDONE 20,25
B41 A41 B41 A41
B41 A41 SBO# 20,25 B41 A41 SBO# 20,25
11,20,25 SERR# B42 A42 11,20,25 SERR# B42 A42
B43 B42 A42 A43 B43 B42 A42 A43
B43 A43 PAR 5,11,20,25 B43 A43 PAR 5,11,20,25
5,11,20 C/BE1#
B44
B44 A44
A44 AD15 5,11,20 C/BE1#
B44
B44 A44
A44 AD15
AD14 B45 A45 AD14 B45 A45
B45 A45 B45 A45
B46
B46 A46
A46 AD13 B46
B46 A46
A46 AD13
AD12 B47
B47 A47
A47 AD11 AD12 B47
B47 A47
A47 AD11
AD10 B48 A48 AD10 B48 A48
B48 A48 B48 A48
B49
B49 A49
A49 AD9 B49
B49 A49
A49 AD9
C C

AD8 B52 A52 AD8 B52 A52

B52 A52 C/BE0# 5,11,20 B52 A52 C/BE0# 5,11,20
AD7 B53 A53 AD7 B53 A53
B53 A53 B53 A53
B54
B54 A54
A54 AD6 B54
B54 A54
A54 AD6
AD5 B55
B55 A55
A55 AD4 AD5 B55
B55 A55
A55 AD4
AD3 B56 A56 AD3 B56 A56
B56 A56 B56 A56
B57
B57 A57
A57 AD2 B57
B57 A57
A57 AD2
AD1 B58
B58 A58
A58 AD0 AD1 B58
B58 A58
A58 AD0
B59 A59 B59 A59
B60 B59 A59 A60 B60 B59 A59 A60
25 ACK64S2# B60 A60 REQ64S2# 25 25 ACK64S3# B60 A60 REQ64S3# 25
B61 A61 B61 A61
B62 B61 A61 A62 B62 B61 A61 A62
B62 A62 B62 A62
PCI CONNECTOR PCI CONNECTOR

D D

5,11,20 AD[31..0]

Intel Corporation
Title
TX DESKTOP PCI SLOTS 3 & 4
Size Document Number Rev
2.1

Date: Thursday, December 19, 1996 Sheet 21 of 29

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

A
ISA A

SLOT#1
SD[15..0] 11,14,23,24,25

+5V

J8
B1 A1
B1 A1 IOCHK# 11,23,24,25
B2 A2 SD7
11,14,23,24 RSTISA B3 B2 A2 A3
-5V B3 A3 SD6
B4 A4 SD5
12,14,23,24,25 IRQ9 B4 A4
B5 A5 SD4
-12V B5 A5
B6 A6 SD3
12,14,23,24,25 DRQ2 B6 A6
+12V B7 A7 SD2
B8 B7 A7 A8
11,23,24,25 ZEROWS# B8 A8 SD1
B9 A9 SD0
B10 B9 A9 A10
B10 A10 IOCHRDY 11,14,23,24,25
B11 A11
11,23,24,25 SMEMW# B11 A11 AEN 11,14,23,24
B12 A12 SA19
11,23,24,25 SMEMR# B12 A12
B13 A13 SA18
11,14,23,24,25 IOW# B13 A13
B14 A14 SA17
11,14,23,24,25 IOR# B14 A14
12,14,23,24 DACK3# B15 A15 SA16
B16 B15 A15 A16
12,14,23,24,25 DRQ3 B16 A16 SA15
B17 A17 SA14
12,14,23,24 DACK1# B17 A17
B B18 A18 SA13 B
12,14,23,24,25 DRQ1 B18 A18
11,23,24,25 REFRESH# B19 A19 SA12
B20 B19 A19 A20
11,23,24 SYSCLK B20 A20 SA11
B21 A21 SA10
12,14,23,24,25 IRQ7 B21 A21
B22 A22 SA9
12,14,23,24,25 IRQ6 B22 A22
B23 A23 SA8
12,14,23,24,25 IRQ5 B24 B23 A23 A24
12,14,23,24,25 IRQ4 B24 A24 SA7
B25 A25 SA6
12,14,23,24,25 IRQ3 B26 B25 A25 A26
12,14,23,24 DACK2# B26 A26 SA5
B27 A27 SA4
12,14,23,24 T/C B28 B27 A27 A28
11,23,24,25 BALE B28 A28 SA3
B29 A29 SA2
B30 B29 A29 A30
3,23,24 OSC B30 A30 SA1
B31 A31 SA0
B31 A31

SA[19..0] 10,11,14,23,24,25
D1 C1
11,23,24,25 MEMCS16# D1 C1 SBHE# 11,23,24,25
D2 C2
11,23,24,25 IOCS16# D2 C2 LA23 11,23,24,25
D3 C3
12,14,23,24,25 IRQ10 D3 C3 LA22 11,23,24,25
D4 C4
12,14,23,24,25 IRQ11 D4 C4 LA21 11,23,24,25
D5 C5
12,14,23,24,25 IRQ12 D5 C5 LA20 11,23,24,25
D6 C6
12,13,14,23,24,25 IRQ15 D6 C6 LA19 11,23,24,25
D7 C7
12,13,14,23,24,25 IRQ14 D7 C7 LA18 11,23,24,25
D8 C8
12,14,23,24 DACK0# D8 C8 LA17 11,23,24,25
D9 C9
12,14,23,24,25 DRQ0 D9 C9 MEMR# 10,11,23,24,25
D10 C10
12,23,24 DACK5# D10 C10 MEMW# 10,11,23,24,25
D11 C11 SD8
12,23,24,25 DRQ5 D12 D11 C11 C12
12,23,24 DACK6# D12 C12 SD9
D13 C13 SD10
12,23,24,25 DRQ6 D14 D13 C13 C14
12,23,24 DACK7# D14 C14 SD11
D15 C15 SD12
C 12,23,24,25 DRQ7 D16 D15 C15 C16 C
D16 C16 SD13
D17 C17 SD14
23,24,25 MASTER# D17 C17
D18 C18 SD15
D18 C18

CON_ISA16B

D D

This drawing contains information Intel Corporation

which has not been verified for Title
manufacturing an end user product TX DESKTOP ISA SLOT#1
Intel is not responsible for h
te
Size Document Number Rev
misuse of this information. 2.1

Date: Thursday, December 19, 1996 Sheet 22 of 29

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

A A

ISA
SLOT#2
SD[15..0] 11,14,22,24,25

+5V

J9
B1 A1
B1 A1 IOCHK# 11,22,24,25
11,14,22,24 RSTISA B2 A2 SD7
B3 B2 A2 A3
-5V B3 A3 SD6
B4 A4 SD5
12,14,22,24,25 IRQ9 B4 A4
B5 A5 SD4
-12V B5 A5
B6 A6 SD3
12,14,22,24,25 DRQ2 B6 A6
+12V B7 A7 SD2
B8 B7 A7 A8
11,22,24,25 ZEROWS# B8 A8 SD1
B9 A9 SD0
B10 B9 A9 A10
B10 A10 IOCHRDY 11,14,22,24,25
11,22,24,25 SMEMW# B11 A11
B11 A11 AEN 11,14,22,24
B12 A12 SA19
11,22,24,25 SMEMR# B12 A12
B13 A13 SA18
11,14,22,24,25 IOW# B13 A13
B B14 A14 SA17 B
11,14,22,24,25 IOR# B14 A14
B15 A15 SA16
12,14,22,24 DACK3# B15 A15
B16 A16 SA15
12,14,22,24,25 DRQ3 B17 B16 A16 A17
12,14,22,24 DACK1# B17 A17 SA14
B18 A18 SA13
12,14,22,24,25 DRQ1 B18 A18
B19 A19 SA12
11,22,24,25 REFRESH# B20 B19 A19 A20
11,22,24 SYSCLK B20 A20 SA11
B21 A21 SA10
12,14,22,24,25 IRQ7 B21 A21
B22 A22 SA9
12,14,22,24,25 IRQ6 B22 A22
B23 A23 SA8
12,14,22,24,25 IRQ5 B24 B23 A23 A24
12,14,22,24,25 IRQ4 B24 A24 SA7
B25 A25 SA6
12,14,22,24,25 IRQ3 B26 B25 A25 A26
12,14,22,24 DACK2# B26 A26 SA5
B27 A27 SA4
12,14,22,24 T/C B28 B27 A27 A28
11,22,24,25 BALE B28 A28 SA3
B29 A29 SA2
B30 B29 A29 A30
3,22,24 OSC B30 A30 SA1
B31 A31 SA0
B31 A31

SA[19..0] 10,11,14,22,24,25
D1 C1
11,22,24,25 MEMCS16# D1 C1 SBHE# 11,22,24,25
D2 C2
11,22,24,25 IOCS16# D2 C2 LA23 11,22,24,25
D3 C3
12,14,22,24,25 IRQ10 D3 C3 LA22 11,22,24,25
D4 C4
12,14,22,24,25 IRQ11 D4 C4 LA21 11,22,24,25
12,14,22,24,25 IRQ12 D5 C5
D5 C5 LA20 11,22,24,25
D6 C6
12,13,14,22,24,25 IRQ15 D6 C6 LA19 11,22,24,25
D7 C7
12,13,14,22,24,25 IRQ14 D7 C7 LA18 11,22,24,25
D8 C8
12,14,22,24 DACK0# D8 C8 LA17 11,22,24,25
D9 C9
12,14,22,24,25 DRQ0 D9 C9 MEMR# 10,11,22,24,25
D10 C10
12,22,24 DACK5# D10 C10 MEMW# 10,11,22,24,25
D11 C11 SD8
C 12,22,24,25 DRQ5 D12 D11 C11 C12 C
12,22,24 DACK6# D12 C12 SD9
D13 C13 SD10
12,22,24,25 DRQ6 D14 D13 C13 C14
12,22,24 DACK7# D14 C14 SD11
D15 C15 SD12
12,22,24,25 DRQ7 D16 D15 C15 C16
D16 C16 SD13
D17 C17 SD14
22,24,25 MASTER# D17 C17
D18 C18 SD15
D18 C18

CON_ISA16B

D D

This drawing contains information Intel Corporation

which has not been verified for Title
manufacturing an end user product TX DESKTOP ISA SLOT#2
Intel is not responsible for h
te
Size Document Number Rev
misuse of this information. 2.1

Date: Thursday, December 19, 1996 Sheet 23 of 29

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

A A

ISA
SLOT#3
SD[15..0] 11,14,22,23,25

+5V

J10
B1 A1
B1 A1 IOCHK# 11,22,23,25
11,14,22,23 RSTISA B2 A2 SD7
B3 B2 A2 A3
-5V B3 A3 SD6
B4 A4 SD5
12,14,22,23,25 IRQ9 B4 A4
B5 A5 SD4
-12V B5 A5
B6 A6 SD3
12,14,22,23,25 DRQ2 B6 A6
+12V B7 A7 SD2
B8 B7 A7 A8
11,22,23,25 ZEROWS# B8 A8 SD1
B9 A9 SD0
B B10 B9 A9 A10 B
B10 A10 IOCHRDY 11,14,22,23,25
B11 A11
11,22,23,25 SMEMW# B11 A11 AEN 11,14,22,23
B12 A12 SA19
11,22,23,25 SMEMR# B12 A12
B13 A13 SA18
11,14,22,23,25 IOW# B13 A13
11,14,22,23,25 IOR# B14 A14 SA17
B15 B14 A14 A15
12,14,22,23 DACK3# B15 A15 SA16
B16 A16 SA15
12,14,22,23,25 DRQ3 B17 B16 A16 A17
12,14,22,23 DACK1# B17 A17 SA14
B18 A18 SA13
12,14,22,23,25 DRQ1 B18 A18
B19 A19 SA12
11,22,23,25 REFRESH# B19 A19
B20 A20 SA11
11,22,23 SYSCLK B20 A20
B21 A21 SA10
12,14,22,23,25 IRQ7 B21 A21
B22 A22 SA9
12,14,22,23,25 IRQ6 B22 A22
B23 A23 SA8
12,14,22,23,25 IRQ5 B23 A23
B24 A24 SA7
12,14,22,23,25 IRQ4 B24 A24
B25 A25 SA6
12,14,22,23,25 IRQ3 B25 A25
B26 A26 SA5
12,14,22,23 DACK2# B26 A26
B27 A27 SA4
12,14,22,23 T/C B28 B27 A27 A28
11,22,23,25 BALE B28 A28 SA3
B29 A29 SA2
B30 B29 A29 A30
3,22,23 OSC B30 A30 SA1
B31 A31 SA0
B31 A31

SA[19..0] 10,11,14,22,23,25
D1 C1
11,22,23,25 MEMCS16# D1 C1 SBHE# 11,22,23,25
D2 C2
11,22,23,25 IOCS16# D2 C2 LA23 11,22,23,25
D3 C3
12,14,22,23,25 IRQ10 D3 C3 LA22 11,22,23,25
D4 C4
12,14,22,23,25 IRQ11 D4 C4 LA21 11,22,23,25
D5 C5
12,14,22,23,25 IRQ12 D5 C5 LA20 11,22,23,25
D6 C6
12,13,14,22,23,25 IRQ15 D6 C6 LA19 11,22,23,25
D7 C7
C 12,13,14,22,23,25 IRQ14 D7 C7 LA18 11,22,23,25 C
D8 C8
12,14,22,23 DACK0# D8 C8 LA17 11,22,23,25
D9 C9
12,14,22,23,25 DRQ0 D9 C9 MEMR# 10,11,22,23,25
12,22,23 DACK5# D10 C10
D10 C10 MEMW# 10,11,22,23,25
D11 C11 SD8
12,22,23,25 DRQ5 D12 D11 C11 C12
12,22,23 DACK6# D12 C12 SD9
D13 C13 SD10
12,22,23,25 DRQ6 D14 D13 C13 C14
12,22,23 DACK7# D14 C14 SD11
D15 C15 SD12
12,22,23,25 DRQ7 D16 D15 C15 C16
D16 C16 SD13
22,23,25 MASTER# D17 C17 SD14
D18 D17 C17 C18
D18 C18 SD15

CON_ISA16B

D D

This drawing contains information Intel Corporation

which has not been verified for Title
manufacturing an end user product TX DESKTOP ISA SLOT#3
Intel is not responsible for h
te
Size Document Number Rev
misuse of this information. 2.1

Date: Thursday, December 19, 1996 Sheet 24 of 29

1 2 3 4 5 6 7 8
 A B C D E

+5V +5V +5V

+5V 10,11,14,22,23,24 SA[19:0] +5V
11,14,22,23,24 SD[15:0]
7 RP13-22 SA0 8 RP11-11 SD0 8 RP9-1 1 PIRQ0# PIRQ0# 12,20,21
10K 10K 2.7K
6 RP26-33 SA1 5 RP7-4 4 SD1 7 RP9-2 2 PIRQ1# 8 RP26-11 2 R165 1
PIRQ1# 12,20,21 BALE 11,22,23,24 REFRESH# 11,22,23,24
10K 10K 2.7K 10K 1K
7 RP26-22 SA2 6 RP7-3 3 SD2 6 RP9-3 3 PIRQ2#
PIRQ2# 12,20,21
10K 10K 2.7K 4 RP47-45 8 RP8-1 1
IOR# 11,14,22,23,24 ZEROWS# 11,22,23,24
5 RP25-44 SA3 7 RP7-2 2 SD3 5 RP9-4 4 PIRQ3# 10K 330
PIRQ3# 12,20,21
4
10K 10K 2.7K 4
6 RP25-33 SA4 8 RP7-1 1 SD4 2 RP47-27 8 RP27-11
IOW# 11,14,22,23,24 MASTER# 22,23,24
10K 10K 10K 330
7 RP25-22 SA5 6 RP5-3 3 SD5 +5V
10K 10K 6 RP39-33 6 RP27-33
MEMR# 10,11,22,23,24 MEMCS16# 11,22,23,24
8 RP25-11 SA6 7 RP5-2 2 SD6 3 RP31-36 ACK64S3# 10K 330
ACK64S3# 21
10K 10K 2.7K
6 RP24-33 SA7 8 RP5-1 1 SD7 8 RP31-11 ACK64S2# 5 RP39-44 5 RP27-44
ACK64S2# 21 MEMW# 10,11,22,23,24 IOCS16# 11,22,23,24
10K 10K 2.7K 10K 330
8 RP24-11 SA8 8 RP45-11 SD8 2 RP30-27 ACK64S1# ACK64S1# 20
10K 10K 2.7K 3 RP47-36 4 RP44-45
SMEMR# 11,22,23,24 IOCHRDY 11,14,22,23,24
7 RP22-22 SA9 7 RP45-22 SD9 5 RP30-44 ACK64S0# 10K 1K
ACK64S0# 20
10K 10K 2.7K R74
5 RP19-44 SA10 6 RP45-33 SD10 1 RP47-18 2 1
SMEMW# 11,22,23,24 IOCHK# 11,22,23,24
10K 10K 10K 4.7K
6 RP19-33 SA11 5 RP45-44 SD11 +5V
10K 10K 8 RP33-11
SBHE# 11,22,23,24
7 RP19-22 SA12 8 RP49-11 SD12 4 RP31-45 REQ64S3# 10K
REQ64S3# 21
10K 10K 2.7K
8 RP19-11 SA13 7 RP49-22 SD13 7 RP31-22 REQ64S2# +3_3V
REQ64S2# 21
10K 10K 2.7K
5 RP13-44 SA14 6 RP49-33 SD14 1 RP30-18 REQ64S1# REQ64S1# 20
10K 10K 2.7K 2 RP41-2 7 8 RP48-11
PAR 5,11,20,21 PHOLD# 5,11
6 RP13-33 SA15 5 RP49-44 SD15 6 RP30-33 REQ64S0# 2.7K 10K
REQ64S0# 20
10K 10K 2.7K
8 RP13-11 SA16 6 RP37-33 5 RP48-44
PERR# 20,21 PHLDA# 5,11
10K 11,22,23,24 LA[23:17] 2.7K 10K
5 RP11-44 SA17 +5V
12,14,22,23,24 DRQ[7:0] 3 RP41-3 6
10K SERR# 11,20,21
6 RP11-33 SA18 5 RP36-44 LA17 2.7K
10K 1 RP46-1 8 DRQ0 10K
7 RP11-22 SA19 5.6K 7 RP36-22 LA18 5 RP37-44
PLOCK# 5,20,21
10K 4 RP16-4 5 DRQ1 10K 2.7K
5.6K 8 RP36-11 LA19
12,13,14,22,23,24 IRQ[15:0]
3 RP16-3 6 DRQ2 10K 1 RP41-1 8
STOP# 5,11,20,21
5.6K 5 RP28-44 LA20 2.7K
2 RP55-27 IRQ1 1 RP16-1 8 DRQ3 10K
10K 5.6K 6 RP28-33 LA21 1 RP40-1 8
DEVSEL# 5,11,20,21
3 5 RP24-44 IRQ3 2 RP46-2 7 DRQ5 10K 2.7K 3
10K 5.6K 7 RP28-22 LA22
7 RP24-22 IRQ4 3 RP46-3 6 DRQ6 10K 2 RP40-2 7
TRDY# 5,11,20,21
10K 5.6K 8 RP28-11 LA23 2.7K
5 RP22-44 IRQ5 4 RP46-4 5 DRQ7 10K
10K 5.6K 3 RP40-3 6
IRDY# 5,11,20,21
6 RP22-33 IRQ6 2.7K
10K +5V
SB3V 8 RP22-11 IRQ7 4 RP40-4 5
FRAME# 5,11,20,21
10K 8 RP14-11 PREQ0# 2.7K
PREQ0# 5,11,20
1 RP55-18 IRQ8 10K
10K 7 RP14-22 PREQ1# 7 RP37-22
PREQ1# 5,11,20 SBO# 20,21
5 RP5-4 4 IRQ9 10K 2.7K
10K 6 RP14-33 PREQ2# PREQ2# 5,11,21
7 RP33-22 IRQ10 10K 8 RP37-11
SDONE 20,21
10K 5 RP14-44 PREQ3# 2.7K
PREQ3# 5,11,21
6 RP33-33 IRQ11 10K
10K
5 RP33-44 IRQ12
10K +3_3V
7 RP39-22 IRQ14
10K 5 RP17-44 PGNT0# PGNT0# 5,20
8 RP39-11 IRQ15 10K
10K 6 RP17-33 PGNT1# PGNT1# 5,20
10K
7 RP17-22 PGNT2# PGNT2# 5,21
10K
8 RP17-11 PGNT3# PGNT3# 5,21
10K

2 2

1 1

Intel Corporation
Title
TX DESKTOP PULL-UPS
Size Document Number Rev
2.1
Date: Thursday, December 19, 1996 Sheet 25 of 29
A B C D E
 A B C D E

+3_3V +3_3V +12V CPUVCORE

MH1
1 2
C97 0.01uF 1 2
1 2 C4 10uF 1 2 1 2 1
C80 0.01uF 1 2 C143 1uF C142 1uF
2 1 1 2 C23 10uF 2 1 1 2
+5V C210 0.1uF C84 0.01uF C128 1uF C122 1uF
MOUNT-HOLE
1 2 2 1 2 1
C104 1uF C103 1uF MH2
C82 0.01uF
2 1 -12V 1 2 1 2
1 2 C134 0.01uF C151 1uF C141 1uF
C33 0.1uF 1 2 1 2 2 1 1 2 1
4 1 2 C116 0.1uF C170 0.01uF C114 1uF 4
C124 1uF
C131 0.1uF 2 1 2 1 1 2
1 2 C171 0.01uF C5 C145 1uF C115 1uF
MOUNT-HOLE
C32 0.1uF 2 1 1 2 2 1 1 2 1 2
1 2 C188 0.1uF C127 1uF C153 1uF MH3
C179 0.01uF
C130 0.1uF 2 1 2 1 2 1 2 1
10uF
1 2 C194 0.1uF C69 0.01uF C155 1uF C123 1uF
C31 0.1uF 2 1 1 2 1 2 1 2 1
1 2 C195 0.1uF C49 0.01uF C112 1uF C121 1uF
C99 0.1uF 1 2 1 2 -5V 1 2 1 2
1 2 C107 0.1uF C213 0.01uF C144 1uF C146 1uF
MOUNT-HOLE
C129 0.1uF 1 2 1 2 1 2
1 2 C118 1uF C152 1uF MH4
C218 0.1uF
C98 0.1uF 1 2 1 2 2 1 1 2
1 2 C6 C157 1uF C154 1uF
C221 0.1uF C137 0.01uF 1
C22 0.1uF 2 1 2 1 2 1 1 2 1 2
1 2 C93 0.1uF C187 0.01uF C113 1uF C271 220uF
C183 0.1uF 2 1 1 2
10uF
2 1 C102 0.1uF C270 220uF
CPUVIO MOUNT-HOLE
C248 0.1uF 2 1
1 2 C66 0.1uF MH5
C17 0.1uF 1 2 1 2
2 1 C94 0.1uF C206 0.01uF 1 2
2 1 C126 220uF 1
C71 0.1uF
2 1 C173 0.01uF STB5V 1 2
C64 0.1uF 1 2 C108 0.1uF
1 2 C199 0.1uF +3_3V 1 2
MOUNT-HOLE
C87 0.1uF 2 1 C109 0.1uF
2 1 C166 0.1uF 1 2 1 2
C25 0.1uF 2 1 C50 0.1uF C110 0.1uF
2 1 C92 0.1uF 1 2 1 2
3 C27 0.1uF 2 1 1 2 C250 0.1uF C111 0.1uF 3
2 1 C181 0.1uF C68 0.001uF 1 2
C243 0.1uF 1 2 2 1 C147 0.1uF MH6
1 2 C136 0.1uF C95 0.001uF 1 2
C184 0.1uF 1 2 2 1 C148 0.1uF
2 1 CPUVCORE +5V 1 2 1
C165 0.1uF C168 0.001uF
C51 0.1uF 1 2 2 1 C149 0.1uF
2 1 C75 0.1uF C174 0.001uF 1 2
C34 0.1uF 1 2 1 2 1 2 C150 0.1uF
MOUNT-HOLE
C156 0.1uF C132 0.001uF C258 0.1uF 1 2
2 1 C120 0.1uF MH7
C222 0.001uF 1 2
+5V 1 2 2 1 C119 0.1uF
1 2 1
C106 0.1uF C219 0.001uF
2 1 +3_3V +5V C139 0.1uF
2 1 C172 0.1uF 1 2
C26 0.01uF 1 2 +3_3V 2 1 C140 0.1uF
MOUNT-HOLE
2 1 C211 0.1uF C264 0.1uF
C35 0.01uF 2 1 2 1 MH8
1 2 C44 0.1uF C265 0.1uF
C88 0.01uF 1 2 1 2
1 2 1 2 C263 0.1uF 1
C65 0.1uF
C42 0.01uF 2 1 C89 10uF 1 2
1 2 C76 0.1uF 1 2 C262 0.1uF
C40 0.01uF 2 1 C175 10uF 1 2
0.1uF MOUNT-HOLE
2 1 C169 1 2 C261 0.1uF
C28 0.01uF 2 1 1 2 +5V +5V MH9
C86 10uF
1 2 C117 0.1uF 1 2 C260 0.1uF STB5V
C18 0.01uF 2 1 C90 10uF 2 1
1 2 1 2 C259 U21C U2D U19C 1
C135 0.1uF 0.1uF
C100 0.01uF 1 2 C185 10uF 14 14 14
2 2
2 1 C203 0.1uF 5 6 9 8 5 6
C237 0.01uF 1 2 +3_3V CPUVCORE 7 7 7
MOUNT-HOLE
C43 0.1uF
2 1 2 1 MH10
7407 74HCT14 7407
C164 0.1uF C268 0.1uF
+5V 2 1 2 1
C267 0.1uF U21D U2E U19D 1
C190 0.1uF
1 2 14 14 14
C182 0.1uF 9 8 11 10 9 8
1 2 1 2 +3_3V CPUVIO 7 7 7
MOUNT-HOLE
C96 0.001uF C81 0.1uF
2 1 1 2
7407 74HCT14 7407
C36 0.001uF C212 0.1uF 2 1
1 2 1 2 C266 0.1uF
C41 0.001uF U21E U2F
C83 0.1uF
2 1 1 2 14 14
C52 0.001uF C177 0.1uF 11 10 13 12
1 2 7 7
C191 0.1uF
+5V 2 1
7407 74HCT14
C161 0.1uF
1 2 U21F
C198 0.1uF 14
1 2 1 2 13 12
C11 10uF C138 0.1uF 7
1 2 2 1
C178 10uF C189 0.1uF 7407
1 2 2 1
C47 10uF C186 0.1uF
1 2 2 1
1 C48 10uF C158 0.1uF 1
1 2 1 2
C125 10uF C105 0.1uF
1 2 1 2
C12 10uF C176 0.1uF
1 2 1 2
C38 10uF C79 0.1uF
1 2
Intel Corporation
C180 0.1uF
1 2 Title
C101 0.1uF TX Desktop Decoupling Capacitor s
1 2
C133 0.1uF Size Document Number Rev
2.1

Date: Thursday, December 19, 1996 Sheet 26 of 29

A B C D E
 A B C D E

U9
2

2
VOUT CPUVIO
+5V 3 R28
VIN
110
1 VRVADJ1 1 R29 2 VRVIO2
SEE NOTE 1 C53 ADJ
+

1
470
4 LT1587 4
220uF

1
R21 C70 C77
R27 +
1K 0.33uF
178
220uF

3
2
+12V D2
1N4148_SMT

C39

2
C46

8
0.1uF 0.1uF
1 R22 2 VROAN 2 -
6 VROAOUT
1K U7 1
VROAP 3 +
LT1006

4
5
2

1
D1
1N4148_SMT R162
3.3M C272
0.1uF

2
3 3
+12V

U11
LT1580
4 1 R37 2
5 VCONT
VIN 2
1 VRSENSE
SENSE
C72
+ SEE NOTE 2
C74 1uF
3
ADJ

22uF VOUT CPUVCORE

+ VRFETD2
2

C55

2
+ 220uF
C54 R36
220uF 107

2
+5V
VRVADJ2 +5V R30
1

10K
1

1
C67
R35

1
.33UF
1

432 R44
VRFETD1 10K C91 + +
R31 C73
22
4

10K 100UF 220UF

2
2

Q2
2 Q3 2
1 VRGATEC
2

2N7002
R26
191 ZVN4206
3
1

Q4
VCC2DET 2
2N3904

Resistors are implemented as copper traces on inter layer:

For 1oz. copper:
Note 1: trace widths are 50 mils, 1.24" long.
Note 2: trace widths are 50 mils, 0.83" long.
1 1

Intel Corporation
Title
TX DESKTOP VOLTAGE REGULATOR
Size Document Number Rev
2.1

Date: Thursday, December 19, 1996 Sheet 27 of 29

A B C D E
 A B C D E

J1 MODE J7 J6
MODE POS. Program Device 1-2 1-2
NORMAL 2-3 Plug -N- Play 2-3 1-2
RECOVERY 1-2 Non-Plug-N-Play X 2-3
Not Used 2-3 2-3

4 4

APPENDIX 1 +5V
U2C
SA16/17 1
J1

2
14
5 6 SA16/17# 3
7
+5V
74HCT14
+12V +5V
INSTALL
J7
SA16 IF R3 +12V
1M FLASH R9 8.2K
2 R2 1 SA16
0

3
8.2K J6
1
INSTALL R1
2 1 SA17 FL VPP 2
SA17 IF 0 C1
2M FLASH C2 FL_PNPPU 3
0.1uF
0.1uF

BIOSMSB
R4
SA[0..19]
3 0 3
U1
U3 2 13 XD0
19 7 3 A16 DQ0 14
XD0 SA15 XD1
22 A17 DQ0 8 29 A15 DQ1 15
SA16 XD1 SA14 XD2
23 A16 DQ1 9 28 A14 DQ2 17
SA15 XD2 SA13 XD3
24 A15 DQ2 10 4 A13 DQ3 18
SA14 XD3 SA12 XD4
25 A14 DQ3 13 25 A12 DQ4 19
SA13 XD4 SA11 XD5
26 A13 DQ4 14 23 A11 DQ5 20
SA12 XD5 SA10 XD6
27 A12 DQ5 15 26 A10 DQ6 21
SA11 XD6 SA9 XD7
17 A11 DQ6 16 27 A9 DQ7
SA10 XD7 SA8
28 A10 DQ7 5 A8 +5V
SA9 +5V SA7
29 A9 6 A7
SA8 SA6
33 A8 11 7 A6 32
SA7 SA5
34 A7 VCC 12 8 A5 VCC 16
SA6 SA4
35 A6 VCC 18 9 A4 GND
SA5 SA3
36 A5 GND 5 10 A3
SA4 SA2
37 A4 GND 1 11 A2
SA3 SA1
38 A3 NC 2 12 A1
SA2 SA0
39 A2 NC 20 +5V A0
SA1
3 A1 NC 21
SA0
A0 NC 40 31
C19
30 NC 24 WE#
6 WE# 0.1uF 22 OE#
4 OE# 30 CE# 1
31 CE# 32 RP# VPP
RP# VPP
P28F001BX-T
P28F002BC-T
2 2

MEMW#
MEMR#
FL2MPU
OPTIONAL 2MB FLASH
ROMCS#

**NOTE: The PA28F002BC-T Chip can be replaced XD[0..7]

with this P28F002BC-T (PDIP) Chip.

When using the P28F002BC-T,simply replace
page 10 of the TX_DESKTOP Design with
this appendix page.
1 1

Intel Corporation
Title
TX DESKTOP FLASH BIOS WITH P28F002BC-T PDIP

Size Document Number Rev

2.1

Date: Thursday, December 19, 1996 Sheet 28 of 29

A B C D E
 A B C D E

+5V +3_3V

CTAG[0..7]

4 APPENDIX 2 4

U17

81 1
Note: 82 GND GND 2
CTAG1 CTAG0
PCIRST#, W/R#, & KRQAK 83 TIO1 TIO0 3
CTAG7 CTAG2
84 TIO7 TIO2 4
CTAG5 CTAG6
85 TIO5 TIO6 5
CTAG3 CTAG4
These (3) signals are 86 TIO3 TIO4 6
87 TIO9 TIO8 7
connected to coast VCC5 VCC3
88 8
module for DRAM 89 TIO10 TWE# 9
TWE#
CACHE use only. CADV# CADV#/CAA4
CADS#/CAA3 CADS#
90 10
91 GND GND 11
COE# HBE#4
92 COE# CWE4# 12
HBE#5 HBE#6
93 CWE5# CWE6# 13
HBE#7 HBE#0
94 CWE7# CWE0# 14
HBE#1 HBE#2
95 CWE1# CWE2# 15
96 VCC5 VCC3 16
HBE#[0..7] HBE#3 CCS#
97 CWE3# CCS#/CAB4 17
KRQAK/CAB3 GWE# CGWE#
98 18
KRQAK CALE/ZZ BWE# CBWE#
99 19
CZZ GND GND
100 20 HA3
PCIRST# RESET# A3
HA4 101 21 HA7
HA6 102 A4 A7 22 HA5
HA8 103 A6 A5 23 HA11
HA10 104 A8 A11 24 HA16
105 A10 A16 25
106 VCC5 VCC3 26
HA17 HA18
107 A17 A18 27
3 108 GND GND 28 3
HA9 HA12
109 A9 A12 29
HA14 HA13
110 A14 A13 30
HA[3..31] HA15 HADSC#
111 A15 ADSP# 31
112 H/WR# ECS1#/CS# 32
W/R# PD0
113 PD0 ECS2# 33
PD2 PD1
114 PD2 PD1 34 PD3
115 BOSEL/SS PD3 35
116 GND GND 36
CPU_IO_VCC HCLKSRAM0 CLK0 CLK1 HCLKSRAM1
117 37
118 GND GND 38
HD63 HD62
119 D63 D62 39
120 VCC5 VCC3 40
HD61 HD60
121 D61 D60 41
HD59 HD58
122 D59 D58 42
HD57 HD56
R216

R217

R218

R219

123 D57 D56 43

124 GND GND 44
HD55 HD54
125 D55 D54 45
HD53 HD52
126 D53 D52 46
22K

22K

22K

22K

HD51 HD50
127 D51 D50 47
R220 HD49 HD48
128 D49 D48 48
HA28 PD0
129 GND GND 49
2.2K HD47 HD46
130 D47 D46 50
HD45 HD44
R221 131 D45 D44 51
HA29 PD1 HD43 HD42
132 D43 D42 52
2.2K VCC5 VCC3
HD41 133 53 HD40
R222 134 D41 D40 54
HA30 PD2 HD39 HD38
135 D39 D38 55
2.2K HD37 HD36
136 D37 D36 56
R223 GND GND
HA31 PD3 HD35 137 57 HD34
138 D35 D34 58
HD33 HD32
2 2.2K 139 D33 D32 59 2
HD31 HD30
140 D31 D30 60
141 VCC5 VCC3 61
HD29 HD28
142 D29 D28 62
HD27 HD26
143 D27 D26 63
HD25 HD24
144 D25 D24 64
145 GND GND 65
HD23 HD22
146 D23 D22 66
HD21 HD20
147 D21 D20 67
Note: The Coast Module page, HD19
148 D19
VCC5
D18
VCC3
68
HD18

149 69
when used replaces HD17
HD15 150 D17 D16 70
HD16
HD14
151 D15 D14 71
the previous two CACHE pages HD13
152 D13 D12 72
HD12
GND GND
(pages 6 & 7). HD11
HD9
153
154 D11 D10
73
74
HD10
HD8
155 D9 D8 75
HD7 HD6
156 D7 D6 76
157 VCC5 VCC3 77
HD5 HD4
158 D5 D4 78
HD3 HD2
159 D3 D2 79
HD1 HD0
160 D1 D0 80
GND GND

COAST 3.1a

Keying Option 2
1 1

HD[0..63]

Intel Corporation
Title

TX DESKTOP COAST MODULE

Size Document Number Rev
2.1

Date: Thursday, December 19, 1996 Sheet 29 of 29

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The following are the changes from the Rev 2.0 to Rev 2.1 schematics:

1. Sheet 2: The value of the pull-up resistors on HRESET and HINIT (R53 and R55 respectively) changed from 4.7K to 330 ohms. These are timing critical, open collector outputs from the PIIX4 and
need strong pull-ups.

2. Sheet 6,7: Cache topology changed from four 32Kx32 parts to two 64Kx32 parts. This reduces parts count and makes layout guidelines easier to meet.

4
3. Sheet 3,8,9: HCLKSRAM0 signal (R112) was removed due to change in cache topology. Clocks to DIMMs from clock synthesizer have also been moved to optimize layout. If SMBus is used to turn off the 4
clocks, BIOS needs to be aware of the clock routing (i.e. which DIMM is connected to which clock). Signals that have moved include: HCLKDIMM0, HCLKDIMM5, HCLKDIMM6.

4. Sheet 10: PA28F002BC-T renamed to E28F002BC-T. The E prefix denotes the 40 pin TSOP part which is shown in the schematics and used on the customer reference board. (PA denotes a 44 pin PSOP package)

5. Sheet 12: An 8 pin thermal device U22 (not populated on the reference board) is added to the SMBus, located as close to the CPU as possible. This is for test purposes only.

6. Sheet 12: R83, a 1M ohm resistor in the PIIX4 RTC oscillator circuit is not required and therefore not installed.

7. Sheet 12: All unused GPIx inputs on the PIIX4 are tied high through 8.2K pull-up resistors to a power plane. GPI13 - GPI21 are tied to the 3.3v core power plane and GPI1 is tied to 3v Stand-by
through 8.2k resistors. If GPI1 is left floating, this will violate ACPI compliance, preventing the GPI_STS bit (register base + 0Ch, bit 9) from functioning properly.

8. Sheet 12: PIIXTHRM is pulled to 3.3v (through resistor RP66-1) instead of SB3v. This signal is not part of the suspend well in the PIIX4.

9. Sheet 14: Open collector gate is added to the IRQ8# path to insure the voltage driven to the PIIX4 does not exceed a 3.3v level. The Super I/O device is a 5v part and could drive IRQ8# to 5v
even if the pull-up on this pin is pulled to 3v Stand-by.

10. Sheet 14: Open collector driver U19B and 0 ohm resistor R123 was added to connect the PIIX4 and the Ultra I/O ring indicate lines. To implement ring indicate during STD/Soff, this part
must be powered by the standby voltage.

11. Sheet 14: Capacitor C37 changed from 0 .1uF to 22pF.

12. Sheet 19: Bypass capacitor C234 changed from 1uF to .1uF.

13. Sheet 19: R145 changed from 390 ohms to 56 ohms to set SB3V correctly.

14. Sheet 19: R99 changed from 1K ohms to 22K ohms to provide adequate delay on RSMRST# at Schmitt triger (U20e) input.
3 3

The following are miscellaneous changes not reflected in the Rev 2.1 Schematics or Gerber files:

1. Sheet 8,9: Series resistors R62, R63, R66, and R67 should be 0 ohm stuffing option resistors, and MRAS[5..4] should have 10 ohm series termination resistors located as close as possible to the MTXC.

2. Sheet 12: SMBCLK and SMBDATA should be pulled up to the 3.3V core plane through 8.2K resistors. It follows that the SMBus cannot be used as a resume event during STD/Soff since it is not tied to a
standby voltage. These should not be pulled up to 3VSB when used with devices being powered from the core voltage (e.g. SDRAM) due to excessive leakage when the core voltage is off. If they are
pulled up to 3VSB then all the devices on the SMBus should be tied to 3VSB.

3. The PCI Boundary Scan signals on the PCI connector are: TRST#, TMS, TDI, TDO, and TCK. Pullup and pulldown resistor values for these signals should follow the recommendations listed in the PCI
Specification, Rev 2.1. If boundary scan is not supported on the motherboard, then TMS (connector pin A3) and TDI (connector pin A4) should be independently bused and pulled up, each with ~ 5K ohm
resistors. TRST# (connector pin A1) and TCK (connector pin B2) should be independently bused and pulled down, each with ~ 5K ohm resistors. TDO (connector pin B4) should be left open.

4. Sheet 25: Change pullups on the following ISA signals from 330 Ohms to 1K: ZEROWS#, MEMCS16#, IOCS16#.

5. (6/27/97) There is no internal pull-up or down on PDD7 or SDD7 of the PIIX4. The ATA3 specification requires a 10K ohm pull-down on DD7 in section 4.3.1. Devices shall not have a pull-up
resistor on DD7. It is recommended that a host have a 10K ohm pull-down resistor on PDD7 and SDD7 to allow the host to recognize the absence of a device at power-up. It is intended that this
recommendation become mandatory in the next revision of this standard.

2 2

1 1

INTEL CORPORATION

Title
TX DESKTOP REVISION HISTORY

Size Document Number Rev

2.1

Date: Thursday, December 19, 1996 Sheet of

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