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Philips 40pfl9605d 78
Philips 40pfl9605d 78
Q551.1L
LA
18941_000_100917.eps
100928
©
Copyright 2010 Koninklijke Philips Electronics N.V.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.
Published by ER-MB/EL 1069 BU TV Consumer Care, the Netherlands Subject to modification EN 3122 785 18941
2010-Oct-01
EN 2 1. Q551.1L LA Revision List
1. Revision List
Manual xxxx xxx xxxx.0 • All chapters: added CTNs to the manual, see Table 2-1.
• First release. • Chapter 5: added section 5.8.3 AV PIP.
Manual xxxx xxx xxxx.1
Notes:
• Figures can deviate due to the different set executions. 2.2 Technical Specifications
• Specifications are indicative (subject to change).
For on-line product support please use the CTN links in Table
2-1. Here is product information available, as well as getting
started, user manuals, frequently asked questions and
software & drivers.
SSB 2 4 7 9 10
Mecha-
nics Descriptions Schematics
CTN Styling
40PFL9605D/78 Monet 64512 2.3 4-1 4.4 7.2 7.5.2 7.10 - 9-1 10-1 10-4 10-7 10-9 10-11 10-13 10-15 10-16 - - 10-18 - - - -
11-1 64513 10-2 10-5 10-8 10-10 10-12 10-14 10-17
58PFL9955D/78 Rubens 64512 2.3 4-1 4.5 7.2 7.5.2 7.10 - 9-2 10-1 10-4 10-7 10-9 10-11 10-13 10-15 10-16 - - 10-18 - - - 10-22
11-2 64513 10-2 10-5 10-8 10-10 10-12 10-14 10-17
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Technical Specifications, and Connections Q551.1L LA 2. EN 3
2.3 Connections
4 3 5 6 7 8
1
9 10 11 11 12 13 14 15
18940_001_100811.eps
100811
Note: The following connector color abbreviations are used 12 - CLK- Data channel j
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= 13 - Easylink/CEC Control channel jk
Grey, Rd= Red, Wh= White, Ye= Yellow. 14 - n.c.
15 - DDC_SCL DDC clock j
2.3.1 Side Connections 16 - DDC_SDA DDC data jk
17 - Ground Gnd H
18 - +5V j
1 - USB2.0
19 - HPD Hot Plug Detect j
20 - Ground Gnd H
1 2 3 4
10000_022_090121.eps 2.3.2 Rear Connections
090121
12345678
1 - +5V k
2 - Data (-) jk
3 - Data (+) jk
4 - Ground Gnd H 10000_025_090121.eps
090121
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EN 4 2. Q551.1L LA Technical Specifications, and Connections
12 - HDMI 1: Digital Video - In, Digital Audio with ARC - In/ Figure 2-6 VGA Connector
Out
1 - Video Red 0.7 VPP / 75 ohm j
19 1
18 2
2 - Video Green 0.7 VPP / 75 ohm j
3 - Video Blue 0.7 VPP / 75 ohm j
10000_017_090121.eps
090428 4 - n.c.
5 - Ground Gnd H
Figure 2-5 HDMI (type A) connector 6 - Ground Red Gnd H
7 - Ground Green Gnd H
1 - D2+ Data channel j 8 - Ground Blue Gnd H
2 - Shield Gnd H 9 - +5VDC +5 V j
3 - D2- Data channel j 10 - Ground Sync Gnd H
4 - D1+ Data channel j 11 - n.c.
5 - Shield Gnd H 12 - DDC_SDA DDC data j
6 - D1- Data channel j 13 - H-sync 0-5V j
7 - D0+ Data channel j 14 - V-sync 0-5V j
8 - Shield Gnd H 15 - DDC_SCL DDC clock j
9 - D0- Data channel j
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Precautions, Notes, and Abbreviation List Q551.1L LA 3. EN 5
The third digit in the serial number (example: 3.4 Abbreviation List
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the 0/6/12 SCART switch control signal on A/V
specific TV set. In general, it is possible that the same TV
board. 0 = loop through (AUX to TV),
model on the market is produced with e.g. two different types
6 = play 16 : 9 format, 12 = play 4 : 3
of displays, coming from two different suppliers. This will then format
result in sets which have the same CTN (Commercial Type
AARA Automatic Aspect Ratio Adaptation:
Number; e.g. 28PW9515/12) but which have a different B.O.M.
algorithm that adapts aspect ratio to
number. remove horizontal black bars; keeps
By looking at the third digit of the serial number, one can
the original aspect ratio
identify which B.O.M. is used for the TV set he is working with.
ACI Automatic Channel Installation:
If the third digit of the serial number contains the number “1” algorithm that installs TV channels
(example: AG1B033500001), then the TV set has been
directly from a cable network by
manufactured according to B.O.M. number 1. If the third digit is
means of a predefined TXT page
a “2” (example: AG2B0335000001), then the set has been ADC Analogue to Digital Converter
produced according to B.O.M. no. 2. This is important for
AFC Automatic Frequency Control: control
ordering the correct spare parts!
signal used to tune to the correct
For the third digit, the numbers 1...9 and the characters A...Z frequency
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
AGC Automatic Gain Control: algorithm that
indicated by the third digit of the serial number.
controls the video input of the feature
box
Identification: The bottom line of a type plate gives a 14-digit AM Amplitude Modulation
serial number. Digits 1 and 2 refer to the production centre (e.g. AP Asia Pacific
AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers AR Aspect Ratio: 4 by 3 or 16 by 9
to the Service version change code, digits 5 and 6 refer to the ASF Auto Screen Fit: algorithm that adapts
production year, and digits 7 and 8 refer to production week (in aspect ratio to remove horizontal black
example below it is 2006 week 17). The 6 last digits contain the bars without discarding video
serial number. information
ATSC Advanced Television Systems
MODEL : 32PF9968/10 MADE IN BELGIUM Committee, the digital TV standard in
220-240V ~ 50/60Hz the USA
128W
ATV See Auto TV
PROD.NO: AG 1A0617 000001 VHF+S+H+UHF
Auto TV A hardware and software control
S BJ3.0E LA system that measures picture content,
and adapts image parameters in a
10000_024_090121.eps dynamic way
100105
AV External Audio Video
AVC Audio Video Controller
Figure 3-1 Serial number (example)
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound
3.3.7 Board Level Repair (BLR) or Component Level Repair carrier distance is 5.5 MHz
(CLR) BDS Business Display Solutions (iTV)
BLR Board-Level Repair
If a board is defective, consult your repair procedure to decide BTSC Broadcast Television Standard
if the board has to be exchanged or if it should be repaired on Committee. Multiplex FM stereo sound
component level. system, originating from the USA and
If your repair procedure says the board should be exchanged used e.g. in LATAM and AP-NTSC
completely, do not solder on the defective board. Otherwise, it countries
cannot be returned to the O.E.M. supplier for back charging! B-TXT Blue TeleteXT
C Centre channel (audio)
3.3.8 Practical Service Precautions CEC Consumer Electronics Control bus:
remote control bus on HDMI
• It makes sense to avoid exposure to electrical shock. connections
While some sources are expected to have a possible CL Constant Level: audio output to
dangerous impact, others of quite high potential are of connect with an external amplifier
limited current and are sometimes held in less regard. CLR Component Level Repair
• Always respect voltages. While some may not be ComPair Computer aided rePair
dangerous in themselves, they can cause unexpected CP Connected Planet / Copy Protection
reactions that are best avoided. Before reaching into a CSM Customer Service Mode
powered TV set, it is best to test the high voltage insulation. CTI Color Transient Improvement:
It is easy to do, and is a good service precaution. manipulates steepness of chroma
transients
CVBS Composite Video Blanking and
Synchronization
DAC Digital to Analogue Converter
DBE Dynamic Bass Enhancement: extra
low frequency amplification
DCM Data Communication Module. Also
referred to as System Card or
Smartcard (for iTV).
DDC See “E-DDC”
D/K Monochrome TV system. Sound
carrier distance is 6.5 MHz
DFI Dynamic Frame Insertion
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Precautions, Notes, and Abbreviation List Q551.1L LA 3. EN 7
DFU Directions For Use: owner's manual SDI), is a digitized video format used
DMR Digital Media Reader: card reader for broadcast grade video.
DMSD Digital Multi Standard Decoding Uncompressed digital component or
DNM Digital Natural Motion digital composite signals can be used.
DNR Digital Noise Reduction: noise The SDI signal is self-synchronizing,
reduction feature of the set uses 8 bit or 10 bit data words, and has
DRAM Dynamic RAM a maximum data rate of 270 Mbit/s,
DRM Digital Rights Management with a minimum bandwidth of 135
DSP Digital Signal Processing MHz.
DST Dealer Service Tool: special remote ITV Institutional TeleVision; TV sets for
control designed for service hotels, hospitals etc.
technicians LS Last Status; The settings last chosen
DTCP Digital Transmission Content by the customer and read and stored
Protection; A protocol for protecting in RAM or in the NVM. They are called
digital audio/video content that is at start-up of the set to configure it
traversing a high speed serial bus, according to the customer's
such as IEEE-1394 preferences
DVB-C Digital Video Broadcast - Cable LATAM Latin America
DVB-T Digital Video Broadcast - Terrestrial LCD Liquid Crystal Display
DVD Digital Versatile Disc LED Light Emitting Diode
DVI(-d) Digital Visual Interface (d= digital only) L/L' Monochrome TV system. Sound
E-DDC Enhanced Display Data Channel carrier distance is 6.5 MHz. L' is Band
(VESA standard for communication I, L is all bands except for Band I
channel and display). Using E-DDC, LPL LG.Philips LCD (supplier)
the video source can read the EDID LS Loudspeaker
information form the display. LVDS Low Voltage Differential Signalling
EDID Extended Display Identification Data Mbps Mega bits per second
(VESA standard) M/N Monochrome TV system. Sound
EEPROM Electrically Erasable and carrier distance is 4.5 MHz
Programmable Read Only Memory MHEG Part of a set of international standards
EMI Electro Magnetic Interference related to the presentation of
EPG Electronic Program Guide multimedia information, standardised
EPLD Erasable Programmable Logic Device by the Multimedia and Hypermedia
EU Europe Experts Group. It is commonly used as
EXT EXTernal (source), entering the set by a language to describe interactive
SCART or by cinches (jacks) television services
FDS Full Dual Screen (same as FDW) MIPS Microprocessor without Interlocked
FDW Full Dual Window (same as FDS) Pipeline-Stages; A RISC-based
FLASH FLASH memory microprocessor
FM Field Memory or Frequency MOP Matrix Output Processor
Modulation MOSFET Metal Oxide Silicon Field Effect
FPGA Field-Programmable Gate Array Transistor, switching device
FTV Flat TeleVision MPEG Motion Pictures Experts Group
Gb/s Giga bits per second MPIF Multi Platform InterFace
G-TXT Green TeleteXT MUTE MUTE Line
H H_sync to the module MTV Mainstream TV: TV-mode with
HD High Definition Consumer TV features enabled (iTV)
HDD Hard Disk Drive NC Not Connected
HDCP High-bandwidth Digital Content NICAM Near Instantaneous Compounded
Protection: A “key” encoded into the Audio Multiplexing. This is a digital
HDMI/DVI signal that prevents video sound system, mainly used in Europe.
data piracy. If a source is HDCP coded NTC Negative Temperature Coefficient,
and connected via HDMI/DVI without non-linear resistor
the proper HDCP decoding, the NTSC National Television Standard
picture is put into a “snow vision” mode Committee. Color system mainly used
or changed to a low resolution. For in North America and Japan. Color
normal content distribution the source carrier NTSC M/N= 3.579545 MHz,
and the display device must be NTSC 4.43= 4.433619 MHz (this is a
enabled for HDCP “software key” VCR norm, it is not transmitted off-air)
decoding. NVM Non-Volatile Memory: IC containing
HDMI High Definition Multimedia Interface TV related data such as alignments
HP HeadPhone O/C Open Circuit
I Monochrome TV system. Sound OSD On Screen Display
carrier distance is 6.0 MHz OAD Over the Air Download. Method of
I2 C Inter IC bus software upgrade via RF transmission.
I2 D Inter IC Data bus Upgrade software is broadcasted in
I2 S Inter IC Sound bus TS with TV channels.
IF Intermediate Frequency OTC On screen display Teletext and
IR Infra Red Control; also called Artistic (SAA5800)
IRQ Interrupt Request P50 Project 50: communication protocol
ITU-656 The ITU Radio communication Sector between TV and peripherals
(ITU-R) is a standards body PAL Phase Alternating Line. Color system
subcommittee of the International mainly used in West Europe (color
Telecommunication Union relating to carrier= 4.433619 MHz) and South
radio communication. ITU-656 (a.k.a. America (color carrier PAL M=
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EN 8 3. Q551.1L LA Precautions, Notes, and Abbreviation List
3.575612 MHz and PAL N= 3.582056 SVHS Super Video Home System
MHz) SW Software
PCB Printed Circuit Board (same as “PWB”) SWAN Spatial temporal Weighted Averaging
PCM Pulse Code Modulation Noise reduction
PDP Plasma Display Panel SXGA 1280 × 1024
PFC Power Factor Corrector (or Pre- TFT Thin Film Transistor
conditioner) THD Total Harmonic Distortion
PIP Picture In Picture TMDS Transmission Minimized Differential
PLL Phase Locked Loop. Used for e.g. Signalling
FST tuning systems. The customer TS Transport Stream
can give directly the desired frequency TXT TeleteXT
POD Point Of Deployment: a removable TXT-DW Dual Window with TeleteXT
CAM module, implementing the CA UI User Interface
system for a host (e.g. a TV-set) uP Microprocessor
POR Power On Reset, signal to reset the uP UXGA 1600 × 1200 (4:3)
PSDL Power Supply for Direct view LED V V-sync to the module
backlight with 2D-dimming VESA Video Electronics Standards
PSL Power Supply with integrated LED Association
drivers VGA 640 × 480 (4:3)
PSLS Power Supply with integrated LED VL Variable Level out: processed audio
drivers with added Scanning output toward external amplifier
functionality VSB Vestigial Side Band; modulation
PTC Positive Temperature Coefficient, method
non-linear resistor WYSIWYR What You See Is What You Record:
PWB Printed Wiring Board (same as “PCB”) record selection that follows main
PWM Pulse Width Modulation picture and sound
QRC Quasi Resonant Converter WXGA 1280 × 768 (15:9)
QTNR Quality Temporal Noise Reduction XTAL Quartz crystal
QVCP Quality Video Composition Processor XGA 1024 × 768 (4:3)
RAM Random Access Memory Y Luminance signal
RGB Red, Green, and Blue. The primary Y/C Luminance (Y) and Chrominance (C)
color signals for TV. By mixing levels signal
of R, G, and B, all colors (Y/C) are YPbPr Component video. Luminance and
reproduced. scaled color difference signals (B-Y
RC Remote Control and R-Y)
RC5 / RC6 Signal protocol from the remote YUV Component video
control receiver
RESET RESET signal
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs
SCL Serial Clock I2C
SCL-F CLock Signal on Fast I2C bus
SD Standard Definition
SDA Serial Data I2C
SDA-F DAta Signal on Fast I2C bus
SDI Serial Digital Interface, see “ITU-656”
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mémoire.
Color system mainly used in France
and East Europe. Color carriers=
4.406250 MHz and 4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link
standard
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
SSC Spread Spectrum Clocking, used to
reduce the effects of EMI
STB Set Top Box
STBY STand-BY
SVGA 800 × 600 (4:3)
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Mechanical Instructions Q551.1L LA 4. EN 9
4. Mechanical Instructions
Index of this chapter:
4.1 Cable Dressing Monet Styling (9605-series)
4.2 Cable Dressing Rubens 21:9 Styling (9955-series)
4.3 Service Positions
4.4 Assy/Panel Removal Monet Styling
4.5 Assy/Panel Removal Rubens 21:9 Styling
4.6 Set Re-assembly
Notes:
• Figures below can deviate slightly from the actual situation,
due to the different set executions.
18760_100_100809.eps
100813
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EN 10 4. Q551.1L LA Mechanical Instructions
18754_113_100930.eps
100930
Note: picture taken from European model with additional 4.4.4 Main Power Supply
panels.
Refer to Figure 4-3 for details.
4.3 Service Positions
1
For easy servicing of a TV set, the set should be put face down 2 2
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the
display. Caution: Failure to follow these guidelines can
seriously damage the display!
Ensure that ESD safe measures are taken.
2 2
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Mechanical Instructions Q551.1L LA 4. EN 11
1 1
2
3
3
2 2
3
2
18750_106_100415.eps
3 100415
5 4 5
18750_103_100414.eps Figure 4-7 IR & LED board [2/2]
100414
18750_104_100414.eps
100414
1 1
1 1 1 1
18750_105_100414.eps
100414
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EN 12 4. Q551.1L LA Mechanical Instructions
Refer to Figure 4-8 to Figure 4-10 for details. The instructions apply to the 58PFL9955x/xx.
Note: pictures taken from European model (with additional
1 1 1 1 panels).
1
1 4.5.1 Rear Cover
18750_108_100415.eps
100415
18750_109_100415.eps
100528
When remounting, ensure that the clips are not bent open!
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Mechanical Instructions Q551.1L LA 4. EN 13
3
2 2 3
2
1 1
1
3
2 2 2
3
4 4
18750_111_100415.eps
100415
2 2
Figure 4-12 SSB
1 1
2 2
2 2 2 2
18754_108_100923.eps
100923
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EN 14 4. Q551.1L LA Mechanical Instructions
18754_109_100923.eps
100923
18750_116_100415.eps
1 1 100415
2
3 3
1 1
18754_110_100924.eps
100924
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Mechanical Instructions Q551.1L LA 4. EN 15
Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position.
• Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.
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EN 16 5. Q551.1L LA Service Modes, Error Codes, and Fault Finding
Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the
activation of the Service modes. For instance the old “MENU”
button is now called “HOME” (or is indicated by a “house” icon).
Purpose
• To create a pre-defined setting, to get the same
measurement results as given in this manual.
• To override SW protections detected by stand-by
processor and make the TV start up to the step just before
protection (a sort of automatic stepwise start-up). See
18770_249_100215.eps
section “5.3 Stepwise Start-up”. 100407
• To start the blinking LED procedure where only LAYER 2
errors are displayed. (see also section “5.5 Error Codes”). Figure 5-1 Service mode pad
Specifications After activating this mode, “SDM” will appear in the upper right
corner of the screen (when a picture is available).
Table 5-1 SDM default settings
How to Navigate
Default When the “MENU” (or “HOME”) button is pressed on the RC
Region Freq. (MHz) system transmitter, the TV set will toggle between the SDM and the
normal user menu.
Europe, AP(PAL/Multi) 475.25 PAL B/G
Europe, AP DVB-T 546.00 PID DVB-T
How to Exit SDM
Video: 0B 06 PID
Use one of the following methods:
PCR: 0B 06 PID
• Switch the set to STAND-BY via the RC-transmitter.
Audio: 0B 07
• Via a standard customer RC-transmitter: key in “00”-
sequence.
• All picture settings at 50% (brightness, color, contrast).
• Sound volume at 25%.
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Service Modes, Error Codes, and Fault Finding Q551.1L LA 5. EN 17
5.2.2 Service Alignment Mode (SAM) button and “XXX” (where XXX is the 3 digit decimal display
code as mentioned on the sticker in the set). Make sure to key
Purpose in all three digits, also the leading zero’s. If the above action is
• To perform (software) alignments. successful, the front LED will go out as an indication that the
• To change option settings. RC sequence was correct. After the display option is changed
• To easily identify the used software version. in the NVM, the TV will go to the Stand-by mode. If the NVM
• To view operation hours. was corrupted or empty before this action, it will be initialized
• To display (or clear) the error code buffer. first (loaded with default values). This initializing can take up to
20 seconds.
How to Activate SAM
Via a standard RC transmitter: Key in the code “062596”
directly followed by the “INFO” or “OK” button. After activating
SAM with this method a service warning will appear on the
Display Option
screen, continue by pressing the “OK” button on the RC. Code
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EN 18 5. Q551.1L LA Service Modes, Error Codes, and Fault Finding
• NVM editor. For NET TV the set “type number” must be How to Activate CSM
entered correctly.
Also the production code (AG code) can be entered here Key in the code “123654” via the standard RC transmitter.
via the RC-transmitter. Note: Activation of the CSM is only possible if there is no (user)
Correct data can be found on the side/rear sticker. menu on the screen!
When CSM is activated and there is a USB stick connected to Software versions
the TV set, the software will dump the CSM content to the USB • Current main SW. Displays the build-in main software
stick. The file (CSM_model number_serial number.txt) will be version. In case of field problems related to software,
saved in the root of the USB stick. This info can be handy if no software can be upgraded. As this software is consumer
information is displayed. upgradeable, it will also be published on the Internet.
Example: Q55xx1.2.3.4
When in CSM mode (and a USB stick connected), pressing • Stand-by SW. Displays the built-in stand-by processor
“OK” will create an extended CSM dump file on the USB stick. software version. Upgrading this software will be possible
This file (Extended_CSM_model number_serial number.txt) via ComPair or via USB (see section 5.9 Software
contains: Upgrading).
• The normal CSM dump information, Example: STDBY_88.68.1.2.
• All items (from SAM “load to USB”, but in readable format), • e-UM version. Displays the electronic user manual SW-
• Operating hours, version (12NC version number). Most significant number
• Error codes, here is the last digit.
• SW/HW event logs. • AV PIP software.
• 3D dongle software version.
To have fast feedback from the field, a flashdump can be
requested by development. When in CSM, push the “red” Quality items
button and key in serial digits ‘2679’ (same keys to form the • Signal quality. Bad / average /good (not for DVB-S).
word ‘COPY’ with a cellphone). A file “Dump_model • Ethernet MAC address. Displays the MAC address
number_serial number.bin” will be written on the connected present in the SSB.
USB device. This can take 1/2 minute, depending on the • Wireless MAC address. Displays the wireless MAC
quantity of data that needs to be dumped. address to support the Wi-Fi functionality.
• BDS key. Indicates if the set is in the BDS status.
Also when CSM is activated, the LAYER 1 error is displayed via • CI module. Displays status if the common interface
blinking LED. Only the latest error is displayed (see also module is detected.
section 5.5 Error Codes). • CI + protected service. Yes/No.
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Service Modes, Error Codes, and Fault Finding Q551.1L LA 5. EN 19
Mains
off Mains
on
- WakeUp requested
WakeUp
- Acquisition needed
requested
- Tact switch pushed
St by Semi
- stby requested and Active
no data Acquisition St by - St by requested
required - tact SW pushed
Tact switch
pushed
WakeUp
requested
- Tact switch pushed
(SDM)
- last status is hibernate
GoToProtection
after mains ON
Hibernate
GoToProtection
Protection
18770_250_100216.eps
100402
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EN 20 5. Q551.1L LA Service Modes, Error Codes, and Fault Finding
Off
Mains is applied
Stand by or
Protection
Standby Supply starts running.
All standby supply voltages become available.
st-by μP resets
Yes
Enter protection
Enable the DCDC converters
(ENABLE-3V3n LOW)
Wait 50ms
EJTAG probe
Yes
connected ?
No
No No Cold boot?
Yes
Release AVC system reset Release AVC system reset Release AVC system reset
Feed warm boot script Feed cold boot script Feed initializing boot script
disable alive mechanism
18770_251_100216.eps
100216
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Service Modes, Error Codes, and Fault Finding Q551.1L LA 5. EN 21
No
AVC releases Reset-Ethernet, Reset-USB and AVC releases Reset-Ethernet, Reset-USB and
This cannot be done through the bootscript, Reset-DVBs when the end of the AVC boot- Reset-DVBs when the end of the AVC boot-
the I/O is on the standby μP script is detected script is detected
Bootscript ready
No
in 1250 ms?
Yes
yes
Switch Standby I/O line high
3-th try?
and wait 4 seconds
The first time after the option turn on of the startup screen or
Startup screen cfg file when the set is virgin, the cfg file is not present and hence
present? the startup screen will not be shown.
Yes
yes
Blink Code as
error code
200Hz set? yes
No
Enter protection
85500 sends out startup screen 85500 sends out startup screen
No
200Hz Tcon has started up the
85500 starts up the display.
display.
No
To keep this flowchart readable, the exact Startup screen visible 85500 requests Lamp on
display turn on description is not copied
here. Please see the Semi-standby to On
description for the detailed display startup
Startup screen visible
During the complete display time of the
Startup screen, the preheat condition of
sequence.
100% PWM is valid. Initialize audio
Semi-Standby
18770_252_100216.eps
100216
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EN 22 5. Q551.1L LA Service Modes, Error Codes, and Fault Finding
The assumption here is that a fast toggle (<2s) can Semi Standby
only happen during ON->SEMI ->ON. In these states,
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STBY->SEMI->ON cannot be
Wait until previous on-state is left more than 2
made in less than 2s, because the standby state will
seconds ago. (to prevent LCD display problems)
be maintained for at least 4s.
No
Start POK line Wait until valid and stable audio and video, corresponding to the
detection algorithm requested output is delivered by the AVC
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time.
return
Yes
Active
18770_253_100216.eps
100216
Figure 5-6 “Semi Stand-by” to “Active” flowchart (EEFL or LED backlight 50/100 Hz only)
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Service Modes, Error Codes, and Fault Finding Q551.1L LA 5. EN 23
return
Switch Audio-Reset low and wait 5ms
Release audio mute and wait 100ms before any other audio
The higher level requirement is that audio and handling is done (e.g. volume change)
video should be demuted without transient
effects and that the audio should be demuted
maximum 1s before or at the same time as the
unblank the video.
unblanking of the video.
Yes
Active
18770_254_100216.eps
100216
Figure 5-7 “Semi Stand-by” to “Active” flowchart (LED backlight 200 Hz)
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EN 24 5. Q551.1L LA Service Modes, Error Codes, and Fault Finding
Active
Wait 100ms
No
Instruct 200Hz
The exact timings to
Tcon to turn off Switch off LVDS output in 85500
switch off the
the display
display (LVDS
delay, lamp delay)
Wait x ms
are defined in the
display file.
Semi Standby
18770_255_100216.eps
100216
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Service Modes, Error Codes, and Fault Finding Q551.1L LA 5. EN 25
Semi Stand by
Delay transition until ramping down of ambient light is *) If this is not performed and the set is
finished. *) switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.
Wait 10ms
Wait 5ms
Important remarks:
18770_256_100216.eps
100216
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EN 26 5. Q551.1L LA Service Modes, Error Codes, and Fault Finding
Introduction The error code buffer contains all detected errors since the last
ComPair (Computer Aided Repair) is a Service tool for Philips time the buffer was erased. The buffer is written from left to
Consumer Electronics products. and offers the following: right, new errors are logged at the left side, and all other errors
1. ComPair helps to quickly get an understanding on how to shift one position to the right.
repair the chassis in a short and effective way. When an error occurs, it is added to the list of errors, provided
2. ComPair allows very detailed diagnostics and is therefore the list is not full. When an error occurs and the error buffer is
capable of accurately indicating problem areas. No full, then the new error is not added, and the error buffer stays
knowledge on I2C or UART commands is necessary, intact (history is maintained).
because ComPair takes care of this. To prevent that an occasional error stays in the list forever, the
3. ComPair speeds up the repair time since it can error is removed from the list after more than 50 hrs. of
automatically communicate with the chassis (when the μP operation.
is working) and all repair information is directly available. When multiple errors occur (errors occurred within a short time
4. ComPair features TV software up possibilities. span), there is a high probability that there is some relation
between them.
Specifications
ComPair consists of a Windows based fault finding program New in this chassis is the way errors can be displayed:
and an interface box between PC and the (defective) product.
The ComPair II interface box is connected to the PC via an • If no errors are there, the LED should not blink at all in
USB cable. For the TV chassis, the ComPair interface box and CSM or SDM. No spacer must be displayed as well.
the TV communicate via a bi-directional cable via the service • There is a simple blinking LED procedure for board
connector(s). level repair (home repair) so called LAYER 1 errors
The ComPair fault finding program is able to determine the next to the existing errors which are LAYER 2 errors (see
problem of the defective television, by a combination of Table 5-2).
automatic diagnostics and an interactive question/answer – LAYER 1 errors are one digit errors.
procedure. – LAYER 2 errors are 2 digit errors.
• In protection mode.
– From consumer mode: LAYER 1.
How to Connect
– From SDM mode: LAYER 2.
This is described in the chassis fault finding database in
ComPair. • Fatal errors, if I2C bus is blocked and the set reboots,
CSM and SAM are not selectable.
– From consumer mode: LAYER 1.
TO TV
– From SDM mode: LAYER 2.
TO TO TO
UART SERVICE I2C SERVICE UART SERVICE • In CSM mode.
CONNECTOR CONNECTOR CONNECTOR
– When entering CSM: error LAYER 1 will be displayed
by blinking LED. Only the latest error is shown.
ComPair II • In SDM mode.
Multi
RC in function
RC out
– When SDM is entered via Remote Control code or the
hardware pins, LAYER 2 is displayed via blinking LED.
Optional Power Link/ Mode
Switch Activity I2C RS232 /UART
• Error display on screen.
– In CSM no error codes are displayed on screen.
– In SAM the complete error list is shown.
PC
Basically there are three kinds of errors:
• Errors detected by the Stand-by software which lead to
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section “5.6 The Blinking LED Procedure”).
ComPair II Developed by Philips Brugge
• Errors detected by the Stand-by software which not
Optional power
HDMI 5V DC lead to protection. In this case the front LED should blink
I2C only
the involved error. See also section “5.5 Error Codes, 5.5.4
Error Buffer”. Note that it can take up several minutes
10000_036_090121.eps
091118 before the TV starts blinking the error (e.g. LAYER 1
error = 2, LAYER 2 error = 15 or 53).
Figure 5-10 ComPair II interface connection • Errors detected by main software (MIPS). In this case
the error will be logged into the error buffer and can be read
Caution: It is compulsory to connect the TV to the PC as out via ComPair, via blinking LED method LAYER 1-2
shown in the picture above (with the ComPair interface in error, or in case picture is visible, via SAM.
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs can be 5.5.2 How to Read the Error Buffer
blown!
Use one of the following methods:
How to Order • On screen via the SAM (only when a picture is visible).
ComPair II order codes: E.g.:
• ComPair II interface: 3122 785 91020. – 00 00 00 00 00: No errors detected
• Software is available via the Philips Service web portal. – 23 00 00 00 00: Error code 23 is the last and only
• ComPair UART interface cable for Q55x.x. detected error.
(using 3.5 mm Mini Jack connector): 3138 188 75051. – 37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.
Note: When you encounter problems, contact your local – Note that no protection errors can be logged in the
support desk. error buffer.
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Service Modes, Error Codes, and Fault Finding Q551.1L LA 5. EN 27
• Via the blinking LED procedure. See section 5.5.3 How to content, as this history can give significant information). This to
Clear the Error Buffer. ensure that old error codes are no longer present.
• Via ComPair. If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
5.5.3 How to Clear the Error Buffer code and not the actual cause (e.g. a fault in the protection
detection circuitry can also lead to a protection).
There are several mechanisms of error detection:
Use one of the following methods:
• Via error bits in the status registers of ICs.
• By activation of the “RESET ERROR BUFFER” command
in the SAM menu. • Via polling on I/O pins going to the stand-by processor.
• Via sensing of analog values on the stand-by processor or
• If the content of the error buffer has not changed for 50+
the PNX85500.
hours, it resets automatically.
• Via a “not acknowledge” of an I2C communication.
Extra Info Other root causes for this error can be due to hardware
• Rebooting. When a TV is constantly rebooting due to problems regarding the DDR’s and the bootscript reading
internal problems, most of the time no errors will be logged from the PNX8550.
or blinked. This rebooting can be recognized via a ComPair • Error 16 (12V). This voltage is made in the power supply
interface and Hyperterminal (for Hyperterminal settings, and results in protection (LAYER 1 error = 3) in case of
see section “5.8 Fault Finding and Repair Tips, 5.8.7 absence. When SDM is activated we see blinking LED
Logging). It’s shown that the loggings which are generated LAYER 2 error = 16.
by the main software keep continuing. In this case • Error 17 (Invertor or Display Supply). Here the status of
diagnose has to be done via ComPair. the “Power OK” is checked by software, no protection will
• Error 13 (I2C bus 3, SSB bus blocked). Current situation: occur during failure of the invertor or display supply (no
when this error occurs, the TV will constantly reboot due to picture), only error logging. LED blinking of LAYER 1
the blocked bus. The best way for further diagnosis here, is error = 3 in CSM, in SDM this gives LAYER 2 error = 17.
to use ComPair. • Error 21 (PNX51X0). When there is no I2C communication
• Error 14 (I2C bus 2, TV set bus blocked). Current towards the PNX51X0 after start-up, LAYER 2 error = 21
situation: when this error occurs, the TV will constantly will be logged and displayed via the blinking LED
reboot due to the blocked bus. The best way for further procedure if SDM is switched on. This device is located on
diagnosis here, is to use ComPair. the 200 Hz panel from the display.
• Error 18 (I2C bus 4, Tuner bus blocked). In case this bus • Error 23 (HDMI). When there is no I2C communication
is blocked, short the “SDM” solder paths on the SSB during towards the HDMI mux after start-up, LAYER 2 error = 23
startup, LAYER error 2 = 18 will be blinked. will be logged and displayed via the blinking LED
• Error 15 (PNX8550 doesn’t boot). Indicates that the main procedure if SDM is switched on.
processor was not able to read his bootscript. This error will • Error 24 (I2C switch). When there is no I2C
point to a hardware problem around the PNX8550 communication towards the I2C switch, LAYER 2
(supplies not OK, PNX 8550 completely dead, I2C link error = 24 will be logged and displayed via the blinking LED
between PNX and Stand-by Processor broken, etc...). procedure when SDM is switched on. Remark: this only
When error 15 occurs it is also possible that I2C1 bus is works for TV sets with an I2C controlled screen included.
blocked (NVM). I2C1 can be indicated in the schematics as • Error 28 (Channel dec DVB-S). When there is no I2C
follows: SCL-UP-MIPS, SDA-UP-MIPS. communication towards the DVB-S channel decoder,
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EN 28 5. Q551.1L LA Service Modes, Error Codes, and Fault Finding
LAYER 2 error = 28 will be logged and displayed via the 2. Two short blinks of 250 ms followed by a pause of 3 s
blinking LED procedure if SDM is switched on. 3. Eight short blinks followed by a pause of 3 s
• Error 31 (Lnb controller). When there is no I2C 4. Six short blinks followed by a pause of 3 s
communication towards this device, LAYER 2 error = 31 5. One long blink of 3 s to finish the sequence (spacer).
will be logged and displayed via the blinking LED 6. The sequence starts again.
procedure if SDM is activated.
• Error 34 (Tuner). When there is no I2C communication 5.6.2 How to Activate
towards the tuner during start-up, LAYER 2 error = 34 will
be logged and displayed via the blinking LED procedure Use one of the following methods:
when SDM is switched on.
• Activate the CSM. The blinking front LED will show only
• Error 35 (main NVM). When there is no I2C
the latest layer 1 error, this works in “normal operation”
communication towards the main NVM during start-up, mode or automatically when the error/protection is
LAYER 2 error = 35 will be displayed via the blinking LED
monitored by the Stand-by processor.
procedure when SDM is switched “on”. All service modes
In case no picture is shown and there is no LED blinking,
(CSM, SAM and SDM) are accessible during this failure, read the logging to detect whether “error devices” are
observed in the UART logging as follows: "<< ERRO >>>
mentioned. (see section “5.8 Fault Finding and Repair
PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)".
Tips, 5.8.7 Logging”).
• Error 36 (Tuner DVB-S). When there is no I2C • Activate the SDM. The blinking front LED will show the
communication towards the DVB-S tuner during start-up,
entire content of the LAYER 2 error buffer, this works in
LAYER 2 error = 36 will be logged and displayed via the
“normal operation” mode or when SDM (via hardware pins)
blinking LED procedure when SDM is switched “on”. is activated when the tv set is in protection.
• Error 42 (Temp sensor). Only applicable for TV sets
equipped with temperature devices.
• Error 53. This error will indicate that the PNX8550 has 5.7 Protections
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because 5.7.1 Software Protections
of hardware problems (NAND flash, ...) or software
initialization problems. Possible cause could be that there
Most of the protections and errors use either the stand-by
is no valid software loaded (try to upgrade to the latest main
microprocessor or the MIPS controller as detection device.
software version). Note that it can take a few minutes
Since in these cases, checking of observers, polling of ADCs,
before the TV starts blinking LAYER 1 error = 2 or in SDM,
and filtering of input values are all heavily software based,
LAYER 2 error = 53.
these protections are referred to as software protections.
• Error 64. Only applicable for TV sets with an I2C controlled
There are several types of software related protections, solving
screen.
a variety of fault conditions:
• Related to supplies: presence of the +5V, +3V3 and 1V2
5.6 The Blinking LED Procedure needs to be measured, no protection triggered here.
• Protections related to breakdown of the safety check
5.6.1 Introduction mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
The blinking LED procedure can be split up into two situations:
guaranteed any more.
• Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
Remark on the Supply Errors
This will be only one digit error, namely the one that is
The detection of a supply dip or supply loss during the normal
referring to the defective board (see table “5-2 Error code
overview”) which causes the failure of the TV. This playing of the set does not lead to a protection, but to a cold
reboot of the set. If the supply is still missing after the reboot,
approach will especially be used for home repair and call
the TV will go to protection.
centres. The aim here is to have service diagnosis from a
distance.
• Blinking LED procedure LAYER 2 error. Via this Protections during Start-up
procedure, the contents of the error buffer can be made During TV start-up, some voltages and IC observers are
visible via the front LED. In this case the error contains actively monitored to be able to optimize the start-up speed,
2 digits (see table “5-2 Error code overview”) and will be and to assure good operation of all components. If these
displayed when SDM (hardware pins) is activated. This is monitors do not respond in a defined way, this indicates a
especially useful for fault finding and gives more details malfunction of the system and leads to a protection. As the
regarding the failure of the defective board. observers are only used during start-up, they are described in
Important remark: the start-up flow in detail (see section “5.3 Stepwise Start-up”).
For an empty error buffer, the LED should not blink at all in
CSM or SDM. No spacer will be displayed. 5.7.2 Hardware Protections
When one of the blinking LED procedures is activated, the front The only real hardware protection in this chassis appears in
LED will show (blink) the contents of the error buffer. Error case of an audio problem e.g. DC voltage on the speakers. This
codes greater then 10 are shown as follows: protection will only affect the Class D audio amplifier (item
1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit 7D10; see diagram B03A) and puts the amplifier in a
2. A pause of 1.5 s continuous burst mode (cyclus approximately 2 seconds).
3. “n” short blinks (where “n”= 1 to 9)
4. A pause of approximately 3 s, Repair Tip
5. When all the error codes are displayed, the sequence • There still will be a picture available but no sound. While
finishes with a LED blink of 3 s (spacer). the Class D amplifier tries to start-up again, the cone of the
6. The sequence starts again. loudspeakers will move slowly in one or the other direction
until the initial failure shuts the amplifier down, this cyclus
Example: Error 12 8 6 0 0. starts over and over again. The headphone amplifier will
After activation of the SDM, the front LED will show: also behaves similar.
1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s
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Service Modes, Error Codes, and Fault Finding Q551.1L LA 5. EN 29
5.8 Fault Finding and Repair Tips • +5V-TUN supply voltage (5V nominal) for tuner and IF
amplifier.
Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra
+3V3-STANDY (3V3 nominal) is the permanent voltage,
Info”.
supplying the Stand-by microprocessor inside PNX85500.
5.8.1 Ambilight Supply voltage +1V1 is started immediately when +12V voltage
becomes available (+12V is enabled by STANDBY signal when
Due to degeneration process of the LED’s fitted on the ambi "low"). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN
module, there can be a difference in the color and/or light are switched "on" by signal ENABLE-3V3 when "low", provided
output of the spare ambilight modules in comparison with the that +12V (detected via 7U40 and 7U41) is present.
originals ones contained in the TV set. Via SAM => alignments
=> ambilight, the spare module can be adjusted. +12V is considered OK (=> DETECT2 signal becomes "high",
+12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter
5.8.2 Audio Amplifier can be started up) if it rises above 10V and doesn’t drop below
9V5. A small delay of a few milliseconds is introduced between
The Class D-IC 7D10 has a powerpad for cooling. When the IC the start-up of 12V to +1V8 DC-DC converter and the two other
is replaced it must be ensured that the powerpad is very well DC-DC converters via 7U48 and associated components.
pushed to the PWB while the solder is still liquid. This is needed
to insure that the cooling is guaranteed, otherwise the Class D- Description DVB-S2:
IC could break down in short time. • LNB-RF1 (0V = disabled, 14V or 18V in normal operation)
LNB supply generated via the second conversion channel
of 7T03 followed by 7T50 LNB supply control IC. It provides
5.8.3 AV PIP
supply voltage that feeds the outdoor satellite reception
equipment.
To check the AV PIP board (if present) functionality, a
• +3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal)
dedicated tespattern can be invoke as follows : select the
and +1V-DVBS (1.03V nominal) power supply for the
“multiview” icon in the User Interface and press the “OK” silicon tuner and channel decoder. +1V-DVBS is generated
button. Apply for the main picture an extended source, e.g.
via a 5V to 1V DC-DC converter and is stabilized at the
HDMI input. Proceed by entering CSM (push ‘123654’ on the
point of load (channel decoder) by means of feedback
remote control) and press the yellow button. A colored signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS
testpattern should appear now, generated by the AV PIP board
are generated via linear stabilizers from +5V-DVBS that by
(can take a few seconds).
itself is generated via the first conversion channel of 7T03.
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EN 30 5. Q551.1L LA Service Modes, Error Codes, and Fault Finding
900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC UART loggings reporting fault conditions, error messages,
converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V error codes, fatal errors:
LNB DC-DC converters operates at 300 kHz while for 5 V • Failure messages should be checked and investigated.For
to 1.1 V DC-DC converter 900 kHz is used. instance fatal error on the PNX51x0: check startup of the
back-end processor, supplies..reset, I2C bus. => error
5.8.6 Exit “Factory Mode” mentioned in the logging as: *51x0 failed to start by itself*.
• Some failures are indicated by error codes in the logging,
check with error codes table (see Table “5-2 Error code
When an “F” is displayed in the screen’s right corner, this
means the set is in “Factory” mode, and it normally overview”).e.g. => <<<ERROR>>>PLFPOW_MERR.C :
First Error (id=10,Layer_1=2,Layer_2=23).
happens after a new SSB is mounted. To exit this mode, push
• I2C bus error mentioned as e.g.: “ I2C bus 4 blocked”.
the “VOLUME minus” button on the TV’s local keyboard for 10
seconds (this disables the continuous mode). • Not all failures or error messages should be interpreted as
fault.For instance root cause can be due to wrong option
Then push the “SOURCE” button for 10 seconds until the “F”
codes settings => e.g. “DVBS2Suppoprted : False/True.
disappears from the screen.
In the UART log startup script we can observe and check the
enabled loaded option codes.
5.8.7 Logging
Defective sectors (bad blocks) in the Nand Flash can also be
When something is wrong with the TV set (f.i. the set is reported in the logging.
rebooting) you can check for more information via the logging
in Hyperterminal. The Hyperterminal is available in every Startup in the SW upgrade application and observe the UART
Windows application via Programs, Accessories, logging:
Communications, Hyperterminal. Connect a “ComPair UART”- Starting up the TV set in the Manual Software Upgrade mode
cable (3138 188 75051) from the service connector in the TV to will show access to USB, meant to copy software content from
the “multi function” jack at the front of ComPair II box. USB to the DRAM.Progress is shown in the logging as follows:
Required settings in ComPair before starting to log: “cosupgstdcmds_mcmdwritepart: Programming 102400 bytes,
- Start up the ComPair application. 40505344 of 40607744 bytes programmed”.
- Select the correct database (open file “Q55X.X”, this will set
the ComPair interface in the appropriate mode). Startup in Jett Mode:
- Close ComPair Check UART logging in Jet mode mentioned as : “JETT UART
After start-up of the Hyperterminal, fill in a name (f.i. “logging”) READY”.
in the “Connection Description” box, then apply the following
settings: UART logging changing preset:
1. COMx => COMMAND: calling DFB source = RC6, system=0, key = 4”.
2. Bits per second = 115200
3. Data bits = 8
4. Parity = none
5.8.9 Loudspeakers
5. Stop bits = 1
6. Flow control = none
During the start-up of the TV set, the logging will be displayed. Make sure that the volume is set to minimum during
disconnecting the speakers in the ON-state of the TV. The
This is also the case during rebooting of the TV set (the same
audio amplifier can be damaged by disconnecting the speakers
logging appears time after time). Also available in the logging
is the “Display Option Code” (useful when there is no picture), during ON-state of the set!
look for item “DisplayRawNumber” in the beginning of the
logging. Tip: when there is no picture available during rebooting 5.8.10 PSL
you are able to check for “error devices” in the logging (LAYER
2 error) which can be very helpful to determine the failure cause In case of no picture when CSM (test pattern) is activated and
of the reboot. For protection state, there is no logging. backlight doesn’t light up, it’s recommended first to check the
inverter on the PSL + wiring (LAYER 2 error = 17 is displayed
5.8.8 Guidelines UART logging in SDM).
UART loggings are displayed: Attention: In case the tuner is replaced, always check the tuner
• When UART loggings are coming out, the first conclusion options!
we can make is that the TV set is starting up and
communication with the flash RAM seems to be supported. 5.8.12 Display option code
The PNX85500 is able to read and write in the DRAMs.
• We can not yet conclude : Flash RAM and DRAMs are fully Attention: In case the SSB is replaced, always check the
operational/reliable.There still can be errors in the data
display option code in SAM, even when picture is available.
transfers, DRAM errors, read/write speed and timing
Performance with the incorrect display option code can lead to
control. unwanted side-effects for certain conditions.
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Service Modes, Error Codes, and Fault Finding Q551.1L LA 5. EN 31
Before starting: ST AR T
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder ”upgrades” in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in Set is still oper ating?
case there are more than one "autorun.upg" files on the USB stick.
No
Yes
1. D isconnect the WiF i module fr om the PC I connector (only for Q549.x SSB)
2. Replace the SSB by a Service SSB.
3. Place the WiFi module in the PCI connector.
4. Mount the Service SSB in the set.
Set the correct “Display code” via “062598 -HOME- xxx” where
“xxx” is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)
H_16771_007a.eps
100402
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EN 32 5. Q551.1L LA Service Modes, Error Codes, and Fault Finding
Noisy picture with bands/lines is visible and the An “F” is displayed (and the HDMI 1
RED LED is continuous on. input is displayed).
- Press the “volume minus” button on the TVs local keyboard for 5 ~10
seconds
- Press the “SOURCE” button for 10 seconds until the “F” disappears
from the screen or the noise on the screen is replaced by “blue mute”
H_16771_007b.eps
100322
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Service Modes, Error Codes, and Fault Finding Q551.1L LA 5. EN 33
18753_211_100811.eps
100811
5.9.5 UART logging 2K10 (see section “5.8 Fault Finding and
Repair Tips, 5.8.7 Logging)
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Alignments Q551.1L LA 6. EN 35
6. Alignments
Index of this chapter: For the next alignments, supply the following test signals via a
6.1 General Alignment Conditions video generator to the RF input:
6.2 Hardware Alignments • EU/AP-PAL models: a PAL B/G TV-signal with a signal
6.3 Software Alignments strength of at least 1 mV and a frequency of 475.25 MHz
6.4 Option Settings • US/AP-NTSC models: an NTSC M/N TV-signal with a
6.5 Reset of Repaired SSB signal strength of at least 1 mV and a frequency of 61.25
6.6 Total Overview SAM modes MHz (channel 3).
• LATAM models: an NTSC M TV-signal with a signal
strength of at least 1 mV and a frequency of 61.25 MHz
6.1 General Alignment Conditions (channel 3).
Perform all electrical adjustments under the following 6.3.1 White Point
conditions:
• Power supply voltage (depends on region):
• Choose “TV menu”, “Setup”, “More TV Settings” and then
– AP-NTSC: 120 VAC or 230 VAC / 50 Hz (r 10%).
“Picture” and set picture settings as follows:
– AP-PAL-multi: 120 - 230 VAC / 50 Hz (r 10%).
– EU: 230 VAC / 50 Hz (r 10%). Picture Setting
• Allow the set to warm up for approximately 15 minutes. Picture format Unscaled
To store the data: Table 6-2 White D alignment values - LED - Minolta CA-210
• Press OK on the RC before the cursor is moved to the
left Value Cool (9420K) Normal (8120K) Warm (6080K)
• In main menu select “Store” and press OK on the RC x 0.282 0.292 0.320
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EN 36 6. Q551.1L LA Alignments
Table 6-3 White D alignment values - LED - Minolta CS-200 6.3.3 TCON/VCOM alignment
Value Cool (11000K) Normal (9000K) Warm (6500K) Sets with forward integration have the TCON on SSB. The
x 0.276 0.287 0.313 alignment of this TCON is stored in the SSB, and is related to
y 0.282 0.296 0.329 the used display. When an SSB or a display is replaced, a new
value must be entered.
If you do not have a color analyzer, you can use the default A default value (see table below) is copied from the display file
(after entering the correct display code) and is shown in the
values. This is the next best solution. The default values are
SAM menu. But on top of this, the default value can be
average values coming from production.
• Select a COLOUR TEMPERATURE (e.g. COOL, overruled manually via the menu item “TCON alignment”.
The current value is shown with 4 digits, and can be changed
NORMAL, or WARM).
by a digit entry. After pressing “OK”, the value is stored.
• Set the RED, GREEN and BLUE default values according
to the values in Table 6-4. The menu item "Reset TCON alignment" can be used to return
to the default value from the display file. A notification is shown:
• When finished press OK on the RC, then press STORE (in
"TCON alignment has been reset".
the SAM root menu) to store the aligned values to the NVM.
• Restore the initial picture settings after the alignments.
Table 6-7 TCON/VCOM default settings
Table 6-4 White tone default setting 40" (Monet)
Supplier Panel TCON/VCOM Alignment
LGD (max: 1023) 32” CCFL (Rembrandt) 420
White Tone e.g. 40PFL9605D/xx
37” CCFL (Rembrandt) 403
Colour Temp R G B
42” CCFL (Rembrandt) 443
Normal 127 118 88
32” LED (Matisse) 428
Cool 126 126 106
37” LED (Matisse) 375
Warm 127 109 54
Sharp (max: 255) 32” LED (Van Gogh) 109
40” LED (Van Gogh) 95
Table 6-5 White tone default setting 58" (Rubens 21:9) 46” LED (Van Gogh) 143
52” LED (Van Gogh) 203
White Tone e.g. 58PFL9955D/xx 40” LED (da Vinci) 0098
Colour Temp R G B 46” LED (da Vinci) 0129
Normal 127 109 115
Cool 126 109 127
Warm 127 104 83 6.4 Option Settings
Every ambient light module is aligned by a matrix and by the The microprocessor communicates with a large number of I2C
brightness. After replacement of a module, the brightness/color ICs in the set. To ensure good communication and to make
must be aligned with the other modules: digital diagnosis possible, the microprocessor has to know
1. Go to SAM. which ICs to address. The presence / absence of these
2. Select “Alignments”. PNX51XX ICs (back-end advanced video picture improvement
3. Select “Ambilight”. A white test pattern shall be displayed IC which offers motion estimation and compensation features
by the ambilight modules. (commercially called HDNM) plus integrated Ambilight control)
4. Select the number of the module that have to be aligned. is made known by the option codes.
Module 1 is the first one which will come across according
the wiring path, starting at the small signal panel, Notes:
proceeding towards the ambient light modules.The first • After changing the option(s), save them by pressing the OK
module will be attached to the next module 2. Module button on the RC before the cursor is moved to the left,
number 2 to number 3 etc..as follows the way to define the select STORE in the SAM root menu and press OK on the
ambilight module numbering. RC.
5. Align the brightness compared with the neighboring • The new option setting is only active after the TV is
modules. The brightness is automatically stored. switched “off” / “stand-by” and “on” again with the mains
6. Select one of 10 matrixes which color matches most with switch (the NVM is then read again).
the neighboring modules, “matrix 0” is the factory
alignment and can always be retrieved. (see table “6-6 6.4.2 Dealer Options
Overview matrix correction table
7. The alignment is stored automatically. For dealer options, in SAM select “Dealer options”.
See Table 6-8 SAM mode overview.
Table 6-6 Overview matrix correction table
6.4.3 (Service) Options
Matrix # fR fG fB
Matrix 0 1 1 1 Select the sub menu's to set the initialization codes (options) of
Matrix 1 1 0.95 0.95 the model number via text menus.
Matrix 2 0.95 1 0.95 See Table 6-8 SAM mode overview.
Matrix 3 0.95 0.95 1
Matrix 4 0.95 1 1
6.4.4 Opt. No. (Option numbers)
Matrix 5 1 0.95 1
Matrix 6 1 1 0.95
Matrix 7 1 0.97 0.95
Select this sub menu to set all options at once (expressed in
Matrix 8 0.97 0.95 1
two long strings of numbers).
Matrix 9 0.95 0.97 1
An option number (or “option byte”) represents a number of
different options. When you change these numbers directly,
you can set all options very quickly. All options are controlled
via eight option numbers.
2010-Oct-01 back to
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Alignments Q551.1L LA 6. EN 37
Diversity
Not all sets with the same Commercial Type Number (CTN)
necessarily have the same option code! 18310_221_090318.eps
Use of Alternative BOM => an alternative BOM number usually 090319
indicates the use of an alternative display or power supply. This
results in another display code thus in another Option code. Figure 6-1 SSB identification
Refer to Chapter 2. Technical Specifications, and Connections.
Refer to the sticker in the set for the correct option codes.
Important: after having edited the option numbers as
described above, you must press OK on the remote control
before the cursor is moved to the left!
After a repaired SSB has been mounted in the set (set repair
on board level), the type number (CTN) and production code of
the TV has to be set according to the type plate of the set. For
this (new in this platform), you can use the NVM editor in
SAM. This action also ensures the correct functioning of the
“Net TV” feature and access to the Net TV portals. The loading
of the CTN and production code can also be done via ComPair
(Model number programming).
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EN 38 6. Q551.1L LA Alignments
2010-Oct-01 back to
div. table
Alignments Q551.1L LA 6. EN 39
back to 2010-Oct-01
div. table
EN 40 6. Q551.1L LA Alignments
2010-Oct-01 back to
div. table
Circuit Descriptions Q551.1L LA 7. EN 41
7. Circuit Descriptions
Index of this chapter: 7.1 Introduction
7.1 Introduction
7.2 Power Supply
The Q551.1L LA is a new chassis launched in 2010. The whole
7.3 Backlight Concept
range is covered by PNX8550x main IC so-called NXP TV550
7.4 DC/DC Converters platform.
7.5 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception
The major deltas versus its predecessor Q543/Q548 are the
7.6 Front-End DVB-S(2) reception
DVBS, DLNA1.5+, Wireless Laptop Live (WLL-Dongle),
7.7 HDMI Ethernet, and WiFi Ready (Net-TV) functionality.
7.8 Video and Audio Processing - PNX85500
7.9 Back-End
The Q551.1L LA chassis comes with the following stylings:
7.10 Ambilight • Monet
7.11 TCON
• Rubens 21:9.
Notes:
7.1.1 Implementation
• Only new circuits (circuits that are not published recently)
are described.
Key components of this chassis are:
• Figures can deviate slightly from the actual situation, due
• PNX85500 System-On-Chip (SOC) TV Processor
to different set executions.
• For a good understanding of the following circuit • TX31XX Hybrid Tuner (DVB-T/C, analogue)
• STV6110AT DVB-S tuner
descriptions, please use the wiring, block (see chapter
• SII9x87 HDMI Switch
9. Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts).Where necessary, • TPA312xD2PWP Class D Power Amplifier
• LAN8710 Dual Port Gigabit Ethernet media access
you will find a separate drawing for clarification.
controller
• PNX51x0 Video back-end Processor (optional; comes
together with LCD panel on a so-called “200 Hz board”).
18750_200_100415.eps
100415
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EN 42 7. Q551.1L LA Circuit Descriptions
18750_201_100415.eps
100415
N -D VBS C onnector
8981x N -D VBS
LVD S
8957x
D C /D C
C las s -D T uner
P N X 85500
89 53 x
8951 x CI
8950 x
DD R4 (51 2)
IO
89 94 x
IO
8952 x 6451 x
18770_257_100427.eps
100428
Figure 7-3 SSB layout cells (top view) (non-DVBS without TCON)
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Circuit Descriptions Q551.1L LA 7. EN 43
18770_234_100127.eps
100127
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EN 44 7. Q551.1L LA Circuit Descriptions
9 - - +Vsnd POK - -
Current
B ac k lightB oos t
7.3 Backlight Concept
PNX B ac k lightP W M
85500
1M99
Lam p -O N
The following backlight applications are implemented:
• Basic (xxPFL8xxx sets)
• xxPFL9xxx sets 32" 100 Hz “0D” scanning S S B TV 550 P S LS
• xxPFL9xxx sets 37" 200 Hz “0D” dimming
• xxPFL9xxx sets 40" & 46" 200 Hz “2D” scanning 18750_203_100415.eps
100415
• xxPFL9xxx sets 58" 21:9 (3-d) 200 Hz “2D” scanning.
Figure 7-6 Backlight application (xxPFL9xxx sets 32" 100 Hz “0D”
The backlight application determines which power board has to scanning)
be used. Refer to section 7.2.2 Diversity for additional
information.
T co n2 0 0H z B a ckL ig h t
LGD S id e L E D
T co n 2 0 0 H z B a ckL ig h t
S h a rp S id e L E D A S IC
A S IC
PNX PNX
5120 5120
PNX PNX
LVD S splitter
5120 5120
LVD S splitter
1G5 1
1G5 1
PWM
Current
1G5 0 1G5 1
PWM
Current
1G5 0 1G5 1
B ac k lightB oos t
PNX B ac k lightP W M
85500 Lam p -O N
1M99
S S B TV 550 PSL
S S B T V 550 PSL 18750_204_100415.eps
100415
18750_202_100415.eps
100423
Figure 7-7 Backlight application (xxPFL9xxx sets 37" 200 Hz “0D”
dimming)
Figure 7-5 Backlight application (xxPFL8xxx sets 200 Hz “0D”
dimming)
2010-Oct-01 back to
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Circuit Descriptions Q551.1L LA 7. EN 45
1F53
xxPFL9xxx sets.
A S IC A S IC
C-balancing Concept for LED driving
The advantages of the C-balancing concept are:
PNX PNX • Cost reduction
5120 5120 • Higher efficiency
PWM
• Higher reliability, because of less components used.
LVD S splitter
The C-balance drivers and -components are mounted on a
2D-D I M
I2S / S PI
1G5 1 separate C-balancer board. This PWB is mounted on the LCD
panel by the LCD manufacturer, though developed by Philips.
Current
• For edge-lit displays & direct-lit displays + “0D” dimming
1G5 0 1G5 1
• For direct-lit displays + “2D” dimming.
Refer to Figure 7-10 and Figure 7-11 for the application.
R e s o n ant R ectifier
85500 Lam p -O N 380 to
1M99
to p o lo g y
ACin 4 0 0 V DC Balan cin g 1
D rive r-part Balan cin g 2
Balan cin g 3
S S B TV 550 PSDL
B alan cin g n
18750_205_100415.eps
100423
Part of Power Supply Part of Display
Figure 7-8 Backlight application (xxPFL9xxx sets 40" & 46" 200 Hz 18750_209_100415.eps
100416
“2D” scanning)
Figure 7-10 Balancing LED-drivers application for edge-lit
displays & direct-lit displays in combination with “0D” dimming
T co n 2 0 0 H z 3D B a ckL ig h t
S h a rp D ire ctL E D
B L-I2S Power Power
sca n n in g Conversion 2a Conversion 2b Backlight-unit
Power
1F53
A S IC A S IC Conversion 1
DC to LED-drivers) DC to LED-drivers) (LED-strings)
R e s o n ant Rectifier
380 to to p o lo g y
FPGA ACin 4 0 0 V DC B alan cin g 1
D rive r-part B alan cin g 2
B alan cin g 3
PNX PNX
B alan cin g n
5120 5120
PWM Part of Power Supply Part of Display
LVD S splitter
2D-D I M 18750_210_100415.eps
I2S / S PI
1G5 1 100416
1G5 0 1G5 1
7.4 DC/DC Converters
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EN 46 7. Q551.1L LA Circuit Descriptions
Diagram B08A contains the DVB-S2-related DC/DC 7.5.1 European/Asia Pacific region
converters and -stabilizers:
• a +24V under-voltage detection circuitry is built around The Front-End for the European/Asia Pacific region consist of
item no. 7T04 the following key components:
• the switching frequency of the 24 to 14...20V switched
mode converter is 350 kHz (item no. 7T03 and +V-LNB • Hybrid Tuner
lines) • Switchable SAW filter 7/8 MHz (Eur.), or single SAW filter
• the output signal on the +V-LNB line goes to the LNBH23Q (8 MHz) (Asia Pacific)
(item no. 7T50) • Bandpass filter
• the LNBH23Q (item no. 7T50) sends a feedback signal via • Amplifier
the V0-CNTRL line • PNX85500 SoC TV processor with integrated DVB-T and
• the switching frequency of the +5V-DVBS to +1-DVBS DVB-C channel decoder and analogue demodulator.
switched mode converter is 900 kHz (item no. 7T00)
• a delay line for the +2V5-DVBS and +1V-DVBS lines is Below find a block diagram of the front-end application for this
created with item no. 3T03 (R=10k) and 2T06 (C=100n) region.
• a 3.3V to 2.5V linear stabilizer is built around item no. 7T01
• a 5V to 3.3V linear stabilizer is built around item no. 7T02.
+ 5V 5-TUN
196 m A
+ 5V + 5V 5-TUN + 5V -TUN
+ 5V + 5V -TUN
2179 m A 196 m A
dc -dc s tabiliz er
18770_235_100127.eps
100219
+ 12V + 3V 3 + 3V 3 + 2V 5
+ 3V 3 + 2V 5 Figure 7-14 Front-End block diagram European/Asia Pacific
2919 m A 2371 m A 450 m A
dc -dc s tabiliz er
region
+ 1V 8 + 1V 8 + 1V 2
7.5.2 Latin American region
+ 1V 8 + 1V 2
2450 m A 550 m A
dc -dc s tabiliz er
2010-Oct-01 back to
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Circuit Descriptions Q551.1L LA 7. EN 47
18770_236_100127.eps
100219
and vivid color management. High flat panel screen resolutions support is available for 2D dimming in combination with LED
and refresh rates are supported with formats including 1366 × backlights for optimum contrast and power savings up to 50%.
768 @ 100Hz/120Hz and 1920 × 1080 @ 100Hz/120Hz. The
combination of Ethernet, CI+ and H.264 supports new TV For a functional diagram of the PNX85500, refer
experiences with IPTV and VOD. On top of that, optional to Figure 7-18.
PNX85500x
MEMORY
CONTROLLER
TS input MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single, dual or
OUTPUT quad channel)
DVB DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO
VIDEO ENCODER analog CVBS
OUTPUT
SCALER,
AUDIO DEMOD DE-INTERLACE
SSIF, LR
AND DECODE AND NOISE
REDUCTION
DMA BLOCK
I2C PWM GPIO IR ADC SPI UART I 2C GPIO Flash USB 2.0 SD Ethernet
x8 Memory MAC
Card
18770_241_100201.eps
100219
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Circuit Descriptions Q551.1L LA 7. EN 49
7.10 Ambilight
1
MTK 1 1 1 1
Glue M
or M M M M
logic 5 AmbiLight AmbiLight
PNX85500 8 8 8 8
9
3 4 3 4
SSB
1M09
1M09
PSU
18770_209a_100202.eps
100202
18750_207_100415.eps
100415
6
×
6 5 3
L × ×
E 6 4 5 2
D L × L ×
E 6 3 E 6 4
D L × D L +
E 6 E 5
D L D L
E E
D D
36 30 24 18 15 12 9
18770_210_100126.eps
100126
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EN 50 7. Q551.1L LA Circuit Descriptions
7
6
driver, as “extra” line is mentioned:
• Non-SPI signals that are required for the LED driver 7B30
3B39-2
3B39-3
1K5 1%
1K5 1%
2
3
FB40
5
• Temperature sensor line. 1
4 TEMP-SENSOR
3
LMV331IDCK
2
RES
10K
10n
3004
2B08
3B11
-T
10K
SPI S P I + e x tra
FB41
PNX C P LD
1
1M 59
10n
2B09
3B39-1
1K5 1%
8
18770_211_100126.eps
100126
18770_215_100126.eps
100126
Figure 7-22 Communication protocol outside LED board
Figure 7-25 Temperature sensor
Refer to figure for an overview of the communication inside the
LED board. The EEPROM (item no. 7B07; diagram AL1A) contains
alignment information about the mounted LEDs and is
programmed during the alignment process in production. Refer
E x tra
to figure 7-26 EEPROM.
+3V3
SPI SPI SPI
LE D
B uffer
D river
100n
2B20
SPI-DATA-IN-BUF
SPI-CLOCK-BUF
1M 84
1M 83
EEPRO M 7B07
8
Tem p M95010-WDW6
+3V3 VCC
sensor 5 2
D Φ Q
7B06 (64K)
5
Te m p 74LVC1G32GW 6
SPI 1
C
SPI-CS
4 1 3B02-2
SPI S
DATA-SWITCH 2 7 +3V3
+3V3 HOLD
1 3B02-1 8 3 7 10K 2
W
3
10K
GND
4
18770_213_100126.eps
100219
SPI-DATA-RETURN
The buffer is built around item no. 7B20 (diagram AL1A) and
Figure 7-26 EEPROM
regenerates the clock signals. Refer to figure 7-24 Ambilight
buffer.
The LED driver is built around item no. 7B26 (diagram AL1A)
+3V3
and controls the LEDs. Refer to figure 7-27 LED driver.
100n
2B17
7B20-1
74LVC2G17
5
33p
2B00
100p
2B02
7B20-2
74LVC2G17
+3V3
5
3B01-1 3B30-4
SPI-CLOCK 1 8 3 4 4 5 SPI-CLOCK-BUF
100R 220R
2
33p
2B01
100p
2B10
18770_214_100126.eps
100126
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Circuit Descriptions Q551.1L LA 7. EN 51
+3V3
2B11
100n
7B26-1
27
TLC5946RHB
3B00-1 VCC
BLANK 1 8 31 4 PWM-R1
BLANK 0
PWM-CLOCK-BUF 150R 24 5 PWM-G1
GSCLK 1
3B18 26 6 PWM-B1
IREF 2
1K8 FB35 3 7 PWM-G3
MODE 3
PROG 4 3B00-4 5 1 8 PWM-R3
SCLK 4
SPI-CLOCK-BUF 150R 2 9 PWM-R2
SIN 5
SPI-DATA-IN-BUF 23 10 PWM-G2
SOUT 6
SPI-DATA-IN 3 6 11 PWM-B2
7
SPI-DATA-OUT 3B00-3 150R 3B21 150R 22 OUT 14 PWM-B3
XERR 8
FB20 +3V3 3B22 25 15 PWM-G4
XHALF 9
LATCH 2 3B00-2 7 10K 32 16 PWM-R4
XLAT 10
150R 17 PWM-B4
11
12 18 PWM-B5
12
13 19 PWM-G5
7
8
5
6
13
28 NC 20 PWM-R5
14
29 21 DATA-SWITCH
15
100p
100p
100p
100p
2B04-2
2B04-1
2B04-4
2B04-3
3B31
GND GND_HS
2
1
4
3
+3V3
30
33
2K0
7B26-2
TLC5946RHB
34 VIA 42
35 41
VIA VIA
36 40
VIA
37
38
39
18770_217_100126.eps
100126
+24V
7B23-1
BC847BS(COL)
10K
6
8 3B07-1 1
1
10K
2 3B07-2 7
FB30
PWM-B1
3B35
+24V
+24V 7000 7001 7002 7003 7004 7005
99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 270R
3B36
7B23-2 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 270R
BC847BS(COL)
3B37
10K
68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
4
10K
1 3B03-1 8
3 3B07-3 6
FB31 1K5
PWM-R1
3B03-2
2 7
+24V
1K5
3 3B03-3 6
1K5
7B25
3B03-4
10K
BC847BW 3 4 5
3 3B13-3 6
1K5
1
100n
2B03
10K
5 3B13-4 4
FB32
PWM-G1
18770_218_100126.eps
100126
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EN 52 7. Q551.1L LA Circuit Descriptions
In p u t c o n n e c to r O p e n in g
Te m p e ra tu re 1M 83 L E D d riv e r fo r c lip
sensor
LED
B u ffe r EEPROM
18750_208_100415.eps
100415
7.11 TCON For the basic application, refer to figure 7-30 TCON
architecture.
This section describes the application with the TCON
integrated on the SSB.
EEPROM
Control
Signals
Gamma
Reference Source Drive IC
Voltage
+3.3 V
+1.8 V
PNX8550
+16 V
+12 V Power TFT – LCD Panel
Block
VGH (+28 V)
VGL (-6 V)
Gate Drive IC
LC D P anel
SSB
18770_238_100127.eps
100402
For the TCON block diagram, refer to figure 7-31 TCON block
diagram.
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Circuit Descriptions Q551.1L LA 7. EN 53
Right h alf
Drive
(Over
Power
Circuit)
data
Control)
Control)
Contrast
(Dynamic
(Optimum
R 2 A ~E
LV D S Gate D river
C trl S ign als
R 2C LK R e c e iv er
Ve rtic a l & H o rizo n ta l
Tim in g g e n e ra tio n Source D river
C trl S ign als
I2 C ROM H s y n c/ Control
I2 C
S lav e M aster Vsync Signal
S S C L K (S p re a d Spectrum C lo c k) Output
DE
EEPROM
18770_239_100127.eps
100127
Notes to figure 7-31 TCON block diagram: • Timing Control Function: generates control signals to
• LVDS receiver: converts the data stream back into RGB column drivers and row drivers (Source Enable - SOE,
data and SYNC signals (Vsync, Hsync, Data Enable - DE) Gate Enable - GOE, Gate Start Pulse - GSP).
• ODC: Over Drive Circuit - to improve LC response For an overview of the TCON DC/DC converters, refer to figure
• Data Path Block: the video RGB data input to data path 7-32 TCON DC/DC converters.
block is delayed to align the column driver start pulse with
the column driver data
To G a te D riv e rs (G a te
VGH +2 8 V +3 5 V
H ig h Vo lta g e )
D C /D C
+ 12V C o n tro lle r To G a te D riv e rs (G a te
VGL -6 V -6 V
L o w Vo lta g e )
Tim in g C o n tro lle r IC
Vcc +3 V 3 +3 V 3
S u p p ly Vo lta g e
Tim in g C o n tro lle r IC
Vcc +1 V 8 +1 V 2
S u p p ly Vo lta g e
G a m m a R e fe renc e
Vre f +1 6 V +1 5 V 2
Vo lta g e
S o u rc e D riv e r S u p p ly
Vdd +1 6 V +1 5 V 6
Vo lta g e
18770_240_100128.eps
100128
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EN 54 7. Q551.1L LA Circuit Descriptions
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IC Data Sheets Q551.1L LA 8. EN 55
8. IC Data Sheets
This chapter shows the internal block diagrams and pin electrical diagrams (with the exception of “memory” and “logic”
configurations of ICs that are drawn as “black boxes” in the ICs).
8.1 Diagram B01 820400090812 Tuner, HDMI & CI, USB2513B (IC 7F25)
Block diagram
To EEPROM or
To Upstream Upstream SMBus Master
24 MHz
VBUS USB Data SDA SCL
Crystal
3.3 V
Bus- Serial
Power Upstream Regulator PLL Interface
Detect/ PHY
Vbus Pulse
Serial
Repeater Interface Controller
Engine
3.3 V
TT TT Port
Regulator #1
... #x Controller
CRFILT
Port #1 Port #x
PHY#1 OC Sense ... PHY#x OC Sense
Switch Driver/ Switch Driver/
LED Drivers LED Drivers
Pinning information
VBUS_DET
RESET_N
HS_IND / CFG_SEL[1]
SCL / SMBCLK / CFG_SEL[0]
VDD33
SDA / SMBDATA / NON_REM[1]
NC
NC
NC
27
26
25
24
23
22
21
20
19
VDD33 29 17 OCS_N[2]
USBDP_UP 31
SMSC 15 VDD33
XTALOUT
USB2512/12A/12B CRFILT
32 14
USB2512i/12Ai/12Bi
XTALIN / CLKIN 33 13 OCS_N[1]
(Top View QFN-36)
PLLFILT 34 12 PRTPWR[1] / BC_EN[1]*
Ground Pad
RBIAS 35 (must be connected to VSS) 11 TEST
VDD33 36 10 VDD33
1
2
3
4
5
6
7
8
9
NC
NC
NC
NC
VDD33
USBDP_DN[1]
USBDP_DN[2]
USBDM_DN[1]
USBDM_DN[2]
18770_301_100217.eps
100217
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div. table
EN 56 8. Q551.1L LA IC Data Sheets
8.2 Diagram B01 820400090812 Tuner, HDMI & CI, LM75BDP (IC 7FD1)
Block diagram
VCC
LM75B
BIAS POINTER CONFIGURATION
REFERENCE REGISTER REGISTER
TEMPERATURE
BAND GAP COUNTER
REGISTER
TEMP SENSOR 11-BIT
SIGMA-DELTA
A-to-D TOS
TIMER
CONVERTER REGISTER
OSCILLATOR
COMPARATOR/ THYST
INTERRUPT REGISTER
POWER-ON
RESET OS
Pinning information
SDA 1 8 VCC
SCL 2 7 A0
LM75BDP
OS 3 6 A1
GND 4 5 A2
18770_300_100217.eps
100217
2010-Oct-01 back to
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IC Data Sheets Q551.1L LA 8. EN 57
Block diagram
PNX8550x
MEMORY
CONTROLLER
TS input MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single, dual or
OUTPUT quad channel)
DVB DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO analog CVBS
VIDEO ENCODER
OUTPUT analog Y/C
Low-IF
DIGITAL IF MULTI-
Direct-IF STANDARD Motion-accurate
VIDEO pixel processing
DECODER
SCALER,
AUDIO DEMOD DE-INTERLACE
SSIF, LR
AND DECODE AND NOISE
REDUCTION
Scatter/Gather
TS Demux
I2C PWM Px_x IR ADC SPI UART I2C GPIO Flash USB 2.0 SD Ethernet
x 10 Memory MAC
Card
Pinning information
ball A1 PNX8550xE
index area 2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
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div. table
EN 58 8. Q551.1L LA IC Data Sheets
Block diagram
TPA3120D2
1 F
0.22 F
LIN BSR
22 H 470 F
RIN ROUT
1 F 0.68 F
PGNDR
PGNDL 0.68 F
1 F
BYPASS LOUT
22 H 470 F
AGND BSL
0.22 F
PVCCL
AVCC
PVCCR
VCLAMP
Shutdown
SD 1 F
Control
MUTE
GAIN0
} Control
GAIN1
Pinning information
PWP (TSSOP) PACKAGE
(TOP VIEW)
PVCCL 1 24 PGNDL
SD 2 23 PGNDL
PVCCL 3 22 LOUT
MUTE 4 21 BSL
LIN 5 20 AVCC
RIN 6 19 AVCC
BYPASS 7 18 GAIN0
AGND 8 17 GAIN1
AGND 9 16 BSR
PVCCR 10 15 ROUT
VCLAMP 11 14 PGNDR
PVCCR 12 13 PGNDR
I_18020_142.eps
100402
2010-Oct-01 back to
div. table
IC Data Sheets Q551.1L LA 8. EN 59
Block diagram
Pinning information
VBST1 1 28 DRVH1
NC 2 27 LL1
EN1 3 26 DRVL1
VO1 4 25 PGND1
VFB1 5 24 TRIP1
NC 6 23 VIN
GND 7 22 VREG5
TEST1 8 21 V5FILT
TPS53124
NC 9 20 TEST2
VFB2 10 19 TRIP2
VO2 11 18 PGND2
EN2 12 17 DRVL2
NC 13 16 LL2
VBST2 14 15 DRVH2
18310_300_090319.eps
100416
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div. table
EN 60 8. Q551.1L LA IC Data Sheets
Block diagram
Pinning information
DFN8 (4 × 4) PowerSO-8
I_18010_083.eps
100402
2010-Oct-01 back to
div. table
IC Data Sheets Q551.1L LA 8. EN 61
Block diagram
LD1117DT
Pinning information
DPAK
F_15710_166.eps
100402
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div. table
EN 62 8. Q551.1L LA IC Data Sheets
Block diagram
MODE0 HP Auto-MDIX
MODE1 Auto- 10M Tx 10M
MODE Control
MODE2 Negotiation Logic Transmitter TXP / TXN
Reset Transmit Section
nRST Control RXP / RXN
Management 100M Tx 100M
RMIISEL SMI Logic Transmitter
Control
MDIX
Control
TXD[0:3] XTAL1/CLKIN
TXEN PLL
100M Rx DSP System: Analog-to-
TXER XTAL2
TXCLK Logic Clock Digital
Data Recovery
Interrupt
Equalizer nINT
RXD[0:3] Generator
RXDV 100M PLL
RXER Receive Section
RXCLK LED1
LED Circuitry
LED2
10M Rx Squelch &
Pinning information
TXD3
RBIAS
RXP
RXN
TXP
TXN
VDD1A
RXDV
32
31
30
29
28
27
26
25
VDD2A 1 24 TXD2
LED2/nINTSEL 2 23 TXD1
LED1/REGOFF 3 22 TXD0
SMSC
XTAL2 4 LAN8710/LAN8710i 21 TXEN
VDDCR 6
(Top View) 19 nRST
RXCLK/PHYAD1 7 18 nINT/TXER/TXD4
VSS
RXD3/PHYAD2 8 17 MDC
9
10
11
12
13
14
15
16
CRS
MDIO
VDDIO
RXD0/MDE0
RXD1/MODE1
RXD2/RMIISEL
RXER/RXD4/PHYAD0
COL/CRS_DV/MODE2
18770_302_100217.eps
100217
2010-Oct-01 back to
div. table
IC Data Sheets Q551.1L LA 8. EN 63
Block diagram
Pinning information
18770_303_100217.eps
100217
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div. table
EN 64 8. Q551.1L LA IC Data Sheets
Block diagram
VDD 8
VDD/2
2 IN 1− VO1 1
−
+
3 BYPASS
6 IN 2−
− VO2 7
+
5 SHUTDOWN Bias 4
Control
Pinning information
D OR DGN PACKAGE
(TOP VIEW)
VO1 1 8 VDD
IN1− 2 7 VO2
BYPASS 3 6 IN2−
GND 4 5 SHUTDOWN
18770_309_100217.eps
100217
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Block Diagrams Q551.1L LA 9. EN 65
9. Block Diagrams
9-1 Wiring diagram Monet 40" - 46" 200 Hz
WIRING DIAGRAM 40" 240Hz MONET
8584
8510
8301
8583
TO BACKLIGHT
8120
8735
25P
1M83
1M20 1M59 1G51 1G50
25P
1M84
9P
B 3104 313 6451.x
1M99
PSL 40 PLDE-P976AREV.1 (1011)
8399
9P
(1050)
1M99
11P
1M95
8395
11P
1M95
1MP1 1G51
4P
5P 51P
1735
ETHER
USB
NET
USB
TUNER
EXT2
200Hz BOARD
HDMI
EXT1
Board is part of display
AL
AL
2P3
1311
Component Level Repair
Only For Authorized Workshop
81P 81P 81P 81P
+ -
+ -
25P
1M83
8408
8411
LCD DISPLAY
(1004)
MAINS INLET
SWITCH LEADING EDGE
1M20 IR/LED BOARD 1820
2K10 ASSY 8P
J (1012) 6P
(8411)
(1110)
8191 6P
KEYBOARD CONTROL J1
1M59 (B13) 1M83 (AL1A) 1M84 (AL2A) 1M95 (B03C) 1M99 (B03C) 1M20 (B09A) 1735 (B03A) 1G51 (B06B) 1M09 (B09A)
1. AMBI-SPI-CLK-OUT 15. AMBI-TEMP 1. +24V 14. +3V3 1. SPI-CLOCK-BUF 14. N.C. 1. +3V3-STANDBY 1. +12VD 1. LIGHT-SENSOR 1. LEFT-SPEAKER 1. +VDISP 1. +24V
2. AMBI-SPI-SDO-OUT 16. GND 2. +24V 15. BLANK 2. SPI-DATA-OUT 15. TEMP-SENSOR 2. STANDBY 2. +12VD 2. GND 2. GND-AUDIO 2. +VDISP 2. +24V
3. AMBI-SPI-SDI-OUT-GI 17. GND 3. +24V 16. PROG 3. SPI-DATA-RETURN 16. GND 3. GND 3. GND 3. RC 3. GND-AUDIO 3. +VDISP 3. GND
4. GND 18. GND 4. +24V 17. GND 4. GND 17. GND 4. GND 4. GND 4. LED-2 4. RIGHT-SPEAKER 4. +VDISP 4. GND
5. AMBI-PWM-CLK_B2 19. GND 5. +24V 18. LATCH 5. PWM-CLOCK-BUF 18. GND 5. GND 5. LAMP-ON 5. +3V3-STANDBY |
6. V-AMBI 20. GND 6. GND 19. SPI-CS 6. +3V3 19. GND 6. +12V 6. BACKLIGHT-PWM_BL-VS 6. LED-1 51. CTRL-DISP
7. AMBI-SPI-CS-OUTn_R2 21. +24V 7. GND 20. +3V3 7. SPI-CS 20. GND 7. +12V 7. BACKLIGHT-BOOST 7. KEYBOARD
8. AMBI-LATCH1_G2 22. +24V 8. GND 21. PWM-CLOCK 8. LATCH 21. +24V 8. +12V 8. 3D-LR 8. +5V
9. GND 23. +24V 9. GND 22. GND 9. GND 22. +24V 9. +24V-AUDIO-POWER 9. POWER-OK
10. AMBI-PROG_B1 24. +24V 10. GND 23. SPI-DATA-RETURN 10. PROG 23. +24V 10. GND-AUDIO
11. AMBI-BLANK_R1 25. +24V 11. TEMP-SENSOR 24. SPI-DATA-IN 11. BLANK 24. +24V 11. MAINS-OK
12. V-AMBI 12. N.C. 25. SPI-CLOCK 12. +3V3 25. +24V
13. AMBI-LATCH2_DIS 13. N.C. 13. N.C. 18940_400_100810.eps
14. AMBI-SPI-CS-EXTLAMPSn 100813
2010-Oct-01 back to
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Block Diagrams Q551.1L LA 9. EN 66
8684 8683
1L00 1L01 1L02 1L03 1L04 1L00 1L01 1L02 1L03 1L04
8685
25P
8584
1M83
25P
1M84
50P 50P 50P 50P 50P 50P 50P 50P 50P 50P
8323
25P
25P
C-BALANCE BOARD
1L12
1L11
C-BALANCE BOARD
3P 14P 14P BB (1053) 15P 14P 14P 14P 14P BB (1054)
1322 1319 1316 1L10 1L19 1L16 1319 1316
8321
8319 8320
8322
8316
8301
1319 1322 1316
1MP1
14P 3P 14P
8P
8153
LCD DISPLAY
(1004)
8735
8510
4P
1M09
8735
8151
MAIN POWER SUPPLY
9P
1M99
AMBILIGHT MODULE 36 LED
(1073)
(1050)
AL
1F53 1F53 1G51
AL
8395
11P
8P 15P
1M95
51P 8583
ETHER
USB
NET
4P
1D38 1735
USB
TUNER
3
2P 8 CINCH
0
13
HDMI
25P
1M83
CINCH
CN1 CN2 CN3 CN3
81P 81P 81P 81P
8408
INLET
8191
IR/LED BOARD 8P
J (1114) 1B20 MAINS
SWITCH
(8408)
1M84 (AL3A,AL8B) 1322 (BB9) 1319 (BB9) 1316 (BB9) 1L10 (BB1) 1M83 (AL1A,AL5A) 1L19 (BB9) 1L16 (BB9) 1L12 (BB9) 1L11 (BB9) 1M95 (B03C) 1M20 (B09A) 1G51 (B06B)
1. SPI-CLOCK-BUF 14. N.C. 1. PROT-0 1. VRES+ / *N.C. 1. VRES- / *N.C. 1. GND 1. +24V 14. +3V3 1. N.C. 1. N.C. 1. GND. 1. GND. 1. +3V3-STANDBY 1. LIGHT-SENSOR 1. +VDISP
2. SPI-DATA-OUT(2) 15. TEMP-SENSOR 2. N.C. 2. VRES+ / *N.C. 2. VRES- / *N.C. 2. +3V3 2. +24V 15. BLANK 2. N.C. 2. N.C. 2. PROT-9 2. PROT-0 2. STANDBY 2. GND 2. +VDISP
3. SPI-DATA-RETURN 16. GND 3. PROT-9 3. VRES+ 3. VRES- 3. V-SYNC 3. +24V 16. PROG 3. VRES+ 3. VRES- 3. GND 3. GND 3. GND 3. RC 3. +VDISP
4. GND 17. GND 4. VRES+ 4. VRES- 4. GND 4. +24V 17. GND 4. VRES+ 4. VRES- 4. +6VB 4. SPI-CS1 4. GND 4. LED-2 4. +VDISP
5. PWM-CLOCK-BUF 18. GND 5. VRES+ 5. VRES- 5. BL-SPI-CSn 5. +24V 18. LATCH 5. VRES+ 5. VRES- 5. GND 5. GND 5. GND 5. +3V3-STANDBY |
6. +3V3 19. GND 1B20 (J1) 6. VRES+ 6. VRES- 6. GND 6. GND 19. SPI-CS 6. VRES+ 6. VRES- 6. +3V3 6. SPI-DATA1 6. +12V 6. LED-1 51. N.C.
7. SPI-CS 20. GND 1. LIGHT-SENSOR 7. VRES+ 7. VRES- 7. +3V3 7. GND 20. +3V3 7. VRES+ 7. VRES- 7. GND 7. GND 7. +12V 7. KEYBOARD
8. LATCH 21. +24V 2. GND 8. VRES+ 8. VRES- 8. GND 8. GND 21. PWM-CLOCK 8. VRES+ 8. VRES- 8. N.C. 8. SPI-CLK1 8. +12V 8. +5V
9. GND 22. +24V 3. RC 9. VRES+ 9. VRES- 9. BL-SPI-MOSI 9. GND 22. GND 9. VRES+ 9. VRES- 9. GND 9. GND 9. +24V-AUDIO-POWER
10. PROG 23. +24V 4. LED2 10. VRES+ 10. VRES- 10. GND 10. GND 23. SPI-DATA-RETURN 10. VRES+ 10. VRES- 10. GND 10. SPI-CS2 10. GND-AUDIO
11. BLANK 24. +24V 5. +3V3-STANDBY 11. VRES+ 11. VRES- 11. BL-SPI-CLK 11. TEMP-SENSOR 24. SPI-DATA-IN 11. VRES+ 11. VRES- 11. GND 11. GND 11. MAINS-OK 1M59 (B09A)
12. +3V3 25. +24V 6. LED1 12. VRES+ 12. VRES- 12. GND 12. N.C. 25. SPI-CLOCK 12. VRES+ 12. VRES- 12. SPI-CLK3 12. SPI-DATA2 1. AMBI-SPI-CLK-OUT 15. AMBI-TEMP
13. N.C. 7. KEYBOARD 13. VRES+ 13. VRES- 13. SCL-BL 13. N.C. 13. VRES+ 13. VRES- 13. GND 13. GND 2. AMBI-SPI-SDO-OUT 16. GND
8. +5V 14. VRES+ 14. VRES- 14. SDA-BL 14. VRES+ 14. VRES- 14. SPI-DATA31 14. SPI-CLK2 1M99 (B03C) 3. AMBI-SPI-SDI-OUT-GI 17. GND
15. GND 15. GND 15. GND 1. +12VD 4. GND 18. GND
*C-balance board on pos (1054) 16. SPI-CS3 16. N.C. 2. +12VD 5. AMBI-PWM-CLK_B2 19. GND
17. GND 17. GND 3. GND 6. V-AMBI 20. GND
18. SPI-CLK4 18. N.C. 4. GND 7. AMBI-SPI-CS-OUTn_R2 21. +24V
19. GND 19. GND 5. LAMP-ON 8. AMBI-LATCH1_G2 22. +24V
20. SPI-DATA4 20. +3V3 6. BACKLIGHT-PWM_BL-VS 9. GND 23. +24V
21. GND 21. GND 7. BACKLIGHT-BOOST 10. AMBI-PROG_B1 24. +24V
22. SPI-CS4 22. +6V 8. 3D-LR 11. AMBI-BLANK_R1 25. +24V
23. GND 23. GND 9. POWER-OK 12. V-AMBI
24. PROT-5 24. PROT-9 13. AMBI-LATCH2_DIS
25. GND 25. GND 14. AMBI-SPI-CS-EXTLAMPSn
1735 (B03A)
1. LEFT-SPEAKER
2. GND-AUDIO
3. GND-AUDIO 18940_404_100928.EPS
4. RIGHT-SPEAKER 100930
2010-Oct-01 back to
div. table
Block Diagrams Q551.1L LA 9. EN 67
1FE0
25M4
N.C. 51
IF+ 30 18
SDA-DISP 50
B02F LVDS B02E
IF- SCL-DISP 49
29 B02E
58 TS-FE-VALID R23 3D-LR 44
TNR_SER1_MIVAL B06C
TS-FE-SOP R22 CTRL-DISP 43
59 B02G
TNR_SER1_SOP
61 TS-FE-CLOCK T22
TNR_SER1_MICLK
60 TS-FE-DATA T21 40
TNR_SER1_DATA
PX3
42
RESET-SYSTEMn
TO
B02E LVDS OUT 200Hz BOARD
7EC1 PNX85500
SII9287BCNU 1E01
18 AV1-R AC13 AV1_R
1P05 Pr
1 90
B01C USB HUB
DRX2+ AV1-G AE13
14
3 DRX2- 89 EXT 1 Y AV1_G
1
2
4 DRX1+ 87 +5V-USB2
10 AVI-B AD13 B02E CONROL
6 DRX1- 86 Pb AV1_B 1P08
RXD 1
7
1
DRX0+ 84
R26 USB-DM 9F26 USB-DM2 2
9 DRX0- 83 USB_DN SIDE USB
18
3 2
19
1E02 R25 USB-DP 9F25 USB-DP2 3
10 DRXC+ 81 USB_DP CONNECTOR
4
AC14 4
HDMI SIDE 12 DRXC- 80 15 AV4-PR
Pr PR_R_C2
CONNECTOR HDMI
11 AV4-Y AE14
SWITCH EXT 2 Y Y_G2 B02A FLASH B01B FLASH
1P04 INSTAPORT 7 AV4-PB
Pb
AD14 PB_B2 7F20
1 ARX2+ 23 NAND04GW3B2DN6F
3 ARX2- 22
1
2
4 ARX1+ 20 NAND
6 ARX1- 19 FLASH
RXA B01I VGA XIO_D XIO-D(00-07)
7 ARX0+ 17 1E05
18
9 ARX0- 16 1 R-VGA 512MB
19
AF16 VGA_R
10 ARXC+ 14 2
10
G-VGA AD16
15
5
VGA_G
HDMI 3 12 ARXC- 13 3 B-VGA AE16
CONNECTOR VGA_B 12,37
13 H-SYNC-VGA AB18
1
6
HSYNC_IN VCC +3V3
11
9,27,64 14 V-SYNC-VGA AC18
+3V3-HDMI VCC33 VSYNC_IN
1P03
VGA
1 BRX2+ 42 CONNECTOR
3 41 B02B MEMORY
BRX2- B05A DDR
1
2
4 BRX1+ 39 B04B ANALOGUE EXTERNALS B
6 BRX1- 39 DQ DDR2-D(0-31)
RXB
7 BRX0+ 36
7B00 7B02 7B03 7B01
9 BRX0- 35
18
1E08 EDE1108AGBG EDE1108AGBG EDE1108AGBG EDE1108AGBG
19
10 BRXC+ 33
D(0-7)
2 AV2_CVBS AB14
D(8-15)
D(16-23)
D(24-31)
3 HDMIA-RXC- W26
CRX2- 71 TXC_N 63 RXC_A_N
A1 E2 A1 E2 A1 E2 A1 E2
1
HDMIA-RX0+
2
4 CRX1+ 69 V25
TX0_P 60 RX2_A_P
6 CRX1- 68 HDMIA-RX0- V26 A DDR2-A(0-13)
TX0_N 61 RX2_A_N
RXC HDMIA-RX1+ U25
7 CRX0+ 66 TX1_P 58 RX1_A_P +1V8
9 65 TX1_N 59 HDMIA-RX1- U26
CRX0- RX1_A_N DDR2-VREF-DDR
18
19
10 56 HDMIA-RX2+ T25
CRXC+ 63 TX2_P RX0_A_P
12 CRXC- 62 HDMIA-RX2- T26
HDMI 1 TX2_N 57 RX0_A_N A2
3S0W W24 VREF_1 DDR2-VREF-CTRL2
CONNECTOR V1
+3V3 RREF
VREF_2 DDR2-VREF-CTRL3
18940_401_100810.eps
100813
2010-Oct-01 back to
div. table
Block Diagrams Q551.1L LA 9. EN 68
1FE0
25M4
18 7D15 15 RIGHT-SPEAKER 4
OUT-R
A-PLOP A-STBY 2
B03H STANDBY A-PLOP SD SPEAKER R
42 B04E
RESET-SYSTEMn 1D38
B02E AC19 AUDIO-MUTE-UP 4 1
PO_7 MUTE
5D03 2
B01F HDMI & CI 1T01 7D03 7D03
DETECT2 3
TX31XX B03C MAIN SWITCH A-STBY STANDBY &
B02I ANALOG VIDEO MAINS-OK PROTECTION
MAIN HYBRID B03C DETECT SUBWOOFER
(RES)
TUNER 9 IF-AGC 3F77 IF-AGC AD12
4MHZ IF_AGC
2F75 3F79-1
B04E HEADPHONE B01J TEMP SENSOR + HEADPHONE
10 TUN-IF-P 9F03 PNX-IF-P AE12
IF-OUT1 TUNER_P
RF IN BANDPASS 7EE0-1 7EE0-2
11 TUN-IF-N 9F02 2F79 3F79-4 FILTER PNX-IF-N AF12 AD1 RESET-AUDIO A-PLOP B03A
IF-OUT2 TUNER_N PO_6
B04A
7EE1
TPA6111A2DGN
HEADPHONE
B01H HDMI B04D HDMI B04A ANALOGUE EXTERNALS A B02D PNX85500: AUDIO AMPLIFIER
5
SHUTDOWN 1328
7EC1 1 AMP1 2
SII9287BCNU VO_1
AF7 ADAC(3) 2
ADAC3 IN-1 7 AMP2 3
1P05 VO_2
1E01
1 HEADPHONE
1 DRX2+ 90 6 AUDIO-IN1-L AD6 ADAC(4) 6 8
AE10 AIN1_L
ADAC4 IN-2 VDD +3V3 OUT 3.5mm
3 DRX2- 89
1
2
4 DRX1+ 87 2 AUDIO-IN1-R AF10
6 DRX1- 86 AIN1_R
RXD
7 DRX0+ 84
9 DRX0- 83
PNX85500 B01C USB HUB
18
19
10 DRXC+ 81 1E02 B02E CONROL
HDMI SIDE 12 DRXC- 80 6 AUDIO-IN2-L AD10
AIN2_L
CONNECTOR
+5V-USB2
2 AUDIO-IN2-R AC10 1P08
AIN2_R
HDMI 1
1
3 ARX2- 22 4
1
2
4 ARX1+ 20
6 ARX1- 19
RXA
7 ARX0+ 17 B02A FLASH B01B FLASH
B04B ANALOGUE EXTERNALS B
18
9 ARX0- 16
19
10 14 1E08
ARXC+ 7F20
HDMI 3 12 ARXC- 13 6 AUDIO-IN3-L AE9
AIN3_L NAND04GW3B2DN6F
CONNECTOR
AUDIO IN
L+R 4 AUDIO-IN3-R AF9 NAND
AIN3_R
FLASH
XIO_D XIO-D(00-07)
9,27,64
+3V3-HDMI VCC33
1E09 512MB
2 AUDIO-IN4-L AD9
AIN4_L
VGA (OR DVI)
AUDIO 3 AUDIO-IN4-R AC9
AIN4_R 12,37
VCC +3V3
1
+3V3
1P03
1E07 7S09
1 BRX2+ 42 2
DIGITAL 1 SPDIF-OUT 3 &
3 BRX2- 41 1 SPDIF-OUT-PNX AF5
AUDIO
1
SPDIF_OUT
2
4 BRX1+ 39 OUT 4
39 B02G STANDBY B02B MEMORY
6 BRX1- B05A DDR
RXB
7 BRX0+ 36
8 5 SEL-HDMI-ARC AF18
9 BRX0- 35 P0_4 DQ DDR2-D(0-31)
18
19
10 BRXC+ 33
7B00 7B02 7B03 7B01
HDMI 2 12 BRXC- 32 EDE1108AGBG EDE1108AGBG EDE1108AGBG EDE1108AGBG
CONNECTOR B02C HDMI_DV
D(0-7)
D(8-15)
D(16-23)
D(24-31)
1
2
4 69 58 HDMIA-RX1+ U25
CRX1+ TX1_P RX1_A_P
VDDL
VREF
VDDL
VREF
VDDL
VREF
VDDL
VREF
6 68 HDMIA-RX1- U26
CRX1- TX1_N 59 RX1_A_N
RXC 56 HDMIA-RX2+ T25 A1 E2 A1 E2 A1 E2 A1 E2
7 CRX0+ 66 TX2_P RX0_A_P
9 CRX0- 65 57 HDMIA-RX2- T26 A DDR2-A(0-13)
TX2_N RX0_A_N
18
19
10 CRXC+ 63 +1V8
12 62 3S0W W24 DDR2-VREF-DDR
HDMI 1 CRXC-
+3V3 RREF
CONNECTOR
5EC2 A2
14 ARC-eHDMI+ eHDMI+ VREF_1 DDR2-VREF-CTRL2
V1
VREF_2 DDR2-VREF-CTRL3
18940_402_100810.eps
100811
2010-Oct-01 back to
div. table
Block Diagrams Q551.1L LA 9. EN 69
D(0-7)
D(8-15)
D(16-23)
D(24-31)
SDRAM SDRAM SDRAM SDRAM
128MB 128MB 128MB 128MB
7E10 F8 E8 F8 E8 F8 E8 F8 E8
1N00 LAN8710A-EZK
A DDR2-A(0-13)
ETH-RXD SDCD DDR-CLK_N
CLK_N
ETHERNET ETH-TXD CLK_P DDR-CLK_P
SDWP
7 ETH-RXCLK AA3
TXCLK B06C AMBILIGHT CPLD B09A NON DVBS CONNECTOR BOARD
20 ETH-TXCLK AA2 7GA0
ETHERNET RXCLK 1M59
XC9572XL
AE17 22 AMBI-SPI-CLK-OUT 1
CONNECTOR PNX85500
RJ45 27 AMBI-SPI-SDO-OUT 2
3
25M
AMBI-SPI-SDI-OUT_G1
1E70
23
AF17 B02H POWER AF1 SENSE+1V1
VDD_1V1 B03B 29 AMBI-PWM-CLK_B2 5
AA15 SENSE+1V2 AMBI-SPI-CS-OUTn_R2 7
VDDA_1V2 B03D 30
19 8
PNX-SPI-CSBn 5 CPLD 31 AMBI-LATCH1_G2 TO AMBILIGHT
RESET-ETHERNETn AMBI-PROG_B1 10 MODULE
B02G B02E CONTROL PNX-SPI-CLK 41 19
PNX-SPI-SDI 40 20 AMBI-BLANK_R1 11
PNX-SPI-SDO 39 28 AMBI-LATCH2_DIS 13
AC5 PXCLK54 43 21 AMBI-SPI-CS-EXTLAMPSn 14
CLK_54_OUT
V22 PNX-SPI-CS-BLn 3 32 AMBI-TEMP 15
GPI0_7
B06B
+5V-USB2
U23 SELECT-SAW 1P08
GPI0_11 B01F
AE4 RESET-SYSTEMn 1
1
4
B02A FLASH
NAND
FLASH B04C ETHERNET + SERVICE
12,37 1E06
VCC +3V3 Y23 RXD1-MIPS 2
GPI0_2
512MB XIO-D(00-07) XIO_D UART
Y24 TXD1-MIPS 3 SERVICE
GPI0_3
1 CONNECTOR
1
1S02
RESET-STBYn
AF17 OUTP
B04D HDMI XTAL_O 2
TO PIN: INP
7EC0 3 ENABLE -3V3-5V
1P02-13 GND +12V B03E
EF CEC-HDMI AF19
1P03-13 PCEC-HDMI P1_2 +3V3-STANDBY ENABLE -1V8
B03B B03D
1
1P04-13
2
AD21 ENABLE-3V3n DETECT2
1P05-13 7EC1 P2_7 B02G B03A
CONTROL
SII9287ACNU
B02C HDMI_DV AF18 SEL-HDMI-ARC 1M99
P0_4 B02D
ARX-HOTPLUG 31 AE20 LAMP-ON 5
P2_2
18
1P04-19 HDMIB-RC HDMI_RX
19
BRX-HOTPLUG 35 HDMI AE18 RESET-ETHERNETn BACKLIGHT-PWM_BL-VS 6 TO
1P03-19 P0_3 B04C B06C
CRX-HOTPLUG 41 SWITCH AB17 CTRL-DISP BACKLIGHT-BOOST 7 POWER
4x HDMI 1P02-19 3S0W P0_0 B06B B01E SUPPLY
CONNECTOR DRX-HOTPLUG 45 W24 AC21 POWER-OK 9
1P05-19 +3V3 RREF P2_6
AB19 RESET-AUDIO 3D-LR 8
P0_6 B04E B06C
AC19 AUDIO-MUTE-UP
P0_7 B03A
1M95
TO
AF20 STANDBY 2 POWER
P2_3
SUPPLY 18940_403_100811.eps
100930
2010-Oct-01 back to
div. table
Block Diagrams Q551.1L LA 9. EN 70
B02E
3S6E
3S6D
B25 3S5Y SDA-SSB
3_SDA
A24 3S5Z SCL-SSB
3_SCL
+3V3 AIN-5V
ERR
3EC5
3EC3
3FE9
3FE8
3FD3
3FD4
13
PNX85500 53 54 46 45 1 2
CONTROL 1P04
3S69
3S6A
C25 3S56 1F52 7EC1 7FE0 7FD1
1
SDA-UP-MIPS
2
16
3EC1-1
3EC1-3
29 ARX-DDC-SDA
1_SDA 3F63 3 SII9287B TC90517FG LM75BDP
C26 3S57 SCL-UP-MIPS DEBUG 30 ARX-DDC-SCL 15
1_SCL 3F62 HDMI DEMODULATOR TEMP
18
1
19
7F52 ONLY
MUX BIN-5V SENSOR
M25P05-AVMN6P B02G PNX85500: STANDBY
B02G HDMI
3F60
3F59
CONTROLER RES
5 6 CONNECTOR 3 ERR
FLASH 6 PNX-SPI-CLK AF24 +3V3-STANDBY ERR 1P03 42
8 SPI_CLK 23
1
2
PNX-SPI-WPn 16
3ECA-1
3ECA-2
+3V3-STANDBY VCC 3 AE22 STANDBY 7F58 33 BRX-DDC-SDA
P6_5
1 PNX-SPI-CSBn AF23 M24C64
512K SPI_CSB BRX-DDC-SCL 15
ERR ERR 34
18
5 PNX-SPI-SDO AE23
3S6V
19
3S2F
3S6W
SPI_SDO 15 53 AC23 EEPROM CIN-5V
2 PNX-SPI-SDI AF25 SPI_SDI MC_SDA (NVM)
3S2G HDMI Only for sets Brazil RES
STANDBY AC24
MC_SCL CONNECTOR 2
SW ERR B01H HDMI
RES 1P02
35
1
2
39 16
3ECA-3
3ECA-4
CRX-DDC-SDA
+3V3-STANDBY
MAIN NVM
40 CRX-DDC-SCL 15
SW
18
19
3S1H
3S1G
AE21 RXD-UP 3F65 3 uP
P3_0
CONNECTOR 1
LEVEL SHIFTED +3V3 1P05
7F20 3F64
AF21 TXD-UP 1 FOR DEBUG
1
2
NAND04GW3B2DN6F 16
3FBF-2
3FBF-1
Y25 DDCA-SDA
3ECU-2
3ECU-4
FLASH DDC_A_SDA
FLASH Y26 DDCA-SCL
XIO-D(00-07) XIO_D DDC_A_SCL +3V3 B01I VGA
512MB
HDMI_DV B04C ETHERNET + SERVICE +5V-EDID +5V-VGA
MAIN
SW 1E06
3S83
3S84
Y23 RXD1-MIPS 3E53-4 3E53-3 1E05
3
3FC1
3FC2
10
GPIO_2
15
9FC1 12
5
3ECP-3
3ECP-1
UART 47 VGA-SDA-EDID-HDMI
Y24 TXD1-MIPS 3E53-2 3E53-1
2 SERVICE EDID
GPIO_3 9FC3 15
CONNECTOR SW 48 VGA-SCL-EDID-HDMI
1
6
1
11
3S6F
3S6G
B24 3S60 SDA-TUNER 3F75 TUN-P7
4_SDA
B02B
A23 3S61 SCL-TUNER 3F76 TUN-P6
D(0-7)
4_SCL
D(8-15)
MEMORY
DDR2-A(0-13) ERR
A 18 7 6
DDR2-D(0-31) DQ
7B02 7B03 1T01
H5PS1G83EFR H5PS1G83EFR TX31XX
EDE1108AGBG EDE1108AGBG MAIN
TUNER
SDRAM SDRAM
D(16-23)
D(24-31)
ERR
34
3S6B
3S6C
B26 3S58 SDA-SET 9S12 SDA-DISP 3G2W 50
2_SDA LVDS
A25 3S5W SCL-SET 9S11 SCL-DISP 3G2Y 49 CONNECTOR
7E10
2_SCL
LAN8710A-EZK +3V3
ERR +3V3 ERR
14 64
11 ETH-RXD(0) Y5 2 1
RXD_0 B09A NON DVBS CONNECTOR BOARD
10 ETH-RXD(1) Y6
3S67
3S65
3S68
3S66
3S81
3S80
1N00 RXD_2 W21 RXD2-MIPS PCA9540B 3C84 2
ETHERNET 8 ETH-RXD(3) AC1 GPIO_2 5
RXD_3 2D
7 ETH-RXCLK AA3 W22 TXD2-MIPS 2 CHAN. 3C85 3
RXCLK GPIO_3 DIMMING
MULTIPLEX.
7
22 ETH-TXD(0) AA1
TXD_0 B04B ANALOGUE ERR 1M71
23 ETH-TXD(1) AA4 8 3C83
TXD_1 EXTERNALS B 24 3
24 ETH-TXD(2) AB1 TO
ETHERNET TXD_2
25 ETH-TXD(3) AB2 1ECB 3C81 1 TEMPERATURE
CONNECTOR TXD_3 RES SENSOR
RJ45 20 ETH-TXCLK AA2 6 5
TXCLK
4 3 9S13 RES
2 1
SDA-BL
9S10 SCL-BL
2010-Oct-01 back to
div. table
Block Diagrams Q551.1L LA 9. EN 71
5U02
7U03
10 10 BL-SPI-SDO +3V3 +3V3 TPS53126PW 7U02-1 12V/1V8 B04D HDMI
N.C. B03e
11 11 BL-SPI-CSn COVERSION
N.C. 12 +3V3 +3V3
12 12 BL-SPI-CLK Dual
N.C. 5U00 +1V8 B03e
Synchronous 7U02-2 B02b,h,B03d, 5EC0 +3V3-HDMI
Optional 1M99 is 12 pin connector Step-Down B05a
Controller 14 +3V3-STANDBY +3V3-STANDBY
B01K TUNER BRAZIL B03c
1M95 1M95
+3V3-STANDBY B01e,B02e, +1V2-BRA-VDDC +1V2-BRA-VDDC +5V-VGA +5V-VGA
1 1 7U01
3V3_ST g,h,B03a,b,h, B01g B01I
2 2 STANDBY B04d,e,B09a, +1V2-BRA-DR1 +1V2-BRA-DR1
STANDBY B02G 1 +5V-EDID
3 3 B01g 12V/1V1
GND1
4 4 +3V3 +3V3 7U04 COVERSION
GND1 B03e
5 5 +5V +5V
6EC1
GND1 5FE7 +3V3-BRA 23 B03e
1U40 +12V 24 5U01 +1V1 B02g,h, 1P04
6 6 B03b,d,e,g, 5FE4 +3V3-BRA-FLT HDMI 3 AIN-5V
+12V B03e 18
7 7 B09a CONNECTOR
+12V T 3.0A
8 8 +5V +5V 1P03
+12V B03e HDMI 2
9 9 +24V-AUDIO-POWER 7FE3 18 BIN-5V
+VSND B02d,B03a DC / DC CONNECTOR
10 10 5FE9 +2V5-BRA B03D
GND_SND IN OUT
11 11 MAINS-OK COM +1V8 +1V8 1P02
N.C. B03A HDMI 1 CIN-5V
B03b 18
CONNECTOR
7UA3 +1V2
B02h DIN-5V DIN-5V
B01h
B02A PNX85500: NANDFLASH
+3V3 +3V3 CONDITIONAL ACCESS
B03e +3V3 +3V3 +12V
B03e HEADPHONE
+5V +5V B04E
B03e +5V +5V
+3V3 +3V3
B03e
3U16 +3V3 B03e
COMMON INTERFACE B02B PNX85500: SDRAM +3V3-STANDBY +3V3-STANDBY
B01A 7UC0 B03c
3U15 +2V5
+3V3 +1V8 +1V8 IN OUT
+3V3 B03b B02h
COM
B03e 3S20 CUA0 +2V5-LVDS
DDR2-VREF-CTRL3
B02h B05A DDR
+5V +5V
B03e 3S06 DDR2-VREF-CTRL2 NOT FOR 5000 SERIES
3F01 +5VCA +5V5-TUN +5V5-TUN +1V8 +1V8
B03b
+T B03e 3B20
+5V-TUN DDR2-VREF-DDR
7UA6
B01f
FLASH B02C PNX85500: DIGITAL VIDEO IN
B01B ENABLE-1V8
+12V +12V B06A DISPLAY INTERFACING-VDISP
+3V3 +3V3 +3V3 B03c
+3V3 B03e 7UA0
B03e 3UA0 +VDISP-INT +VDISP-INT
VOLT. +2V5-REF
REG. B03h
1G03 +VDISP
B01C USB HUB B06b
B02D PNX85500: AUDIO
T 3.0A
+3V3 +3V3
OR
5G01
B03e DC / DC
+3V3 +3V3
B03E 1G00
+5V +5V B03e 5G02
+1V1 +1V1
B03e 3S11 B01,a,b,c,d,e,
3F25 +5V-USB1 +3V3-ARC B03b T 3.0A
+12V +12V g,j,k,
+T 7S08 B03c
3F32 B02a,c,d,e,h,
+5V-USB2 +2V5-AUDIO
IN OUT B02h B03c,f,g,h,
+T 5UD3 7UD1 5UD2 +3V3
COM B04a,c,d,e,
B06B VIDEO OUT - LVDS
+24V-AUDIO-POWER +24V-AUDIO-POWER IN OUT B06b,c,d,
B03c COM B09a
+3V3 +3V3
3S0Z +24V-AUDIO-VDD 7UD0 B03e
B01D SD-CARD 5UD0 5UD1 +5V5-TUN
IN OUT
COM
B03d +VDISP +VDISP
+3V3 +3V3 B06a
B03e PNX85500: MIPS 6UD0 B01,a,c,e,k,
3F40 B02E +5V
+3V3-SD B03c,d,B04a,d,
B09a
+T +3V3 +3V3 B06C .
B03e
+3V3-STANDBY +3V3-STANDBY +3V3 +3V3
B03c B03e
B03F TEMPSENSOR + AMBILIGHT 5GA0 VINT
B01E PNX85500: CONTROL
+3V3 +3V3 5GA1 VIO
+3V3 +3V3 B02G PNX85500: STANDBY CONTROLLER B03e
B03e
+3V3-STANDBY +3V3-STANDBY 5UM1 1UM0 V-AMBI
B03c +1V1 +1V1
B03b
T 1.0A B06D SPI-BUFFER
+5V +5V
B03e +3V3 +3V3
+3V3-STANDBY +3V3-STANDBY B03e
B03c FAN - CONTROL
B03G
B01F HDMI & CI +3V3 +3V3
B09A (*NON) DVBS CONNECTOR BOARD
B03e
+5V-TUN +5V-TUN B02H PNX85500: POWER
+12V +12V +3V3 +3V3
B03d B03c B03e
9F71 +5V-TUN-PIN +1V1 +1V1
B03b +3V3-STANDBY +3V3-STANDBY
B03c
+1V2 +1V2 +5V +5V
B03d B03H VDISP - SWITCH B03e
+1V8 +1V8 1M20
B03b +3V3 +3V3 5
B01G TOSHIBA SUPPLY +2V5 +2V5 B03e
B03d +3V3-STANDBY +3V3-STANDBY 8 TO
B03c
+2V5-AUDIO +2V5-AUDIO IR/LED
+3V3 +3V3 B02d 1M09
+12VD +12VD PANEL
B03e B03c 1 +24V
7FA3 +2V5-LVDS +2V5-LVDS
B03d +VDISP-INT
5FA3 +1V2-BRA-VDDC 7UU1 B06a 2 1C86 1M59
IN OUT B01k +3V3 +3V3
B03e *1T86 21
COM
5FA4 +1V2-BRA-DR1
B01k +3V3-STANDBY +3V3-STANDBY T 2.0A
B03c 7UU2
+12V +12V
LCD-PWR-ONn
B03c
18760_407_100810.eps
100929
2010-Oct-01 back to
div. table
Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 72
27
+24V TLC5946RHB
1
3B00-1 VCC 2B04-2 B6
2
BLANK 1 8 31 4 PWM-R1
3 BLANK 0 2B04-3 B8
PWM-CLOCK-BUF 150R 24 5 PWM-G1
4 GSCLK 1
3B18 26 6 PWM-B1 2B04-4 B7
5 IREF 2
1K8 FB35 3 7 PWM-G3
6 MODE 3 2B08 E12
FB03 PROG 4 3B00-4 5 1 8 PWM-R3
7 SCLK 4
SPI-CLOCK-BUF 150R 2 9 PWM-R2 2B09 E12
8 SIN 5
SPI-DATA-IN-BUF 23 10 PWM-G2
9 SOUT 6 2B10 F9
SPI-DATA-IN 3 6 11 PWM-B2
10 FB04 7
TEMP-SENSOR SPI-DATA-OUT 3B00-3 150R 3B21 22 OUT 14 PWM-B3 2B11 A9
11 XERR 8
FB20 +3V3 150R 3B22 25 15 PWM-G4
12 XHALF 9 2B17 D8
FB05 LATCH 2 3B00-2 7 10K 32 16 PWM-R4
13 XLAT 10
B +3V3 150R 17 PWM-B4 B
14 FB06 11 2B20 D4
BLANK 12 18 PWM-B5
15 12
FB07 PROG 13 19 PWM-G5 3004 E12
7
8
5
6
16 13
FB08 28 NC 20 PWM-R5
17 FB10 14 3B00-1 A6
LATCH 29 21 DATA-SWITCH
18 15
FB11
100p
100p
100p
100p
SPI-CS 3B00-2 B6
2B04-2
2B04-1
2B04-4
2B04-3
19 3B31
GND GND_HS
2
1
4
3
20 +3V3 FB12 +3V3 3B00-3 B6
30
33
21 PWM-CLOCK 2K0
22 7B26-2 3B00-4 B6
FB13 SPI-DATA-RETURN TLC5946RHB
23 3B01-1 E7
FB15 SPI-DATA-IN 34 VIA 42
24
FB16 SPI-CLOCK 35 41 3B01-2 D7
25 VIA VIA
27 26 36 40
VIA 3B02-1 E3
C 1M83 C 3B02-2 E5
37
38
39
3B03-1 H14
3B03-2 H14
3B03-3 H14
+3V3
3B03-4 H14
3B07-1 F3
+3V3 3B07-2 G3
3B34 3B07-3 H3
+3V3 +3V3 3B07-4 G3
100n
2B20
SPI-DATA-IN-BUF 100K RES
D D 3B11 E12
+3V3
100n
2B17
SPI-CLOCK-BUF
7
6
3B13-3 H3
7B07 7B20-1
8
M95010-WDW6 74LVC2G17 3B13-4 I3
5
+3V3 VCC 7B30
3B39-2
3B39-3
1K5 1%
1K5 1%
5 2 3B18 A8
2
3
FB40
5
D Φ Q PWM-CLOCK-BUF
7B06 PWM-CLOCK 2 3B01-2 7 1 6 1 3B30-1 8 1 3B21 B7
(64K) 4 TEMP-SENSOR
5
74LVC1G32GW 6
C 100R 220R 3B22 B8
SPI-CS 1 3
2
4 1 LMV331IDCK
2
S 3B02-2 3B30-1 D9
RES
33p
2B00
DATA-SWITCH 2 7 +3V3
+3V3 HOLD
10K
10n
100p
3004
3B30-4 E9
2B02
2B08
1 3B02-1 8 3 7 10K 2
3B11
3
-T
10K
4
E E 3B34 D13
7B20-2
1
5
2B09
3B39-1
1K5 1%
3B37 G14
8
3B01-1 3B30-4
SPI-DATA-RETURN SPI-CLOCK 1 8 3 4 4 5 SPI-CLOCK-BUF 3B39-1 E13
100R 220R 3B39-2 D12
2
3B39-3 D13
33p
2B01
+24V 7000 G5
100p
2B10
7001 G7
F F 7002 G8
7B23-1
BC847BS(COL) 7003 G10
10K
6
7004 G11
8 3B07-1 1
2 7005 G13
1 7B06 D3
7B07 D4
10K
2 3B07-2 7
7B20-1 D8
FB30 7B20-2 E8
PWM-B1
3B35
+24V 7B23-1 F4
+24V 7000
LTW-008RGB 7001 7002 7003 7004 7005 270R
G LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB G 7B23-2 G4
3B36
7B25 H3
5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 270R
7B23-2 7B26-1 A8
BC847BS(COL) 3B37
10K
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 7B26-2 C9
5 3B07-4 4
68R 7B30 D13
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
FB01 A1
4
FB03 B1
10K
1 3B03-1 8
FB04 B1
3 3B07-3 6
FB31 1K5
FB05 B1
PWM-R1 FB06 B2
3B03-2
H 2 7 H
+24V FB07 B1
1K5
3 3B03-3 6
FB08 B1
1K5 FB10 B2
7B25
3B03-4 FB11 B1
10K
BC847BW 3 4 5
3 3B13-3 6
1K5 FB12 B2
1
FB13 C1
100n
2B03
2
FB15 C1
10K
FB16 C1
5 3B13-4 4
FB20 B7
I FB32
I FB30 G3
PWM-G1
FB31 H3
FB32 I3
FB35 A8
FB40 D12
FB41 E13
1 2 3 4 5 6 7 8 9 10 11 12 13 14
B001 B002 B007 6 2009-12-04
5 2009-10-28
AL 2K10 LiteOn 4 2009-10-07
8204 000 8978
15 LED Common 3 2009-08-27
2 2009-07-03
18770_600_100212.eps
100218
2010-Oct-01 back to
div. table
Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 73
10K
A BC847BS(COL) 6 A 3B52 B7
5 3B55-4 4
2
3B53-1 B7
1
3B53-2 C7
10K
3 3B55-3 6
FB70
3B53-3 C7
PWM-B2
3B50 3B53-4 C7
+24V 7105 7104 7103 7102 7101 7100
LTW-008RGB LTW-008RGB 270R LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB 3B55-1 C3
3B51
B 5 BLUE 6 5 BLUE 6 270R 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 B 3B55-2 B3
7B50-2
3B52
10K
BC847BS(COL) 3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
7 3B55-2 2
68R
3B55-3 A3
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
3B53-1
1 8 3B55-4 A3
4
1K5 +24V
10K
2 3B53-2 7 3B57-2 D3
1 3B55-1 8
1K5
FB71 3B57-3 C3
100n
2B50
PWM-G2 3 3B53-3 6
1K5 3C00-1 G3
+24V
C 4 3B53-4 5 C
1K5
3C00-2 F3
7B51 3C00-3 F3
10K
BC847BW 3
3 3B57-3 6
1 3C00-4 E3
2
3C06-1 G3
10K
3C06-2 H3
7 3B57-2 2
D FB72 D 3C10 F4
PWM-R2
3C11 F4
3C12 F4
3C15-1 G4
3C15-2 G4
+24V
3C15-3 G4
E 7C20-1 E 3C15-4 G4
10K
BC847BS(COL) 6
7100 B11
5 3C00-4 4
2
7101 B10
1
7102 B9
10K
3 3C00-3 6
FC01
7103 B7
PWM-B3
1 3C10 2 7104 B6
+24V 7200 7201 7202
270R LTW-008RGB LTW-008RGB
LTW-008RGB
F 1 3C11 2 F 7105 B5
270R 5 BLUE 6 5 BLUE 6 5 BLUE 6 Blue
7C20-2
3C12
7200 F8
10K
BC847BS(COL) 3 1 GREEN 2 1 GREEN 2 1 GREEN 2 Green
7 3C00-2 2
5
68R
3 RED 4 3 RED 4 3 RED 4
7201 F9
Red
1 3C15-1 8
7202 F10
4
1K5
10K
3C15-2
7B50-1 A3
2 7
1 3C00-1 8
FC02 1K5 7B50-2 B3
PWM-G3
3 3C15-3 6
G +24V
1K5
G 7B51 C3
4 3C15-4 5 7C20-1 E3
1K5
7C22 7C20-2 F3
10K
BC847BW 3
1 3C06-1 8
1 7C22 G3
2
FB70 B3
10K
FB71 C3
7 3C06-2 2
H FC03
H FB72 D3
PWM-R3
FC01 F3
FC02 G3
FC03 H3
1 2 3 4 5 6 7 8 9 10 11 12
6 2009-12-04
5 2009-10-28
AL 2K10 LiteOn 4 2009-10-07
8204 000 8978
15 LED Common 3 2009-08-27
2 2009-07-03
18770_601_100212.eps
100212
2010-Oct-01 back to
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 74
15 LED LiteOn
AL2A AL2A
1 2 3 4 5 6 7 8 9 10
1M84 A10
2D01 B6
7203 A3
7204 A4
7205 A5
A A
FD18 C7
FH12-25S-0.5SH(55)
100n
2D01
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22 C
23
24
+24V 25
26 27
FD18
D D
1 2 3 4 5 6 7 8 9 10
3 2009-12-07
2 2009-10-07
15 LED LiteOn 8204 000 8970 1 2009-07-02
AL 2K10 3104 313 63823
18770_620_100212.eps
100218
2010-Oct-01 back to
div. table
Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 75
15 LED LiteOn
15 LED LiteOn
AL2B AL2B
1 2 3 4 5 6 7 8 9 10 11 12 13 2D10 C13
2D11 H13
3D02-1 A1
+24V
3D02-2 A1
7D01-1
3D02-3 B1
BC847BS(COL)
10K
6
3D02-4 B1
8 3D02-1 1
2
A A 3D03-3 H2
1
10K
3D03-4 G2
2 3D02-2 7
FD01
3D04-1 F2
PWM-B4
3D10
+24V 3D04-2 G2
+24V 7300 7301 7302 7303 7304 7305 270R
LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB
3D11 3D04-3 E2
5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 270R
7D01-2
BC847BS(COL) 3D12 3D04-4 F2
10K
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
B B
6 3D02-3 3
68R 3D05-3 C1
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
4 3D05-4 D1
10K
1 3D13-1 8
3D10 B12
4 3D02-4 5
FD02 1K5
PWM-R4 3D11 B12
2 3D13-2 7
+24V
1K5 3D12 B12
3 3D13-3 6
C 1K5 C 3D13-1 B12
7D02
10K
BC847BW 3 4 3D13-4 5 3D13-2 C12
3 3D05-3 6
1K5
1
3D13-3 C12
100n
2D10
2
3D13-4 C12
10K
5 3D05-4 4
FD03
3D15 F12
PWM-G4
3D16 F12
D D 3D17 F12
3D18-1 G12
3D18-2 G12
3D18-3 G12
+24V
3D18-4 G12
7300 B5
3
E 7D03-1 E 7301 B6
BC847BS(COL)
10K
6
3D04-3
6
2
7302 B7
5
1 7303 B8
10K
3D04-4
7304 B10
4
FD04 7305 B11
PWM-B5
3D15
+24V
+24V 7400 7401 7402 7403 7404 7405 7400 F5
270R
LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB
F 3D16 F
1
5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 270R
7401 F6
7D03-2
BC847BS(COL) 3D17
10K
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 7402 F7
3D04-1
8
68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 7403 F8
7
4
7404 F10
10K
3D04-2
1 3D18-1 8
2
7405 F11
FD05 1K5
PWM-R5 7D01-1 A2
2 3D18-2 7
G +24V
1K5
G
7D01-2 B2
3 3D18-3 6
5
1K5 7D02 C2
7D04
10K
BC847BW 3 4 3D18-4 5
3D03-4
4
1K5
7D03-1 E2
1
7D03-2 F2
3
100n
2D11
10K
7D04 G2
3D03-3
6
H FD06 H FD01 A1
PWM-G5
FD02 C1
FD03 D1
FD04 F1
FD05 G1
FD06 H1
1 2 3 4 5 6 7 8 9 10 11 12 13
3 2009-12-07
2 2009-10-07
15 LED LiteOn 8204 000 8970
1 2009-07-02
AL 2K10 3104 313 63823
18770_621_100212.eps
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2010-Oct-01 back to
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 76
AmbiLight LiteOn
36 LED
FB01 FC01
FB32
3D21
FD03 FD05
3B35
3B36
7B25 FB04 FB12
7B06 3B51 3D18
FB11
3D22
3B03
3B37
3C00
3B31
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205 7300 7301 7302 7303 7304 7305 7400 7401 7402 7403 7404 7405 7500 7501 7502 7503 7504 7505
3B52
3B55
FB07 2B03 3B50 3B53 2D04 2D11
3C12
3B18
3B34 3C15 3D00
2B09
2E10
3B30
3D10 FD18
2D10
FB70 3C11
3F12
3B01
FB40 FB05 FB06 FB35 3E11 FD19 3F10
FB41 3B21 3B22 7B50 2C01
7D26
3B07
2B17 2B50 2B11
7B26
3B13
3D12
FF02 FF01
3D11
3E12
7F01
3F02
3F05
3C10 FD01 FD02
3E02
7E01
3D13
7F02
3F11
2B01
FB13 3E10
3E05
7D01
2F10
3E13
3D05
3D02
7B30 FB03 3B57 3F13
2B00
2B04
7D02
7E02
7B23 7B20 FB72 FB20 FD04
B001
B007
B002
B003
B005
B004
B006
FB30 FB10
3B00
3B39 FB08 FB16 FB31 FB15 FC02 FC03 FB71 FD06 FF03
7C20
3B02
3C06
2B10
2B02
2B20
7B51
7C22
7B07
3004
2B08
3B11
1M83 1M84
3104 313 6383.2
19030_602_100809.eps
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2010-Oct-01 back to
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 77
27
+24V TLC5946RHB 2B04-2 B6
1
3B00-1 VCC
2 2B04-3 B8
BLANK 1 8 31 4 PWM-R1
3 BLANK 0
PWM-CLOCK-BUF 150R 24 5 PWM-G1 2B04-4 B7
4 GSCLK 1
3B18 26 6 PWM-B1
5 IREF 2 2B08 E12
1K8 FB35 3 7 PWM-G3
6 MODE 3
FB03 PROG 4 3B00-4 5 1 8 PWM-R3
7 SCLK 4 2B09 E12
SPI-CLOCK-BUF 150R 2 9 PWM-R2
8 SIN 5
SPI-DATA-IN-BUF 23 10 PWM-G2 2B10 F9
9 SOUT 6
SPI-DATA-IN 3 6 11 PWM-B2
10 FB04 7 2B11 A9
TEMP-SENSOR SPI-DATA-OUT 3B00-3 150R 3B21 22 OUT 14 PWM-B3
11 XERR 8
FB20 +3V3 150R 3B22 25 15 PWM-G4 2B17 D8
12 XHALF 9
FB05 LATCH 2 3B00-2 7 10K 32 16 PWM-R4
13 XLAT 10 2B20 D4
B +3V3 150R 17 PWM-B4 B
14 FB06 11
BLANK 12 18 PWM-B5 3004 E12
15 12
FB07 PROG 13 19 PWM-G5
7
8
5
6
16 13 3B00-1 A6
FB08 28 NC 20 PWM-R5
17 FB10 14
LATCH 29 21 DATA-SWITCH 3B00-2 B6
18 15
FB11
100p
100p
100p
100p
SPI-CS
2B04-2
2B04-1
2B04-4
2B04-3
19 3B31 3B00-3 B6
GND GND_HS
2
1
4
3
20 +3V3 FB12 +3V3
30
33
21 PWM-CLOCK 2K0 3B00-4 B6
22 7B26-2
FB13 SPI-DATA-RETURN TLC5946RHB 3B01-1 E7
23
FB15 SPI-DATA-IN 34 VIA 42 3B01-2 D7
24
FB16 SPI-CLOCK 35 41
25 VIA VIA 3B02-1 E3
27 26 36 40
VIA
3B02-2 E5
C 1M83 C
37
38
39
3B03-1 H14
3B03-2 H14
3B03-3 H14
3B03-4 H14
+3V3 3B07-1 F3
3B07-2 G3
+3V3
3B07-3 H3
3B34
3B07-4 G3
+3V3 +3V3
100n
2B20
SPI-DATA-IN-BUF 100K RES 3B11 E12
D +3V3
D
100n
3B13-3 H3
2B17
SPI-CLOCK-BUF
7
6
8
M95010-WDW6 74LVC2G17
5
+3V3 VCC 7B30 3B18 A8
3B39-2
3B39-3
1K5 1%
1K5 1%
5 2
2
3
FB40
5
D Φ Q PWM-CLOCK-BUF
3B21 B7
7B06 PWM-CLOCK 2 3B01-2 7 1 6 1 3B30-1 8 1
(64K) 4 TEMP-SENSOR
5
74LVC1G32GW 6 3B22 B8
C 100R 220R
SPI-CS 1 3
3B30-1 D9
2
4 1 LMV331IDCK
2
S 3B02-2
RES
33p
2B00
DATA-SWITCH 2 7 +3V3 3B30-4 E9
+3V3 HOLD
10K
10n
100p
3004
2B02
1 3B02-1 8 3 7 2 2B08
10K
3B11
W
3
3B31 B10
-T
10K
10K
GND 3B34 D13
FB41
4
E 7B20-2
E 3B35 G14
1
74LVC2G17
+3V3
3B36 G14
10n
5
3B37 G14
2B09
3B39-1
1K5 1%
8
33p
2B01
7000 G5
+24V
100p
2B10
7001 G7
7002 G8
F 7B23-1
F 7003 G10
BC847BS(COL)
10K
6 7004 G11
8 3B07-1 1
2 7005 G13
7B06 D3
1
7B07 D4
10K
7B20-1 D8
2 3B07-2 7
FB30
7B20-2 E8
PWM-B1 7B23-1 F4
3B35
+24V
+24V 7000 7B23-2 G4
99-235/RSBB7C-A24/2D 7001 7002 7003 7004 7005 270R
G 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D G
3B36 7B25 H3
5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 270R 7B26-1 A8
7B23-2
BC847BS(COL) 3B37 7B26-2 C9
10K
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
5 3B07-4 4
68R 7B30 D13
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
FB01 A1
4 FB03 B1
10K
FB04 B1
1 3B03-1 8
3 3B07-3 6
FB05 B1
FB31 1K5 FB06 B2
PWM-R1
3B03-2
H 2 7 H FB07 B1
+24V
1K5
FB08 B1
3 3B03-3 6 FB10 B2
1K5
7B25 FB11 B1
3B03-4
10K
BC847BW 3 4 5
FB12 B2
3 3B13-3 6
1K5
1 FB13 C1
FB15 C1
100n
2B03
2
FB16 C1
10K
FB20 B7
5 3B13-4 4
I FB32
I FB30 G3
PWM-G1
FB31 H3
FB32 I3
FB35 A8
FB40 D12
FB41 E13
1 2 3 4 5 6 7 8 9 10 11 12 13 14
B001 B002 B007
2 2009-11-27
1 2009-11-03
AL 2K10 Everlight
8204 000 9059
15 LED Common
18770_670_100212.eps
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2010-Oct-01 back to
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 78
10K
A BC847BS(COL) 6 A
5 3B55-4 4
2 3B53-1 B7
1
3B53-2 C7
10K
3B53-3 C7
3 3B55-3 6
FB70
PWM-B2 3B53-4 C7
3B50
+24V 7105 7104 7103 7102 7101 7100
99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 270R 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 3B55-1 C3
99-235/RSBB7C-A24/2D
3B51
B 5 BLUE 6 5 BLUE 6 270R 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 B 3B55-2 B3
7B50-2
3B52
10K
BC847BS(COL) 3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
3B55-3 A3
7 3B55-2 2
68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
3B53-1
1 8 3B55-4 A3
4
1K5 +24V
3B57-2 D3
10K
2 3B53-2 7
1 3B55-1 8
1K5 3B57-3 C3
FB71
100n
2B50
PWM-G2 3 3B53-3 6
1K5 3C00-1 G3
+24V
C 4 3B53-4 5 C 3C00-2 F3
1K5
7B51 3C00-3 F3
10K
BC847BW 3
3 3B57-3 6
1
3C00-4 E3
2
3C06-1 G3
10K
3C06-2 H3
7 3B57-2 2
D FB72 D 3C10 F4
PWM-R2
3C11 F4
3C12 F4
3C15-1 G4
3C15-2 G4
+24V
3C15-3 G4
E 7C20-1 E 3C15-4 G4
10K
BC847BS(COL) 6
5 3C00-4 4
7100 B11
2
7101 B10
10K
7102 B9
3 3C00-3 6
FC01 7103 B7
PWM-B3
1 3C10 2
+24V 7200 7201 7202 7104 B6
270R 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D
99-235/RSBB7C-A24/2D
F 1 3C11 2 F 7105 B5
270R 5 BLUE 6 5 BLUE 6 5 BLUE 6 Blue
7C20-2
3C12
10K
BC847BS(COL) 3 1 GREEN 2 1 GREEN 2 1 GREEN 2 Green
7200 F8
7 3C00-2 2
68R
5 3 RED 4 3 RED 4 3 RED 4 Red 7201 F9
1 3C15-1 8
4
1K5
7202 F10
10K
3C15-2
2 7
1 3C00-1 8
7B50-1 A3
FC02 1K5
PWM-G3 7B50-2 B3
3 3C15-3 6
G +24V G
1K5
7B51 C3
4 3C15-4 5
1K5 7C20-1 E3
7C22
10K
BC847BW 3
7C20-2 F3
1 3C06-1 8
1
7C22 G3
10K
FB70 B3
7 3C06-2 2
H H FB71 C3
FC03
PWM-R3
FB72 D3
FC01 F3
FC02 G3
1 2 3 4 5 6 7 8 9 10 11 12 FC03 H3
2 2009-11-27
1 2009-11-03
AL 2K10 Everlight
8204 000 9059
15 LED Common
18770_671_100212.eps
100212
2010-Oct-01 back to
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 79
15 LED Everlight
AL2A AL2A
1 2 3 4 5 6 7 8 9 10
1M84 A10
2D01 B6
7203 A3
A A 7204 A4
7205 A5
7203 7204 7205 1M84
99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D FD18 C7
SPI-CLOCK-BUF 1
SPI-DATA-OUT 2
Blue 5 BLUE 6 5 BLUE 6 5 BLUE 6 SPI-DATA-RETURN
+24V 3
4
Green 1 GREEN 2 1 GREEN 2 1 GREEN 2 PWM-CLOCK-BUF 5
+3V3 6
Red 3 RED 4 3 RED 4 3 RED 4 SPI-CS 7
LATCH 8
B 9
B
100n
2D01
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22 C
23
24
+24V 25
FD18 26 27
D D
1 2 3 4 5 6 7 8 9 10
1 2009-11-27
18770_660_100212.eps
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 80
15 LED Everlight
15 LED Everlight
AL2B AL2B
1 2 3 4 5 6 7 8 9 10 11 12 13
2D10 C13
+24V 2D11 H13
3D02-1 A1
7D01-1
BC847BS(COL) 3D02-2 A1
10K
6
8 3D02-1 1
A 2
A 3D02-3 B1
1 3D02-4 B1
10K
3D03-3 H2
2 3D02-2 7
FD01 3D03-4 G2
PWM-B4
3D10
+24V
+24V 7300 7301 7302 7303 7304 7305 68R 3D04-1 F2
99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D
3D11 RES
7D01-2
5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 68R
3D04-2 G2
BC847BS(COL) 3D12
10K
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 3D04-3 E2
B B
6 3D02-3 3
68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3D04-4 F2
4
3D05-3 C1
10K
1 3D13-1 8
4 3D02-4 5
3D05-4 D1
FD02 1K5
PWM-R4 3D10 B12
2 3D13-2 7
+24V
1K5
3D11 B12
3 3D13-3 6
C 1K5 C 3D12 B12
7D02
10K
BC847BW 3 4 3D13-4 5
3D13-1 B12
3 3D05-3 6
1K5
1
3D13-2 C12
100n
2D10
2
3D13-3 C12
10K
5 3D05-4 4
FD03
3D13-4 C12
PWM-G4
3D15 F12
D D 3D16 F12
3D17 F12
3D18-1 G12
3D18-2 G12
+24V
3D18-3 G12
3D18-4 G12
3
E 7D03-1 E 7300 B5
BC847BS(COL)
10K
6
3D04-3
6
2
7301 B6
5
1
7302 B7
10K
7303 B8
3D04-4
4
FD04 7304 B10
PWM-B5
3D15
+24V
+24V 7400 7401 7402 7403 7404 7405
7305 B11
68R
99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D
F 3D16 RES F 7400 F5
1
5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6 68R
7D03-2
BC847BS(COL) 3D17 7401 F6
10K
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
3D04-1
8
68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 7402 F7
7
4 7403 F8
10K
3D04-2
1 3D18-1 8
7404 F10
2
FD05 1K5
PWM-R5 7405 F11
2 3D18-2 7
G +24V
1K5
G 7D01-1 A2
3 3D18-3 6
5
1K5
7D01-2 B2
7D04
10K
BC847BW 3 4 3D18-4 5
3D03-4
7D02 C2
4
1K5
1
7D03-1 E2
3
100n
2D11
2
7D03-2 F2
10K
3D03-3
6
7D04 G2
H FD06 H
PWM-G5
FD01 A1
FD02 C1
FD03 D1
FD04 F1
FD05 G1
FD06 H1
1 2 3 4 5 6 7 8 9 10 11 12 13
1 2009-11-27
18770_661_100212.eps
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2010-Oct-01 back to
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 81
AmbiLight Everlight
30 LED
FB01 FC01
FB32
FD03 FD05
3B35
3B36
FB04
7B06 3B51
FB12
7B25 FB11
3B03
3B37
3C00
3B31
3B52
3B55
2B03 3B50 3B53
7203 7204 7205 7300 7301 7302 7303 7304 7305 7400 7401 7402 7403 7404 7405
FB07
3C12
3B18
7000 3B34
7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 3C15 7201 7202
2B09
3B30
FD18 3D17
FB70
3B01
FB40 3D10
2D10
FB05 FB06
3D12
FB41 FB35 7B50
3B07
3B13
2B17 3B21 2B11
7B26 2D01 3D05 3D15
2B50 3C11
3B22
2D11
FD01 FD02
2B01
3D02
3D03
FB13 7D01 3D11 7D03 3D18
7B30 FB03
B003
B005
B004
3B57
3D13
3D04
3D16
7D02
FB72 FB20 3C10 3C06 FD04
7D04
7B23 7B20
B001
3B00
B007
B002
FB30 FB16 FB10 FB31 FB15 FC02 FB71 FD06
7C20
FB08 FC03
2B04
3B39
3B02
2B10
2B02
2B20
7B51
7C22
3004
7B07
2B08
3B11
2B00
1M83 1M84
3104 313 6421.1
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 82
Common Interface
B01A B01A
1 2 3 4 5 6 7 8 9 10 11
1P00-A D10
1P00-B G10
+3V3
2F00 A6
3F06
3F01 CA-RST 100K 2F01 A2
2F00
+5V +5VCA TRANSPORT STREAM FROM CAM RES
7F00 CA-CD1n 4 3F07-4 5 2F02 B6
+T 0R4 100n
20
74LVC245A 10K
1
3EN1 CA-CD2n 2 3F07-2 7 2F03 D6
2F01
3EN2 10K
22u 16V
3F07-3 2F04 E6
19 CA-DATAENn 3 6
G3 +3V3
RES
A IF01 10K A
3F02 3F07-1 2F05 G6
CA-MOCLK 2 18 MOCLK CA-DATADIR 1 8
1
100R IF02 2 10K 2F06 H6
3F03-1
CA-MOVAL 1 8 3 17 MOVAL
CA-MOSTRT 3F03-2 2 7 100R 4 16 MOSTRT CA-ADDENn 1 3F08-1 8 3F01 A2
100R IF03 5 15 10K
6 14 MOCLK 2 3F08-2 7 3F02 A4
7 13 10K
8 12 MOVAL 3 3F08-3 6 3F03-1 A4
9 11 10K
MOSTRT 4 3F08-4 5 3F03-2 A4
10K
10
3F04-1 C4
MDO0 1 3F09-1 8 3F04-2 C4
B +3V3 10K B
MDO1 2 3F09-2 7 3F04-3 C4
2F02
RES 10K
7F01 MDO2 3 3F09-3 6 3F04-4 C4
100n
20
74LVC245A 10K
1 MDO3 4 3F09-4 5 IF04 3F05-1 C4
3EN1
3EN2 10K
19 3F05-2 C4
G3 3F10-1
IF05 MDO4 1 8
CA-MDO0 3F04-1 1 8 100R 2 18 MDO0 10K
3F05-3 C4
1 3F10-2
IF06 MDO5 2 7 3F05-4 C4
2
CA-MDO1 3F04-2 2 7 100R 3 17 MDO1 10K
CA-MDO2 3F04-3 3 6 100R 4 16 MDO2 MDO6 3 3F10-3 6 3F06 A9
CA-MDO3 3F04-4 4 5 100R 5 15 MDO3 10K
C CA-MDO4 3F05-1 1 8 100R 6 14 MDO4 MDO7 4 3F10-4 5 C 3F07-1 A9
CA-MDO5 3F05-2 2 7 100R 7 13 MDO5 10K
CA-MDO6 3F05-3 3 6 100R 8 12 MDO6 3F07-2 A9
CA-MDO7 3F05-4 4 5 100R 9 11 MDO7
3F12 3F07-3 A9
IF07 CA-RDY +3V3
10K
10
CA-WAITn 2 3F11-2 7
3F07-4 A9
10K 3F08-1 A9
+3V3 3 3F11-3 6 IF08
CA-INPACKn +5VCA
2F03 10K 3F08-2 A9
15-BIT ADDRESS RES CA-WP 4 3F11-4 5
7F02 100n 10K 3F08-3 B9
20
74LVC245A CA-VS1n 8 3F11-1 1 +3V3 ROW_A
1 10K 1P00-A 3F08-4 B9
3EN1
D GND1 D
3EN2 1 3F09-1 B9
19 CA-ADDENn CA-D03 D3
G3 2
CA-D04 D4 3F09-2 B9
3
XIO-A00 18 2 CA-A00 CA-D05 D5
1 4
CA-D06 D6 3F09-3 B9
2 5
XIO-A01 17 3 CA-A01 CA-D07 D7
6
XIO-A02 16 4 CA-A02 CA-CE1n CE1 3F09-4 B9
7
XIO-A03 15 5 CA-A03 CA-A10 A10
8 3F10-1 C9
XIO-A04 14 6 CA-A04 CA-OEn OE
9
XIO-A05 13 7 CA-A05 CA-A11 A11
10 3F10-2 C9
XIO-A06 12 8 CA-A06 CA-A09 A9
11
XIO-A07 11 9 CA-A07 CA-A08 A8
12 3F10-3 C9
CA-A13 A13
13
A14
10
CA-A14 14 3F10-4 C9
E CA-WEn WE|P E
15
CA-RDY RDY|BSY 3F11-1 D9
16
+3V3 +5VCA VCC1
17
VPP1 3F11-2 C9
2F04 18
RES CA-MIVAL A16
19 3F11-3 D9
7F03 CA-MICLK A15
100n 20
20
74LVC245A CA-A12 A12
21 3F11-4 D9
1 CA-A07 A7
3EN1 22
CA-A06 A6
3EN2 23 3F12 C9
19 CA-ADDENn CA-A05 A5
G3 24
CA-A04 A4 7F00 A5
25
XIO-A08 18 2 CA-A08 CA-A03 A3
1 26
CA-A02 A2 7F01 B5
2 27
XIO-A09 17 3 CA-A09 CA-A01 A1
28
F XIO-A10 16 4 CA-A10 CA-A00 A0 F 7F02 D5
29
XIO-A11 15 5 CA-A11 CA-D00 D0
30 7F03 E5
XIO-A12 14 6 CA-A12 CA-D01 D1
31
XIO-A13 13 7 CA-A13 CA-D02 D2
32 7F04 G5
XIO-A14 12 8 CA-A14 CA-WP WP|IOIS16
33
11 9 GND2
34 7F05 I5
70 69
10
IF01 A4
10074595-050MLF
IF02 A5
+3V3 ROW_B
1P00-B IF03 A4
2F05
8-BIT DATA RES GND3
35 IF04 B9
7F04 100n CA-CD1n CD1
36
20
G 74LVC245A MDO3 D11 G
37 IF05 C4
1 CA-DATADIR MDO4 D12
3EN1 38
MDO5 D13
3EN2 39 IF06 C5
19 CA-DATAENn MDO6 D14
G3 40
MDO7 D15 IF07 C5
41
XIO-D00 18 2 CA-D00 CA-CE2n CE2
1 42
CA-VS1n VS1 IF08 D9
2 43
XIO-D01 17 3 CA-D01 CA-IORDn IORD
44
XIO-D02 16 4 CA-D02 CA-IOWRn IOWR
45
XIO-D03 15 5 CA-D03 CA-MISTRT A17
46
XIO-D04 14 6 CA-D04 CA-MDI0 A18
47 1X04
XIO-D05 13 7 CA-D05 CA-MDI1 A19 REF EMC HOLE
48
XIO-D06 12 8 CA-D06 CA-MDI2 A20
49
XIO-D07 11 9 CA-D07 CA-MDI3 A21
50
H +5VCA VCC2 H
51
VPP2
10
52
CA-MDI4 A22
53
CA-MDI5 A23
54
+3V3 CA-MDI6 A24
55
CA-MDI7 A25
2F06 56
CONTROL RES MOCLK VS2
57
7F05 CA-RST RESET
100n 58
20
74LVC245A CA-WAITn WAIT
59
1 CA-INPACKn INPACK
3EN1 60 1X01
CA-REGn REG
3EN2 61 REF EMC HOLE
19 CA-ADDENn MOVAL BVD2|SPKR
G3 62
MOSTRT BVD1|STSCHG
63
XIO-D11 18 2 CA-REGn MDO0 D8
1 64
I MDO1 D9 I
2 65
XIO-D09 17 3 CA-CE1n MDO2 D10
66
XIO-D08 16 4 CA-CE2n CA-CD2n CD2
67
XIO-OEn 15 5 CA-OEn GND4
68
XIO-WEn 14 6 CA-WEn 72 71
XIO-D14 13 7 CA-IORDn
XIO-D15 12 8 CA-IOWRn 10074595-050MLF
CA-WAITn 11 9 XIO-D10
10
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 83
Flash
Flash
B01B B01B
1 2 3 4
+3V3
A A
100n
100n
2F20
2F21
7F20
12
37
NAND04GW3B2DN6F
1
VCC
B Φ 2 B
[FLASH] 3
4G × 16 4
5
XIO-D00 3F20-1 1 8 100R 29 6
0
XIO-D01 3F20-2 2 7 100R 30 10
1
XIO-D02 3F20-3 3 6 100R 31 11
2
XIO-D03 3F20-4 4 5 100R 32 14
3
XIO-D04 3F21-1 1 8 100R 41 IO 15
4
XIO-D05 3F21-2 2 7 100R 42 20
5
XIO-D06 3F21-3 3 6 100R 43 21
6
XIO-D07 3F21-4 4 5 100R 44 22
7
NC 23
24
IF21
C NAND-CE1n 25 C
26
NAND-CLE 3F22-2 2 7 100R 16 27
CLE
NAND-ALE 3F22-3 3 6 100R 17 28
ALE
+3V3 3F23 10K 9 33
CE
XIO-OEn 3F22-1 1 8 100R 8 34
RE
XIO-WEn 3F22-4 4 5 100R 18 35
WE
NAND-WPn IF22 19 38
WP
+3V3 3F24 7 39
R
40
2K2 B
NAND-RDY1n 45
IF23 46
47
48
VSS
10K
3F19
D D
13
36
+3V3
1 2 3 4
2F20 A3 3F20-1 B1 3F20-4 C2 3F21-3 C1 3F22-2 C1 3F23 C2 IF21 C3
2F21 A3 3F20-2 B2 3F21-1 C1 3F21-4 C2 3F22-3 C2 3F24 D2 IF22 D3 2 2010-02-01
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 84
USB Hub
USB Hub
B01C B01C
1 2 3 4 5 6 7 8 9
1F24 E9
1F25 B1
1P07 B9
1P08 D9
2F25 A2
IF44 +5V
2F26 A2
+3V3 2F27 A2
2F28 A4
3F25
2F29 A4
100n
2F25
+T 0R4
FF40 2F30 A4
+5V-USB1
3F26-1
1 2F31 A5
A 100K
A 2F32 A5
IF43 3F26-2
USB-OC1n 2 7 2F33 A5
100K 2F34 B1
3F26-3 2F35 B2
3 6
1u0
1u0
3F25 A8
100n
100n
100n
100n
100n
100n
2F26
2F27
2F28
2F29
2F30
2F31
2F32
2F33
100K
3F26-4
3F26-1 A8
4 5
3F26-2 A8
100K
3F26-3 A8
1M0
+3V3 3F28 7F25 3F26-4 B8
14
34
36
23
15
5
10
29
1F25 USB2513B-AEZG
1 3 CR PLL 9F25
3F28 B2
VDD_3V3 USB-DP USB-DP2
B FILT B 3F30 C2
24M 9F26
4
2
Φ USB-DM USB-DM2 3F31-2 C2
IF33
USB HUB IF35 3F31-3 C2
3F35
10p
10p
10K
2F34
2F35
33 13 USB-OC1n SIDE USB BOTTOM
XTALIN|CLKIN OSC1 3F31-4 D2
2 USB-DP1
IF34 USBDP_DN1|PRT_DIS_P1
9F20
9F21
32 1 USB-DM1 1P07 3F32 C8
XTALOUT USBDM_DN1|PRT_DIS_M1
IF30 12 +5V-USB1 3F34-1 C8
BC_EN1|PWRTPWR1 1
RESET-USBn 26 IF36 USB-DM1 FF34
RESET 2 3F34-2 C8
17 USB-OC2n USB-DP1 FF35
OSC2 3
11 4 USB-DP2 3F34-3 D8
TEST USBDP_DN2|PRT_DIS_P2 +5V 4
3 USB-DM2 5 6 3F34-4 D8
3F31-2 IF42 USBDM_DN2|PRT_DIS_M2
2 7 28 16
SUSP_IND|LOCAL_PWR|NON_REM0BC_EN2|PWRTPWR2 3F35 B1
10K IF37 292303-4
USB-DP IF31 31 19 USB-OC3n 3F36 D6
C IF32 DP OSC3 C
USB-DM 30 USBUP 7 USB-DP3 7F25 B2
DM USBDP_DN3|PRT_DIS_P3
+3V3 27 6 USB-DM3
3F32
37
38
39
40
41
+3V3 USB-OC3n
3F34-4
10K 4 5 FF34 C7
D 100K SIDE USB TOP D FF35 C7
1P08 FF36 D7
+5V-USB2 1 FF37 D7
USB-DM2 FF36
2 FF38 E9
USB-DP2 FF37
3 FF39 E8
4 IF45
FF32 5 6 FF40 A8
IF30 C2
292303-4
IF31 C1
IF32 C1
IF33 B2
1F24 IF34 B2
E FF38 E
FF39 +5V 1
IF35 B5
USB-DM3 2 IF36 C5
USB-DP3 3 IF37 C5
FF30 4
FF31 IF39 D2
5
7 6 IF40 C2
502382-0570
IF41 C2
IF42 C2
IF43 A3
IF44 A3
IF45 D9
1 2 3 4 5 6 7 8 9
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 85
SD Card
SD Card
B01D B01D
1 2 3 4
A A
3F40 FF45
+3V3 +3V3-SD
+T 0R4
2F40
22u 16V
B B
+3V3
1P09-2
3F42-2 FF44
2 7 SDIO-CDn SDIO-CDn 10
D 47K 11 D
3F42-3 IF46 12
3 6 SDIO-WP SDIO-WP FF50
1939115-1
47K
1 2 3 4
1P09-1 C4 3F41-1 C1 3F42-1 C1 3F43-2 C3 3F44-3 C3 FF43 C3 FF47 C3 IF46 D1
1P09-2 D4 3F41-2 C1 3F42-2 D1 3F43-3 C3 3F45 C1 FF44 D3 FF48 C3 IF47 B1
2F40 A2 3F41-3 C1 3F42-3 D1 3F44-1 C3 FF41 C3 FF45 A2 FF49 C3 2 2010-02-01
3F40 A2 3F41-4 C1 3F43-1 C3 3F44-2 C3 FF42 C3 FF46 C4 FF50 D3 TUNER, HDMI & CI
8204 000 9081
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 86
PNX85500 Control
PNX85500 Control
B01E B01E
1 2 3 4 5 6 7 8 9
1F51 F8
1F52 D8
2F52 B1
2F53 D6
2F58 D2
A A 3F51 B1
+3V3-STANDBY +3V3-STANDBY
3F52 B3
3F53 C6
+3V3-STANDBY
+3V3 +3V3 +3V3 3F54 D7
10K
100n
3F51
RES
2F52
3F58 E1
3F59 E3
3F60 E3
RES
10K
3F66
8
10K
3F52
7F52 3F62 D5
B M25P05-AVMN6 BACKLIGHT-BOOST B
3F67
10K
RES
VCC IF50 3F63 E5
PNX-SPI-SDI IF51 2 5 PNX-SPI-SDO 7F53 RES
Q Φ D PDTA114EU +5V 3F64 F5
512K IF52
6 PNX-SPI-CLK
FLASH C 3F65 F5
IF53
1 PNX-SPI-CSBn 3F66 B7
S
RES
IF54
3 PNX-SPI-WPn BOOST-PWM IF55 3F67 B6
W
47K
3F68
7F54-1 RES 3F68 C7
7 BC847BPN(COL) 6
HOLD +3V3-STANDBY
FF29 IF61 7F54-2 RES IF56 3F69 D7
VSS SPI-PROG BC847BPN(COL)
4 2 7F52 B2
IF57
1
4
C IF62 5
C 7F53 B7
FF04
SDM 7F54-1 C7
3
7F54-2 C7
3F53 FF58 7F58 D1
9CH0
10K RES 9CH0 C7
RES
RES
FF04 C4
1K0
2F53
3F69
3F54
RES
1u0
FF29 C4
10K
+3V3 MAIN NVM FF55 E3
D DEBUG ONLY D FF56 E3
FF57 E2
IF58 1F52
2F58 RES FF61 3F62 100R FF58 C7
SCL-SSB 1 SCL
FF62 FF61 D4
100n 2
7F58 SDA-SSB 3 SDA
8
FF63 3F63 4 5 FF62 D7
100R
Φ FF63 E4
10K
3F58 (8K × 8) 7
WC FF64 F7
EEPROM 3F59 FF55
IF59 1 6 SCL-UP-MIPS FF65 F4
0 SCL
2 100R
1 ADR 3F60 FF56 FF66 F4
3 5 SDA-UP-MIPS
E 2 SDA E
100R IF50 B3
4
IF51 B1
FF57
IF52 B3
DEBUG / RS232 INTERFACE LEVEL IF53 B3
SHIFTED
IF54 C3
1F51 IF55 C6
FF65 3F64
TXD-UP 1
100R FF64 FOR IF56 C7
FF66 3F65 2 UP
RXD-UP 3 IF57 C7
RESET-STBYn 100R
F 4 DEBUG F
SPI-PROG 5 IF58 D2
7 6
USE ONLY IF59 E1
IF61 C4
IF62 C4
1 2 3 4 5 6 7 8 9
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 87
HDMI & CI
HDMI & CI
B01F B01F
1 2 3 4 5 6 7 8 9 10
IF10
IF11
A 1T01 A
TX31XX PNX-IF-P
2F71
FF71 +5V-TUN-PIN
TUNER
9F00
9F01
9F02
9F03
15 14 10n
7F75
1
15p
1p0
2F72
2F73
16 13 UPC3221GV-E1
AF72
RF_IO
B+_LNA
RF_AGC
TUN
I2C_ADR
I2C_SCL
I2C_SDA
B+_TUN
4MHZ_REF
IF_OUT1
IF_OUT2
NC
IF75 2F74 IF73 2F75 IF76 3F79-1
15p
IF74
VCC
2F65
1
2
3
4
5
6
7
8
9
10
11
12
I O1 10n 10n 220R IF16
2 5 IF77
IGND O2 2F78 IF78
22p
10p
1p0
680n
820n
5F71
2F76
2F77
5F74
2F62
2F70
AF71 TUN-IF-N 3 4
GND IF81 10n
FF74 FF76 AF70 TUN-IF-P 220R
10n AF73 3F82
330n
5F76
820R
GND1
GND2
9F04 IF-AGC
RES
RES
15p
1p0
2F80
2F82
8
5
4u7
100n
2F81
2F59
2F60
2F61
FF75
4n7
PNX-IF-N
4u7
IF82 3F77
100n
2F93
TUN-P6 FF81 PNX-IF-AGC IF12 IF13
3F80 2F63
TUN-P7 FF82 4K7 IF79 IF-
FF01 220R 10n
IF-AGC IF72
+5V-TUN-PIN
22p
680n
5F66
2F66
9F05
9F06
C 220R 10n C
47n
10n
4K7
1K0
3F71
2F85
6F72
3F72
2F92
BA591
+5V-TUN-PIN
IF86 2F90
2F84 3F76 IF87 SCL-TUNER 10n
15p 47R 5F73
3K3
TUN-P6 TUN-IF-N 3 2 3F78
470n
5F70
SDA-TUNER TUN-IF-P
15p 47R ATB2012 2F91
TUN-P7
10n RES
IF89
D SELECT-SAW
IF90
7F70
D
PDTC114EU
10n
RES
2F94
9F71
E 5F72 E
+5V-TUN +5V-TUN-PIN
30R RES
22u
2F88
1 2 3 4 5 6 7 8 9 10
1F75 B5 2F62 B10 2F70 B10 2F75 B8 2F80 B9 2F86 D1 2F93 C2 3F76 C2 3F80 C9 5F71 B9 6F72 C7 9F02 A8 9F71 E4 FF00 B2 FF76 B1 IF12 C9 IF72 C5 IF77 B6 IF82 C4 IF90 D7
1T01 A1 2F63 C9 2F71 A7 2F76 B9 2F81 B1 2F88 E5 2F94 D7 3F77 C4 3F81 C9 5F72 E4 7F70 D8 9F03 A8 AF70 B3 FF01 C4 FF81 C1 IF13 C9 IF73 B6 IF78 B8 IF86 C5
2F59 B1 2F64 C9 2F72 A9 2F77 B9 2F82 B9 2F90 C6 3F71 C7 3F78 C7 3F82 B10 5F73 C5 7F75 A6 9F04 B3 AF71 B3 FF71 A1 FF82 C2 IF14 C9 IF74 B8 IF79 C5 IF87 C2
2F60 B1 2F65 B10 2F73 A9 2F78 B6 2F84 C1 2F91 D6 3F72 C7 3F79-1 B8 5F66 C10 5F74 B10 9F00 A6 9F05 C4 AF72 B9 FF74 B1 IF10 A5 IF15 C9 IF75 B6 IF80 B8 IF88 D2
2F61 B1 2F66 C10 2F74 B6 2F79 B8 2F85 C4 2F92 C7 3F75 D2 3F79-4 B8 5F70 D6 5F76 B10 9F01 A6 9F06 C4 AF73 B9 FF75 B2 IF11 A5 IF16 B10 IF76 B8 IF81 B6 IF89 D5
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 88
Toshiba Supply
Toshiba Supply
B01G B01G
2FA2 C1
1 2 3 2FA3 C2
2FA4 C3
5FA3 B2
5FA4 B3
7FA3 B2
FFA2 C2
FFAF B2
A A
+3V3 +1V2-BRA-DR1
+1V2-BRA-VDDC
B B
7FA3
30R
30R
5FA3
5FA4
LD1117DT12
FFAF
3 2
IN OUT
COM
10u
100n
100n
2FA2
2FA3
2FA4
1
FFA2
C C
D D
2 2010-02-01
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 89
HDMI
HDMI
B01H B01H
1 2 3 4
A A
1 2 3 4
1P05 B1 3FBF-1 C4 3FBF-2 C4 FFB1 C2 FFB2 C2 FFB3 C2 FFB4 C2 FFB5 C1 FFB6 C2 2 2010-02-01
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 90
VGA
VGA
B01I B01I
1 2 3 4 5 6 7 8 9
1E05 B2
1FC1 B4
1FC2 B4
1FC3 C4
A A 1FC4 C4
1FC5 D4
FFC1 3FC5
R-VGA 1FC6 F4
18R
2FC1 B4
12V
100p
2FC1
1FC1
2FC2 B4
CDS4C12GTA
2FC3 C4
RES 6FC1
FFC2 3FC6
2FC4 C4
G-VGA
B 18R B 2FC5 D4
2FC6 E4
12V
100p
2FC2
1FC2
2FC7 E4
RES 6FC2
CDS4C12GTA
1E05
1
2FC8 F4
2 3FC7 3FC1 D3
3 B-VGA
4 FFC3 18R 3FC2 E3
5
6 3FC3 C6
12V
100p
2FC3
1FC3
VGA 7
8
CDS4C12GTA
CONNECTOR 3FC4 D6
RES 6FC3
C 9 FFC4 C
10 3FC5 A6
11 FFC5
9FC5 H-SYNC-VGA
12 3FC6 B6
13
14 3FC7 C6
15
47p
12V
4K7
16
2FC4
1FC4
3FC3
17
6FC1 B5
RES 6FC4
FFC6
1216-00D-15S-1EF
6FC2 B5
CDS4C12GTA
FFC7 6FC3 C5
9FC6 V-SYNC-VGA
6FC4 C5
D D 6FC5 D5
47p
12V
4K7
2FC5
1FC5
3FC4
RES 6FC5
6FC6 E5
CDS4C12GTA
9FC1 VGA-SDA-EDID-HDMI 6FC7 E5
RES
3FC1 FFC8
9FC2 VGA-SDA-EDID 6FC8 F5
10K RES
9FC1 D6
47p
12V
6FC6
2FC6
9FC2 E6
CDS4C12GTA
9FC3 E6
9FC3 VGA-SCL-EDID-HDMI
E RES E 9FC4 E6
3FC2 FFC9
9FC4 VGA-SCL-EDID
10K RES
9FC5 C6
9FC6 D6
47p
12V
2FC7
6FC7
FFC1 A4
CDS4C12GTA
FFC2 B4
+5V-VGA
FFC3 C4
FFC4 C3
FFC5 C4
47p
12V
F F
2FC8
1FC6
6FC8
CDS4C12GTA
FFC6 D2
FFC7 D4
FFC8 D4
FFC9 E4
1 2 3 4 5 6 7 8 9
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 91
1K0
3FD3 B3
3FD1
1K0
100n
2FD1
9FD1
9FD2
3FD4 B2
3FD2 RES
3FD6 C4
8
RES 7FD1
LM75BDP 3FD7 C4
6FD1
LTST-C190KGKT
3FDG-1 D4
+VS
3 7 IFD1
B OS A0 B
3FD3 IFD2 3FDG-2 D4
SDA-SSB 1 6 IFD3
SDA A1
3FD4 100R IFD4 6FD1 B3
SCL-SSB 2 5 IFD5
SCL A2
100R 6FD2 D4
GND
6FD3 D5
1K0
1K0
9FD5
4
3FD6 RES
3FD7 RES
7FD1 B3
9FD1 A4
9FD2 A4
C C 9FD5 C5
FFDA D5
1329 FFDB D5
1 FFDC D6
2
3 IFD1 B4
5 4
502382-0370 IFD2 B3
IFD3 B4
D D IFD4 B3
FFDA 1328
AMP1 2
AMP2 3
IFD5 B4
1
8
7
FFDB
FFDC
MSJ-035-29D PPO (PHT)
1n0
1n0
1K0
1K0
12V
12V
3FDG-1 3FDG-2
1FD2
6FD2
1FD3
6FD3
2FDC
2FDD
1
2
CDS4C12GTA
CDS4C12GTA
E E
1 2 3 4 5 6 7 8 9
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 92
Tuner Brazil
Tuner Brazil
B01K B01K
1 2 3 4 5 6 7 8 9 10 11 12 13
1FE0 C2
2FE0 A3
2FE3 A6
2FE4 A6
2FE5 A6
2FE6 B3
2FE8 C3
2FF0 A6
A A 2FF1 A7
5FE0 IF63 IF64 2FF2 B6
+2V5-BRA +1V2-BRA-VDDC 2FF3 B6
30R
2FF4 B6
2FF5 B6
1u0
1u0
100n
100n
100n
100n
2FF0
2FF1
2FE0
2FE3
2FE4
2FE5
2FF6 B7
2FF7 C6
AGND
2FF8 C6
+3V3-BRA-FLT
5FE3 IF65 IF66 5FE4
+3V3-BRA-FLT
+3V3-BRA 2FF9 C7
30R 30R 2FG0 C6
B B 2FG1 C7
1u0
1u0
100n
100n
100n
100n
2FF2
2FF3
2FF4
2FF5
2FF6
2FE6
2FG2 D1
2FG3 D2
AGND 2FG4 D3
5FE5 IF67 IF68
+1V2-BRA-DR1 2FG6 D3
30R 5FE7 IF48 2FG7 E3
+3V3 +3V3-BRA
30R
2FG8 E3
1u0
1u0
100n
100n
2FF7
2FF8
2FF9
2FE8
2FG9 E3
2FH2 D11
C IF69 5FE8 C 2FH3 D12
+2V5-BRA 2FH4 D12
30R 7FE3
1FE0 LD3985M25 2FH5 D6
1 3 5FE9 FF03
1u0
2FH6 E3
100n
1 5
2FG0
2FG1
25M4 +5V IN OUT +2V5-BRA
30R
2FH7 E3
4 2 3 4
INH BP 2FH8 F7
18p
18p
2FG2
2FG3
COM 3FE5 E7
7FE0 3FE6 F3
32
22
20
16
36
56
63
13
35
49
64
34
43
TC90517FG
2
3FE7 F3
2FH2
2FH3
2FH4
PLLVDD
X 1n5
DR2VDD
3FE9 F3
DR1VDD 48
D 18 58 3FG6-4 4 5 33R D
AD_AVDD
AD_DVDD
O PBVAL TS-FE-VALID
DFE6 3FG2-1 F6
3 53 4 9F27-4 5 TS-DVBS-VALID
0 RERR 3FG2-2 F7
2 XSEL
1 DFE7
54 3FG4-1 F7
RLOCK
IF+ 2FG4 10n IF17 30
P DFE8 3FG4-2 F6
IF- 2FG6 10n IF18 29 ADI_AI 55 2 9F27-2 7 TS-DVBS-SOP
N RSEORF
3FG6-2 E7
2FG7 100n 28 59 3FG6-3 3 6 33R TS-FE-SOP
2FG8 100n BFE2 27
P
ADQ_AI
SBYTE 3FG6-3 E7
N DFE9
52 9F28 TS-DVBS-CLOCK 5FG0
3FG6-4 D7
AGND BFE3 SLOCK
2FG9 100n 24 3FG7 E7
P
2FH6 100n 25 AD_VREF 61 3FG7 33R TS-FE-CLOCK
N SRCK 30R 5FE0 A3
E AGND E
2FH7 100n 26 60 3FG6-2 2 7 33R TS-FE-DATA 5FG2 5FE3 B3
AD_VREF SRDT
DFF1 5FE4 B7
39 38 1 9F27-1 8 TS-DVBS-DATA
AGND DTCLK STSFLG1 30R
IF27 3FE5 IF28 AGND 5FE5 B3
40 9 IF-AGC
+3V3-BRA-FLT DTMB AGCCNTI 5FE7 C11
18K
8 10 5FE8 C7
S_INFO AGCCNTR
10n
2FH8
DFF2 5FE9 C11
3FE6 10K 1 51
0 STSFLG0 5FG0 E11
41 TSMD
1
42 5FG2 E11
SYRSTN
3FE7 10K IF29 7
AGCI 3FG2-1 7FE0 D4
6 RESET-SYSTEMn
0 3FG2-2
11 SLADRS 5 10K 7FE3 C11
F CKI 1 F
10K
3FE8 100R IF49 45 12 3FG4-2 9F27-1 E8
SCL-SSB SCL SCL
SDA-SSB 3FE9 100R 46 TN 14 4K7 3FG4-1 9F27-2 D8
SDA SDA +3V3-BRA-FLT
4K7
VSS 9F27-4 D8
AD_AVSS
AD_DVSS
PLLVSS
4
9F28 E8
23
31
17
15
33
37
44
47
50
57
62
BFE2 E4
BFE3 E4
DFE6 D6
AGND AGND DFE7 D6
DFE8 D6
G G DFE9 E6
DFF1 E6
DFF2 F6
FF03 C12
IF17 D4
IF18 D4
IF27 E7
IF28 E7
IF29 F4
IF48 C12
H H IF49 F4
IF63 A4
IF64 A5
IF65 B4
IF66 B5
IF67 B4
IF68 B5
IF69 C6
1 2 3 4 5 6 7 8 9 10 11 12 13
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 93
Common Interface
B01A B01A
1 2 3 4 5 6 7 8 9 10 11
1P00-A D10
1P00-B G10
+3V3 2F00 A6
3F06
3F01 CA-RST 100K
2F00 2F01 A2
+5V +5VCA TRANSPORT STREAM FROM CAM RES
7F00 CA-CD1n 4 3F07-4 5
+T 0R4 100n 2F02 B6
20
74LVC245A 10K
1 CA-CD2n 2 3F07-2 7
3EN1 2F03 D6
2F01
3EN2 10K
22u 16V
3F07-3
19 CA-DATAENn 3 6
G3 +3V3 2F04 E6
RES
A IF01 10K A
3F02 3F07-1
CA-MOCLK 2 18 MOCLK CA-DATADIR 1 8 2F05 G6
1
100R IF02 2 10K
3F03-1
CA-MOVAL 1 8 3 17 MOVAL 2F06 H6
CA-MOSTRT 3F03-2 2 7 100R 4 16 MOSTRT CA-ADDENn 1 3F08-1 8
100R IF03 5 15 10K 3F01 A2
6 14 MOCLK 2 3F08-2 7
7 13 10K 3F02 A4
8 12 MOVAL 3 3F08-3 6
9 11 10K 3F03-1 A4
MOSTRT 4 3F08-4 5
10K 3F03-2 A4
10
MDO0 1 3F09-1 8 3F04-1 C4
B +3V3 10K B
MDO1 2 3F09-2 7
3F04-2 C4
2F02
RES 10K
7F01 MDO2 3 3F09-3 6
3F04-3 C4
100n
20
74LVC245A 10K 3F04-4 C4
1 4 3F09-4 5 IF04
3EN1 MDO3
3EN2 10K 3F05-1 C4
19
G3 3F10-1
IF05 MDO4 1 8 3F05-2 C4
CA-MDO0 3F04-1 1 8 100R 2 18 MDO0 10K
1 3F10-2
IF06 MDO5 2 7 3F05-3 C4
2
CA-MDO1 3F04-2 2 7 100R 3 17 MDO1 10K
CA-MDO2 3F04-3 3 6 100R 4 16 MDO2 MDO6 3 3F10-3 6 3F05-4 C4
CA-MDO3 3F04-4 4 5 100R 5 15 MDO3 10K
C CA-MDO4 3F05-1 1 8 100R 6 14 MDO4 MDO7 4 3F10-4 5 C 3F06 A9
CA-MDO5 3F05-2 2 7 100R 7 13 MDO5 10K
CA-MDO6 3F05-3 3 6 100R 8 12 MDO6
3F07-1 A9
CA-MDO7 3F05-4 4 5 100R 9 11 MDO7
3F12 3F07-2 A9
IF07 CA-RDY +3V3
10K
10
CA-WAITn 2 3F11-2 7
3F07-3 A9
10K 3F07-4 A9
+3V3 3 3F11-3 6 IF08
CA-INPACKn +5VCA
2F03 10K 3F08-1 A9
15-BIT ADDRESS RES CA-WP 4 3F11-4 5
7F02 100n 10K 3F08-2 A9
20
74LVC245A CA-VS1n 8 3F11-1 1 +3V3 ROW_A
1 10K 1P00-A 3F08-3 B9
3EN1
D GND1 D
3EN2 1 3F08-4 B9
19 CA-ADDENn CA-D03 D3
G3 2
CA-D04 D4
3 3F09-1 B9
XIO-A00 18 2 CA-A00 CA-D05 D5
1 4
CA-D06 D6
2 5 3F09-2 B9
XIO-A01 17 3 CA-A01 CA-D07 D7
6
XIO-A02 16 4 CA-A02 CA-CE1n CE1
7 3F09-3 B9
XIO-A03 15 5 CA-A03 CA-A10 A10
8
XIO-A04 14 6 CA-A04 CA-OEn OE
9 3F09-4 B9
XIO-A05 13 7 CA-A05 CA-A11 A11
10
XIO-A06 12 8 CA-A06 CA-A09 A9 3F10-1 C9
11
XIO-A07 11 9 CA-A07 CA-A08 A8
12
CA-A13 A13 3F10-2 C9
13
A14
10
CA-A14 14
E CA-WEn WE|P E 3F10-3 C9
15
CA-RDY RDY|BSY
16
+3V3 +5VCA VCC1 3F10-4 C9
17
VPP1
2F04 18 3F11-1 D9
RES CA-MIVAL A16
19
7F03 CA-MICLK A15
100n 20
20
74LVC245A CA-A12 A12 3F11-2 C9
21
1 CA-A07 A7
3EN1 22 3F11-3 D9
CA-A06 A6
3EN2 23
19 CA-ADDENn CA-A05 A5
G3 24 3F11-4 D9
CA-A04 A4
25
XIO-A08 18 2 CA-A08 CA-A03 A3 3F12 C9
1 26
CA-A02 A2
2 27
XIO-A09 17 3 CA-A09 CA-A01 A1 7F00 A5
28
F XIO-A10 16 4 CA-A10 CA-A00 A0 F
29
XIO-A11 15 5 CA-A11 CA-D00 D0 7F01 B5
30
XIO-A12 14 6 CA-A12 CA-D01 D1
31
XIO-A13 13 7 CA-A13 CA-D02 D2 7F02 D5
32
XIO-A14 12 8 CA-A14 CA-WP WP|IOIS16
33
11 9 GND2 7F03 E5
34
70 69
7F04 G5
10
10074595-050MLF
7F05 I5
+3V3 ROW_B
1P00-B
IF01 A4
2F05
8-BIT DATA RES GND3
35 IF02 A5
7F04 100n CA-CD1n CD1
36
20
G 74LVC245A MDO3 D11 G
37 IF03 A4
1 CA-DATADIR MDO4 D12
3EN1 38
MDO5 D13 IF04 B9
3EN2 39
19 CA-DATAENn MDO6 D14
G3 40
MDO7 D15 IF05 C4
41
XIO-D00 18 2 CA-D00 CA-CE2n CE2
1 42
CA-VS1n VS1 IF06 C5
2 43
XIO-D01 17 3 CA-D01 CA-IORDn IORD
44
XIO-D02 16 4 CA-D02 CA-IOWRn IOWR IF07 C5
45
XIO-D03 15 5 CA-D03 CA-MISTRT A17
46 IF08 D9
XIO-D04 14 6 CA-D04 CA-MDI0 A18
47
XIO-D05 13 7 CA-D05 CA-MDI1 A19
48
XIO-D06 12 8 CA-D06 CA-MDI2 A20
49
XIO-D07 11 9 CA-D07 CA-MDI3 A21
50
H +5VCA VCC2 H
51
VPP2
10
52
CA-MDI4 A22
53
CA-MDI5 A23
54
+3V3 CA-MDI6 A24
55
CA-MDI7 A25
2F06 56
CONTROL RES MOCLK VS2
57
7F05 CA-RST RESET
100n 58
20
74LVC245A CA-WAITn WAIT
59
1 CA-INPACKn INPACK
3EN1 60
CA-REGn REG
3EN2 61
19 CA-ADDENn MOVAL BVD2|SPKR
G3 62 1X04 1X01
MOSTRT BVD1|STSCHG REF EMC HOLE REF EMC HOLE
63
XIO-D11 18 2 CA-REGn MDO0 D8
1 64
I MDO1 D9 I
2 65
XIO-D09 17 3 CA-CE1n MDO2 D10
66
XIO-D08 16 4 CA-CE2n CA-CD2n CD2
67
XIO-OEn 15 5 CA-OEn GND4
68
XIO-WEn 14 6 CA-WEn 72 71
XIO-D14 13 7 CA-IORDn
XIO-D15 12 8 CA-IOWRn 10074595-050MLF
CA-WAITn 11 9 XIO-D10
10
3 2010-03-12
2 2010-02-01
TUNER, HDMI & CI
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 94
Flash
Flash
B01B B01B
1 2 3 4
+3V3
A A
100n
100n
2F20
2F21
7F20
12
37
NAND04GW3B2DN6F
1
VCC
B Φ 2 B
[FLASH] 3
4G × 16 4
5
XIO-D00 3F20-1 1 8 100R 29 6
0
XIO-D01 3F20-2 2 7 100R 30 10
1
XIO-D02 3F20-3 3 6 100R 31 11
2
XIO-D03 3F20-4 4 5 100R 32 14
3
XIO-D04 3F21-1 1 8 100R 41 IO 15
4
XIO-D05 3F21-2 2 7 100R 42 20
5
XIO-D06 3F21-3 3 6 100R 43 21
6
XIO-D07 3F21-4 4 5 100R 44 22
7
NC 23
24
IF21
C NAND-CE1n 25 C
26
NAND-CLE 3F22-2 2 7 100R 16 27
CLE
NAND-ALE 3F22-3 3 6 100R 17 28
ALE
+3V3 3F23 10K 9 33
CE
XIO-OEn 3F22-1 1 8 100R 8 34
RE
XIO-WEn 3F22-4 4 5 100R 18 35
WE
NAND-WPn IF22 19 38
WP
+3V3 3F24 7 39
R
40
2K2 B
NAND-RDY1n 45
IF23 46
47
48
VSS
10K
3F19
D D
13
36
+3V3
1 2 3 4
2F20 A3 3F20-1 B1 3F20-4 C2 3F21-3 C1 3F22-2 C1 3F23 C2 IF21 C3
2F21 A3 3F20-2 B2 3F21-1 C1 3F21-4 C2 3F22-3 C2 3F24 D2 IF22 D3 3 2010-03-12
2 2010-02-01
3F19 D2 3F20-3 B 1 3F21-2 C2 3F22-1 C2 3F22-4 C2 7F20 B3 IF23 D3 TUNER, HDMI & CI
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 95
USB Hub
USB Hub
B01C B01C
1 2 3 4 5 6 7 8 9
1F24 E9
1F25 B1
1P07 B9
1P08 D9
2F25 A2
IF44 +5V 2F26 A2
+3V3 2F27 A2
2F28 A4
3F25
2F29 A4
100n
2F25
+T 0R4
FF40 2F30 A4
+5V-USB1
3F26-1
1 2F31 A5
A 100K
A 2F32 A5
IF43 3F26-2
USB-OC1n 2 7 2F33 A5
100K 2F34 B1
3F26-3 2F35 B2
3 6
1u0
1u0
3F25 A8
100n
100n
100n
100n
100n
100n
2F26
2F27
2F28
2F29
2F30
2F31
2F32
2F33
100K
3F26-1 A8
3F26-4
4 5 3F26-2 A8
100K 3F26-3 A8
1M0
+3V3 3F28 7F25 3F26-4 B8
14
34
36
23
15
5
10
29
1F25 USB2513B-AEZG 3F28 B2
1 3 CR PLL VDD_3V3 USB-DP 9F25 USB-DP2
B FILT B 3F30 C2
24M 9F26 3F31-2 C2
4
2
Φ USB-DM USB-DM2
IF33
USB HUB IF35 3F31-3 C2
3F35
10p
10p
10K
2F34
2F35
33 13 USB-OC1n SIDE USB BOTTOM
XTALIN|CLKIN OSC1 3F31-4 D2
2 USB-DP1
IF34 USBDP_DN1|PRT_DIS_P1
9F20
9F21
32 1 USB-DM1 1P07 3F32 C8
XTALOUT USBDM_DN1|PRT_DIS_M1
IF30 12 +5V-USB1 3F34-1 C8
BC_EN1|PWRTPWR1 1
RESET-USBn 26 IF36 USB-DM1 FF34
RESET 2 3F34-2 C8
17 USB-OC2n USB-DP1 FF35
OSC2 3
11 4 USB-DP2 3F34-3 D8
TEST USBDP_DN2|PRT_DIS_P2 +5V 4
3 USB-DM2 5 6 3F34-4 D8
3F31-2 IF42 USBDM_DN2|PRT_DIS_M2
2 7 28 16
SUSP_IND|LOCAL_PWR|NON_REM0BC_EN2|PWRTPWR2 3F35 B1
10K IF37 292303-4
USB-DP IF31 31 19 USB-OC3n 3F36 D6
C IF32 DP OSC3 C
USB-DM 30 USBUP 7 USB-DP3 7F25 B2
DM USBDP_DN3|PRT_DIS_P3
+3V3 27 6 USB-DM3
3F32
37
38
39
40
41
+3V3 USB-OC3n
3F34-4
10K 4 5 FF34 C7
D 100K SIDE USB TOP D FF35 C7
1P08 FF36 D7
+5V-USB2 1 FF37 D7
USB-DM2 FF36
2 FF38 E9
USB-DP2 FF37
3 FF39 E8
4 IF45
FF32 5 6 FF40 A8
292303-4
IF30 C2
IF31 C1
IF32 C1
IF33 B2
1F24 IF34 B2
E FF38 E
FF39 +5V 1 IF35 B5
USB-DM3 2 IF36 C5
USB-DP3 3 IF37 C5
FF30 4
FF31 5 IF39 D2
7 6 IF40 C2
502382-0570 IF41 C2
IF42 C2
IF43 A3
IF44 A3
IF45 D9
1 2 3 4 5 6 7 8 9
3 2010-03-12
2 2010-02-01
TUNER, HDMI & CI
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 96
SD Card
SD Card
B01D B01D
1 2 3 4
A A
3F40 FF45
+3V3 +3V3-SD
+T 0R4
2F40
22u 16V
B B
+3V3
1P09-2
3F42-2 FF44
2 7 SDIO-CDn SDIO-CDn 10
D 47K 11 D
3F42-3 IF46 12
3 6 SDIO-WP SDIO-WP FF50
1939115-1
47K
1 2 3 4
1P09-1 C4 3F41-1 C1 3F42-1 C1 3F43-2 C3 3F44-3 C3 FF43 C3 FF47 C3 IF46 D1
1P09-2 D4 3F41-2 C1 3F42-2 D1 3F43-3 C3 3F45 C1 FF44 D3 FF48 C3 IF47 B1
3 2010-03-12
2F40 A2 3F41-3 C1 3F42-3 D1 3F44-1 C3 FF41 C3 FF45 A2 FF49 C3 TUNER, HDMI & CI 2 2010-02-01
3F40 A2 3F41-4 C1 3F43-1 C3 3F44-2 C3 FF42 C3 FF46 C4 FF50 D3 8204 000 9081
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 97
PNX85500 Control
PNX85500 Control
B01E B01E
1 2 3 4 5 6 7 8 9
1F51 F8
1F52 D8
2F52 B1
2F53 D6
2F58 D2
A A 3F51 B1
+3V3-STANDBY +3V3-STANDBY
3F52 B3
3F53 C6
+3V3-STANDBY 3F54 D7
+3V3 +3V3 +3V3
10K
3F58 E1
100n
3F51
RES
2F52
3F59 E3
3F60 E3
RES
10K
3F66
8
10K
3F52
7F52 3F62 D5
B M25P05-AVMN6 BACKLIGHT-BOOST B
3F67
10K
3F63 E5
RES
VCC IF50
PNX-SPI-SDI IF51 2 5 PNX-SPI-SDO 7F53 RES
Q Φ D PDTA114EU +5V 3F64 F5
512K IF52
6 PNX-SPI-CLK 3F65 F5
FLASH C
IF53
1 PNX-SPI-CSBn 3F66 B7
S
RES
IF54
3 PNX-SPI-WPn BOOST-PWM IF55 3F67 B6
W
47K
3F68
7F54-1 RES 3F68 C7
7 BC847BPN(COL) 6
HOLD +3V3-STANDBY
FF29 IF61 7F54-2 RES IF56
3F69 D7
VSS SPI-PROG BC847BPN(COL)
4 2 7F52 B2
IF57
1
4
C IF62 5
C 7F53 B7
FF04
SDM 7F54-1 C7
3
7F54-2 C7
3F53 FF58
9CH0 7F58 D1
10K RES
9CH0 C7
RES
RES
FF04 C4
1K0
2F53
3F69
3F54
RES
1u0
FF29 C4
10K
+3V3 MAIN NVM
FF55 E3
D DEBUG ONLY D FF56 E3
1F52
FF57 E2
IF58 2F58 RES FF61 3F62 100R
SCL-SSB 1 SCL FF58 C7
FF62
100n 2
7F58 SDA-SSB 3 SDA FF61 D4
8
FF63 3F63 4 5
100R FF62 D7
Φ
FF63 E4
10K
3F58 (8K × 8) 7
WC
EEPROM 3F59 FF55 FF64 F7
IF59 1 6 SCL-UP-MIPS
0 SCL
2 100R
FF65 F4
1 ADR 3F60 FF56
3 5 SDA-UP-MIPS
E 2 SDA E FF66 F4
100R
4
IF50 B3
FF57 IF51 B1
LEVEL IF52 B3
DEBUG / RS232 INTERFACE
IF53 B3
SHIFTED IF54 C3
1F51
FF65 3F64
TXD-UP 1 IF55 C6
100R FF64 FOR
FF66 3F65 2 UP
RXD-UP 3
IF56 C7
RESET-STBYn 100R
F 4 DEBUG F IF57 C7
SPI-PROG 5
7 6 IF58 D2
USE ONLY
IF59 E1
IF61 C4
IF62 C4
1 2 3 4 5 6 7 8 9
3 2010-03-12
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 98
HDMI & CI
HDMI & CI
B01F B01F
1 2 3 4 5 6 7 8 9 10
IF10
IF11
A 1T01 A
TX31XX PNX-IF-P
2F71
FF71 +5V-TUN-PIN
TUNER
9F00
9F01
9F02
9F03
15 14 10n
7F75
1
15p
1p0
2F72
2F73
16 13 UPC3221GV-E1
AF72
RF_IO
B+_LNA
RF_AGC
TUN
I2C_ADR
I2C_SCL
I2C_SDA
B+_TUN
4MHZ_REF
IF_OUT1
IF_OUT2
NC
IF75 2F74 IF73 2F75 IF76 3F79-1
15p
IF74
VCC
2F65
1
2
3
4
5
6
7
8
9
10
11
12
I O1 10n 10n 220R IF16
2 5 IF77
IGND O2 2F78 IF78
22p
10p
1p0
680n
820n
5F71
2F76
2F77
5F74
2F62
2F70
5F76
820R
GND1
GND2
9F04 IF-AGC
RES
RES
15p
1p0
2F80
2F82
8
5
4u7
100n
2F81
2F59
2F60
2F61
FF75
4n7
PNX-IF-N
4u7
IF82 3F77
100n
2F93
TUN-P6 FF81 PNX-IF-AGC IF12 IF13
3F80 2F63
TUN-P7 FF82 4K7 IF79 IF-
FF01 220R 10n
IF-AGC IF72
+5V-TUN-PIN
22p
680n
5F66
2F66
9F05
9F06
C 220R 10n C
47n
10n
4K7
1K0
3F71
2F85
6F72
3F72
2F92
BA591
+5V-TUN-PIN
IF86 2F90
2F84 3F76 IF87 SCL-TUNER 10n
15p 47R 5F73
3K3
TUN-P6 TUN-IF-N 3 2 3F78
470n
5F70
SDA-TUNER TUN-IF-P
15p 47R ATB2012 2F91
TUN-P7
10n RES
IF89
D SELECT-SAW
IF90
7F70
D
PDTC114EU
10n
RES
2F94
9F71
E 5F72 E
+5V-TUN +5V-TUN-PIN
30R RES
22u
2F88
1 2 3 4 5 6 7 8 9 10
1F75 B5 2F62 B10 2F70 B10 2F75 B8 2F80 B9 2F86 D1 2F93 C2 3F76 C2 3F80 C9 5F71 B9 6F72 C7 9F02 A8 9F71 E4 FF00 B2 FF76 B1 IF12 C9 IF72 C5 IF77 B6 IF82 C4 IF90 D7
1T01 A1 2F63 C9 2F71 A7 2F76 B9 2F81 B1 2F88 E5 2F94 D7 3F77 C4 3F81 C9 5F72 E4 7F70 D8 9F03 A8 AF70 B3 FF01 C4 FF81 C1 IF13 C9 IF73 B6 IF78 B8 IF86 C5
2F59 B1 2F64 C9 2F72 A9 2F77 B9 2F82 B9 2F90 C6 3F71 C7 3F78 C7 3F82 B10 5F73 C5 7F75 A6 9F04 B3 AF71 B3 FF71 A1 FF82 C2 IF14 C9 IF74 B 8 IF79 C5 IF87 C2
2F60 B1 2F65 B10 2F73 A9 2F78 B6 2F84 C1 2F91 D6 3F72 C7 3F79-1 B8 5F66 C10 5F74 B10 9F00 A6 9F05 C4 AF72 B9 FF74 B1 IF10 A5 IF15 C9 IF75 B6 IF80 B8 IF88 D2
2F61 B1 2F66 C10 2F74 B6 2F79 B8 2F85 C4 2F92 C7 3F75 D2 3F79-4 B8 5F70 D6 5F76 B10 9F01 A6 9F06 C4 AF73 B9 FF75 B2 IF11 A5 IF16 B10 IF76 B8 IF81 B6 IF89 D5
3 2010-03-12
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 99
Toshiba Supply
Toshiba Supply
B01G B01G
1 2 3
2FA2 C1
2FA3 C2
2FA4 C3
5FA3 B2
5FA4 B3
7FA3 B2
FFA2 C2
FFAF B2
A A
+3V3 +1V2-BRA-DR1
+1V2-BRA-VDDC
B B
7FA3
30R
30R
LD1117DT12
5FA3
5FA4
FFAF
3 2
IN OUT
COM
10u
100n
100n
2FA2
2FA3
2FA4
1
FFA2
C C
D D
3 2010-03-12
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 100
HDMI
HDMI
B01H B01H
1 2 3 4
A A
12 DRXC-
1 3FBF-1 8
13 PCEC-HDMI
14
FFB1 DRX-DDC-SCL DRX-DDC-SCL
15 3FBF-2
FFB2 DRX-DDC-SDA DRX-DDC-SDA 2 7 DIN-5V
16
17 47K
FFB3
18 DIN-5V
C 19 FFB4 DRX-HOTPLUG C
FFB5 21 20
23 22 FFB6
1 2 3 4 3 2010-03-12
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 101
VGA
VGA
B01I B01I
1 2 3 4 5 6 7 8 9
1E05 B2
1FC1 B4
1FC2 B4
1FC3 C4
A A 1FC4 C4
1FC5 D4
FFC1 3FC5
R-VGA 1FC6 F4
18R
2FC1 B4
12V
100p
2FC1
1FC1
2FC2 B4
CDS4C12GTA
RES 6FC1
2FC3 C4
FFC2 3FC6 2FC4 C4
G-VGA
B 18R B 2FC5 D4
2FC6 E4
12V
100p
2FC2
1FC2
2FC7 E4
RES 6FC2
CDS4C12GTA
1E05
1
2FC8 F4
2 3FC7
3 B-VGA 3FC1 D3
4 FFC3 18R
5
3FC2 E3
6
12V
100p
2FC3
1FC3
VGA 7
3FC3 C6
8
CDS4C12GTA
CONNECTOR 3FC4 D6
RES 6FC3
C 9 FFC4 C
10 3FC5 A6
11 FFC5
9FC5 H-SYNC-VGA
12 3FC6 B6
13
14 3FC7 C6
15
47p
12V
4K7
16
2FC4
1FC4
3FC3
17 6FC1 B5
RES 6FC4
FFC6
1216-00D-15S-1EF 6FC2 B5
CDS4C12GTA
FFC7 6FC3 C5
9FC6 V-SYNC-VGA
6FC4 C5
D D 6FC5 D5
47p
12V
4K7
2FC5
1FC5
3FC4
RES 6FC5
6FC6 E5
CDS4C12GTA
9FC1 VGA-SDA-EDID-HDMI
RES 6FC7 E5
3FC1 FFC8
9FC2 VGA-SDA-EDID 6FC8 F5
10K RES
9FC1 D6
47p
12V
6FC6
2FC6
9FC2 E6
CDS4C12GTA
9FC3
9FC3 E6
RES VGA-SCL-EDID-HDMI
E 3FC2 FFC9
E 9FC4 E6
9FC4 VGA-SCL-EDID
10K RES 9FC5 C6
9FC6 D6
47p
12V
2FC7
6FC7
FFC1 A4
CDS4C12GTA
FFC2 B4
+5V-VGA FFC3 C4
FFC4 C3
47p
12V
F F
2FC8
1FC6
6FC8
FFC5 C4
CDS4C12GTA
FFC6 D2
FFC7 D4
FFC8 D4
FFC9 E4
1 2 3 4 5 6 7 8 9
3 2010-03-12
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 102
1K0
3FD4 B2
3FD1
1K0
100n
2FD1
9FD1
9FD2
3FD6 C4
3FD2 RES
3FD7 C4
8
RES 7FD1 3FDG-1 D4
LM75BDP
3FDG-2 D4
6FD1
LTST-C190KGKT
+VS
3 7 IFD1
B OS A0 B 6FD1 B3
3FD3 IFD2
SDA-SSB 1 6 IFD3
SDA A1 6FD2 D4
3FD4 100R IFD4
SCL-SSB 2 5 IFD5 6FD3 D5
SCL A2
100R
GND
7FD1 B3
9FD1 A4
1K0
1K0
9FD5
4
3FD6 RES
3FD7 RES
9FD2 A4
9FD5 C5
FFDA D5
C C FFDB D5
FFDC D6
IFD1 B4
1329
1
IFD2 B3
2 IFD3 B4
3
5 4 IFD4 B3
502382-0370 IFD5 B4
D FFDA 1328
D
AMP1 2
AMP2 3
1
8
7
FFDB
FFDC
MSJ-035-29D PPO (PHT)
1n0
1n0
1K0
1K0
12V
12V
3FDG-1 3FDG-2
1FD2
6FD2
1FD3
6FD3
2FDC
2FDD
1
2
CDS4C12GTA
CDS4C12GTA
E E
1 2 3 4 5 6 7 8 9
3 2010-03-12
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 103
Tuner Brazil
Tuner Brazil
B01K B01K
1 2 3 4 5 6 7 8 9 10 11 12 13
1FE0 C2
2FE0 A3
2FE3 A6
2FE4 A6
2FE5 A6
2FE6 B3
2FE8 C3
2FF0 A6
A A 2FF1 A7
5FE0 IF63 IF64 2FF2 B6
+2V5-BRA +1V2-BRA-VDDC 2FF3 B6
30R
2FF4 B6
1u0
1u0
2FF5 B6
100n
100n
100n
100n
2FF0
2FF1
2FE0
2FE3
2FE4
2FE5
2FF6 B7
2FF7 C6
AGND
2FF8 C6
+3V3-BRA-FLT
5FE3 IF65 IF66 5FE4
+3V3-BRA-FLT
+3V3-BRA 2FF9 C7
30R 30R 2FG0 C6
B B 2FG1 C7
1u0
1u0
100n
100n
100n
100n
2FF2
2FF3
2FF4
2FF5
2FF6
2FE6
2FG2 D1
2FG3 D2
AGND 2FG4 D3
5FE5 IF67 IF68
+1V2-BRA-DR1 2FG6 D3
30R 5FE7 IF48 2FG7 E3
+3V3 +3V3-BRA
30R
2FG8 E3
1u0
1u0
100n
100n
2FF7
2FF8
2FF9
2FE8
2FG9 E3
2FH2 D11
C IF69 5FE8 C 2FH3 D12
+2V5-BRA 2FH4 D12
30R 7FE3
1FE0 LD3985M25 2FH5 D6
1 3 5FE9 FF03
1u0
2FH6 E3
100n
1 5
2FG0
2FG1
25M4 +5V IN OUT +2V5-BRA
30R
2FH7 E3
4 2 3 4
INH BP 2FH8 F7
18p
18p
2FG2
2FG3
COM 3FE5 E7
7FE0 3FE6 F3
32
22
20
16
36
56
63
13
35
49
64
34
43
TC90517FG
2
3FE7 F3
2FH2
2FH3
2FH4
PLLVDD
X 1n5
DR2VDD
3FE9 F3
DR1VDD 48
D 18 58 3FG6-4 4 5 33R D
AD_AVDD
AD_DVDD
O PBVAL TS-FE-VALID
DFE6 3FG2-1 F6
3 53 4 9F27-4 5 TS-DVBS-VALID
0 RERR 3FG2-2 F7
2 XSEL
1 DFE7
54 3FG4-1 F7
RLOCK
IF+ 2FG4 10n IF17 30
P DFE8 3FG4-2 F6
IF- 2FG6 10n IF18 29 ADI_AI 55 2 9F27-2 7 TS-DVBS-SOP
N RSEORF
3FG6-2 E7
2FG7 100n 28 59 3FG6-3 3 6 33R TS-FE-SOP
2FG8 100n BFE2 27
P
ADQ_AI
SBYTE 3FG6-3 E7
N DFE9
52 9F28 TS-DVBS-CLOCK 5FG0
3FG6-4 D7
AGND BFE3 SLOCK
2FG9 100n 24 3FG7 E7
P
2FH6 100n 25 AD_VREF 61 3FG7 33R TS-FE-CLOCK
N SRCK 30R 5FE0 A3
E AGND E
2FH7 100n 26 60 3FG6-2 2 7 33R TS-FE-DATA 5FG2 5FE3 B3
AD_VREF SRDT
DFF1 5FE4 B7
39 38 1 9F27-1 8 TS-DVBS-DATA
AGND DTCLK STSFLG1 30R
IF27 3FE5 IF28 AGND
5FE5 B3
40 9 IF-AGC
+3V3-BRA-FLT DTMB AGCCNTI 5FE7 C11
18K
8 10 5FE8 C7
S_INFO AGCCNTR
10n
2FH8
DFF2 5FE9 C11
3FE6 10K 1 51
0 STSFLG0 5FG0 E11
41 TSMD
1
42 5FG2 E11
SYRSTN
3FE7 10K IF29 7
AGCI 3FG2-1 7FE0 D4
6 RESET-SYSTEMn
0 3FG2-2
11 SLADRS 5 10K 7FE3 C11
F CKI 1 F
10K
3FE8 100R IF49 45 12 3FG4-2 9F27-1 E8
SCL-SSB SCL SCL
SDA-SSB 3FE9 100R 46 TN 14 4K7 3FG4-1 9F27-2 D8
SDA SDA +3V3-BRA-FLT
4K7
VSS 9F27-4 D8
AD_AVSS
AD_DVSS
PLLVSS
4
9F28 E8
23
31
17
15
33
37
44
47
50
57
62
BFE2 E4
BFE3 E4
DFE6 D6
AGND AGND DFE7 D6
DFE8 D6
G G DFE9 E6
DFF1 E6
DFF2 F6
FF03 C12
IF17 D4
IF18 D4
IF27 E7
IF28 E7
IF29 F4
IF48 C12
H H IF49 F4
IF63 A4
IF64 A5
IF65 B4
IF66 B5
IF67 B4
IF68 B5
IF69 C6
1 2 3 4 5 6 7 8 9 10 11 12 13
3 2010-03-12
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 104
FLASH
3S03 F3
D25 XIO-D00
00 3S04-1 F3
D26 XIO-D01
01
C24 XIO-D02
02 3S04-2 F3
D23 XIO-D03
03
NAND-ALE D22 C23 XIO-D04 3S15 B6
ALE 04
NAND-CLE C21 NAND B23 XIO-D05
CLE 05
A22 XIO-D06 3S1R F7
06
XIO-A00 J25 E22 XIO-D07
00 07 3S1S G7
XIO-A01 J26 XIO_D F24 XIO-D08
01 08
XIO-A02 H21 F25 XIO-D09 3S1T G7
02 09
XIO-A03 H22 F26 XIO-D10
03 10
B XIO-A04 H23 E23 XIO-D11 B 3S1U G7
04 11
XIO-A05 H24 E24
05 12 IS26 3S15 3S23 G7
XIO-A06 H25 E25 INPACK INPACK
06 13
XIO-A07 H26 E26 XIO-D14 10K
07 14 3S24 G7
XIO-A08 G21 XIO_A D24 XIO-D15
08 15
XIO-A09 G22 3S28 G7
09
XIO-A10 G23 B22 XIO-OEn
10 OE_
XIO-A11 G24 XIO C22 XIO-WEn 3S29 H7
11 WE_
XIO-A12 G25
12 7S00-11 E3
XIO-A13 G26 B21
13 CLK_BURST
XIO-A14 F22
IS25 14 7S00-5 A4
XIO-A15 F23 E21 NAND-CE1n
15 CE1_
D21 9S00 F5
CE2_
A20
NAND RDY2 9S08 C5
C F21 NAND-RDY1n C
RDY1
A21 9S08 NAND-WPn
WP_ IS00 C5
IS00
IS25 C3
IS26 B6
D D
7S00-11
PNX85500
1X06
EMC HOLE
H H
1 2 3 4 5 6 7 8 9 10 11 12 2 2010-02-04
PNX85500
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 105
PNX SDRAM
PNX SDRAM
B02B B02B
1 2 3 4 5 6 7 8 9 10
2S12 D4
2S17 E7
2S20 E7
2S24 E7
2S25 E7
3S06 D3
3S07 D3
A A 3S0V F8
3S20 D2
3S22 D2
3S30 C7
3S33 C8
3S6P E10
3S6Q E10
B B 7S00-8 B6
7S00-8
PNX85500 FS01 D3
DDR2-BA0 H1 MEMORY J1 DDR2-A0
0 0 FS02 D2
DDR2-BA1 H2 J3 DDR2-A1
1 BA 1
DDR2-BA2 G1 K1 DDR2-A2 IS42 E8
2 2
G4 DDR2-A3
3
DDR2-DQM0 D1 M0 L3 DDR2-A4
0 4
DDR2-DQM1 D5 G3 DDR2-A5
1 5
DDR2-DQM2 R3 DM L2 DDR2-A6
2 6
DDR2-DQM3 T5 H5 DDR2-A7
3 7
L1 DDR2-A8
A 8
DDR2-D0 F3 J5 DDR2-A9
0 9
DDR2-D1 C2 J2 DDR2-A10
1 10
C DDR2-D3 F2 M3 DDR2-A11 C
+1V8 2 11
DDR2-D2 C3 J4 DDR2-A12
3 12
DDR2-D6 B4 M2 DDR2-A13
4 13
DDR2-D5 F1 K5 DDR2-A14
5 14
DDR2-D4 C1
6
DDR2-D7 E1 N5 3S30 DDR2-CLK_N
7 N
DDR2-D8 F4 CLK N4 10R 3S33 DDR2-CLK_P
8 P
DDR2-D9 B2 10R
9
3S20
3S06
2S12
DDR2-D10 E5 E2 DDR2-DQS0_N
10 N
180R 1%
180R 1%
C5 DQS0 E3
100u 2.0V
FS02 DDR2-D11 DDR2-DQS0_P
11 P
DDR2-D12 A4
DDR2-VREF-CTRL3 FS01 12
DDR2-D13 G5 D3 DDR2-DQS1_N
DDR2-VREF-CTRL2 13 N
DDR2-D14 B3 DQS1 D4 DDR2-DQS1_P
14 P
DDR2-D15 F5
15
3S22
D DDR2-D16 U3 DQ R1 DDR2-DQS2_N D
16 N
180R 1%
DDR2-D17 P2 DQS2 R2 DDR2-DQS2_P
17 P
3S07
DDR2-D19 U2
18
180R 1%
DDR2-D18 P3 T3 DDR2-DQS3_N
19 N
DDR2-D22 N1 DQS3 T4 DDR2-DQS3_P
20 P
DDR2-D23 U1
21
DDR2-D20 P1 K3 DDR2-CAS
22 CASB 3S6Q
DDR2-D21 T1 K4 DDR2-CKE DDR2-CKE
23 CKE
DDR2-D24 V4 L5 DDR2-CS 10K
24 CSB
DDR2-D30 R5 M4 DDR2-ODT
25 ODT
DDR2-D26 U5 M1
26 PCAL 3S6P
DDR2-D25 P5 M5 DDR2-RAS DDR2-ODT
27 RASB
DDR2-D28 N3 H3 DDR2-WE 10K
28 WEB
DDR2-D31 V3
29
E DDR2-D27 R4 A2 DDR2-VREF-CTRL2
E
30 1
DDR2-D29 V5 VREF V1 DDR2-VREF-CTRL3
31 2
IS42
1%
2S20
2S17
100p
100n
100n
100p
2S24
2S25
261R
3S0V
F F
1 2 3 4 5 6 7 8 9 10
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 106
2S2E F5
3S0W E5
7S00-6 D6
A A IS01 E6
IS10 E7
B B
C C
D D
7S00-6
PNX85500
HDMIA-RX1+ U25
P
HDMIA-RX1- U26 RX1_A Y26 DDCA-SCL
N SCL
DDC_A Y25 DDCA-SDA
SDA
HDMIA-RX0+ V25 IS10
P
HDMIA-RX0- V26 RX2_A T24
N HOT_PLUG_A
E HDMIA-RXC+ W25 E
P
HDMIA-RXC- W26 RXC_A
N
+3V3 IS01
3S0W W24
RREF
12K
RES
10u
2S2E
F F
G G
H H
I I
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2 2010-02-04
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 107
PNX Audio
PNX Audio
B02D B02D
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2S2G C12 3S19 H5
2S2H D12 3S25 H9
2S2J G12 3S32 G12
2S2K F12 3S34 G11
A A 2S2L D4 3S36-1 C12
2S2R B7 3S36-2 B11
3S0Z 2S2S B9 3S36-3 D11
3S53-1 +2V5-AUDIO +24V-AUDIO-POWER
4R7 +24V-AUDIO-VDD 2S2T B8 3S36-4 D12
100R +3V3
3S53-2
2S2V B3 3S37 F11
7S08
220n
2S3J
100R LD3985M25 2S2W B3 3S38 B13
1 1 3S16-1 8
3S12-1 2S2W 3S53-3 FS08 FS03 2S2Y C3 3S39 C13
AUDIO-IN1-L 8 10K 5 1
OUT IN
22K 1u0 100R IS12 IS13 4
4 3 3S14 12 7S05-4 2S2Z B3 3S3F E4
2 BP INH ADAC(1)
RES
7 3S53-4 +2V5 3S38
3S16-2 LM324 14
+AUDIO-L 3S3G-1 C7
B 2 3S12-2 2S2V 22K B 2S30 C3
10u
7 10K COM IS02
2S2S
13
2S2R
AUDIO-IN1-R 100R 100R
10u
22K 1u0
2S31 C3 3S3G-2 D8
11
100n
2S2T
2
3S16-3 3 6
100n
2S32 D3 3S3G-3 C8
2S34
3S12-3 6 2S2Z
3 10K
AUDIO-IN2-L
2S33 C3 3S3G-4 D7
22K 1u0 10K
2 3S36-2 7 2S34 B9 3S3H D7
3S16-4 5
IS0V 4 2S2Y 10K
8 3S36-1 1
AUDIO-IN2-R 4 3S12-4 5 10K 2S36 C6 3S3U D8
2S2G
1u0
4R7
3S51
2S42
2S41
22K 1u0
100u 4V
47p
2S38 E9 3S51 C6
3S13-4 IS0R 4 3S17-4 5 7S00-2
2S31 2S39 E9 3S53-1 A6
AUDIO-IN3-L 10K PNX85500 +24V-AUDIO-VDD
4 5 2S36
C 22K 1u0 AUDIO 3S3G-1 C 2S3A E8 3S53-2 B6
3 AE10 AC7 1 8 ADAC(1)
6 L P
3S13-3 3S17-3 AF10 AIN1 ADACL AB7 IS1N 33R 3S3G-3 4 2S3B E8 3S53-3 B6
2S30 R N 1u0 IS03
AUDIO-IN3-R 3 6 10K 3 6 ADAC(2) ADAC(2) 10 7S05-3
AD10 AC6 LM324 8 3S39
22K 1u0 L P 33R -AUDIO-R 2S3C E8 3S53-4 B6
AC10 AIN2 ADACR AB6 9
3S17-1 R N 100R 3S6L F12
3S13-1
1 8
2S33
2S3D E8
AUDIO-IN4-L 10K AE9 AD7 11
L 1 3S3G-2 2S3E E3 3S6M H8
1 22K 8 AF9 AIN3 AE7 2 7 ADAC(3)
1u0 R 2
AF7
2 3 33R 2S3F E2 7S00-2 C5
3S17-2 7 AD9 ADAC AD6 4 3S3G-4 5 ADAC(4)
2S32 L 4 IS1S
AUDIO-IN4-R 2 3S13-2 10K AC9 AIN4 AE6 33R 2S3G E3 7S05-1 E12
7 R 5
22K AF6
1u0 6
AF8 2S3H E3 7S05-2 G12
L 10K
AE8 AIN5 AD4 3 3S36-3 6
D R OSCLK D 2S3J B11 7S05-3 C12
3S10 AD1 5 3S36-4 4
I2S_OUT SCK 3S3H 10K
2S2L 100R AB9 AD2 ADAC(5)
POS WS 2S2H 2S3K G6 7S05-4 B12
IS1B AB8 VR_AADC 33R
1u0 NEG
IS19 AE1 2S3L H8 7S08 B8
1 3S3U 47p
AD8 AF2 ADAC(6)
VREF_AADC 2
AE3 +24V-AUDIO-VDD 2S3M H9 7S09-1 G6
IS1A I2S_OUT_SD 3 33R
AC8 AF3
VCOM_AADC 4 2S3Q G5 7S09-2 H6
3S3F
AF5
SPDIF_OUT 2S41 C6 7S09-3 H7
56R
1n0
1n0
1n0
1n0
1n0
1n0
DBS8
2S39
2S38
AE5
2S3B
2S3A
2S3D
2S3C
SPDIF_IN1 IS07 4 2S42 C6 7S09-4 I7
ADAC(5) 3 7S05-1
10u
10u
100n
100n
2S3F
2S3E
2S3H
2S3G
LM324 1
AUDIO-OUT-L 3S0Z A11 9S06 E4
9S06
E 2 E 3S10 D4 DBS8 E4
11
3S11 F5 FS03 B12
3S12-1 B2 FS08 B7
3S12-2 B2 IS02 B11
3S37 3S6L
3S12-3 B2 IS03 C11
10K 22K
3S12-4 C2 IS06 G11
2S2K 3S13-1 C2 IS07 E11
+3V3 47p 3S13-2 D2 IS0R C2
F +3V3-ARC F 3S13-3 C2 IS0V C2
+24V-AUDIO-VDD
3S11
3S13-4 C2 IS12 B8
IS1L
1R0
3S14 B9 IS13 B9
3S16-1 B3 IS19 D3
4
ADAC(6) 5 7S05-2 3S16-2 B3 IS1A D3
100n
LM324 7
2S3Q
IS06 AUDIO-OUT-R
6 3S16-3 B3 IS1B D4
11 3S16-4 C3 IS1D G5
7S09-1
14
74LVC00APW
IS1D 3S17-1 C3 IS1E H5
SPDIF-OUT-PNX SPDIF-OUT-PNX 1 &
G 2S3K G
3 IS1G 1 3S18-1 8 SPDIF-OUT 3S17-2 D3
2
IS1G G7
100n 220R 3S34 3S32
+3V3 3S17-3 C3 IS1K H9
7
+3V3 10K 22K
220R
220R
2S2J
3S17-4 C3 IS1L F5
2 3S18-2 7
3 3S18-3 6
3S18-1 G7 IS1N C7
+3V3-ARC 47p
7S09-2 +3V3-ARC
3S18-2 G8 IS1S D7
10K
14
3S19
74LVC00APW 7S09-3 3S18-3 G8 IS44 H9
14
4 & 74LVC00APW
6 9 & IS1K IS44
IS1E 2S3L 180R 2S3M
SEL-HDMI-ARC 5 8 eHDMI+
10 3S6M
H +3V3 100n 100n H
7
7
68R
3S25
+3V3-ARC
7S09-4
14
74LVC00APW
12 &
11
13
I +3V3 I
7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 108
PNX Mips
PNX Mips
B02E B02E
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1F10 A12
2S89 D8
3S00 C5
3S21 B1
3S26 C5
3S27 C6
3S40 B1
+3V3
3S45 A1
A 7S00-3 A
PNX85500 3S4A C3
CONTROL C25 1 3S56 2 3S69 1F10 3S4B D3
IS05 SDA SDA-UP-MIPS SDA-UP-MIPS
3S45 1 C26 100R 1 2 3S57 3S6A 4K7 4K7 FS44 3S55 C3
+3V3 BOOTMODE SCL SCL-UP-MIPS SCL-UP-MIPS EJTAG-TRSTn-PNX85500 1
100R EJTAG-TMS-PNX85500 FS49
10K 2 3S56 A5
BOOTMODE Y21 B26 1 3S58 2 SDA-SET SDA-SET 3S6B 4K7 EJTAG-TDO-PNX85500 FS50
3S40 IS17 GPIO_0 SDA 3 FOR FACTORY
+3V3 3D-LR 3D-LR 9S09 IS16 Y22 2 A25 100R 1 2 3S5W SCL-SET SCL-SET 3S6C 4K7 EJTAG-TCK-PNX85500 FS51 3S57 A6
GPIO_1 SCL 4
10K RXD1-MIPS Y23 100R EJTAG-TDI-PNX85500 FS52 USE ONLY
GPIO_2 5 3S58 A5
DS52 TXD1-MIPS Y24 B25 1 3S5Y 2 SDA-SSB SDA-SSB 3S6D 2K2
3S82 RES GPIO_3 SDA 3S5Z 6
BOOST-PWM RXD2-MIPS W21 3 A24 100R 1 2 SCL-SSB SCL-SSB 3S6E 2K2 EJTAG-DETECTn FS53 3S5W B6
+3V3 GPIO_4 SCL 7
10K TXD2-MIPS W22 100R
3S80 GPIO_5 8 3S5Y B5
FS10 TXD2-MIPS GPIO6 W23 B24 1 3S60 2 SDA-TUNER SDA-TUNER 3S6F 4K7 10 9
+3V3 GPIO_6 SDA
3S81 10K FS11 RXD2-MIPS PNX-SPI-CS-BLn V22 4 A23 100R 1 2 3S61 SCL-TUNER SCL-TUNER 3S6G 4K7
+3V3
10K V23
GPIO_7 SCL 100R
3S5Z B6
B BOOST-PWM GPIO_10 B
RES 3S21 U23 AA25 3S6K 3S60 B5
+3V3 GPIO6 SELECT-SAW GPIO_11 TRSTN EJTAG-TRSTn-PNX85500 EJTAG-TRSTn-PNX85500
IS04 AA24 EJTAG-TMS-PNX85500 EJTAG-TMS-PNX85500 1 8 3S6H-1 10K +3V3
10K TMS +3V3-STANDBY FS57 BM08B-SRSS-TBT 3S61 B6
USB-DM R26 AA23 EJTAG-TCK-PNX85500 EJTAG-TCK-PNX85500 10K 3 6 3S6H-3
3S62 PNX-SPI-CS-BLn DN TCK
+3V3 USB-DP R25 AB26 EJTAG-TDO-PNX85500 EJTAG-TDO-PNX85500 10K 2 7 3S6H-2 3S62 B1
IS4Z R24 DP USB TDO
10K AB25 EJTAG-TDI-PNX85500 EJTAG-TDI-PNX85500 10K 4 5 3S6H-4
RREF TDI 3S64 C1
10K
AE4 3S00
RESET_SYS RESET-SYSTEMn 3S65 E11
3S64 FS64 33R
5K6
3S66 E11
3S55
SELECT-SAW AD5 BACKLIGHT-PWM
+3V3 BL_PWM
10K 3S67 E11
AC5
CLK_54_OUT
3S68 E11
10K
10K
10K
3S6J
3S26
3S27
3S69 A9
C 3S83
RXD1-MIPS
C 3S6A A8
+3V3 IS14
10K 3D-VS
+3V3 +3V3
3S6B A9
3S84
+3V3 TXD1-MIPS IS40 3S6C B8
3S72
10K PXCLK54
3S4A 3S6D B9
BACKLIGHT-PWM 47R
100R 3S6E B8
IS15 3S4B
3S6F B9
3D-VS-DISP 3S6G B8
100R RES 3S6H-1 B8
D D 3S6H-2 B9
+3V3
3S6H-3 B9
3S6H-4 B9
2S89 3S6J C5
100n
3S6K B9
+3V3
3
3S72 C6
7S01
PCA9540B 3S65 3S80 B1
VDD SC0 5 SCL-DISP SCL-DISP 2 1
3S81 B1
3S66 4K7
SC1 8 SCL-BL SCL-BL 2 1 3S82 B1
3S67 4K7
E SCL-SET 1 SCL SD0 4 SDA-DISP SDA-DISP 2 1 E 3S83 C1
I 2 C 4K7
INP 3S68
-BUS 3S84 C1
SDA-SET 2 SDA FIL SD1 7 SDA-BL SDA-BL 2 1
CTRL
4K7 7S00-3 A4
VSS
7S00-4 G12
6
7S01 E8
FS31
9S09 B3
9S10 F8
9S11 F8
9S10 SCL-BL 9S12 F8
IS08
F SCL-SET 9S11 FS2W SCL-DISP F 9S13 F8
9S12 FS2Y SDA-DISP
DS52 B2
IS09
FS10 B2
SDA-SET 9S13 SDA-BL
FS11 B2
FS2W F9
FS2Y F9
7S00-4 FS31 F8
PNX85500
FS44 A12
ETH-RXCLK AA3 ETHERNET
RXCLK FS49 A12
ETH-RXD(0) Y5 FS50 A12
G 0 G
ETH-RXD(1) Y6 AA2 ETH-TXCLK
IS50 1 TXCLK FS51 B12
ETH-RXD(2) AB4 RXD ETH
2
ETH-RXD(3) AC1 AA1 ETH-TXD(0) FS52 B12
3 0
AA4 ETH-TXD(1)
1 FS53 B12
ETH-RXDV AC2 TXD AB1 ETH-TXD(2)
RXDV 2
ETH-RXER Y4 AB2 ETH-TXD(3) FS57 B12
RXER 3
ETH AA5 ETH-TXEN
TXEN
SDIO-DAT3 W2 AB3 ETH-TXER FS64 C2
CC_DAT3 TXER
SDIO-CLK W1 AC3 ETH-COL
CLK COL IS04 B2
SDIO-CMD W6 Y2 ETH-CRS
CMD CRS
SDIO-DAT0 W5 Y3 ETH-MDC IS05 A2
0 MDC
SDIO-DAT1 W4 SDIO Y1 ETH-MDIO
1 DAT MDIO IS08 F8
SDIO-DAT2 W3
2
SDIO-CDn U6 IS09 F8
H SDCD H
SDIO-WP V6
SDWP IS14 C3
IS15 D3
IS16 B4
IS17 B3
IS40 C6
IS4Z B4
IS50 G12
1 2 3 4 5 6 7 8 9 10 11 12 13 14
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 109
A A
B B
7S00-7
C PNX85500 C
PX1A- A7 LVDS D7 PX3A-
N N
PX1A+ B7 A A E7 PX3A+
P P
PX1B- C8 E8 PX3B-
N N
PX1B+ B8 B B D8 PX3B+
P P
F F
G G
1 2 3 4 5 6 7 8 9 10 11 12 13 14
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 110
POL
+1V1
2S4F B9
IS3B
2S4G B9
2S4K G10
30R
RES
5S04
1u0
2S13
100n
2S10
3S1B C2
2S37 3S1C C1
1u0 3S1D C2
RES
9S24
B 2S11 B 3S1E C1
100n IS20
3S1F C2
DS50 2S4G
3
3S1G D2
1 10p
7S00-9
3S1H D1
54M
AA17
AF26
AC17
1S02
PNX85500 2S4F 3S1J D2
1
+3V3-STANDBY 2S4D AE17 +3V3-STANDBY 3S1K D1
3S1B XTAL_IN 10p
1n0 RC RC AD19
3S1C 0
RES 10K TACHO TACHO AE19 AF17 3S1L E2
VDD_XTAL
3S1D 1 XTAL_OUT
10K CEC-HDMI CEC-HDMI AF19
2 P1 3S1P D11
3S1E RES 27K AA20 AA26
VDDA_ADC2V5
BACKLIGHT-PWM-ANA-DISP BACKLIGHT-PWM-ANA-DISP RESET-STBYn
VDDA_1V1_DCS
3 RESET_IN
10K 3S1F SDM SDM AB20 IS3F
C 7 3S44 C 3S2A D2
+3V3-STANDBY 10K STANDBY AB24 EA EA
3S3L RES EA
LCD-PWR-ONn LCD-PWR-ONn AC20 IS3E
0 ALE 10K 3S43 3S2F D7
3S3M 10K EJTAG-DETECTn EJTAG-DETECTn AD20 AB23 ALE
3S3N RES 1 ALE
10K LAMP-ON LAMP-ON AE20 IS3D 10K 3S2G D7
2 10K 3S42
3S3P 10K STANDBY STANDBY AF20 AC26 PSEN PSEN
3 PSEN
10K 3S3Q RES FAN-CTRL1 FAN-CTRL1 AA21 P2 3S2H D7
RES 3S3S 4 3S2F 100R RES 3S6V
10K FAN-CTRL2 FAN-CTRL2 AB21 AC23 SDA-UP-MIPS SDA-UP-MIPS
5 SDA 3S2K D7
10K 3S3R POWER-OK POWER-OK AC21 MC AC24 3S2G 100R SCL-UP-MIPS SCL-UP-MIPS 4K7 3S6W
6 SCL
3S3T 10K RES ENABLE-3V3n ENABLE-3V3n AD21 4K7 RES
7 LED1 RES 3S1P 3S2L D10
+3V3-STANDBY 10K AD26 3S2H 100R LED1
3S1G 0 3S2K 100R
RXD-UP RXD-UP AE21 PWM AC25 LED2 LED2 10K 3S41 3S2M E10
0 1
3S1H 10K TXD-UP TXD-UP AF21
1 10K
10K DETECT2 AA22 AE23 PNX-SPI-SDO 3S2S E10
3S2A RES 2 SDO
DETECT2 AB22 P3 AF25 PNX-SPI-SDI
D 3 SDI D 3S2V F11
10K AC22 SPI AF24 PNX-SPI-CLK
4 CLK
AD22 AF23 PNX-SPI-CSBn
5 CSB 3S3L C2
3S1K RES RES 3S2L
RESET-SYSTEMn RESET-SYSTEMn AD23 AB17 IS2V CTRL-DISP CTRL-DISP 3S3M C1
0 0 RES 3S46
AV2-BLK AE26 AA18 IS2Z RESET-DVBS RESET-DVBS 10K
10K 1 1
AV1-BLK AE25 P5 AD18 RESET-USBn RESET-USBn RES 3S3Y 10K 3S3N C2
3S1J KEYBOARD 2 2 +3V3-STANDBY
KEYBOARD AE24 AE18 RESET-ETHERNETn RESET-ETHERNETn 10K RES 3S47
3 3 3S2S
100K LIGHT-SENSOR P0 AF18 SEL-HDMI-ARC SEL-HDMI-ARC 10K 3S3P C1
2S4E 4 3S2M
AV1-STATUS AF22 AA19 RESET-AVPIP RESET-AVPIP 10K RES
4 5 3S3W 3S3Q C2
AV2-STATUS AE22 P6 AB19 RESET-AUDIO RESET-AUDIO 10K RES
100n 5 6
AC19 AUDIO-MUTE-UP AUDIO-MUTE-UP 4K7 3S49
3S1L 7 3S3R D2
SPI-PROG SPI-PROG 4K7
VSS_XTAL
AD17
10K PNX-SPI-WPn 3S3S D1
E E 3S3T D1
3S3W E9
3S3Y D9
3S41 D12
3S42 C11
3S43 C11
3S44 C11
3S46 D10
F F 3S47 E10
+3V3-STANDBY +3V3-STANDBY
3S49 E10
3S6V C11
3S6W D12
10K
FS0Z
9S0E
1 3S2V 2
9S0E G9
RES
100n
2S4K
9S0D
9S24 B6
DS50 B8
FS0Z G11
FS45 G9
IS20 B6
IS2U G10
IS2V D7
H H
IS2Z D7
IS3B A6
IS3D C10
IS3E C10
IS3F C10
1 2 3 4 5 6 7 8 9 10 11 12 13
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 111
PNX Power
PNX Power
B02H B02H
1 2 3 4 5 6 7 8 9 10 11 12 13 14
IS3Q 5S80 2S21 F6
+1V1 2S23 B6
2
30R
2S26 A6
2S27 B3
100n
2S6A
2S5A
RES 10u
2S28 B3
1
2S29 C6
5S81 2S43 B2
2
+2V5 2S45 F11
A 30R A
2S46 F11
2S4M B12
100n
2S6B
2S5B
RES 10u
2S4N C11
1
+1V8 2S4P C11
IS3S 5S82
2S4Q B3
47u
+3V3
100n
100n
100n
100n
100n
100n
100n
100n
100n
2S26
2S60
2S61
2S62
2S63
2S64
2S65
2S66
2S67
2S68
2S4R B4
2
30R
2S4S F5
100n
2S5C
2S5D
2S4T H11
RES 10u
2S4U D11
SENSE+1V1 c001 2S4V D11
5S93
7S00-10 2S4W D11
+2V5
L6
L7
R6
R7
U7
A5
A6
B5
B6
C6
D6
E6
F6
G6
F7
G7
PNX85500 30R
2
B B 2S4Y D11
VDD_1V8
+1V1 AF1 V20 2S4Z E11
7
100n
100n
AE2 HDMI_VDDA_1V1 V21
2S6E 2
2S6D
2S4M
8
7
6
5
8
6
5
AD3
2S50 E11
220u 6.3V
1
AC4 U20 2S51 E9
1
VDD
22u
22u
47u
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
2S43
2S28
2S27
2S23
AB5 HDMI_VDDA_2V5 U21
2S4R
2S4Q
2S5H-1
2S5H-2
2S5H-3
2S5H-4
2S52 E9
2S5G-1
2S5G-2
2S5G-3
2S5G-4
H20
1
2
3
1
3
4
F11 U22 2S53 H11
4
2
HDMI_VDDA_3V3_TERM +2V5-LVDS
G11 2S55 G11
F13 N6
G13 VDD_2V5 N7
2S56 G11
10u
100n
F15 2S57 G11
2S4P
2S4N
8
7
6
5
7
5
G15 C7 2S58 H11
F17 C9
2S59 I11
100n
100n
100n
100n
100n
100n
100n
100n
C G17 C11 C
2S5J-3 6
2S5J-1 8
2S5J-2
2S5J-4
2S5K-1
2S5K-2
2S5K-3
2S5K-4
2S29 5S85
F19 VDD_2V5_LVDS C14
1
2
4
2
4
2S5A A11
2
2
2
G19 C16 +3V3
100u 2.0V
3
3
1
30R 2S5B A11
J9 C18
10u
100n
100n
100n
100n
2S5C B11
2S6F
J11
2S6P
2S6N
2S6C
J13 W20
1
1 2S6G 2
1
1
7S00-12 2S5D B11
Y9
AA8
Y11
Y14
AA16
Y16
PNX85500 J15 P20
J17 M20 2S5G-1 B4
VSSA
A1 M7 L9 VDD_3V3 K20 2S5G-2 B4
A10 N2 L11 V7 +3V3-STANDBY
A12 N20 L13 Y8
2S5G-3 B4
10u
100n
A15 P10 L15 2S5G-4 B5
2S4V
2S4U
VDD_1V1
A17 P12 L17 Y19 2S5H-1 B5
A19 P14 N9 VDD_3V3_SBY Y18
D A26 P16 N11 D 2S5H-2 B5
VSS IS3K 5S83
A3 P18 N13 B13 2S5H-3 B5
VDDA_1V1_LVDS_PLL +1V1
A8 P4 N15 30R
IS3L 2S5H-4 B5
B1 P6 N17 AA15
2S5J-1 C5
100n
B20 P7 R9 Y15
2S4Y
2S4W
VDDA_1V2
C20 T10 R11 AA13 2S5J-2 C5
RES 1u0
C4 T12 R13 5S95 +2V5 2S5J-3 C5
D2 VSS T14 R15 Y12
VSS VDDA_2V5 5S84
D20 T16 R17 2S5J-4 C5
30R +1V2
E13 T18 U9 AA9
VDDA_2V5_AADC 30R 2S5K-1 C4
6.3V
E20 T2 U11
10u
2S5K-2 C4
100n
100n
2S51
2S52
2S50
2S4Z
E4 T6 U13 AA7 c000 SENSE+1V2
VDDA_2V5_ADAC
10u
F10 T7 U15 2S5K-3 C4
F12 U4 U17 Y17
E VDDA_2V5_DCS E 2S5K-4 C5
F14 V10 J6
F16 V12 AA6 D13 2S5M G11
VDDA_2V5_LVDS_BG
F18 V14 Y7 2S5P F5
F20 V16 W7 T20 POL
VDDA_2V5_USB 2S60 A6
F8 V18 F9
G10 V2 G9 Y13 +2V5-AUDIO 2S61 A6
VDDA_2V5_VADC
G12 Y20
5S94 2S62 A7
J7 Y10
VSS +1V1 VDD_1V1_DDR VDDA_2V5_VDAC
100n
2S46
30R 2S63 A7
2
R21
L4
K2
K6
K7
H4
H6
H7
G2
G8
M6
VDDA_3V3_USB 2S64 A7
J20
L20
K10
K12
K14
K16
K18
G14
G16
G18
G20
M10
M12
M14
M16
M18
RES
10u
1u0
2S65 A7
VSSA_1V1_LVDS_PLL
VSSA_2V5_LVDS_BG
VSSA_USB
100n
2S21
2S4S
2S5P
1
2S66 A7
V24 HDMI_AGND
A13
U24
C13
R20
F +2V5-AUDIO F 2S67 A8
2S68 A8
100n
2S45
2S6A A11
2S6B A11
5S87 2S6C C11
+2V5 2S6D B11
30R
2S6E B11
2S6F C11
1u0
100n
2S55
2S56
2S6G C11
2S6H H11
G 5S88 G 2S6K H11
+2V5-LVDS 2S6L I11
30R
2S6M I11
10u
100n
2S57
2S5M
2S6N C11
2S6P C12
5S89 2SHW I11
2
2
100n
100n
2S6K
2S6H
2S58
5S82 A12
1
1
5S83 D12
H 5S90 H 5S84 E12
+2V5 5S85 C12
30R
5S87 F12
5S88 G12
10u
100n
2S53
2S4T
5S89 H12
5S90 H12
5S92 I12
5S93 B12
5S94 F5
100n
5S95 E10
2SHW
I I 7S00-10 B6
7S00-12 C1
IS58 5S92
IS3K D10
2
2
+3V3
30R IS3L D10
1u0
100n
100n
2S6L
2S59
IS3Q A10
2S6M
1
1
IS3S A10
IS58 I10
c000 E13
c001 B5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2 2010-02-04
PNX85500
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2010-Oct-01 back to
div. table
Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 112
47R
22n
3S59
Connectivity 2S22 A11
47R
3S5B
A A 2S40 B11
AV1-R 2S7J 2S75 F11
22n 2S22 C-SVHS 2S76 F11
56R
22n 2S77 F12
3S4J
56R
3S05
2S78 G12
2S7E G6
EU: SCART1 CVBS-MON-OUT1 2S7H B6
AV1-B 2S7K
AP: - 22n 2S7J A6
560R
3S5E
2S7K B6
56R
3S4L
B B 2S7L C6
IS4V
2S7M C6
47p
2S7N D6
2S40
3S08
560R
2S7H
AV1-G 2S7P D6
22n
IS4W 2S7Q E6
56R
3S4K
2S7R F6
8K2
3S09
2S7U F6
C 2S7M C 2S84 G6
YPBPR1-SYNCIN1
10n
2S85 H6
2S7L 2S86 H6
AV3-Y
22n 2S87 A6
56R
3S4P
2S8A A11
2S7N 2S8G E6
AV3-PR
YPBPR1 22n
3S05 A11
EU:
56R
3S08 B11
3S4R
7S00-1
D AP: YPBPR1 PNX85500 D
2S7P ANALOG_VIDEO 3S09 C11
AV3-PB
AB15 AC12
3S4G G6
22n CVBS_Y1 ATV_CVBS_Y3
AC13 AF13 IS5C
R C3 3S4J A6
22n
22n
22n
22n
22n
56R
2S19
2S18
2S16
2S15
2S14
AD13
3S4T
B AV1
AE13 AD11 3S4K C6
G CVBS_Y7
AC11
C7
AV2-CVBS 2S8G AF15 3S4L B6
SYNCIN1 BS13
AE15 AF11
22n Y_G1 CVBS1_OUT
AC15 AE11 3S4P C6
PR_R_C1 CVBS2_OUT
AD15
PB_B1
47R
3S5L
RESREF AB10 3S4R D6
AB14 AA11 IS5E 3S5S
CVBS_Y2 CURREF 3S4T D6
E AF14 10K E
2S7Q SYNCIN2
YPBPR2-SYNCIN2 AE14 AC16 IS5D
Y_G2 1 3S4U F6
AC14 AB16 IS5F
10n PR_R_C2 2
AD14 AB13 IS5G
PB_B2 3 3S4W F6
REF 4 AB12 IS5H
AF16 AA12 IS5J 3S50 G6
R 5 3S75
AD16 AA10 PNX-IF-AGC
G VGA 6
AE16 47K 3S52 H6
B
AV4-Y 2S7R AB18 AD12 BS15
HSYNC_IN IF_AGC
10n
2S75
56R
AD25 BS10
3S4U
AP: YPBPR2 SDA TUNER N AF12 IS11
3S76 3S5B A11
PNX-RF-AGC
F +CVBS 47K F 3S5E B11
AGND
10n
2S76
AV4-PR 2S7U
3S5L E6
AA14
22n
3S5S E9
2S77
56R
3S4W
PNX-IF-P 3S5T-1 I5
10n
3S5T-2 I11
2S7E
3S5T-3 I5
AV4-PB
22n 2S78
3S5T-4 I11
PNX-IF-N
3S5V-1 I5
56R
3S4G
G 10n G
3S5V-2 I12
2S84 3S5V-3 I5
R-VGA
22n 3S5V-4 I12
56R
3S50
3S75 E12
3S76 F12
2S85 7S00-1 D8
G-VGA
22n 9S14 I3
56R
3S52
H H 9S15 I3
9S17 A13
2S86
B-VGA BS10 F9
22n
BS13 E9
56R
EU: VGA
3S54
BS15 F9
AP: VGA
IS11 F13
100R
100R
100R
100R
H-SYNC-VGA 1 3S5T-1 8
4 3S5T-4 5
2 3S5T-2 7
4 3S5V-4 5
2 3S5V-2 7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2 2010-02-04
PNX85500
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2010-Oct-01 back to
div. table
Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 113
33R
100n
3S04
2S09
7S02
5
1
4
H 2 H
3
74LVC1G08GW
1X06
EMC HOLE
I I
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3 2010-03-04
2 2010-02-04
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 114
PNX SDRAM
PNX SDRAM
B02B B02B
1 2 3 4 5 6 7 8 9 10 11
2S12 D4
2S17 E7
2S20 E7
2S24 E7
2S25 E7
3S06 D3
3S07 D3
A A
3S0V F8
3S20 D2
3S22 D2
3S30 C7
3S33 C8
3S6P E10
3S6Q E10
B B 7S00-8 B6
7S00-8
PNX85500 FS01 D3
DDR2-BA0 H1 MEMORY J1 DDR2-A0
0 0 FS02 D2
DDR2-BA1 H2 J3 DDR2-A1
1 BA 1
DDR2-BA2 G1 K1 DDR2-A2
2 2 IS42 E8
G4 DDR2-A3
3
DDR2-DQM0 D1 M0 L3 DDR2-A4
0 4
DDR2-DQM1 D5 G3 DDR2-A5
1 5
DDR2-DQM2 R3 DM L2 DDR2-A6
2 6
DDR2-DQM3 T5 H5 DDR2-A7
3 7
L1 DDR2-A8
A 8
DDR2-D0 F3 J5 DDR2-A9
0 9
DDR2-D1 C2 J2 DDR2-A10
1 10
C DDR2-D3 F2 M3 DDR2-A11 C
+1V8 2 11
DDR2-D2 C3 J4 DDR2-A12
3 12
DDR2-D6 B4 M2 DDR2-A13
4 13
DDR2-D5 F1 K5 DDR2-A14
5 14
DDR2-D4 C1
6
DDR2-D7 E1 N5 3S30 DDR2-CLK_N
7 N
DDR2-D8 F4 CLK N4 10R 3S33 DDR2-CLK_P
8 P
DDR2-D9 B2 10R
9
3S20
3S06
2S12
DDR2-D10 E5 E2 DDR2-DQS0_N
10 N
180R 1%
180R 1%
C5 DQS0 E3
100u 2.0V
FS02 DDR2-D11 DDR2-DQS0_P
11 P
DDR2-D12 A4
DDR2-VREF-CTRL3 FS01 12
DDR2-D13 G5 D3 DDR2-DQS1_N
DDR2-VREF-CTRL2 13 N
DDR2-D14 B3 DQS1 D4 DDR2-DQS1_P
14 P
DDR2-D15 F5
15
3S22
D DDR2-D16 U3 DQ R1 DDR2-DQS2_N D
16 N
180R 1%
DDR2-D17 P2 DQS2 R2 DDR2-DQS2_P
17 P
3S07
DDR2-D19 U2
18
180R 1%
DDR2-D18 P3 T3 DDR2-DQS3_N
19 N
DDR2-D22 N1 DQS3 T4 DDR2-DQS3_P
20 P
DDR2-D23 U1
21
DDR2-D20 P1 K3 DDR2-CAS
22 CASB 3S6Q
DDR2-D21 T1 K4 DDR2-CKE DDR2-CKE
23 CKE
DDR2-D24 V4 L5 DDR2-CS 10K
24 CSB
DDR2-D30 R5 M4 DDR2-ODT
25 ODT
DDR2-D26 U5 M1
26 PCAL 3S6P
DDR2-D25 P5 M5 DDR2-RAS DDR2-ODT
27 RASB
DDR2-D28 N3 H3 DDR2-WE 10K
28 WEB
DDR2-D31 V3
29
E DDR2-D27 R4 A2 DDR2-VREF-CTRL2
E
30 1
DDR2-D29 V5 VREF V1 DDR2-VREF-CTRL3
31 2
IS42
1%
2S20
2S17
100p
100n
100n
100p
2S24
2S25
261R
3S0V
F F
1 2 3 4 5 6 7 8 9 10 11
3 2010-03-04
2 2010-02-04
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 115
B B
C C
D D
7S00-6
PNX85500
HDMIA-RX1+ U25
P
HDMIA-RX1- U26 RX1_A Y26 DDCA-SCL
N SCL
DDC_A Y25 DDCA-SDA
SDA
HDMIA-RX0+ V25 IS10
P
HDMIA-RX0- V26 RX2_A T24
N HOT_PLUG_A
E HDMIA-RXC+ W25 E
P
HDMIA-RXC- W26 RXC_A
N
+3V3 IS01
3S0W W24
RREF
12K
RES
10u
2S2E
F F
G G
H H
I I
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3 2010-03-04
2 2010-02-04
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 116
PNX Audio
PNX Audio
B02D B02D
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2S2G C12 3S19 H5
2S2H D12 3S25 H9
2S2J G12 3S32 G12
A A 2S2K F12 3S34 G11
2S2L D4 3S36-1 C12
3S0Z
3S53-1 +2V5-AUDIO +24V-AUDIO-POWER 2S2R B7 3S36-2 B11
4R7 +24V-AUDIO-VDD
100R +3V3 2S2S B9 3S36-3 D11
3S53-2
7S08
220n
2S3J
100R LD3985M25 2S2T B8 3S36-4 D12
1 1 3S16-1 8
3S12-1 2S2W 3S53-3 FS08 FS03
AUDIO-IN1-L 8 10K 5 1 2S2V B3 3S37 F11
OUT IN
22K 1u0 100R IS12 IS13 4
4 3 3S14 12 7S05-4
2 BP INH ADAC(1) 3S38 B13
RES
3S16-2 7 3S53-4 +2V5 LM324 14 3S38
+AUDIO-L
2S2W B3
B 2 3S12-2 2S2V 22K B
10u
7 10K COM IS02
2S2S
13
2S2R
AUDIO-IN1-R 100R 100R 3S39 C13
2S2Y C3
10u
22K 1u0 11
100n
2S2T
2
3S16-3 3 6
100n
2S34
3
3S12-3 6 2S2Z
2S2Z B3 3S3F E4
AUDIO-IN2-L 10K
22K 1u0 10K
2S30 C3 3S3G-1 C7
2 3S36-2 7
3S16-4 5
IS0V 4 2S2Y 10K
8 3S36-1 1 2S31 C3 3S3G-2 D8
AUDIO-IN2-R 4 3S12-4 5 10K
2S2G
1u0
4R7
3S51
2S42
2S41
22K 1u0 2S32 D3 3S3G-3 C8
100u 4V
47p
3S13-4 IS0R 4 3S17-4 5 7S00-2
2S31 2S33 C3 3S3G-4 D7
AUDIO-IN3-L 10K PNX85500 +24V-AUDIO-VDD
4 5 2S36
C 22K 1u0 AUDIO 3S3G-1 C
3 AE10 AC7 1 8 ADAC(1) 2S34 B9 3S3H D7
6 L P
3S13-3 3S17-3 AF10 AIN1 ADACL AB7 IS1N 33R 3S3G-3 4
2S30 R N 1u0 IS03
AUDIO-IN3-R 3 6 10K 3 6 ADAC(2) ADAC(2) 10 7S05-3 2S36 C6 3S3U D8
AD10 AC6 LM324 8 3S39
22K 1u0 L P 33R -AUDIO-R
AC10 AIN2 ADACR AB6 9
3S17-1 R N 100R 2S38 E9 3S51 C6
1 8
3S13-1 2S33 11
AUDIO-IN4-L 10K AE9 AD7
L 1 3S3G-2 2S39 E9 3S53-1 A6
1 22K 8 AF9 AIN3 AE7 2 7 ADAC(3)
1u0 R 2
AF7
2 3 33R 2S3A E8 3S53-2 B6
3S17-2 7 AD9 ADAC AD6 4 3S3G-4 5 ADAC(4)
2S32 L 4 IS1S
AUDIO-IN4-R 2 3S13-2 10K AC9 AIN4 AE6 33R
7 R 5
22K AF6 2S3B E8 3S53-3 B6
1u0 6
AF8
L 10K
AE8 AIN5 AD4 3 3S36-3 6 2S3C E8 3S53-4 B6
D R OSCLK D
3S10 AD1 5 3S36-4 4
I2S_OUT SCK 3S3H 10K
2S2L 100R AB9 AD2 ADAC(5)
POS WS 2S2H 2S3D E8 3S6L F12
IS1B AB8 VR_AADC 33R
1u0 NEG
IS19 AE1
1 3S3U 47p 2S3E E3 3S6M H8
AD8 AF2 ADAC(6)
VREF_AADC 2
AE3 +24V-AUDIO-VDD
IS1A I2S_OUT_SD 3 33R
AC8 AF3 2S3F E2 7S00-2 C5
VCOM_AADC 4
3S3F
AF5 2S3G E3 7S05-1 E12
SPDIF_OUT
56R
1n0
1n0
1n0
1n0
1n0
1n0
DBS8
2S39
2S38
AE5
2S3B
2S3A
2S3D
2S3C
SPDIF_IN1 IS07 4 2S3H E3 7S05-2 G12
ADAC(5) 3 7S05-1
10u
10u
100n
100n
2S3F
2S3E
2S3H
2S3G
LM324 1
AUDIO-OUT-L 2S3J B11 7S05-3 C12
9S06
E 2 E
11 2S3K G6 7S05-4 B12
2S3L H8 7S08 B8
2S3M H9 7S09-1 G6
3S37 3S6L 2S3Q G5 7S09-2 H6
10K 22K 2S41 C6 7S09-3 H7
2S2K
+3V3 47p
2S42 C6 7S09-4 I7
F +3V3-ARC F 3S0Z A11 9S06 E4
+24V-AUDIO-VDD
3S11 IS1L
3S10 D4 DBS8 E4
1R0 3S11 F5 FS03 B12
4 FS08 B7
ADAC(6) 5 7S05-2 3S12-1 B2
100n
LM324 7
2S3Q
IS06 AUDIO-OUT-R
6 3S12-2 B2 IS02 B11
11
7S09-1 3S12-3 B2 IS03 C11
14
74LVC00APW
IS1D
SPDIF-OUT-PNX SPDIF-OUT-PNX 1 &
G 2S3K G 3S12-4 C2 IS06 G11
3 IS1G 1 3S18-1 8 SPDIF-OUT
2 220R
100n 3S34 3S32 3S13-1 C2 IS07 E11
+3V3
7
+3V3 10K 22K IS0R C2
220R
220R
2S2J
3S13-2 D2
2 3S18-2 7
3 3S18-3 6
+3V3-ARC 47p
3S13-3 C2 IS0V C2
7S09-2 +3V3-ARC 3S13-4 C2 IS12 B8
10K
14
3S19
74LVC00APW 7S09-3
14
4 & 74LVC00APW
6 9 & IS1K IS44
3S14 B9 IS13 B9
IS1E 2S3L 180R 2S3M
SEL-HDMI-ARC 5 8 eHDMI+
H +3V3
10
100n 3S6M 100n H 3S16-1 B3 IS19 D3
7
7
3S16-2 B3 IS1A D3
68R
3S25
3S16-3 B3 IS1B D4
3S16-4 C3 IS1D G5
+3V3-ARC
3S17-1 C3 IS1E H5
7S09-4
14
74LVC00APW 3S17-2 D3 IS1G G7
12 &
11 3S17-3 C3 IS1K H9
13
I +3V3 I 3S17-4 C3 IS1L F5
7
3S18-1 G7 IS1N C7
3S18-2 G8 IS1S D7
3S18-3 G8 IS44 H9
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3 2010-03-04
2 2010-02-04
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 117
PNX Mips
PNX Mips
B02E B02E
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1F10 A12
2S89 D8
3S00 C5
3S21 B1
3S26 C5
3S27 C6
3S40 B1
+3V3
3S45 A1
A 7S00-3 A
PNX85500 3S4A C3
CONTROL C25 1 3S56 2 3S69 1F10 3S4B D3
IS05 SDA SDA-UP-MIPS SDA-UP-MIPS
3S45 1 C26 100R 1 2 3S57 3S6A 4K7 4K7 FS44
+3V3 BOOTMODE SCL SCL-UP-MIPS SCL-UP-MIPS EJTAG-TRSTn-PNX85500 1
3S55 C3
100R EJTAG-TMS-PNX85500 FS49
10K 2 3S56 A5
BOOTMODE Y21 B26 1 3S58 2 SDA-SET SDA-SET 3S6B 4K7 EJTAG-TDO-PNX85500 FS50
3S40 IS17 GPIO_0 SDA 3 FOR FACTORY
+3V3 3D-LR 3D-LR 9S09 IS16 Y22 2 A25 100R 1 2 3S5W SCL-SET SCL-SET 3S6C 4K7 EJTAG-TCK-PNX85500 FS51 3S57 A6
GPIO_1 SCL 4
10K RXD1-MIPS Y23 100R EJTAG-TDI-PNX85500 FS52 USE ONLY
GPIO_2 5 3S58 A5
DS52 TXD1-MIPS Y24 B25 1 3S5Y 2 SDA-SSB SDA-SSB 3S6D 2K2
3S82 RES GPIO_3 SDA 3S5Z 6
BOOST-PWM RXD2-MIPS W21 3 A24 100R 1 2 SCL-SSB SCL-SSB 3S6E 2K2 EJTAG-DETECTn FS53 3S5W B6
+3V3 GPIO_4 SCL 7
10K TXD2-MIPS W22 100R
3S80 GPIO_5 8
FS10 TXD2-MIPS GPIO6 W23 B24 1 3S60 2 SDA-TUNER SDA-TUNER 3S6F 4K7 10 9 3S5Y B5
+3V3 GPIO_6 SDA
3S81 10K FS11 RXD2-MIPS PNX-SPI-CS-BLn V22 4 A23 100R 1 2 3S61 SCL-TUNER SCL-TUNER 3S6G 4K7
+3V3 GPIO_7 SCL 100R
3S5Z B6
10K BOOST-PWM V23
B RES 3S21 GPIO_10 B
+3V3 GPIO6 SELECT-SAW U23 AA25 EJTAG-TRSTn-PNX85500 EJTAG-TRSTn-PNX85500 3S6K 3S60 B5
IS04 TRSTN
GPIO_11
AA24 EJTAG-TMS-PNX85500 EJTAG-TMS-PNX85500 1 8 3S6H-1 10K +3V3
10K TMS +3V3-STANDBY FS57 BM08B-SRSS-TBT 3S61 B6
USB-DM R26 AA23 EJTAG-TCK-PNX85500 EJTAG-TCK-PNX85500 10K 3 6 3S6H-3
3S62 PNX-SPI-CS-BLn DN TCK
+3V3 USB-DP R25 AB26 EJTAG-TDO-PNX85500 EJTAG-TDO-PNX85500 10K 2 7 3S6H-2 3S62 B1
IS4Z R24 DP USB TDO
10K AB25 EJTAG-TDI-PNX85500 EJTAG-TDI-PNX85500 10K 4 5 3S6H-4
RREF TDI 3S64 C1
10K
AE4 3S00
RESET_SYS RESET-SYSTEMn 3S65 E11
3S64 FS64 33R
5K6
3S55
SELECT-SAW AD5 BACKLIGHT-PWM 3S66 E11
+3V3 BL_PWM
10K 3S67 E11
AC5
CLK_54_OUT
3S68 E11
10K
10K
10K
3S6J
3S26
3S27
C C 3S69 A9
3S83
+3V3 RXD1-MIPS 3S6A A8
3D-VS IS14
10K
+3V3 +3V3 3S6B A9
3S84
+3V3 TXD1-MIPS IS40 3S6C B8
3S72
10K PXCLK54
3S4A 3S6D B9
BACKLIGHT-PWM 47R
100R 3S6E B8
IS15 3S4B
3S6F B9
3D-VS-DISP
3S6G B8
100R RES
3S6H-1 B8
D D 3S6H-2 B9
+3V3 3S6H-3 B9
3S6H-4 B9
2S89 3S6J C5
100n +3V3
3S6K B9
3
7S01
3S72 C6
PCA9540B 3S65 3S80 B1
VDD SC0 5 SCL-DISP SCL-DISP 2 1
3S66 4K7
3S81 B1
SC1 8 SCL-BL SCL-BL 2 1
3S82 B1
3S67 4K7
E SCL-SET 1 SCL SD0 4 SDA-DISP SDA-DISP 2 1 E 3S83 C1
I 2 C
INP 3S68 4K7
-BUS 3S84 C1
SDA-SET 2 SDA FIL SD1 7 SDA-BL SDA-BL 2 1
CTRL
4K7 7S00-3 A4
VSS
7S00-4 G12
6
FS31
7S01 E8
9S09 B3
9S10 F8
9S11 F8
9S10 SCL-BL
9S12 F8
IS08
F SCL-SET 9S11 FS2W SCL-DISP F 9S13 F8
9S12 FS2Y SDA-DISP DS52 B2
IS09 FS10 B2
SDA-SET 9S13 SDA-BL
FS11 B2
FS2W F9
FS2Y F9
7S00-4
PNX85500 FS31 F8
FS44 A12
ETH-RXCLK AA3 ETHERNET
RXCLK FS49 A12
ETH-RXD(0) Y5
G 0 G FS50 A12
ETH-RXD(1) Y6 AA2 ETH-TXCLK
1 TXCLK
ETH-RXD(2) IS50 AB4 RXD ETH FS51 B12
2
ETH-RXD(3) AC1 AA1 ETH-TXD(0)
3 0 FS52 B12
AA4 ETH-TXD(1)
1
ETH-RXDV AC2 TXD AB1 ETH-TXD(2) FS53 B12
RXDV 2
ETH-RXER Y4 AB2 ETH-TXD(3)
RXER 3 FS57 B12
ETH AA5 ETH-TXEN
TXEN
SDIO-DAT3 W2 AB3 ETH-TXER FS64 C2
CC_DAT3 TXER
SDIO-CLK W1 AC3 ETH-COL
CLK COL IS04 B2
SDIO-CMD W6 Y2 ETH-CRS
CMD CRS
SDIO-DAT0 W5 Y3 ETH-MDC
0 MDC IS05 A2
SDIO-DAT1 W4 SDIO Y1 ETH-MDIO
1 DAT MDIO
SDIO-DAT2 W3 IS08 F8
2
SDIO-CDn U6
H SDCD H IS09 F8
SDIO-WP V6
SDWP
IS14 C3
IS15 D3
IS16 B4
IS17 B3
IS40 C6
IS4Z B4
IS50 G12
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3 2010-03-04
2 2010-02-04
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 118
A A
B B
7S00-7
C PNX85500 C
PX1A- A7 LVDS D7 PX3A-
N N
PX1A+ B7 A A E7 PX3A+
P P
PX1B- C8 E8 PX3B-
N N
PX1B+ B8 B B D8 PX3B+
P P
F F
G G
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3 2010-03-04
2 2010-02-04
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2010-Oct-01 back to
div. table
Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 119
POL
+1V1
2S4F B9
IS3B
2S4G B9
2S4K G10
30R
RES
5S04
1u0
2S13
100n
2S10
3S1B C2
2S37
3S1C C1
1u0 3S1D C2
RES
9S24
B 2S11 B 3S1E C1
100n IS20
3S1F C2
DS50 2S4G
3
3S1G D2
1 10p
7S00-9 3S1H D1
54M
AA17
AF26
AC17
1S02
PNX85500 2S4F 3S1J D2
1
+3V3-STANDBY 2S4D AE17 +3V3-STANDBY
3S1B XTAL_IN 10p 3S1K D1
1n0 RC RC AD19
3S1C 0
RES 10K TACHO TACHO AE19 AF17
VDD_XTAL
3S1D 1 XTAL_OUT 3S1L E2
10K CEC-HDMI CEC-HDMI AF19
2 P1
3S1E RES 27K AA20 AA26
VDDA_ADC2V5
BACKLIGHT-PWM-ANA-DISP BACKLIGHT-PWM-ANA-DISP RESET-STBYn 3S1P D11
VDDA_1V1_DCS
3 RESET_IN
10K 3S1F SDM SDM AB20 IS3F
C 7 3S44 C 3S2A D2
+3V3-STANDBY 10K STANDBY AB24 EA EA
3S3L RES EA
LCD-PWR-ONn LCD-PWR-ONn AC20 IS3E
0 ALE 10K 3S43 3S2F D7
3S3M 10K EJTAG-DETECTn EJTAG-DETECTn AD20 AB23 ALE
3S3N RES 1 ALE
10K LAMP-ON LAMP-ON AE20 IS3D 10K
2 10K 3S42
3S2G D7
3S3P 10K STANDBY STANDBY AF20 AC26 PSEN PSEN
3 PSEN
10K 3S3Q RES FAN-CTRL1 FAN-CTRL1 AA21 P2 3S2H D7
RES 3S3S 4 3S2F 100R RES 3S6V
10K FAN-CTRL2 FAN-CTRL2 AB21 AC23 SDA-UP-MIPS SDA-UP-MIPS
5 SDA
10K 3S3R POWER-OK POWER-OK AC21 MC AC24 3S2G 100R SCL-UP-MIPS SCL-UP-MIPS 4K7 3S6W 3S2K D7
6 SCL
3S3T 10K RES ENABLE-3V3n ENABLE-3V3n AD21 4K7 RES
7 LED1 RES 3S1P 3S2L D10
+3V3-STANDBY 10K AD26 3S2H 100R LED1
3S1G 0 3S2K 100R
RXD-UP RXD-UP AE21 PWM AC25 LED2 LED2 10K 3S41
0 1 3S2M E10
3S1H 10K TXD-UP TXD-UP AF21
1 10K
10K DETECT2 AA22 AE23 PNX-SPI-SDO 3S2S E10
3S2A RES 2 SDO
DETECT2 AB22 P3 AF25 PNX-SPI-SDI
D 3 SDI D
10K AC22 SPI AF24 PNX-SPI-CLK 3S2V F11
4 CLK
AD22 AF23 PNX-SPI-CSBn
5 CSB 3S3L C2
3S1K RES RES 3S2L
RESET-SYSTEMn RESET-SYSTEMn AD23 AB17 IS2V CTRL-DISP CTRL-DISP
0 0 RES 3S46 3S3M C1
AV2-BLK AE26 AA18 IS2Z RESET-DVBS RESET-DVBS 10K
10K 1 1
AV1-BLK AE25 P5 AD18 RESET-USBn RESET-USBn RES 3S3Y 10K
3S1J KEYBOARD 2 2 +3V3-STANDBY 3S3N C2
KEYBOARD AE24 AE18 RESET-ETHERNETn RESET-ETHERNETn 10K RES 3S47
3 3 3S2S
100K LIGHT-SENSOR P0 AF18 SEL-HDMI-ARC SEL-HDMI-ARC 10K 3S3P C1
2S4E 4 3S2M
AV1-STATUS AF22 AA19 RESET-AVPIP RESET-AVPIP 10K RES
4 5 3S3W
AV2-STATUS AE22 P6 AB19 RESET-AUDIO RESET-AUDIO 10K RES 3S3Q C2
100n 5 6
AC19 AUDIO-MUTE-UP AUDIO-MUTE-UP 4K7 3S49
3S1L 7 3S3R D2
SPI-PROG SPI-PROG 4K7
VSS_XTAL
AD17
10K PNX-SPI-WPn 3S3S D1
E E 3S3T D1
3S3W E9
3S3Y D9
3S41 D12
3S42 C11
3S43 C11
3S44 C11
3S46 D10
F F 3S47 E10
+3V3-STANDBY +3V3-STANDBY
3S49 E10
3S6V C11
10K
FS0Z
3S6W D12
9S0E
1 3S2V 2
7S20 RESET-STBYn
NCP303LSN28 5S04 B6
FS45 2
INP 7S00-9 B6
1 IS2U 1
OUTP
5 7S20 G10
CD
NC GND
G G 9S0D G9
4
3
9S0E G9
RES
100n
2S4K
9S0D
9S24 B6
DS50 B8
FS0Z G11
FS45 G9
IS20 B6
IS2U G10
H H IS2V D7
IS2Z D7
IS3B A6
IS3D C10
IS3E C10
IS3F C10
1 2 3 4 5 6 7 8 9 10 11 12 13
3 2010-03-04
2 2010-02-04
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 120
PNX Power
PNX Power
B02H B02H
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2S21 F6
IS3Q 5S80
+1V1
2S23 B6
2
30R 2S26 A6
2S27 B3
100n
2S6A
2S5A
2S28 B3
RES 10u
1
2S29 C6
5S81 2S43 B2
2
+2V5 2S45 F11
A 30R A 2S46 F11
2S4M B12
100n
2S6B
2S5B
RES 10u
2S4N C11
1
2S4P C11
+1V8
IS3S 5S82 2S4Q B3
47u
+3V3
100n
100n
100n
100n
100n
100n
100n
100n
100n
2S26
2S60
2S61
2S62
2S63
2S64
2S65
2S66
2S67
2S68
2S4R B4
2
30R
2S4S F5
2S4T H11
100n
2S5C
2S5D
RES 10u
2S4U D11
SENSE+1V1 c001
2S4V D11
5S93
7S00-10 2S4W D11
+2V5
L6
L7
R6
R7
U7
A5
A6
B5
B6
C6
D6
E6
F6
G6
F7
G7
PNX85500 30R 2S4Y D11
2
B VDD_1V8
B
+1V1 AF1 V20 2S4Z E11
7
100n
100n
AE2 HDMI_VDDA_1V1 V21
2S6E 2
2S6D
2S4M
2S50 E11
8
7
6
5
8
6
5
AD3
220u 6.3V
1
AC4 U20
2S51 E9
1
VDD
22u
22u
47u
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
2S43
2S28
2S27
2S23
AB5 HDMI_VDDA_2V5 U21
2S4R
2S52 E9
2S4Q
2S5H-1
2S5H-2
2S5H-3
2S5H-4
2S5G-1
2S5G-2
2S5G-3
2S5G-4
H20
1
2
3
1
3
4
2S53 H11
F11 U22
4
2
HDMI_VDDA_3V3_TERM +2V5-LVDS
G11 2S55 G11
F13 N6 2S56 G11
G13 VDD_2V5 N7
2S57 G11
10u
100n
F15
2S4P
2S4N
8
7
6
5
7
5
G15 C7 2S58 H11
F17 C9 2S59 I11
100n
100n
100n
100n
100n
100n
100n
100n
C G17 C11 C
2S5J-3 6
2S5J-1 8
2S5J-2
2S5J-4
2S5K-1
2S5K-2
2S5K-3
2S5K-4
2S29 5S85 2S5A A11
F19 VDD_2V5_LVDS C14
1
2
4
2
4
2
2
2
G19 C16 +3V3
100u 2.0V
3
3
1
30R 2S5B A11
J9 C18
2S5C B11
10u
100n
100n
100n
100n
2S6F
J11
2S6P
2S6N
2S6C
J13 W20
1
1 2S6G 2
1
1
7S00-12 2S5D B11
Y9
AA8
Y11
Y14
AA16
Y16
PNX85500 J15 P20 2S5G-1 B4
VSSA J17 M20
A1 M7 L9 VDD_3V3 K20 2S5G-2 B4
A10 N2 L11 V7 +3V3-STANDBY
2S5G-3 B4
A12 N20 L13 Y8
2S5G-4 B5
10u
100n
A15 P10 L15
2S4V
2S4U
VDD_1V1
A17 P12 L17 Y19 2S5H-1 B5
A19 P14 N9 VDD_3V3_SBY Y18 2S5H-2 B5
D A26 VSS P16 N11 IS3K 5S83
D
A3 P18 N13 B13 2S5H-3 B5
VDDA_1V1_LVDS_PLL +1V1
A8 P4 N15 30R 2S5H-4 B5
IS3L
B1 P6 N17 AA15
2S5J-1 C5
100n
B20 P7 R9 Y15
2S4Y
2S4W
VDDA_1V2
C20 T10 R11 AA13 2S5J-2 C5
RES 1u0
C4 T12 R13 5S95 +2V5 2S5J-3 C5
D2 VSS T14 R15 Y12
VSS VDDA_2V5 5S84 2S5J-4 C5
D20 T16 R17
30R +1V2
E13 T18 U9 AA9 2S5K-1 C4
VDDA_2V5_AADC 30R
6.3V
E20 T2 U11
2S5K-2 C4
10u
100n
100n
2S51
2S52
2S50
2S4Z
E4 T6 U13 AA7 c000 SENSE+1V2
VDDA_2V5_ADAC
10u
F10 T7 U15 2S5K-3 C4
F12 U4 U17 Y17 2S5K-4 C5
E VDDA_2V5_DCS E
F14 V10 J6
F16 V12 AA6 D13 2S5M G11
VDDA_2V5_LVDS_BG
F18 V14 Y7 2S5P F5
F20 V16 W7 T20 POL
VDDA_2V5_USB 2S60 A6
F8 V18 F9
G10 V2 G9 Y13 +2V5-AUDIO 2S61 A6
VDDA_2V5_VADC
G12 Y20 2S62 A7
5S94
J7 Y10
VSS +1V1 VDD_1V1_DDR VDDA_2V5_VDAC 2S63 A7
100n
2S46
30R
2
R21
L4
K2
K6
K7
H4
H6
H7
2S64 A7
G2
G8
M6
VDDA_3V3_USB
J20
L20
K10
K12
K14
K16
K18
G14
G16
G18
G20
M10
M12
M14
M16
M18
RES 2S65 A7
10u
1u0
VSSA_1V1_LVDS_PLL
VSSA_2V5_LVDS_BG
VSSA_USB
100n
2S21
2S4S
2S5P
1
2S66 A7
V24 HDMI_AGND
A13
U24
C13
R20
F +2V5-AUDIO F 2S67 A8
2S68 A8
100n
2S45
2S6A A11
2S6B A11
5S87 2S6C C11
+2V5 2S6D B11
30R 2S6E B11
2S6F C11
1u0
100n
2S55
2S56
2S6G C11
2S6H H11
G 5S88 G 2S6K H11
+2V5-LVDS 2S6L I11
30R
2S6M I11
10u
100n
2S57
2S5M
2S6N C11
2S6P C12
5S89 2SHW I11
2
2
100n
100n
2S6K
2S6H
2S58
5S82 A12
1
1
5S83 D12
H 5S90 H 5S84 E12
+2V5 5S85 C12
30R
5S87 F12
10u
5S88 G12
100n
2S53
2S4T
5S89 H12
5S90 H12
5S92 I12
5S93 B12
5S94 F5
100n
5S95 E10
2SHW
I I 7S00-10 B6
5S92
7S00-12 C1
IS58
IS3K D10
2
2
+3V3
30R IS3L D10
1u0
100n
100n
2S6L
2S59
2S6M
IS3Q A10
1
1
IS3S A10
IS58 I10
c000 E13
c001 B5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3 2010-03-04
2 2010-02-04
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div. table
Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 121
47R
22n
3S59
Connectivity 2S18 D12
47R
2S19 D11
3S5B
A A
AV1-R 2S7J 2S22 A11
22n 2S22 C-SVHS
2S40 B11
2S75 F11
56R
22n
3S4J
56R
3S05
2S76 F11
2S77 F12
EU: SCART1 CVBS-MON-OUT1
2S78 G12
AV1-B 2S7K
AP: - 22n 2S7E G6
560R
3S5E
2S7H B6
56R
3S4L
B B 2S7J A6
IS4V
2S7K B6
2S7L C6
47p
2S40
3S08
560R
2S7H
AV1-G
2S7M C6
22n 2S7N D6
IS4W
56R
3S4K
2S7P D6
2S7Q E6
8K2
3S09
2S7R F6
C 2S7M C 2S7U F6
YPBPR1-SYNCIN1
10n 2S84 G6
2S7L
AV3-Y 2S85 H6
22n
2S86 H6
56R
3S4P
2S87 A6
2S7N
AV3-PR 2S8A A11
YPBPR1 22n 2S8G E6
EU:
56R
3S4R
7S00-1 3S05 A11
D AP: YPBPR1 PNX85500 D
2S7P ANALOG_VIDEO 3S08 B11
AV3-PB
AB15 AC12 3S09 C11
22n CVBS_Y1 ATV_CVBS_Y3
AC13 AF13 IS5C
R C3
22n
22n
22n
22n
22n
56R
2S19
2S18
2S16
2S15
2S14
AD13
3S4T
B AV1
3S4G G6
AE13 AD11
G CVBS_Y7 3S4J A6
AC11
C7
AV2-CVBS 2S8G AF15
SYNCIN1 BS13 3S4K C6
AE15 AF11
22n Y_G1 CVBS1_OUT
AC15 AE11
PR_R_C1 CVBS2_OUT 3S4L B6
AD15
PB_B1
47R
3S5L
RESREF AB10 3S4P C6
AB14 AA11 IS5E 3S5S
CVBS_Y2 CURREF
E AF14 10K E 3S4R D6
2S7Q SYNCIN2
YPBPR2-SYNCIN2 AE14 AC16 IS5D
Y_G2 1
AC14 AB16 IS5F 3S4T D6
10n PR_R_C2 2
AD14 AB13 IS5G
PB_B2 3 3S4U F6
REF 4 AB12 IS5H
AF16 AA12 IS5J
R 5 3S75 3S4W F6
AD16 AA10 PNX-IF-AGC
G VGA 6
AE16 47K
B 3S50 G6
AV4-Y 2S7R AB18 AD12 BS15
HSYNC_IN IF_AGC
10n
2S75
56R
AD25 BS10
3S4U
AP: YPBPR2 SDA TUNER N AF12 IS11
3S76 3S59 A6
PNX-RF-AGC
F +CVBS 47K F
AGND 3S5B A11
10n
2S76
AV4-PR 2S7U
3S5E B11
AA14
22n
3S5L E6
2S77
56R
3S4W
PNX-IF-P 3S5S E9
10n
3S5T-1 I5
2S7E
3S5T-2 I11
AV4-PB
3S5T-3 I5
22n 2S78
PNX-IF-N 3S5T-4 I11
56R
3S4G
G 10n G
3S5V-1 I5
2S84 3S5V-2 I12
R-VGA
22n
3S5V-3 I5
56R
3S5V-4 I12
3S50
3S75 E12
2S85 3S76 F12
G-VGA
22n 7S00-1 D8
56R
3S52
H H 9S14 I3
9S15 I3
2S86 9S17 A13
B-VGA
22n BS10 F9
56R
EU: VGA
3S54
BS13 E9
AP: VGA BS15 F9
100R
100R
100R
100R
H-SYNC-VGA 1 3S5T-1 8
4 3S5T-4 5
2 3S5T-2 7
4 3S5V-4 5
2 3S5V-2 7
100R
IS11 F13
V-SYNC-VGA 3 3S5T-3 6 IS4V B10
100R IS4W C10
I 3 3S5V-3 6 I IS5C D9
VGA-SCL-EDID
100R IS5D E9
VGA-SDA-EDID 1 3S5V-1 8 IS5E E9
100R
VGA-SCL-EDID-TCON 9S14 IS5F E9
VGA-SDA-EDID-TCON 9S15
* = TCON ONLY
IS5G E9
* * IS5H E9
IS5J E9
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3 2010-03-04
2 2010-02-04
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 122
Audio
B03A B03A
1 2 3 4 5 6 7 8 9
1735 E8 3D16 A5
1D38 E9 5D01 C7
1D50 E8 5D02 C7
+AVCC
7D03-1 +24V-AUDIO-POWER 1D52 F8 5D03 E7
3D09 BC847BS(COL) FD14
6
1
+24V-AUDIO-POWER 2D01 F7 5D04 C8
4R7
A A 2D02 F4 5D05 C8
220n
2D06
2
3D16
2D03 E3 5D07 A6
ID12
ID11 2D05 A5 5D08 A6
22K
5D07
220R
5D08
220R
GND-AUDIO 2D06 A5 6D01 E3
2D05
2D07 B5 7D03-1 A5
10u 35V
ID27 ID28
FD01 2D28 ID14 2D24 2D08 B6 7D03-2 F5
-AUDIO-R
8
5
6
7
8
1u0 47n 2D09 C7 7D10-1 B6
6
220n
220n
2D20
2D07
2D19
2D08
3D02-3
2D10 C7 7D10-2 E5
4K7
22K
22K
22K
22K
3D02-1
220n
220n
2D22
2D26
220u 35V
220u 35V
A-PLOP 6 3 2 7D15-1
3D14-4
3D14-3
3D14-2
3D14-1
BC847BS(COL) 2D11 C8 7D11-1 D2
1
4
3
2
1
B 4K7 B
1
2D12 C8 7D11-2 D3
GND-AUDIO GND-AUDIO
2D13 F8 7D13-1 E1
2D14 E8 7D13-2 E2
7D10-1
FD03 2D29 ID15 2D23 TPA3120D2PWP 2D16 C4 7D15 B3
19
20
1
3
10
12
+AUDIO-L
AVCC L R 2D17 C4 7D15 C3
5
1u0 47n
3
PVCC ID32 2D10
16 5D02 5D05
2D19 B6 CD10 D5
3D02-2 ID19 BSR ID10 2D12 RIGHT-SPEAKER
4K7
7 2 5 7D15-2 3D02-4 6
Φ
BC847BS(COL) R CLASS-D 220n 2D20 B5 FD01 B1
15
4
4K7 ID18 ID06 ID08
IN AUDIO AMP R 22u 220R 25V 220u
4 5 2D21 D8 FD02 F8
L OUT
22 5D01 5D04
C L ID09 ID07 2D11 LEFT-SPEAKER C
18 2D22 B8 FD03 B1
0 ID31 2D09
17 GAIN 21 22u ID05 220R
1 BSL 25V 220u 2D23 B4 FD05 E8
GND-AUDIO 2D16 ID29 220n
11 2D24 B4 FD06 E8
VCLAMP
2D17 1u0 7
BYPASS
1u0 ID30 4 2D26 B8 FD07 F4
MUTE
2
AUDIO-MUTE-UP ID37 SD 2D27 D8 FD14 A5
PGND
ID38 AGND L R GND_HS
2D28 B2 ID05 C8
A-STBY
8
9
23
24
13
14
25
2D29 B2 ID06 C8
8
5
6
7
8
+3V3-STANDBY 3D01-1 D3 ID07 C8
4K7
6 CD10
3D15-4
3D01-2 D3 ID08 C8
47K
22K
22K
22K
22K
D D
220n
220n
3D01-1
3D10-4
3D10-3
3D10-2
3D10-1
1
4
3
2
1
5
BC847BS(COL) 3D02 B4 ID12 A5
47K
6 4
GND-AUDIO GND-AUDIO
47K
40
39
38
7D10-2 3D02 C4 ID13 E3
3D01-4
GND-AUDIO
100p
2D03
2 TPA3120D2PWP
4
7D13-1
BC847BS(COL) LEFT-SPEAKER
3D04 E2 ID14 B3
ID36 VIA
1 3 GND-AUDIO 26 37 3D06-1 F4 ID15 B3
ID39 GND-AUDIO +AVCC 27 36
7D13-2 5 1
3D15-1
8 7
3D15-2
2 ID13 6D01 28 VIA
VIA VIA 35 3D06-2 F4 ID18 C5
10n
E BC847BS(COL) E
1D50
2D14
4K7 4K7 29 34
V_NOM
2K2
3D04
1735 1D38
FD05
30
31
32
33
GND-AUDIO GND-AUDIO 5D03 1 1
3D09 A3 ID28 B6
FD06
2 2 3D10-1 D8 ID29 C5
GND-AUDIO 220R 3 3
GND-AUDIO FD02
GND-AUDIO 4 3D10-2 D8 ID30 C5
10n
2D01
3 7D03-2 1735446-3
10n
2D13
2D02
3D14-4 B7 ID36 E2
3D06-3
RIGHT-SPEAKER 3 6 3D15-1 E2 ID37 D4
100K 10u
GND-AUDIO
3D15-2 E3 ID38 D5
3D15-4 D5 ID39 E2
1 2 3 4 5 6 7 8 9
2 2010-02-04
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 123
DC/DC
DC/DC
B03B B03B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A A
5U03 RES
30R
FU05 5U02 IU22
+12V
30R
7U02-1
SI4952DY
10u
10u
10u
10u
1u0
2U24
2U23
2U25
2U19
2U20
B 7 8 B
IU10
2
12V/1V8 CONVERSION
3R3
3U11
2U21 FU02 5U00 FU03
+1V8
5
6
7
8
IU11 220p 3u6
22u
7U02-2
47u
47R
47R
47R
47R
3U23-4 3U23-3
2U15
2U16
3U23-2 3U23-1
SI4952DY
4
3
2
1
5 6
C IU09 C
4 IU23
3
1n0
2U17
IU15
7U01
SI4778DY
1n0
5 6 7 8
2U18
IU08 3U27 IU12
4
10R 1 2 3
10u
D D
2U00
3U14
3R3
3R3
3U04
2U22
IU06 2U02 IU07
IU05 IU13 220p
100n
10R
3U28
7U04
3R3
100n
3U05
2U01
7U03 SI4778DY
TPS53126PW
5 6 78
IU16
2 23 4
1 1 1 2 3
IU24 11 VBST DRVL 14 IU14
2 2
3 1 12V/1V1 CONVERSION
E 1 1 E
ENABLE-1V8 10 EN DRVH 12
2 2
FU06 5U01 FU01
+1V1 4 24 +1V1
1 1
2U03
+1V8 9 VO SW 13
2 2 2u0
1n0 RES
5 22
1 1
6U00
2U14
STPS2L30A
47u
47R
47R
47R
47R
10R
3U20
2U12
2U13
1 1
3 22K 3U03 16 TRIP TEST 17
IU03 2 2
1 22K IU02 GND-SIG
GND-SIG
20 18 FU04 IU17
GND-SIG VIN V5FILT
2 19 IU25
VREG5
+3V3-STANDBY 3U00 2U06
1n0
F F
2U11
+1V1 GND
6
10K 100n
10u
1u0
2U04
2U05
IU18
10K
3U01 GND-SIG
1n0
1u0
2U09
2U10
GND-SIG
3U21 FU00
IU19 SENSE+1V1
100R 1%
3U17
RES
100n
2U29
1% 330R
G IU20 G
5K6
3U19
2U08
3U18
3U08 3U22
100p RES
IU04
1% 1K0
+1V8
330R 1% 1K0 1% IU21
22K
3U09
3U10
2U07
GND-SIG GND-SIG GND-SIG
1K0 1%
RES 100p
CU00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2U00 D2 2U04 F4 2U08 G9 2U12 F11 2U16 C10 2U20 B14 2U24 B5 3U01 F1 3U05 E4 3U11 B6 3U19 G9 3U23-1 C9 3U24-1 F9 3U27 D5 5U02 B13 7U01 D8 7U04 E8 FU02 B9 FU06 E8 IU04 G3 IU08 D4 IU12 D7 IU16 E5 IU20 G9 IU24 E3
2U01 E3 2U05 F4 2U09 F9 2U13 F12 2U17 C9 2U21 C6 2U25 B12 3U02 F2 3U08 G2 3U14 D7 3U20 F11 3U23-2 C9 3U24-2 F9 3U28 D5 5U03 A13 7U02-1 B6 CU00 H7 FU03 C14 IU01 F3 IU05 D3 IU09 C6 IU13 D7 IU17 F9 IU21 H9 IU25 F4
2U02 D4 2U06 F1 2U10 F10 2U14 E14 2U18 D9 2U22 D8 2U29 G14 3U03 F3 3U09 H3 3U17 G10 3U21 G13 3U23-3 C9 3U24-3 F9 5U00 C10 6U00 E8 7U02-2 C6 FU00 G13 FU04 F4 IU02 F3 IU06 D3 IU10 B 6 IU14 E8 IU18 F9 IU22 B13
2U03 E2 2U07 H3 2U11 F9 2U15 C10 2U19 B12 2U23 B5 3U00 F1 3U04 D3 3U10 H3 3U18 G10 3U22 G2 3U23-4 C8 3U24-4 F8 5U01 E10 7U00 F1 7U03 E3 FU01 E14 FU05 B9 IU03 F1 IU07 D4 IU11 C6 IU15 C9 IU19 G10 IU23 C9
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 124
DC/DC
DC/DC
B03C B03C
1 2 3 4 5 6 7 8
1M95 E1 3U83-3 E5
1M99 C1 3U83-4 C5
1U40 E2 3U84 D2
2U41 B1 6U40 E3
2U42 C2 7U40-1 F4
2U43 D2 7U40-2 E4
A +3V3 +3V3-STANDBY A 2U44 D3 7U41-1 F4
2U45 D3 7U41-2 F5
LED-2 2U46 D3 7U42 B5
2U47 E1 7U43 B3
+5V +3V3-STANDBY
3U74
3U75
RES 10K
RES 10K
2U48 F1 7U48-1 C6
IU43
9U41
2U49 F1 7U48-2 E6
LED-1
2U50 F1 9U41 B5
10K
3U68
3U69
IU44 3U41 3U59 2U51 D1 9U42 B4
RES 10K
IU45 LED2 LED2
9U42 10K RES 10K RES
2U52 D1 FU07 C3
B RES B 2U53 D2 FU48 C1
optionally 1M99 is a 9 pin connector 7U42 RES +3V3
∗ BC847BW 2U54 F2 FU49 C1
2U41 RES IU47 3U70 3U53
7U43 LED1 LED1 2U55 F3 FU50 C1
BC847BW 2U68 E1 FU51 C1
100p 10K 10K
+12VD
2U71 D5 FU52 C3
∗ 2U72 D1 FU53 C2
1M99
FU48 2U42
1 3U81 IU56 3U41 B5 FU54 C2
FU49 +3V3
2 FU50 1u0 3U42 C3 FU55 C1
3 10K
4 3U45
3U43 C3 FU56 D1
FU51 LAMP-ON
C 5 C 3U44 C3 FU57 D1
FU52 100R IU64
6 3U82
FU53 3U42 BACKLIGHT-PWM_BL-VS 3U45 C3 FU58 E1
7
8 100R 1K0 RES
FU55 3U64 3U43 BACKLIGHT-BOOST 3U53 B6 FU59 E1
9 7U48-1
10 1K0 FU54 100R FU07 3U83-4 BC857BS(COL) 3U56 D3 FU60 E1
3U44 3D-LR
1
6
4 5 ENABLE-3V3-5V
11
12 100R 100K 3U59 B6 FU61 E1
3U56 IU41
1n0
10n
10n
1n0
100p
3U60-1 F5 FU62 E1
2U51
2U52
2U53
3U65
1-1735446-2
RES 1K0
100p
RES 100p
2
RES 100p
+3V3 10K 3U60-2 F4 FU63 E1
100K
2U72
3U83-1
2U44
2U45
2U46
2U43
FU64 F1
100n
3U60-3 E5
2U71
8
IU55
RES
POWER-OK 3U60-4 F5 FU65 F1
D 3U66 D
FU56 BL-SPI-SDO 3U61 E5 FU66 F1
RES 100R 3U67 3U62-1 F4 FU67 F1
FU57 BL-SPI-CSn +3V3-STANDBY
100R RES 3U84 3U62-2 E3 FU68 F1
4
3
FU74 BL-SPI-CLK
100R RES
3U62-3 E4 FU72 F4
3U71
STANDBY 3U62-4 E3 FU73 E5
2U68 7U48-2
100R BC857BS(COL) 3U63 F5 FU74 D1
5
1u0 7U40-2 3U83-3 3U83-2 3U64 C2 IU40 E5
BC847BPN(COL) 3 6 7 2
2U47
10K
3U62-4 4 3U65 D2 IU41 D5
IU48 100K IU40 100K
4
10n 3U66 D2 IU43 B5
1M95 5
+3V3-STANDBY
2
E FU58 3
E 3U67 D2 IU44 B5
1 3U60-3 FU73
FU59 IU61 3 6 ENABLE-1V8
2
10K
FU60 3U68 B3 IU45 B4
3U62-2
22K
6
3
7
FU61
4 3U69 B3 IU47 B4
3U61
FU62
5 1U40 +12V IU49
10K
3U62-3
6U40
RES 10K
FU63 3U70 B4 IU48 E4
2
6 6
3
FU64 7U40-1
7 T 3.0A 32V IU51
BZX384-C6V2
FU65 BC847BPN(COL) FU72 DETECT2
3U71 D3 IU49 E3
8 FU66
22K
+24V-AUDIO-POWER 2 3U60-2 3U72 F3 IU50 F4
9 FU67 1
7
10 3U76 7U41-2
1K0
FU68 MAINS-OK 3U72 3 BC847BS(COL) 3U73 F3 IU51 F3
5
11 IU63
100R 3U60-1 IU57 3U74 A4 IU52 F5
ENABLE-3V3n
2U55
1-1735446-1 5 8 1
1u0 RES
3U60-4
4K7
22K
IU62
3U80
GND-AUDIO 3U62-1 22K
3U75 A4 IU55 D3
F 3U73 IU50 F
4
4
+3V3-STANDBY IU52
3U76 F2 IU56 C3
10n
10n
6
100p RES
100p RES
8 1
2U48
2U49
2U50
2U54
3K3 10K
7U41-1 3U80 F4 IU57 F6
BC847BS(COL)
3U63
2
1 3U81 C3 IU61 E4
RES 10K
3U82 C5 IU62 F4
3U83-1 D6 IU63 F3
3U83-2 E5 IU64 C6
1 2 3 4 5 6 7 8
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 125
DC/DC
DC/DC
B03D B03D
1 2 3 4 5 6 7 8 9
2UA0 A5 3UB1 E6
2UA1 A4 3UB2 E6
RESERVED 2UA2 B5 3UB3 F6
+2V5-REF +12V +3V3 2UA3 B5 3UB4 F5
7UC0
LF25ABDT *
2UA0
2UA4 A7 3UB5 F5
+12V 1 3
1K0
3UA4 IN OUT 2UA5 B6 3UB6-1 C2
3UA1
A 100n 7UA2 A
3K3 1%
PHD38N02LT COM 2UA6 B7 3UB6-2 C2
2
7UA1-1
8
1u0
IUA1 3 LM833
2UA4
2
IUA3 3UA5 IUA4 2UA7 D4 3UB6-3 C2
2K2
1 1
*
3UA0
2 2UA8 D5 3UB6-4 C2
3
FUA0 22R
100n
+2V5-REF FUA1 2UA9 D5 3UB7-1 D3
2UA1
1 3UA3
47K
2UA3
3UA2
2UB0 C7 3UB7-2 D2
3K3 1%
1n0
7UA0
TS2431
K
IUA9
2UB1 D6 3UB7-3 D2
R
2UA2
2UB2 D7 3UB7-4 C2
330p
2
A
3UA6 2UB3 F6 5UA0 E8
B B
1K0
3 3UA7 FUA4 2UB4 F6 7U06-1 F2
+2V5
IUA2 1K0
2UB5 F8 7U06-2 F1
CUA0
2UB6 F8 7UA0 B2
22K
+2V5-LVDS
1u0
1u0
IUB6 3UA8
2UA5
2UA6
+5V5-TUN +5V-TUN 2UB7 F7 7UA1-1 A5
2UB8 D2 7UA1-2 C5
7UA6 3U12 C3 7UA2 A6
BC817-25W
1%
3UB6-2 3U12 3U13 C3 7UA3 C6
330R
+12V 2 7 IUB3
1K0 IUB2 +1V8 3U15-1 C8 7UA4 E5
3UB6-3 *
C 3 6 6 +12V +3V3 * +3V3 C
3U15-1 3U16-1 3U15-2 C8 7UA5 E8
1K0 +5V 1 8 +5V 1 8
3UB6-4
4 5 2 IU26 100R 100R
1K0 7UA3
3U15-3 D8 7UA6 C3
3UB6-1 IUB5 7UA7-1 3U15-2 3U16-2
1 8 3 1 PHD38N02LT 2 7 2 7 3U15-4 D8 7UA7-1 C3
BC847BS(COL)
1u0
1K0
2UB0
+2V5-REF 7UA1-2
1%
100R 100R
8
3UB7-4 3U13
330R
4 5 5 IUA7 5 LM833 FUA2 3U16-1 C9 7UA7-2 D2
3UB0 IUA5 3U15-3 3U16-3
470R 7 3 6 3 6
7UA7-2 4 IUB4 6 100R 100R
3U16-2 C9 7UC0 A8
BC847BS(COL) 22R
4
4
3U15-4
5 4
3U16-4
5
3U16-3 D9 CUA0 B9
FUA3
7
6
8
470R
470R
100n
+1V2 100R 100R 3U16-4 D9 FUA0 A2
2UA7
22u
1n0
3UB7-23UB7-3
3UB7-1
470R
3U25-1 E3 FUA1 A7
2UB8
2UA9
2
3
1
D 1u0 D 3U25-2 E3 FUA2 D5
2UB1
2UB2
IUA8
330p
2UA8
NOT FOR 5000 SERIES 3U25-3 E2 FUA3 D7
RES 1u0
* 3U25-4 E2 FUA4 B9
1K0
3UA9
ENABLE-1V8 3U26-1 F3 IU26 C3
3U25-4 3U26-2 F3 IU29 E2
4 5
3UB1 SENSE+1V2
100K RES RESERVED 3U26-3 F3 IU30 F3
7
IUA6 1K0 5UA0
3U25-3
3U26-4 F3 IUA1 A4
3 6 3U25-2
30R 3U29-1 E3 IUA2 B5
2
100K RES
100K RES 3U29-1 RES
E 1 8 +12V 7UA5 E 3U29-2 E3 IUA3 A6
470R LDS3985M50
IU29 3U29-3 E3 IUA4 A6
1
3U29-2 RES
2 7 +5V5-TUN 1 5 +5V-TUN
IN OUT 3U29-4 F3 IUA5 C6
470R 7UA4
4K7
3U25-1 3UB2 3 4
3U29-3 RES TS431AILT INH BP IUB1 3UA0 A2 IUA6 E5
3 6 3 6
8
100K RES
+3V3
RES RES IU30 470R 5 3 COM 3UA1 A3 IUA7 C4
A K
7U06-2 5 7U06-1 2
3U29-4 RES
1u0
1u0
BC847BS(COL) BC847BS(COL)
100n
4 5 2 1
2UB7
2
2UB5
2UB6
NC NC
3UA2 B3 IUA8 D5
4 1 470R REF
4K7
470R
3U26-2 RES 3UA5 A6 IUB1 E8
F 2 7 F
3UB5 3UB4 IUB0 2UB3 3UA6 B5 IUB2 C2
470R +5V
3U26-3 RES 100K 1K0 22n 3UA7 B6 IUB3 C3
+3V3 3 6
2UB4
470R 3UA8 B5 IUB4 D3
3U26-4 RES 330p
4 5 RES 3UA9 D5 IUB5 C2
470R 3UB0 D6 IUB6 B3
1 2 3 4 5 6 7 8 9
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 126
DC/DC
DC/DC
B03E B03E
1 2 3 4 5 6 7 8
2U27 B8
2U28 D8
2UD0 A2
2UD1 A2
2UD2 A3
2UD3 B3
A 5UD0 IUD0
A
+12V
2UD4 B5
30R +5V5-TUN 2UD5 B5
7UD0-1
1
6
ST1S10PH 2UD6 B6
10u
10u
10u
A
2UD0
2UD1
2UD2
IUD3 5UD1 6UD0 FUD3
IUD7
SW
ENABLE-3V3-5V 2 7 +5V
2UD7 B6
INH VIN SW
3u6 SS36 +1V1
2UD8 C2
5 3
SYNC VFB 2UD9 C2
GND
22u
22u
22u
100n
A P HS
2UD3
2UD4
2UD5
2UD6
2UE0 C3
4
8
9
RES 1n0
6
220u 16V
RES 2UE9
RES 2U27
2UE1 D5
7U05-1 2
BC847BS(COL) IU27 2UE2 D6
B IUD6 2UD7 B
RES 1 2UE3 D6
7UD0-2 4n7
13
15
ST1S10PH 2UE4 D6
3UD2
10K
3U06
2UE5 E4
1%
1%
68K
33K
10 12
3UD0
3UD1
VIA 120K
2UE6 E6
RES
11
2UE7 F4
14
2UE8 F5
2UE9 B8
∗∗ 3U06 B8
5UD3 IUD1
C +12V C 3U07 D8
30R 3UD0 B5
7UD1-1
1
6
ST1S10PH 3UD1 B5
10u
10u
10u
A
2UE0
2UD8
2UD9
IUD4 5UD2 FUD2
SW
ENABLE-3V3-5V 2 7 +3V3
3UD2 B6
INH VIN SW
3u6 +1V1
3UD3 D5
5 3
SYNC VFB 3UD4 D5
GND
4n7
22u
22u
100n
A P HS
2UE1
2UE2
2UE3
2UE4
3UD3
3UD5 D5
4
8
9
3
220u 16V
BC847BS(COL)
1% 100K
5UD0 A2
RES 2U28
7U05-2 5 IU28
5UD1 A5
RES
IUD2 4 5UD2 C5
D 7UD1-2
D
5UD3 C2
13
15
ST1S10PH
3U07
10K
6UD0 A6
1%
33K
1M0
10 12
3UD4
3UD5
VIA
6UD1 E4
RES
11
7U05-1 B7
14
7U05-2 D7
7UD0-1 A4
7UD2 7UD0-2 B4
∗ LD1117DT25
6UD1 IUD5
7UD1-1 C4
+5V 3 2 +2V5 7UD1-2 D4
E IN OUT E
S1D COM (∗) FOR 5000 SERIES ONLY 7UD2 E5
7UD3 F5
100n
2UE5
1
2UE6
22u 16V
100n
2UE7
1
2UE8
IUD3 A5
22u 16V
IUD4 C5
IUD5 E4
IUD6 B6
IUD7 A5
1 2 3 4 5 6 7 8
2 2010-02-04
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 127
B B
C C
D D
E E
1 2 3 4 5 6 7 2 2010-02-04
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 128
Fan Control
Fan-Control
B03G B03G
1 2 3 4 5 6 7 8 9
2US3 A7
+12V +12V 3US2 A3
3US3 B3
3US4-1 A4
+3V3
3US4-2 D4
8
3US4-3 C4
7
3US4-4 C5
10K
+12V
3US4-1
3US5-1 B6
1
10K
10K
100n
A 3US2 A
2US3
3 7US1-1 3US5-2 A6
3US5-2
3US7 LM339P
9
2
IUS3 3US5-3 IUS6 3US5-3 A5
1K0 14 6 3
FAN-CTRL1
3US5-4 B5
8 10K
7US2 3US6 C6
IUT1 12 BC807-25W 3US7 A4
+12V IUS7 3US9 B6
+3V3 7US1-1 A5
7US1-2 B5
8
7US1-3 C5
22R
3US9
+12V 7US1-4 D5
10K
7US2 A6
3US5-1
10K
3US3
1
3 7US1-2 7US3 B6
B 11 LM339P B
IUS4 3US5-4 9US0 D4
IUT2 13 5 4 BC807-25W
FAN-CTRL2 10 7US3 IUS0 D5
10K IUS8 IUS3 A5
12 IUS4 B5
IUS9
IUS5 C5
IUS6 A6
IUS7 B7
47R
3US6
IUS8 B6
FAN-DRV IUS9 B6
IUT1 A4
+3V3 IUT2 B4
C C
+12V
5
IUS5
+12V
6
10K
3US4-4
4
7US1-3
10K
5 LM339P
3US4-3
2
3
TACH01 4
12
+12V
RES
D +12V D
9US0
7
7US1-4
10K
7 LM339P
3US4-2
1
2
IUS0
TACH02 6
12
TACHO
E E
F F
1 2 3 4 5 6 7 8 9
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 129
Vdisp Switch
VDisp-Switch
B03H B03H
1 2 3 4 5 6 7
2UU0 C6
2UU1 C4
1 9UU0-1 8 3UU0-1 C4
RES 3UU0-2 C4
2 9UU0-2 7
RES
3UU0-3 C2
3 9UU0-3 6 3UU1 C4
RES 3UU2 D6
4 9UU0-4 5
A RES A 3UU3-1 C4
1 9UU1-1 8 3UU3-2 C5
RES
2 9UU1-2 7 3UU3-3 C6
RES 3UU3-4 C7
3 9UU1-3 6
RES
7UU0 B4
FUU0
4 9UU1-4 5 7UU1 B5
RES
7UU2-1 C3
7UU2-2 C3
7UU3 C6
9UU0-1 A4
9UU0-2 A4
B 7UU0
B 9UU0-3 A4
SI4835DDY 9UU0-4 A4
RES 7UU1 +VDISP-INT
9UU1-1 A4
+12VD SI3441BDV
9UU1-2 A4
9UU1-3 A4
3UU3-1
8 1 9UU1-4 A4
4
47K RES FUU0 A5
PUMD12 IUU3
7UU2-2 3UU1 2UU1 3UU3-2
5 2 7 IUU0 C3
47R 1u0 IUU2 47K RES IUU1 C4
3 IUU1
IUU0 3UU0-2 7UU3 RES
7 2 BC847BW
IUU2 C5
1
C 47K
C IUU3 C6
6 3 IUU4 3UU3-3 IUU5 3UU3-4
47K
3UU0-1 1 6 3 4 5 IUU4 C6
3UU0-3 +3V3
2
8
7UU2-1 47K RES 47K RES IUU5 C7
+3V3-STANDBY PUMD12
6 3 2
47K IUU6 D6
1
100n
2UU0
IUU6
VDISP-SWITCH
3UU2
+3V3
4K7 RES
D D
LCD-PWR-ONn
E E
1 2 3 4 5 6 7
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 130
Audio
B03A B03A
1 2 3 4 5 6 7 8 9
1735 E8 3D16 A5
1D38 E9 5D01 C7
+AVCC
7D03-1 +24V-AUDIO-POWER
1D50 E8 5D02 C7
3D09 BC847BS(COL) FD14 1D52 F8 5D03 E7
6
1
+24V-AUDIO-POWER
4R7 2D01 F7 5D04 C8
A A 2D02 F4 5D05 C8
220n
2D06
2
3D16 ID12 2D03 E3 5D07 A6
ID11
22K 2D05 A5 5D08 A6
5D07
220R
5D08
220R
GND-AUDIO
2D06 A5 6D01 E3
2D05
10u 35V
ID27 ID28 2D07 B5 7D03-1 A5
FD01 2D28 ID14 2D24
-AUDIO-R
2D08 B6 7D03-2 F5
8
5
6
7
8
1u0 47n
6 2D09 C7 7D10-1 B6
220n
220n
2D20
2D07
2D19
2D08
3D02-3
4K7
22K
22K
22K
22K
3D02-1
220n
220n
2D22
2D26
6 3 2
220u 35V
220u 35V
A-PLOP 7D15-1 2D10 C7 7D10-2 E5
3D14-4
3D14-3
3D14-2
3D14-1
BC847BS(COL)
1
4
3
2
1
B 4K7 B 2D11 C8 7D11-1 D2
1
2D12 C8 7D11-2 D3
GND-AUDIO GND-AUDIO 2D13 F8 7D13-1 E1
7D10-1 2D14 E8 7D13-2 E2
FD03 2D29 ID15 2D23 TPA3120D2PWP
19
20
1
3
10
12
+AUDIO-L 2D16 C4 7D15 B3
AVCC L R
5
1u0 47n
3 2D17 C4 7D15 C3
PVCC ID32 2D10
16 5D02 5D05
3D02-2 ID19 BSR ID10 2D12 RIGHT-SPEAKER
4K7
7 2 5 7D15-2 3D02-4 6
R
Φ
220n
2D19 B6 CD10 D5
BC847BS(COL) CLASS-D 15
4
4K7 ID18 ID06 ID08
IN AUDIO AMP R 22u 220R 25V 220u 2D20 B5 FD01 B1
4 5
L OUT
22 5D01 5D04 2D21 D8 FD02 F8
C L ID09 ID07 2D11 LEFT-SPEAKER C
18
0 ID31 2D09
17 GAIN 21 22u ID05 220R 2D22 B8 FD03 B1
1 BSL 25V 220u
GND-AUDIO 2D16 ID29 220n 2D23 B4 FD05 E8
11
VCLAMP
2D17 1u0 7 2D24 B4 FD06 E8
BYPASS
1u0 ID30 4
MUTE
2 2D26 B8 FD07 F4
AUDIO-MUTE-UP ID37 SD
PGND 2D27 D8 FD14 A5
ID38 AGND L R GND_HS
A-STBY 2D28 B2 ID05 C8
8
9
23
24
13
14
25
5
2D29 B2 ID06 C8
8
5
6
7
8
+3V3-STANDBY
4K7
6 CD10 3D01-1 D3 ID07 C8
3D15-4
47K
22K
22K
22K
22K
D D
220n
220n
3D01-1
3D10-4
3D10-3
3D10-2
3D10-1
2
3D01-2 D3 ID08 C8
1
4
3
2
1
7D11-1
BC847BS(COL) 3D01-4 E2 ID09 C7
ID34 GND-AUDIO
1 3 +3V3-STANDBY
+3V3-STANDBY ID35
3D01-2
3D02 B3 ID10 C7
7D11-2 5 2 7 DETECT2
5
BC847BS(COL) 3D02 C3 ID11 A4
47K
6 4 3D02 B4 ID12 A5
GND-AUDIO GND-AUDIO
47K
40
39
38
7D10-2
3D01-4
GND-AUDIO
100p
2D03
2 TPA3120D2PWP
4
7D13-1 3D02 C4 ID13 E3
BC847BS(COL) LEFT-SPEAKER
ID36 VIA 3D04 E2 ID14 B3
1 3 GND-AUDIO 26 37
ID39 GND-AUDIO +AVCC 27 36 ID15 B3
7D13-2 5 1
3D15-1
8 7
3D15-2
2 ID13 6D01 28 VIA
VIA VIA 35
3D06-1 F4
10n
E BC847BS(COL) E
1D50
2D14
2K2
3D04
1735 1D38
FD05
3D06-4 F3 ID27 B6
30
31
32
33
GND-AUDIO GND-AUDIO 5D03 1 1
FD06 3D09 A3 ID28 B6
2 2
GND-AUDIO 220R 3 3
GND-AUDIO FD02 3D10-1 D8 ID29 C5
GND-AUDIO 4
10n
2D01
3 7D03-2 1735446-3
10n
3D10-2 D8 ID30 C5
2D13
BC847BS(COL) 1735446-4
3D06-4 FD07 3D06-2
LEFT-SPEAKER 5 3D10-3 D7 ID31 C6
4 100K 5 7 100K 2
4 3D10-4 D7 ID32 C6
RIGHT-SPEAKER
F 3D06-1 F 3D14-1 B8 ID33 F4
8 1
ID33
100K 3D14-2 B8 ID34 D3
GND-AUDIO
1D52
3D14-3 B7 ID35 D3
V_NOM
2D02
3D06-3 3D14-4 B7 ID36 E2
RIGHT-SPEAKER 3 6
100K 10u 3D15-1 E2 ID37 D4
GND-AUDIO
3D15-2 E3 ID38 D5
3D15-4 D5 ID39 E2
1 2 3 4 5 6 7 8 9
3 2010-03-05
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 131
DC/DC
DC/DC
B03B B03B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A A
5U03 RES
30R
FU05 5U02 IU22
+12V
30R
7U02-1
SI4952DY
10u
10u
10u
10u
1u0
2U24
2U23
2U25
2U19
2U20
B 7 8 B
IU10
2
12V/1V8 CONVERSION
3R3
3U11
2U21 FU02 5U00 FU03
+1V8
5
6
7
8
IU11 220p 3u6
22u
7U02-2
47u
47R
47R
47R
47R
3U23-4 3U23-3
2U15
2U16
3U23-2 3U23-1
SI4952DY
4
3
2
1
5 6
C IU09 C
4 IU23
3
1n0
2U17
IU15
7U01
SI4778DY
1n0
5 6 7 8
2U18
IU08 3U27 IU12
4
10R 1 2 3
10u
D D
2U00
3U14
3R3
3R3
3U04
2U22
IU06 2U02 IU07
IU05 IU13 220p
100n
10R
3U28
7U04
3R3
100n
3U05
2U01
7U03 SI4778DY
TPS53126PW
5 6 78
IU16
2 23 4
1 1 1 2 3
IU24 11 VBST DRVL 14 IU14
2 2
3 1 12V/1V1 CONVERSION
E 1 1 E
ENABLE-1V8 10 EN DRVH 12
2 2
FU06 5U01 FU01
+1V1 4 24 +1V1
1 1
2U03
+1V8 9 VO SW 13
2 2 2u0
1n0 RES
5 22
1 1
6U00
2U14
STPS2L30A
47u
47R
47R
47R
47R
10R
3U20
2U12
2U13
1 1
3 22K 3U03 16 TRIP TEST 17
IU03 2 2
1 22K IU02 GND-SIG
GND-SIG
20 18 FU04 IU17
GND-SIG VIN V5FILT
2 19 IU25
VREG5
+3V3-STANDBY 3U00 2U06
1n0
F F
2U11
+1V1 GND
6
10K 100n
10u
1u0
2U04
2U05
IU18
10K
3U01 GND-SIG
1n0
1u0
2U09
2U10
GND-SIG
3U21 FU00
IU19 SENSE+1V1
100R 1%
3U17
RES
100n
2U29
1% 330R
G IU20 G
5K6
3U19
2U08
3U18
3U08 3U22
100p RES
IU04
1% 1K0
+1V8
330R 1% 1K0 1% IU21
22K
3U09
3U10
2U07
GND-SIG GND-SIG GND-SIG
1K0 1%
RES 100p
CU00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2U00 D2 2U04 F4 2U08 G9 2U12 F11 2U16 C10 2U20 B14 2U24 B5 3U01 F1 3U05 E4 3U11 B6 3U19 G9 3U23-1 C9 3U24-1 F9 3U27 D5 5U02 B13 7U01 D8 7U04 E8 FU02 B9 FU06 E8 IU04 G3 IU08 D4 IU12 D7 IU16 E5 IU20 G9 IU24 E3
2U01 E3 2U05 F4 2U09 F9 2U13 F12 2U17 C9 2U21 C6 2U25 B12 3U02 F2 3U08 G2 3U14 D7 3U20 F11 3U23-2 C9 3U24-2 F9 3U28 D5 5U03 A13 7U02-1 B6 CU00 H7 FU03 C14 IU01 F3 IU05 D3 IU09 C6 IU13 D7 IU17 F9 IU21 H9 IU25 F4
2U02 D4 2U06 F1 2U10 F10 2U14 E14 2U18 D9 2U22 D8 2U29 G14 3U03 F3 3U09 H3 3U17 G10 3U21 G13 3U23-3 C9 3U24-3 F9 5U00 C10 6U00 E8 7U02-2 C6 FU00 G13 FU04 F4 IU02 F3 IU06 D3 IU10 B 6 IU14 E8 IU18 F9 IU22 B13
2U03 E2 2U07 H3 2U11 F9 2U15 C10 2U19 B12 2U23 B5 3U00 F1 3U04 D3 3U10 H3 3U18 G10 3U22 G2 3U23-4 C8 3U24-4 F8 5U01 E10 7U00 F1 7U03 E3 FU01 E14 FU05 B9 IU03 F1 IU07 D4 IU11 C6 IU15 C9 IU19 G10 IU23 C9
3 2010-03-05
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 132
DC/DC
DC/DC
B03C B03C
1 2 3 4 5 6 7 8 9
1M95 E1 3U83-3 E5
1M99 C1 3U83-4 C5
1U40 E2 3U84 D2
2U41 B1 6U40 E3
2U42 C2 7U40-1 F4
2U43 D2 7U40-2 E4
A A 2U44 D3 7U41-1 F4
+3V3 +3V3-STANDBY
2U45 D3 7U41-2 F5
LED-2 2U46 D3 7U42 B5
2U47 E1 7U43 B3
+5V +3V3-STANDBY
3U74
3U75
2U48 F1 7U48-1 C6
RES 10K
RES 10K
IU43
9U41 2U49 F1 7U48-2 E6
LED-1
2U50 F1 9U41 B5
10K
3U68
3U69
IU44 3U41 3U59
2U51 D1 9U42 B4
RES 10K
IU45 LED2 LED2
9U42 2U52 D1 FU07 C3
optionally 1M99 is a 9 pin connector 10K RES 10K RES
B * RES B 2U53 D2 FU48 C1
7U42 RES +3V3
BC847BW 2U54 F2 FU49 C1
2U41 RES IU47 3U70 3U53 2U55 F3 FU50 C1
7U43 LED1 LED1
BC847BW 2U68 E1 FU51 C1
* 100p 10K 10K
+12VD
2U71 D5 FU52 C3
2U72 D1 FU53 C2
1M99
FU48 2U42 FU54 C2
1 IU56 3U41 B5
3U81
FU49 +3V3
2 FU50 1u0 3U42 C3 FU55 C1
3 10K
4 3U45
3U43 C3 FU56 D1
FU51 LAMP-ON
C 5 C 3U44 C3 FU57 D1
FU52 100R IU64
6 3U82
FU53 3U42 BACKLIGHT-PWM_BL-VS 3U45 C3 FU58 E1
7
8 100R 1K0 RES
FU55 3U64 3U43 BACKLIGHT-BOOST 3U53 B6 FU59 E1
9 7U48-1
10 1K0 FU54 100R FU07 3U83-4 BC857BS(COL) 3U56 D3 FU60 E1
3U44 3D-LR
1
6
4 5 ENABLE-3V3-5V
11
12 100R 100K 3U59 B6 FU61 E1
3U56 IU41
1n0
10n
10n
1n0
100p
3U60-1 F5 FU62 E1
2U51
2U52
2U53
3U65
1-1735446-2
RES 1K0
100p
RES 100p
2
RES 100p
+3V3 10K 3U60-2 F4 FU63 E1
100K
2U72
3U83-1
2U44
2U45
2U46
2U43
100n
2U71
FU64 F1
8
IU55 3U60-3 E5
RES
POWER-OK 3U60-4 F5 FU65 F1
D 3U66 D
FU56 BL-SPI-SDO 3U61 E5 FU66 F1
RES 100R 3U67
BL-SPI-CSn +3V3-STANDBY
3U62-1 F4 FU67 F1
FU57
100R RES 3U84 3U62-2 E3 FU68 F1
4
3
FU74 BL-SPI-CLK
100R RES 3U62-3 E4 FU72 F4
3U71
STANDBY 3U62-4 E3 FU73 E5
2U68 7U48-2
100R BC857BS(COL)
5
3U63 F5 FU74 D1
5
1u0 7U40-2 3U83-3 3U83-2
BC847BPN(COL) 3 6 7 2 3U64 C2 IU40 E5
2U47
10K
3U62-4 4
IU48 100K IU40 100K 3U65 D2 IU41 D5
4
10n
1M95 5 3U66 D2 IU43 B5
+3V3-STANDBY
2
E FU58 3
E
1 3U60-3 FU73 3U67 D2 IU44 B5
FU59 IU61 3 6 ENABLE-1V8
2
10K
FU60 3U68 B3 IU45 B4
3U62-2
22K
6
3
7
FU61
4 3U69 B3 IU47 B4
3U61
FU62
5 1U40 +12V IU49
10K
3U62-3
6U40
RES 10K
FU63 3U70 B4 IU48 E4
2
6 6
3
FU64 7U40-1
7 T 3.0A 32V IU51
BZX384-C6V2
FU65 BC847BPN(COL) FU72 DETECT2 3U71 D3 IU49 E3
8 FU66
22K
+24V-AUDIO-POWER 2 3U60-2
9 FU67 3U72 F3 IU50 F4
1
7
10 3U76 7U41-2
1K0
FU68 3
3U72
MAINS-OK BC847BS(COL) 3U73 F3 IU51 F3
5
11 IU63
100R 3U60-1 IU57
ENABLE-3V3n 3U74 A4 IU52 F5
2U55
1-1735446-1 5 8 1
1u0 RES
3U60-4
4K7
22K
IU62
3U80
F GND-AUDIO 3U73 3U62-1 IU50 22K F 3U75 A4 IU55 D3
4
4
+3V3-STANDBY IU52
10n
10n
6
100p RES
100p RES
8 1
2U48
2U49
2U50
2U54
3K3 10K 3U76 F2 IU56 C3
7U41-1
BC847BS(COL) 3U80 F4 IU57 F6
3U63
2
1 3U81 C3 IU61 E4
RES 10K
3U82 C5 IU62 F4
3U83-1 D6 IU63 F3
3U83-2 E5 IU64 C6
1 2 3 4 5 6 7 8 9
3 2010-03-05
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 133
DC/DC
DC/DC
B03D B03D
1 2 3 4 5 6 7 8 9
2UA0 A5 3UB1 E6
2UA1 A4 3UB2 E6
RESERVED 2UA2 B5 3UB3 F6
+2V5-REF +12V +3V3 2UA3 B5 3UB4 F5
7UC0
LF25ABDT * 2UA4 A7 3UB5 F5
+12V 2UA0
1 3
1K0
3UA4 IN OUT 2UA5 B6 3UB6-1 C2
3UA1
A 100n 7UA2 A
3K3 1%
PHD38N02LT COM 2UA6 B7 3UB6-2 C2
2
7UA1-1
8
1u0
IUA1 3 LM833
2UA4
2
IUA3 3UA5 IUA4 * 2UA7 D4 3UB6-3 C2
2K2
1 1
3UA0
2 2UA8 D5 3UB6-4 C2
3
FUA0 22R
100n
+2V5-REF FUA1 2UA9 D5 3UB7-1 D3
2UA1
1 3UA3
47K
2UA3
3UA2
2UB0 C7 3UB7-2 D2
3K3 1%
1n0
7UA0
TS2431
K
IUA9
2UB1 D6 3UB7-3 D2
R
2UA2
2UB2 D7 3UB7-4 C2
330p
2
A
3UA6 2UB3 F6 5UA0 E8
B B
1K0
3 3UA7 FUA4 2UB4 F6 7U06-1 F2
+2V5
IUA2 1K0
2UB5 F8 7U06-2 F1
CUA0
2UB6 F8 7UA0 B2
22K
+2V5-LVDS
1u0
1u0
IUB6 3UA8
2UA5
2UA6
+5V5-TUN +5V-TUN 2UB7 F7 7UA1-1 A5
2UB8 D2 7UA1-2 C5
7UA6 3U12 C3 7UA2 A6
BC817-25W
1%
3UB6-2 3U12 3U13 C3 7UA3 C6
330R
+12V 2 7 IUB3
1K0 IUB2 +1V8 3U15-1 C8 7UA4 E5
3UB6-3 *
C 3 6 6 +12V +3V3 * +3V3 C
3U15-1 3U16-1
1K0 +5V 1 8 +5V 1 8 3U15-2 C8 7UA5 E8
3UB6-4
4 5 2 IU26 100R 100R
1K0 7UA3
3U15-3 D8 7UA6 C3
3UB6-1 IUB5 7UA7-1 3U15-2 3U16-2
1 8 3 1 PHD38N02LT 2 7 2 7
BC847BS(COL) 3U15-4 D8 7UA7-1 C3
1u0
1K0
2UB0
+2V5-REF 7UA1-2
1%
100R 100R
8
3UB7-4 3U13
330R
4 5 5 IUA7 5 LM833 FUA2 3U16-1 C9 7UA7-2 D2
3UB0 IUA5 3U15-3 3U16-3
470R 7 3 6 3 6
7UA7-2 4 IUB4 6 3U16-2 C9 7UC0 A8
BC847BS(COL) 22R 100R 100R
4
3U15-4 3U16-4 3U16-3 D9 CUA0 B9
FUA3 4 5 4 5
7
6
8
470R
100n
+1V2 100R 100R 3U16-4 D9 FUA0 A2
2UA7
22u
1n0
470R
2UB8
2UA9
3U25-1 E3 FUA1 A7
3UB7-3
3UB7-2
3UB7-1470R
2
3
1
D D
1u0
3U25-2 E3
2UB1
2UB2
IUA8
FUA2 D5
330p
2UA8
NOT FOR 5000 SERIES
RES 1u0
* 3U25-3 E2 FUA3 D7
3U25-4 E2 FUA4 B9
1K0
3UA9
ENABLE-1V8 3U26-1 F3 IU26 C3
3U25-4 3U26-2 F3
4 5 IU29 E2
3UB1 SENSE+1V2
100K RES RESERVED
7
3U26-3 F3 IU30 F3
IUA6 1K0 5UA0
3
3U25-3
6 3U25-2
3U26-4 F3 IUA1 A4
30R
2
100K RES
100K RES 3U29-1 RES
3U29-1 E3 IUA2 B5
E 1 8 +12V 7UA5 E
470R LDS3985M50 3U29-2 E3 IUA3 A6
IU29
1
3U29-2 RES 3U29-3 E3 IUA4 A6
2 7 +5V5-TUN 1 5 +5V-TUN
IN OUT
470R 7UA4
3U29-4 F3 IUA5 C6
4K7
3U25-1 3UB2 3 4
3U29-3 RES TS431AILT INH BP IUB1
3 6 3 6
8
100K RES
+3V3 3UA0 A2 IUA6 E5
RES RES IU30 470R 5 3 COM
A K 3UA1 A3 IUA7 C4
7U06-2 5 7U06-1 2
3U29-4 RES
1u0
1u0
BC847BS(COL) BC847BS(COL)
100n
4 5 2 1
2UB7
2
2UB5
2UB6
NC NC 3UA2 B3 IUA8 D5
4 1 470R REF
4K7
470R
3UA4 A4 IUB0 F6
3U26-2 RES 3UA5 A6 IUB1 E8
F 2 7 F
3UB5 3UB4 IUB0 2UB3
470R +5V 3UA6 B5 IUB2 C2
3U26-3 RES 100K 1K0 22n
+3V3 3 6 3UA7 B6 IUB3 C3
2UB4
470R
RES 330p
3UA8 B5 IUB4 D3
3U26-4
4 5 RES 3UA9 D5 IUB5 C2
470R
3UB0 D6 IUB6 B3
1 2 3 4 5 6 7 8 9
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 134
DC/DC
DC/DC
B03E B03E
1 2 3 4 5 6 7 8
2U27 B8
2U28 D8
2UD0 A2
2UD1 A2
A 5UD0 IUD0
A
+12V
2UD2 A3
30R +5V5-TUN 2UD3 B3
7UD0-1
1
6
ST1S10PH 2UD4 B5
10u
10u
10u
A
2UD0
2UD1
2UD2
IUD3 5UD1 6UD0 FUD3
IUD7
SW
ENABLE-3V3-5V 2 7
2UD5 B5
INH SW +5V
VIN 2UD6 B6
3u6 SS36 +1V1
5 3
SYNC VFB 2UD7 B6
GND
22u
22u
22u
100n
A P HS
2UD3
2UD4
2UD5
2UD6
2UD8 C2
4
8
9
RES 1n0
6
220u 16V
RES 2UE9
2UD9 C2
RES 2U27
7U05-1 2 2UE0 C3
BC847BS(COL) IU27
B IUD6 2UD7 B 2UE1 D5
RES 1
7UD0-2 4n7 2UE2 D6
13
15
ST1S10PH
3UD2
10K
3U06 2UE3 D6
1%
1%
68K
33K
10 12
3UD0
3UD1
VIA 120K 2UE4 D6
RES
11 2UE5 E4
14
2UE6 E6
2UE7 F4
2UE8 F5
** 5UD3
2UE9 B8
IUD1
C +12V C 3U06 B8
30R
7UD1-1 3U07 D8
1
6
ST1S10PH
3UD0 B5
10u
10u
10u
A
2UE0
2UD8
2UD9
IUD4 5UD2 FUD2
SW
ENABLE-3V3-5V 2 7 +3V3 3UD1 B5
INH VIN SW
3u6 +1V1 3UD2 B6
5 3
SYNC VFB
GND 3UD3 D5
4n7
22u
22u
100n
A P HS
2UE1
2UE2
2UE3
2UE4
3UD3
3UD4 D5
4
8
9
3
220u 16V
BC847BS(COL)
1% 100K
3UD5 D5
RES 2U28
7U05-2 5 IU28
RES
5UD0 A2
IUD2 4 5UD1 A5
D 7UD1-2
D
5UD2 C5
13
15
ST1S10PH
3U07
10K
5UD3 C2
1%
33K
1M0
10 12
3UD4
3UD5
VIA 6UD0 A6
RES
11 6UD1 E4
14
7U05-1 B7
7U05-2 D7
7UD2
7UD0-1 A4
* LD1117DT25 7UD0-2 B4
6UD1 IUD5
+5V 3 2 +2V5
7UD1-1 C4
E IN OUT E
S1D COM FOR 5000 SERIES ONLY 7UD1-2 D4
(*) 7UD2 E5
100n
2UE5
1
2UE6
7UD3 F5
22u 16V
100n
2UE7
1
2UE8
22u 16V
IUD3 A5
IUD4 C5
IUD5 E4
IUD6 B6
IUD7 A5
1 2 3 4 5 6 7 8
3 2010-03-05
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 135
B B
C C
D D
E E
1 2 3 4 5 6 7
3 2010-03-05
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 136
Fan Control
Fan-Control
B03G B03G
1 2 3 4 5 6 7 8 9
2US3 A7
+12V +12V
3US2 A3
+3V3 3US3 B3
8
3US4-1 A4
10K
+12V
3US4-1
3US4-2 D4
1
10K
10K
100n
A 3US2 A
2US3
3 7US1-1
3US5-2
3US7 LM339P 3US4-3 C4
9
2
IUS3 3US5-3 IUS6
1K0 14 6 3
FAN-CTRL1 8
3US4-4 C5
10K
7US2 3US5-1 B6
IUT1 12 BC807-25W
+12V IUS7 3US5-2 A6
+3V3
3US5-3 A5
8
22R
3US9
3US5-4 B5
+12V
10K
3US6 C6
3US5-1
10K
3US3
1
3 7US1-2
B 11 LM339P B 3US7 A4
IUS4 3US5-4
IUT2 13 5 4 BC807-25W
FAN-CTRL2 10 10K
7US3 3US9 B6
IUS8
12 7US1-1 A5
IUS9
7US1-2 B5
7US1-3 C5
47R
3US6
7US1-4 D5
FAN-DRV
7US2 A6
+3V3 7US3 B6
C C
+12V 9US0 D4
5
IUS5 IUS0 D5
+12V
6
10K
3US4-4
IUS3 A5
4
7US1-3
10K
5 LM339P
3US4-3
2
IUS4 B5
3
TACH01 4
IUS5 C5
12
IUS6 A6
+12V IUS7 B7
RES
D +12V D
9US0
IUS8 B6
7
7US1-4 IUS9 B6
10K
7 LM339P
3US4-2
1 IUT1 A4
2
IUS0
TACH02 6
IUT2 B4
12
TACHO
E E
F F
1 2 3 4 5 6 7 8 9
3 2010-03-05
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 137
Vdisp Switch
VDisp-Switch
B03H B03H
1 2 3 4 5 6 7
2UU0 C6
2UU1 C4
1 9UU0-1 8
3UU0-1 C4
RES
2 9UU0-2 7 3UU0-2 C4
RES
3 9UU0-3 6 3UU0-3 C2
RES 3UU1 C4
4 9UU0-4 5
A RES A 3UU2 D6
1 9UU1-1 8
RES 3UU3-1 C4
2 9UU1-2 7
RES
3UU3-2 C5
3 9UU1-3 6 3UU3-3 C6
RES FUU0
4 9UU1-4 5 3UU3-4 C7
RES
7UU0 B4
7UU1 B5
7UU2-1 C3
7UU2-2 C3
B 7UU0
B 7UU3 C6
SI4835DDY 9UU0-1 A4
RES 7UU1 +VDISP-INT
+12VD SI3441BDV 9UU0-2 A4
9UU0-3 A4
8
3UU3-1
1
9UU0-4 A4
4 9UU1-1 A4
47K RES
PUMD12 IUU3
7UU2-2 3UU1 2UU1 3UU3-2
5 2 7 9UU1-2 A4
47R 1u0 IUU2 47K RES
3 IUU1 9UU1-3 A4
IUU0 3UU0-2 7UU3 RES
7 2 BC847BW 9UU1-4 A4
1
C 47K
C
6 3 IUU4 3UU3-3 IUU5 3UU3-4 FUU0 A5
47K
3UU0-1 1 6 3 4 5
3UU0-3 +3V3
2 IUU0 C3
8
7UU2-1 47K RES 47K RES
+3V3-STANDBY PUMD12
6 3 2
47K IUU1 C4
1
100n
2UU0
IUU2 C5
IUU6 IUU3 C6
VDISP-SWITCH
3UU2 IUU4 C6
+3V3
4K7 RES IUU5 C7
D D IUU6 D6
LCD-PWR-ONn
E E
1 2 3 4 5 6 7
3 2010-03-05
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 138
Analogue Externals A
B04A B04A
1 2 3 4 5 6 7 8 9 10 11 12 13
1E00 A4 3E16 D11 7E06-1 E7
1E01-1 D5 3E17 E10 7E06-2 E6
RESET-AVPIP 1E01-2 H5 3E18 E7 7E09-1 H2
1E02 C13 3E19 E7 7E09-2 G10
AP-SCART-OUT-R 3E63-1 FE60
1E12 D4 3E24 C7 9E01 D6
FE70 IEC0 IE67 1 8
3E37-4 3EA7-1 2EA4 100R 1E18 F4 3E25 C13 9E02 D7
AP-SCART-OUT-R AUDIO-OUT-L
A 4 100R 5 8 470R 1 1u0 16V A 1E19 F4 3E31 E3 9E05 F5
FEA0
12V
1E22 H4 3E32 E3 9E06 G5
100p
100p
2E29
1E45
2E50
7E01-1 6 AP-SCART-OUT-L
IEC1 1E23 I4 3E37-1 C3 9E07 F5
CDS4C12GTA
12V
100p
100p
2E01
1E00
2E87
2
RES 6E10
1E24 I11 3E37-2 G13 9E08 F5
CDS4C12GTA
1
RES 6E01
PUMH7
1E25 I4 3E37-3 H13 9E09 G5
AUDIO-IN2-R IE20 3E11-1 FE61 1E26 G11 3E37-4 A3 9E10 F5
IEC2 2EA5 IE68 1 1K0 8 1E27 H11 3E39 H10 9E50 D1
3EA7-4
IE22 FE71 AUDIO-OUT-R
3E07-4 1E31 B4 3E43 H2 9E51 D2
AUDIO-IN1-R 5 470R 4 1u0 16V
4 1K0 5 FEA1 1E45 A11 3E44 G2 9E52 E1
12V
100p
100p
2E30
1E46
2E51
7E01-2 3 AP-SCART-OUT-R
1E46 B11 3E45 G7 9E53 E2
B FEC8 B
CDS4C12GTA
5
RES 6E08
1E47 C11 3E48 G7 9E54 F1
12V
100p
100p
2E06
1E31
2E88
+3V3 1E48 C11 3E49 I7 9E55 F2
4
FE62
CDS4C12GTA
PUMH7 AP-SCART-OUT-L 3E63-4
RES 6E03
4 5
1E49 D11 3E52 H7 BEC0 D10
100R
1E52 F11 3E61 G11 BEC1 E10
3E37-1 FE72 1E53 C4 3E62 H2 BEC2 F10
10K
AP-SCART-OUT-L 3E25
12V
100p
100p
1E54 D4 3E63-1 A11 BEC3 D2
2E32
1E47
2E70
1 100R 8
3E24
A-PLOP 1E55 E4 3E63-2 I13 BEC5 F2
CDS4C12GTA
RES 6E12
2K2
1E56 E11 3E63-3 I13 FE55 D9
12V
100p
100p
2E10
1E53
2E90
AUDIO-IN2-L IE21 3E11-4
SCART2 1E57 E11 3E63-4 B11 FE60 A12
C C
CDS4C12GTA
4 5 1EP2 F13 3E73 G10 FE61 B12
RES 6E07
1K0 (AV2)
1E02
2E01 A3 3E74 D2 FE62 B12
IE23 3E07-1 * EU
AUDIO-IN1-L 2E04 D3 3E75 D2 FE63 D12
12V
100p
100p
2E31
1E48
2E82
1 1
1K0 8 2E06 B3 3E76 E2 FE64 D12
3E80 18R
CDS4C12GTA
+5V 2 2E10 C3 3E77 E2 FE66 E12
RES 6E14
AP 2E12 F4 3E78 F2 FE67 E12
12V
100p
100p
2E04
1E54
2E91
YPBPR1-PB 9E50 9E51 3E82 3
FE55 5E77 BEC0
AV4-PB 2E13 G11 3E79 F2 FE68 D12
3E74 18R
CDS4C12GTA
4
RES 6E09
SCART1 1u8 18R 2E14 F4 3E80 D10 FE70 A5
1R0
3EA2
150p
150p
2E89
2E92
(AV1) IE90 5 2E15 D4 3E82 D10 FE71 B5
IE53 BEC3
5E73 3E75
12V
100p
1E49
2E16
D AV1-B D 2E16 D12 3E83 E10 FE72 C5
1u8 18R 1E01-1 6
CDS4C12GTA
2E17 E12 3E84 E10 FE73 E5
RES 6E24
RES FE68
1 7
2E18 E4 3E85 F10 FE74 E5
1K0
* EU
12V
150p
150p
100p
100n
2E79
2E80
1E12
2E15
9E01
9E02
2EB1
3EA1
AV2-STATUS FE63
2 8 2E19 F12 3E86 F10 FE75 E5
IE89
CDS4C12GTA
IE05
RES 6E23
RES IE13 3E16 12K FE64 2E24 G2 3EA1 D6 FE76 G12
3 9
IE61 YPBPR2-SYNCIN2 2E29 A10 3EA2 D6 FE77 H12
4K7
12V
100p
3E17
1E56
* EU 4 4 7E06-2 2E99 2E33 10
12 2E30 B10 3EA7-1 A7 FE78 H12
1u0
39K
3E18 2
2EB3
3E31 3E83 18R FE66 11
CDS4C12GTA
IE18 5 5 11
RES 6E02
AV1-STATUS 2E31 C10 3EA7-2 H13 FE79 F13
1
5p6 10
6 7E06-1
12K FE73 9 2E32 C10 3EA7-3 I13 FE80 E4
6 3 BC847BPN(COL) IE70 5E80 5E78 12
2E81 IE59 CVBS-MON-OUT1 AV4-Y IE56 BEC1 3E84 8
AP 2 2E33 E12 3EA7-4 B7 FE81 F5
E FE74 7 E
4K7
12V
100p
3E32
1E55
2E18
YPBPR1-SYNCIN1 9E52 9E53 7 13
2
IE60 2u2 10u 1u8 18R 6 2E41 H12 3EB1 E6 FE82 F5
1 3EB1 2 1
3E76 18R FE75 5
CDS4C12GTA
39p
18p
150p
2E97
2E98
8 BC847BPN(COL) 14
2E94
2E44 I4 3EB3 E6 FE83 G5
RES 6E22
820R 4
18K
12V
150p
100p
3E19
2E93
1E57
2E17
1
IE54 5E74 3E77 FE80 2
CDS4C12GTA
RES 6E34
330R
AV1-G IE08 RES 1
2E51 B12 3EB6-2 H13 FE85 G5
9E08 10 16
1 3EB3 2
1u8 18R 2E70 C12 3EB6-3 I13 FEA0 A7
3E85 18R 1EP2
150p
150p
2E83
2E84
11 17 2E73 H7 3EB6-4 G6 FEA1 B7
12V
100p
6E26
1E18
2E14
IE14 IE57 5E79 BEC2 3E86 2E74 F7 3EB9-1 H6 FEC8 B13
9E07 12 AV4-PR 18
CDS4C12GTA
12V
100p
1E52
2E19
RES
AP 1u8
YPBPR1-PR 9E10 13 19
2E76 I4 3EB9-3 I13 IE08 E5
CDS4C12GTA
RES 6E35
150p
9E54 9E55 IE16
2E96
F +5V F
150p
2E95
3E78 18R 9E05 14 20 2E77 G12 3EB9-4 I6 IE13 D6
IE55 5E76 3E79BEC5 FE81 2E78 I12 5E73 D2 IE14 F5
AV1-R 15 RES 21
+3V3
1u8 18R FE82 FE79 2E79 D1 5E74 E2 IE16 F5
16
2E80 D2 5E76 F2 IE17 G5
150p
150p
100n
2E85
2E86
2E74
MTJ-505H-01 NI LF
12V
100p
1E19
2E12
9E09 17 2E81 E7 5E77 D10 IE18 E3
IE17 IE96 IE91
CDS4C12GTA
4K7
9E06 18 1 3EB6-1 8
RES 6E28
RES
100n 16V
5
* EU
G 7E09-2 5 G
21 PUMH7 2E86 F2 6E02 E11 IE48 G2
3EB6-4 FE76
470R
4 2E87 A4 6E03 B3 IE51 G10
4K7
100n
3E44
2E24
4
FE85
12V
75R
2E88 B4 6E07 C3
100p
3E61
1E26
IE52 H2
MRC-021V-29 PC RES
3E48 3E37-2 2E89 D9 6E08 B11 IE53 D1
CDS4C12GTA
RES 2E77
RES 6E36
IE48
AV1-BLK 6 2E90 C4 6E09 D3 IE54 E1
1E01-2 68R 2 100R 7
12V
75R
2E94 E9 6E22 E3
100p
3E43
1E22
2 1K0 7 IE59 E8
H 3E07-3 H 2E95 F10 6E23 D3 IE60 E6
CDS4C12GTA
12V
2E73
RES 6E29
100n
100p
RES 2E75
1E27
2E41
RES 6E37
5
3EA7-3
3
3EB6-3
6
IE68 B8
68R
100p
2EA4 A7 6E30 I3
12V
1E25
2E44
3 470R 6 470R
IE70 E7
3EB9-4
470R
3E63-2 2EA5 B7 6E31 I11 IE89 D7
12V
CDS4C12GTA
100p
1E24
2 3EB9-2 7
RES 6E32
2 7 2EB1 D6 6E32 I3 IE90 D7
100R 470R
CDS4C12GTA
RES 2E78
RES 6E31
3E63-3 3 3EB9-3 6
2EB3 E7 6E34 E11 IE91 G6
CVBS-OUT-SC1
RES 3 6 3E07-1 C3 6E35 F11 IE92 G7
I 3E49 100R 470R I
3E11-2 1X02 3E07-2 H13 6E36 G11 IE93 H7
68R REF EMC HOLE
12V
100p
1E23
2 7 3E07-3 H13 6E37 H11 IE94 H6
1K0
3E11-3 3E07-4 B3 7E01-1 A6 IE96 G6
CDS4C12GTA
RES 2E76
RES 6E30
3 1K0 6 3E11-1 B11 7E01-2 B6 IEC0 A7
3E11-2 I13 7E04 H6 IEC1 A6
3E11-3 I13 7E05 G6 IEC2 B7
3E11-4 C11
1 2 3 4 5 6 7 8 9 10 11 12 13
2 2010-02-01
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 139
Analogue Externals B
Analogue Externals B
B04B B04B
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1E03 B3
1E04 C3
1E07 A12
1E08-1 B3
1E08-2 E3
1E08-3 D3
1E09 F3
1E28 B4
A A 1E29 D4
1E37 F4
1E38 G4
SPDIF out 1E39 C4
YPBPR 1E42 E4
1E07 1E43 B4
FE54 IE71 3E87 IE72 IE15 5E06 FE59 CON_JACK
YKC21-5598 EU 9E29 AV3-Y SPDIF-OUT 1E44 B11
1E08-1 2 1 1E75 I4
18R 30R
YPBPR1-SYNCIN1 1E76 I5
1 2 YKB11-0946V
1E77 I5
10p
12V
12V
YELLOW
100p
2E27
1E43
2E22
1E44
3E88 IE73 FE41
AP 9E04 AV2-CVBS 1E78 I6
CDS4C12GTA
RES 6E46
1E79 I7
RES 6E40
B 27R B
CDS4C12GTA
1ECB H3
FE51 EU IE74 3E89 IE75 2E20 I5
MTJ-032-21B-41 NI FE 9E57 AV3-PB
1E03 2 2E21 I5
18R
YPBPR1-PB 2E22 B11
1
2E23 I6
12V
100p
2E67
1E28
2E25 I6
CDS4C12GTA
RES 6E51
2E26 I7
2E27 B4
FE48 EU 9E58 IE76 3E90 IE77 2E35 F6
MTJ-032-21B-41 NI FE AV3-PR
1E04 2
18R
2E36 F4
C YPBPR1-PR C 2E37 G4
1
2E38 G6
100p
2E68
12V
1E39
FE42
2E39 D4
CDS4C12GTA
2E40 E4
RES 6E52
2E67 B4
2E68 C4
2E71 E5
YPBPR AUDIO 2E72 D5
3E20 G5
3E21 F5
YKC21-5598 3E97 3E36 H7
AUDIO-IN3-R
6 3E38 H8
D 1E08-3 FE50 1K0 IE31 D
5 3E41 H8
12V
RED 3E54 H5
100p
100p
2E39
1E29
2E72
FE43 3E55 H5
CDS4C12GTA
RES 6E06
3E56 H6
3E57 H7
FE49 3E96 IE29
YKC21-5598 AUDIO-IN3-L 3E58 H6
1E08-2 4 3E87 B6
1K0
3
3E88 B6
12V
WHITE 3E89 B6
100p
100p
2E40
1E42
2E71
3E90 C6
CDS4C12GTA
E E 3E96 E5
RES 6E38
3E97 D5
5E06 B10
6E06 D5
6E15 I7
VGA ( OR DVI ) AUDIO 6E16 I8
6E17 I8
6E18 I8
YKB21-5157V FE02 IE09 6E19 F5
3E21
AUDIO-IN4-L
2 6E20 G5
1K0
3 6E38 E5
F 1E09 1 F 6E40 B5
1n0
12V
100p
2E36
1E37
6E19
2E35
V_NOM
6E46 B11
CDS4C12GTA
6E51 B4
6E52 C4
FE01 9E04 B5
9E29 B5
IE10 9E57 B5
FE03 3E20
AUDIO-IN4-R 9E58 C5
1K0 FE01 F4
FE02 F5
1n0
12V
100p
2E37
1E38
6E20
2E38
FE03 G5
V_NOM
G G FE41 B12
CDS4C12GTA
FE42 C4
FE43 D4
FE44 I4
FE45 I4
FE46 I5
FE47 I5
FE48 C4
FE49 E4
FE50 D4
IE36 RXD2-MIPS FE51 B4
H 3E54 100R 3E38 100R 3D-VS H FE52 I6
3E55 100R IE35 TXD2-MIPS
3E56 100R IE34 3E41 100R 3D-LR
FE53 H6
1ECB 3E58 +5V
3E57 100R 3E36 100R FE54 B4
1481-702-06S-51
+T 0R4 FE59 B11
6
5 IE09 F6
FE53
4
9
FE52
IE10 G6
FE47 IE15 B10
8
3 FE44
100p
1E79
2E26
6E15
6E16
6E17
6E18
2
IE29 E6
100p
1E78
2E25
BZX384-C5V1
BZX384-C5V1
BZX384-C5V1
BZX384-C5V1
1 IE31 D6
7
100p
1E77
2E23
FE46
FE45
IE34 H7
IE35 H8
100p
1E76
2E21
I I IE36 H8
100p
1E75
2E20
IE71 B6
IE72 B7
IE73 B7
IE74 B6
IE75 B7
IE76 C6
IE77 C7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 140
Ethernet + Service
Ethernet + Service
B04C B04C
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1E06 A13
1E70 B3
1E85 A11
1E86 A11
5E08 IE07
+3V3 +3V3-ET-ANA 1N00 G7
30R 2E48 B5
IE49 3E53-1
8 1 FE56
TXD1-MIPS 2 3E53-2 7 2E49 B5
100n
100n
2E62
2E63
2E66
A 47R 47R 1E06
A
10u
IE50 3E53-3 FE57 UART 2E52 B3
RXD1-MIPS 4 3E53-4 5 6 3 2
3 SERVICE 2E53 B4
+3V3-ET-ANA +3V3 47R 47R 1 CONNECTOR 2E54 B3
YKB21-5157V
6E43
6E44
1E85
1E86
FE58 2E55 B3
IE32 IE38 IE06
BZX384-C5V1
2E56 H2
BZX384-C5V1
3E30 IE33 2E57 H2
1M0 2E58 H3
10u
4n7
100n
100n
2E52
2E53
2E48
2E49
+3V3 1E70 2E59 H4
NX3225GA
B B 2E60 H5
25M 2E62 A3
7E10-1 2E63 A3
10p
10p
6
27
1
12
LAN8710A-EZK
2E54
CR 1A 2A IO 2E66 A3
10K
10K
10K
2E55
3E66 RES
3E67 RES
3E33
VDD
CLKIN 3E22-1 F2
5
1
4 XTAL 31 ETH-RXP 3E22-2 F3
2 P
RX 30 ETH-RXN
IE26 N
RESET-ETHERNETn 19 3E22-3 F2
RST
29 ETH-TXP
P 3E22-4 F2
ETH-RXD(0) 11 TX 28 ETH-TXN
0 N
ETH-RXD(1) 10 MODE 3E26 F5
1
C ETH-RXD(2) 9 20 ETH-TXCLK C
RMIISEL TXCLK
ETH-RXD(3) 8 3E30 B3
PHYAD2
3E69 10K 26 ETH-RXDV
RXD<0:3> RXDV 3E33 B2
3E70 RES
IE63
ETH-COL RES 10K 15 13 ETH-RXER 3E34 D6
COL RXER 3E64 10K
9E43 3E71 10K +3V3
CRS_DV RXD4 3E35 D6
RES MODE2 0 IE64 RES
PHYAD 7 ETH-RXCLK
1 3E65 10K 3E40 D5
ETH-TXEN 21 +3V3
TXEN RXCLK
RES 3E51 E1
ETH-TXD(0) 22 3 ETH-REGOFF
0 REGOFF 3E68 10K 3E53-1 A10
ETH-TXD(1) 23 10K 3E34 +3V3
1 1
ETH-TXD(2) 24 LED 2 RES ETH-INTSEL
2 TXD 2 3E53-2 A9
ETH-TXD(3) 25 10K 3E72 3E35 10K +3V3
3 INTSEL
D ETH-TXER 18 RES D 3E53-3 A10
4
14 9E42 ETH-CRS
INT CRS 3E53-4 A9
TXER
32
RBIAS 3E64 C6
ETH-MDC 17 IE39
MDC
1%
ETH-MDIO 16 3E65 D6
MDIO
3E40
12K1
3E51 1K5 +3V3 VSS 3E66 B2
33
3E67 B2
7E10-2 3E68 D6
LAN8710A-EZK
34 VIA 36 3E69 C2
35 37 3E70 C1
E E
3E71 C3
3E72 D6
3E95-1 F3
3E95-2 F3
3E95-3 F4
3E95-4 F4
+3V3-ET-ANA 3E98 F5
5E08 A3
F F 6E43 A9
6E44 A10
6E47 G2
22R
22R
3E98
3E26
6E48 G3
3E95-1
3E95-2
3E95-3
3E22-2
3E22-3
3E22-4
3E95-4
CONFIGURATION RESISTOR SETTINGS
8 100R 1
7 100R 2
6 100R 3
5 100R 4
3 100R 6
4 100R 5
1 100R 8
2 100R 7
6E49 G4
RES 3E22-1
RES
RES
RES
6E47
6E48
6E49
6E50
6E50 G5
7E10-1 B4
Resistor POP EMPTY 7E10-2 E4
NUP1301ML3
NUP1301ML3
NUP1301ML3
NUP1301ML3
ETHERNET CONNECTOR
G G 9E42 D5
9E43 C3
1N00
ETH-TXP FE27
FE27 G6
1 3E64 (RES) PHYADD(0) = 1 PHYADD(0) = 0
ETH-TXN FE28 FE28 G6
2
ETH-RXP FE29
3 FE29 G6
FE30 3E65 (RES) PHYADD(1) = 1
4 PHYADD(1) = 0
5 FE30 G6
ETH-RXN FE31
6
7 3E66 (RES) PHYADD(2) = 1 PHYADD(2) = 0 FE31 H6
8 FE32 I5
3E67 (RES) RMII mode selected MII mode selected FE33 I5
15p
15p
15p
15p
22n
2E58
2E59
2E60
1551151-1
H FE34
H FE34 H6
RES 2E56
RES 2E57
RES
RES
3E68 (RES) Internal 1.2V reg. disabled Internal 1.2V reg. enabled FE56 A11
FE57 A11
3E69 (RES) MODE(0) = 0 MODE(0) = 1 FE58 B11
IE06 B4
3E70 (RES) MODE(1) = 0 MODE(1) = 1
IE07 A3
3E71 (RES) MODE(2) = 0 MODE(2) = 1 IE26 C2
FE32 IE32 B3
3E72 INTERRUPT FUNCTION INTERRUPT FUNCTION IE33 B3
I ETH-INTSEL I IE38 B4
DISABLED ON ENABLED ON
ETH-REGOFF IE39 D5
FE33 nINT/TXER/TXD4 SIGNAL nINT/TXER/TXD4 SIGNAL
IE49 A10
IE50 A9
IE63 C6
IE64 D6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 141
HDMI
HDMI
B04D B04D
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1P02 E2
1P03 C2
1P04 A2
I2C Address 2EC0 A9
5EC0 FEC0 FEC3 MICOM-VCC33 2EC1 A8
SII9187A = 0xB2 2EC2 A10
+3V3 30R
HDMI CONNECTOR 3 2EC3 B10
10u
1u0
10K
3ECH
100n
1P04
2EC0
2EC2
2ECV
2EC6 B9
1 ARX2+
A A 2EC7 B9
220u 16V
RES 2EC1
2 FECB
3 ARX2- 2EC8 B9
4 ARX1+
2ECC G8
5 RES
6 ARX1- AIN-5V FEC7 5EC3 +3V3
2ECM B8
7 ARX0+ +3V3-HDMI 2ECN D8
8 30R 2ECP E8
9 ARX0-
10u
100n
100n
100n
100n
2EC6
2EC7
2EC8
2EC3
10 ARXC+ 2ECQ F8
11 2ECU I3
RES 2ECW
12 ARXC-
47K
13 PCEC-HDMI 2ECV A9
3 3EC1-3 6
14 7EC1
2ECW B10
9
27
64
37
38
FEC1 ARX-DDC-SCL ARX-DDC-SCL SII9287B
B 15 B
16 FEC2 ARX-DDC-SDA ARX-DDC-SDA VCC33 3E23 F4
17 ARX-HOTPLUG +5V-EDID 3EC1-1 B4
FEC4 1 8 31
AIN-5V
8
6
18 3ECM-4 IE42 (CBUS) HPD0
SBVCC33
19 FEC5 ARX-HOTPLUG AIN-5V
4 5 3ECN-1 100K 32
R0PWR5V
3EC1-3 B4
47K
FEC6 21 20 10R 3EC3 E10
10K
10K
1u0 2ECM 29
MICOM_VCC33
8 3EC1-1 1
23 22 ARX-DDC-SDA DSDA0
3ECP-1
3ECP-3
30 49 3EC5 E10
1
3
ARX-DDC-SCL DSCL0 R4PWR5V
3ECA-1 D4
ARXC- 65 48 VGA-SCL-EDID-HDMI
N DSCL4 3ECA-2 D4
ARXC+ 66 R0XC 47 VGA-SDA-EDID-HDMI
AIN-5V P DSDA4
HDMI CONNECTOR 2 3ECA-3 F4
1P03 ARX0- 67 51 9EC2 CEC-HDMI
N CEC_D 3ECA-4 F4
BRX2+ ARX0+ 68 R0X0 RES
1 P
C 2 C 3ECD G3
BRX2- ARX1- 69
3
70
N
R0X1
3ECE H3
4 BRX1+ ARX1+ P 3ECF I3
5
BRX1- ARX2- 71 3ECG I3
6 BIN-5V N
BRX0+ ARX2+ 72 R0X2
7 P 3ECH A10
BRX-HOTPLUG 57 HDMIA-RX2-
8 N
BRX0- 2 7 35 TX2 56 HDMIA-RX2+ 3ECJ D10
9 IE43 (CBUS) HPD1 P
BRXC+ 3 3ECM-3 6 3ECN-2 100K 36
10 BIN-5V R1PWR5V 3ECK D11
10R 59 HDMIA-RX1-
11 N
BRXC- BRX-DDC-SDA 1u0 2ECN 33 TX1 58 HDMIA-RX1+ 3ECL E11
12 DSDA1 P
PCEC-HDMI BRX-DDC-SCL 34
47K
13 DSCL1 3ECM-1 F8
61
7 3ECA-2 2
14 N HDMIA-RX0-
15
FECC BRX-DDC-SCL BRX-DDC-SCL BRXC- 1
N
TX0
P
60 HDMIA-RX0+ 3ECM-2 E8
FECD BRX-DDC-SDA BRX-DDC-SDA BRXC+ 2 R1XC 3ECM-3 D8
D 16 P D
63 HDMIA-RXC-
17 FECE N 3ECM-4 B8
BIN-5V BRX0- 3 TXC 62 HDMIA-RXC+
18 N P
19 FECF BRX-HOTPLUG BRX0+ 4 R1X0 3ECN-1 B8
FECG 21 P 3ECJ RES RES
20
47K
3ECK MICOM-VCC33 3ECN-2 D8
5 55 4K7
1 3ECA-1 8
23 22 BRX1- N TPWR_CI2CA
BRX1+ 6 R1X1 IE12 4K7 3ECN-3 E8
P
FECR 3ECN-4 F8
BRX2- 7 50 9EC3 PCEC-HDMI
N CEC_A
BRX2+ 8 R1X2 RES 3ECP-1 B10
BIN-5V P
CRX-HOTPLUG FECY 3ECP-3 B10
3 6 41 52 3ECL RES
IE44 (CBUS) HPD2 INT +3V3
HDMI CONNECTOR 1 2 3ECM-2 7 3ECN-3 100K 42 4K7
3ECU-2 I8
CIN-5V R2PWR5V
1P02 10R 3ECU-4 I8
CRX2+ CRX-DDC-SDA 1u0 2ECP 39
E 1 DSDA2 E 5EC0 A8
CRX-DDC-SCL 40
2 DSCL2
3 CRX2- 5EC2 F7
CRX1+ CRXC- 11
4 N 5EC3 A11
CRXC+ 12 R2XC 54 SCL-SSB
5 P CSCL
CRX1- 53 3EC3 100R SDA-SSB 6EC1 H3
6 CIN-5V CSDA
CRX0+ CRX0- 13 3EC5 100R
7 N 7E02 G3
CRX0+ 14 R2X0
8 P 7EC0 G3
CRX0- 10
9
CRXC+ CRX1- 15 RSVDL 28 7EC1 B9
10 N
CRX1+ 16 R2X1
11 P 9EC0 G4
12 CRXC-
FECJ PCEC-HDMI CRX2- 17
47K
13 N 9EC2 C11
FECA 18 R2X2
5 3ECA-4 4
14 ARC-eHDMI+ CRX2+ P
FECK CRX-DDC-SCL CRX-DDC-SCL DRX-HOTPLUG
9EC3 E11
F 15 F
FECL CRX-DDC-SDA CRX-DDC-SDA 4 5 45 FEC0 A9
16 IE45 (CBUS) HPD3
1 3ECM-1 8 3ECN-4 100K 46 74
17 DIN-5V R3PWR5V FEC1 B2
FECM CIN-5V 10R 75
18 1u0
FECP19 FECN CRX-HOTPLUG DRX-DDC-SDA 2ECQ 43 76 FEC2 B2
DSDA3
21 20 DRX-DDC-SCL 44 77
47K
DSCL3 FEC3 A10
78
3 3ECA-3 6
23 22 5EC2
3E23 +3V3-STANDBY 19 79 FEC4 B2
eHDMI+ DRXC- N
RES 22K DRXC+ 20 R3XC 80 FEC5 B2
30R P
7E02 81
RES FEC6 B2
BC847BW ARC-eHDMI+ DRX0- 21 VIA 82
CIN-5V N
DRX0+ 22 R3X0 83 FEC7 A10
P
84
DRX1- 23 85
FECA F3
N
10p
24 R3X1 86 FECB A10
2ECC
7EC0 DRX1+ P
G BC847BW IEC6 87
G FECC D2
3ECD 9EC0 25 88
PCEC-HDMI CEC-HDMI DRX2- N
100R IEC4 DRX2+ 26
P
R3X2 89 FECD D2
IEC5
FECE D2
EPAD FECF D2
73
FECG D2
IEC7 FECJ F2
FECW 7EC1 3ECN 3ECF FECK F2
FECL F2
22K
3ECE +3V3-STANDBY
NON-INSTAPORT 9187A 4X 3K3 3K3 FECM F2
H H FECN F2
INSTAPORT 9287B 4X 100K 100K FECP F2
6EC1
FECR E10
+5V +5V-VGA FECW H9
BAT54 FECY E10
FECZ I3
IE11
IE11 I3
IE65 +3V3 IE12 D10
DDCA-SDA 2 3ECU-2 7
4R7
3ECG IE42 B8
10K
IE66 IE43 D8
DDCA-SCL 4 3ECU-4 5
I 3ECF FECZ 2ECU I IE44 E8
10K
100K 1u0 IE45 F8
IE65 I7
IE66 I7
+5V-EDID IEC4 G3
IEC5 G3
IEC6 G4
IEC7 H3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2 2010-02-01
HDMI
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 142
Headphone
Headphone
B04E B04E
1 2 3 4 5 6 7 8 9
2EE0 C5
2EE1 D5
2EE2 E4
+3V3-STANDBY 2EE3 E2
A A 2EE4 E3
2EE5 D5
2EE6 E6
4 2EE7 E6
PUMD12
5 7EE0-2 3EE0-1 E3
A-PLOP
3 3EE0-3 F3
3EE0-4 E3
3EE1-1 C5
B B 3EE1-2 D8
6 A-STBY 3EE1-3 D8
FEE0
RESET-AUDIO 2 7EE0-1 3EE1-4 D5
PUMD12
1 3EE2-1 D7
3EE2-2 E7
3EE2-3 E7
3EE2-4 E7
C C 7EE0-1 B5
7EE0-2 B6
2EE0
7EE1 D4
47p
1
3EE1-1
8
FE35 E7
7
6
22K FE36 E7
3EE1-2
22K
22K
3EE1-3 FEE0 B4
3EE1-4
4 5
2
3
22K
IEE0 E2
2EE5 IEE1 E2
D 47p +3V3 D IEE2 E2
IEE3 E3
IEE4 E3
7EE1
100n
IEE5 F3
2EE1
TPA6111A2DGN 3EE2-1
8
1 8
VDD 33R
IEE6 E4
IEE0 IEE1 IEE3
Φ 2EE6 FE36
2EE3 3EE0-1 AMPLIFIER IEE7 3EE2-2 IEE7 E6
ADAC(3) 8 1 2 1 2 7 AMP1
1 1
IEE2 1u0 2EE4 10K 3EE0-4 IN- 4V 100u 33R IEE8 E6
ADAC(4) 5 4 6
2 VO
1u0 10K IEE4 2EE7 IEE8 3EE2-3 FE35
5 7 3 6 AMP2
E SHUTDOWN 2 E
2EE2 IEE6 4V 100u 33R
3 10
BYPASS 3EE2-4
VIA 11 4 5
1u0
GND GND_HS 33R
4
9
3EE0-3
A-PLOP 3 6
10K IEE5
F F
1 2 3 4 5 6 7 8 9
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 143
Analogue Externals A
B04A B04A
1 2 3 4 5 6 7 8 9 10 11 12 13
1E00 A4 3E16 D11 7E06-1 E7
RESET-AVPIP
1E01-1 D5 3E17 E10 7E06-2 E6
1E01-2 H5 3E18 E7 7E09-1 H2
AP-SCART-OUT-R 3E63-1 FE60 1E02 C13 3E19 E7 7E09-2 G10
FE70 IEC0 IE67 1 8 1E12 D4 3E24 C7 9E01 D6
3E37-4 3EA7-1 2EA4 100R
AP-SCART-OUT-R AUDIO-OUT-L
1E18 F4 3E25 C13 9E02 D7
A 4 100R 5 8 470R 1 1u0 16V A
FEA0 1E19 F4 3E31 E3 9E05 F5
12V
100p
100p
2E29
1E45
2E50
7E01-1 6 AP-SCART-OUT-L
1E22 H4 3E32 E3 9E06 G5
IEC1
CDS4C12GTA
12V
100p
100p
2E01
1E00
2E87
2 1E23 I4 3E37-1 C3 9E07 F5
RES 6E10
1E24 I11 3E37-2 G13
CDS4C12GTA
1
9E08 F5
RES 6E01
PUMH7 1E25 I4 3E37-3 H13 9E09 G5
AUDIO-IN2-R IE20 3E11-1 FE61
1 8
1E26 G11 3E37-4 A3 9E10 F5
3EA7-4 IEC2 2EA5 IE68 1K0
IE22 FE71 AUDIO-OUT-R 1E27 H11 3E39 H10 9E50 D1
3E07-4
AUDIO-IN1-R 5 470R 4 1u0 16V 1E31 B4 3E43 H2 9E51 D2
4 1K0 5 FEA1
12V
100p
100p
2E30
1E46
2E51
7E01-2 3 AP-SCART-OUT-R 1E45 A11 3E44 G2 9E52 E1
B FEC8 B 1E46 B11 3E45 G7 9E53 E2
CDS4C12GTA
5
RES 6E08
12V
100p
100p
2E06
1E31
2E88
1E47 C11 3E48 G7 9E54 F1
+3V3
4 3E49 I7
FE62 1E48 C11 9E55 F2
CDS4C12GTA
PUMH7 AP-SCART-OUT-L 3E63-4
RES 6E03
4 5 1E49 D11 3E52 H7 BEC0 D10
100R
1E52 F11 3E61 G11 BEC1 E10
3E37-1 FE72
10K
AP-SCART-OUT-L 3E25 1E53 C4 3E62 H2 BEC2 F10
12V
100p
100p
2E32
1E47
2E70
1 100R 8
3E24 1E54 D4 3E63-1 A11 BEC3 D2
A-PLOP
CDS4C12GTA
1E55 E4 3E63-2 I13 BEC5 F2
RES 6E12
2K2
1E56 E11 3E63-3 I13 FE55 D9
12V
100p
100p
2E10
1E53
2E90
AUDIO-IN2-L IE21 3E11-4
SCART2
C C 1E57 E11 3E63-4 B11 FE60 A12
CDS4C12GTA
4 5
RES 6E07
1K0 (AV2) 1EP2 F13 3E73 G10 FE61 B12
IE23 1E02 2E01 A3 3E74 D2 FE62 B12
3E07-1 * EU
AUDIO-IN1-L 2E04 D3 3E75 D2 FE63 D12
12V
100p
100p
2E31
1E48
2E82
1 1
1K0 8 2E06 B3 3E76 E2 FE64 D12
3E80 18R
CDS4C12GTA
+5V 2
RES 6E14
2E10 C3 3E77 E2 FE66 E12
AP
2E12 F4 FE67 E12
12V
3E78 F2
100p
100p
2E04
1E54
2E91
YPBPR1-PB 9E50 9E51 3E82 3
FE55 5E77 BEC0
AV4-PB 2E13 G11 3E79 F2 FE68 D12
3E74 18R
CDS4C12GTA
4
RES 6E09
SCART1 1u8 18R 2E14 F4 FE70 A5
1R0
3E80 D10
3EA2
150p
150p
2E89
2E92
(AV1) IE90 5 2E15 D4 3E82 D10 FE71 B5
IE53 BEC3
5E73 3E75
12V
100p
1E49
2E16
D AV1-B D
1u8 6
2E16 D12 3E83 E10 FE72 C5
18R 1E01-1
CDS4C12GTA
RES 6E24
RES FE68 2E17 E12 3E84 E10 FE73 E5
1 7
2E18 E4 3E85 F10 FE74 E5
1K0
* EU
12V
150p
150p
100p
100n
2E79
2E80
1E12
2E15
9E01
9E02
2EB1
3EA1
AV2-STATUS FE63
2 8 2E19 F12 3E86 F10 FE75 E5
IE89
CDS4C12GTA
IE05
RES 6E23
RES IE13 3E16 12K FE64 2E24 G2 3EA1 D6 FE76 G12
3 9
IE61 YPBPR2-SYNCIN2 2E29 A10 3EA2 D6 FE77 H12
4K7
12V
100p
3E17
1E56
2E33
4 4 7E06-2 2E99 10
* EU 12 2E30 B10 3EA7-1 A7 FE78 H12
1u0
39K
3E18 2
2EB3
3E31 3E83 18R FE66 11
CDS4C12GTA
IE18 5 5 11 2E31 C10
RES 6E02
AV1-STATUS 3EA7-2 H13 FE79 F13
1
5p6 10
6 7E06-1
12K FE73 9 2E32 C10 3EA7-3 I13 FE80 E4
6 3 BC847BPN(COL) IE70 5E80 5E78 12
2E81 IE59 CVBS-MON-OUT1 AV4-Y IE56 BEC1 3E84 8
E AP FE74
2
7 E 2E33 E12 3EA7-4 B7 FE81 F5
4K7
12V
100p
3E32
1E55
2E18
YPBPR1-SYNCIN1 9E52 9E53 7 13
2
IE60 2u2 10u 1u8 18R 6 2E41 H12 3EB1 E6 FE82 F5
1 3EB1 2 1
3E76 18R FE75 5
CDS4C12GTA
39p
18p
150p
FE83 G5
2E97
2E98
8 BC847BPN(COL) 14 2E44 I4 3EB3 E6
2E94
RES 6E22
820R 4
18K
12V
150p
100p
3E19
2E93
1E57
2E17
1
IE54 5E74 3E77 FE80 2
CDS4C12GTA
330R
AV1-G IE08 RES 1
3EB6-2 H13
9E08 10 16
1 3EB3 2
1u8 18R 2E70 C12 3EB6-3 I13 FEA0 A7
3E85 18R 1EP2
2E73 H7 FEA1 B7
150p
150p
2E83
2E84
11 17 3EB6-4 G6
12V
100p
6E26
1E18
2E14
IE14 IE57 5E79 BEC2 3E86 2E74 F7 3EB9-1 H6 FEC8 B13
9E07 12 AV4-PR 18
CDS4C12GTA
2E75 H4 IE05 D10
12V
3EB9-2 I13
100p
1E52
2E19
RES 18R
RES
AP 1u8
YPBPR1-PR 9E10 13 19 2E76 I4 3EB9-3 I13 IE08 E5
CDS4C12GTA
RES 6E35
150p
9E54 9E55 IE16
2E96
F +5V F 2E77 G12 3EB9-4 I6 IE13 D6
150p
2E95
3E78 18R 9E05 14 20
IE55 5E76 3E79BEC5 FE81 2E78 I12 5E73 D2 IE14 F5
AV1-R 15 RES 21
+3V3 2E79 D1 5E74 E2 IE16 F5
1u8 18R FE82 FE79
16 2E80 D2 5E76 F2 IE17 G5
150p
150p
100n
2E85
2E86
2E74
MTJ-505H-01 NI LF 2E81 E7 IE18 E3
12V
5E77 D10
100p
1E19
2E12
9E09 17
IE17 IE96 IE91 2E82 C12 5E78 E10 IE20 B11
CDS4C12GTA
4K7
3E73
2E13
9E06 18 1 3EB6-1 8
RES 6E28
RES 2E83 F1 5E79 F10 IE21 C11
100n 16V
FE83 470R
19 IE92 IE51 2E84 F2 5E80 E8 IE22 B3
7E05 3E45
CVBS-OUT-SC1 AV2-BLK 3
+3V3 FE84 BC847BW 2E85 F1 6E01 A3 IE23 C3
20 68R
5
* EU
G 7E09-2 5 G 2E86 F2 6E02 E11 IE48 G2
21 PUMH7
3EB6-4 FE76 2E87 A4 6E03 B3 IE51 G10
470R
4
4K7
100n
3E44
2E24
4
FE85 2E88 B4 6E07 C3 IE52 H2
12V
75R
100p
3E61
1E26
2E90 C4 6E09 D3
RES 6E36
IE48 IE54 E1
AV1-BLK 6 68R 2 100R 7
1E01-2 2E91 D4 6E10 A11 IE55 F1
2 MT 3E37-3 2E92 D10
7E09-1 6E12 C11 IE56 E9
PUMH7 23 22 +5V
IE62 3 6
3E39 FE78 100R 2E93 E10 6E14 C11 IE57 F9
1 AV2-CVBS
MRC-021V-29 PC 3E07-2 2E94 E9 6E22 E3 IE59 E8
27R
12V
75R
100p
3E43
1E22
2 1K0 7 2E95 F10 6E23 D3 IE60 E6
H 3E07-3 H
CDS4C12GTA
12V
2E73
RES 6E29
100n
100p
RES 2E75
2E96 F9
1E27
2E41
RES 6E37
IE52 1 8
3E62 3EA7-2 2 3EB6-2 7 2E98 E8 6E28 F3 IE67 A8
AV1-CVBS 470R
27R 7E04 IE93 3E52 FE77 2 470R 7 470R 2E99 E8 6E29 H3 IE68 B8
BC847BW
5
3EA7-3 3EB6-3 2EA4 A7 6E30 I3 IE70 E7
68R 3 6
100p
12V
1E25
2E44
3EB9-4
3 470R 6 470R 2EA5 B7 6E31 I11 IE89 D7
470R
3E63-2
12V
2EB1 D6
CDS4C12GTA
6E32 I3
100p
IE90 D7
1E24
2 3EB9-2 7
RES 6E32
2 7 2EB3 E7 6E34 E11
100R 470R IE91 G6
CDS4C12GTA
RES 2E78
RES 6E31
12V
100p
1E23
2 7 3E07-4 B3 7E01-1 A6 IE96 G6
1K0
3E11-3 3E11-1 B11
CDS4C12GTA
7E01-2 B6 IEC0 A7
RES 2E76
RES 6E30
3 1K0 6 3E11-2 I13 7E04 H6 IEC1 A6
3E11-3 I13 7E05 G6 IEC2 B7
3E11-4 C11
1 2 3 4 5 6 7 8 9 10 11 12 13
3 2010-03-05
2 2010-02-01
CLASS D
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 144
Analogue Externals B
Analogue Externals B
B04B B04B
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1E03 B3
1E04 C3
1E07 A12
1E08-1 B3
1E08-2 E3
1E08-3 D3
1E09 F3
1E28 B4
A A 1E29 D4
1E37 F4
1E38 G4
SPDIF out 1E39 C4
YPBPR 1E42 E4
1E07 1E43 B4
FE54 IE71 3E87 IE72 IE15 5E06 FE59 CON_JACK
YKC21-5598 EU 9E29 AV3-Y SPDIF-OUT
1E44 B11
1E08-1 2 1 1E75 I4
18R 30R
YPBPR1-SYNCIN1 1E76 I5
1 2 YKB11-0946V
1E77 I5
10p
12V
12V
YELLOW
100p
2E27
1E43
2E22
1E44
3E88 IE73 FE41
AP 9E04 AV2-CVBS 1E78 I6
CDS4C12GTA
RES 6E46
1E79 I7
RES 6E40
B 27R B
CDS4C12GTA
1ECB H3
FE51 EU IE74 3E89 IE75 2E20 I5
MTJ-032-21B-41 NI FE 9E57 AV3-PB
1E03 2
18R
2E21 I5
YPBPR1-PB 2E22 B11
1
2E23 I6
12V
100p
2E67
1E28
2E25 I6
CDS4C12GTA
2E26 I7
RES 6E51
2E27 B4
FE48 EU 9E58 IE76 3E90 IE77 2E35 F6
MTJ-032-21B-41 NI FE AV3-PR
1E04 2 2E36 F4
18R
C YPBPR1-PR C 2E37 G4
1
2E38 G6
100p
2E68
12V
1E39
FE42
2E39 D4
CDS4C12GTA
2E40 E4
RES 6E52
2E67 B4
2E68 C4
2E71 E5
YPBPR AUDIO 2E72 D5
3E20 G5
3E21 F5
YKC21-5598 3E97 3E36 H7
AUDIO-IN3-R
6 3E38 H8
D 1E08-3 FE50 1K0 IE31 D
5
3E41 H8
12V
RED 3E54 H5
100p
100p
2E39
1E29
2E72
FE43 3E55 H5
CDS4C12GTA
RES 6E06
3E56 H6
3E57 H7
FE49 3E96 IE29
YKC21-5598 AUDIO-IN3-L 3E58 H6
1E08-2 4 3E87 B6
1K0
3
3E88 B6
3E89 B6
12V
WHITE
100p
100p
2E40
1E42
2E71
3E90 C6
CDS4C12GTA
E E 3E96 E5
RES 6E38
3E97 D5
5E06 B10
6E06 D5
6E15 I7
VGA ( OR DVI ) AUDIO 6E16 I8
6E17 I8
6E18 I8
YKB21-5157V FE02 IE09 6E19 F5
3E21
AUDIO-IN4-L
2 6E20 G5
1K0
3 6E38 E5
F 1E09 1 F 6E40 B5
1n0
12V
100p
2E36
1E37
6E19
2E35
V_NOM
6E46 B11
CDS4C12GTA
6E51 B4
6E52 C4
FE01 9E04 B5
9E29 B5
IE10 9E57 B5
FE03 3E20
AUDIO-IN4-R 9E58 C5
1K0 FE01 F4
FE02 F5
1n0
12V
100p
2E37
1E38
6E20
2E38
FE03 G5
V_NOM
G G FE41 B12
CDS4C12GTA
FE42 C4
FE43 D4
FE44 I4
FE45 I4
FE46 I5
FE47 I5
FE48 C4
FE49 E4
FE50 D4
IE36 RXD2-MIPS FE51 B4
H 3E54 100R 3E38 100R 3D-VS H FE52 I6
3E55 100R IE35 TXD2-MIPS
3E56 100R IE34 3E41 100R 3D-LR
FE53 H6
1ECB 3E58 +5V
3E57 100R 3E36 100R FE54 B4
1481-702-06S-51
+T 0R4 FE59 B11
6
5 IE09 F6
FE53
4
9
FE52
IE10 G6
FE47 IE15 B10
8
3 FE44
100p
1E79
2E26
6E15
6E16
6E17
6E18
2
IE29 E6
100p
1E78
2E25
BZX384-C5V1
BZX384-C5V1
BZX384-C5V1
BZX384-C5V1
1 IE31 D6
7
100p
1E77
2E23
FE46
FE45
IE34 H7
IE35 H8
100p
1E76
2E21
I I IE36 H8
100p
1E75
2E20
IE71 B6
IE72 B7
IE73 B7
IE74 B6
IE75 B7
IE76 C6
IE77 C7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3 2010-03-05
2 2010-02-01
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 145
Ethernet + Service
Ethernet + Service
B04C B04C
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1E06 A13
1E70 B3
1E85 A11
1E86 A11
5E08 IE07
+3V3 +3V3-ET-ANA 1N00 G7
30R 2E48 B5
IE49 3E53-1
8 1 FE56
TXD1-MIPS 2 3E53-2 7 2E49 B5
100n
100n
2E62
2E63
2E66
A 47R 47R 1E06
A
10u
IE50 3E53-3 FE57 UART 2E52 B3
RXD1-MIPS 4 3E53-4 5 6 3 2
3 SERVICE 2E53 B4
+3V3-ET-ANA +3V3 47R 47R 1 CONNECTOR 2E54 B3
YKB21-5157V
6E43
6E44
1E85
1E86
FE58 2E55 B3
IE32 IE38 IE06
BZX384-C5V1
2E56 H2
BZX384-C5V1
3E30 IE33 2E57 H2
1M0 2E58 H3
10u
4n7
100n
100n
2E52
2E53
2E48
2E49
+3V3 1E70 2E59 H4
NX3225GA
B B 2E60 H5
25M 2E62 A3
7E10-1 2E63 A3
10p
10p
6
27
1
12
LAN8710A-EZK
2E54
CR 1A 2A IO 2E66 A3
10K
10K
10K
2E55
3E66 RES
3E67 RES
3E33
VDD
CLKIN 3E22-1 F2
5
1
4 XTAL 31 ETH-RXP
2 P 3E22-2 F3
RX 30 ETH-RXN
IE26 N
RESET-ETHERNETn 19 3E22-3 F2
RST
29 ETH-TXP
P 3E22-4 F2
ETH-RXD(0) 11 TX 28 ETH-TXN
0 N
ETH-RXD(1) 10 MODE
1 3E26 F5
C ETH-RXD(2) 9 20 ETH-TXCLK C
RMIISEL TXCLK
ETH-RXD(3) 8 3E30 B3
PHYAD2
3E69 10K 26 ETH-RXDV
RXD<0:3> RXDV 3E33 B2
3E70 RES
IE63
ETH-COL RES 10K 15 13 ETH-RXER 3E34 D6
COL RXER 3E64 10K
9E43 3E71 10K +3V3
CRS_DV RXD4
RES MODE2 0 IE64 RES
3E35 D6
PHYAD 7 ETH-RXCLK
1 3E65 10K 3E40 D5
ETH-TXEN 21 +3V3
TXEN RXCLK
RES 3E51 E1
ETH-TXD(0) 22 3 ETH-REGOFF
0 REGOFF 3E68 10K
ETH-TXD(1) 23 10K 3E34 +3V3
3E53-1 A10
1 1
ETH-TXD(2) 24 LED 2 RES ETH-INTSEL
2 TXD 2 3E53-2 A9
ETH-TXD(3) 25 10K 3E72 3E35 10K +3V3
3 INTSEL
D ETH-TXER 18 RES D 3E53-3 A10
4
14 9E42 ETH-CRS
INT CRS
TXER
3E53-4 A9
32
RBIAS 3E64 C6
ETH-MDC 17 IE39
MDC
1%
ETH-MDIO 16 3E65 D6
MDIO
3E40
12K1
3E51 1K5 +3V3 VSS 3E66 B2
33
3E67 B2
7E10-2 3E68 D6
LAN8710A-EZK
34 VIA 36 3E69 C2
35 37
E E 3E70 C1
3E71 C3
3E72 D6
3E95-1 F3
3E95-2 F3
3E95-3 F4
3E95-4 F4
+3V3-ET-ANA 3E98 F5
5E08 A3
F F 6E43 A9
6E44 A10
6E47 G2
22R
22R
3E98
3E26
3E95-1
3E95-2
3E95-3
3E22-2
6E48 G3
3E22-3
3E22-4
3E95-4
CONFIGURATION RESISTOR SETTINGS
8 100R 1
7 100R 2
6 100R 3
5 100R 4
3 100R 6
4 100R 5
1 100R 8
2 100R 7
6E49 G4
RES 3E22-1
RES
RES
RES
6E47
6E48
6E49
6E50
6E50 G5
7E10-1 B4
Resistor POP EMPTY 7E10-2 E4
NUP1301ML3
NUP1301ML3
NUP1301ML3
NUP1301ML3
ETHERNET CONNECTOR
G G 9E42 D5
9E43 C3
1N00
ETH-TXP FE27 3E64 (RES) PHYADD(0) = 1 PHYADD(0) = 0
FE27 G6
1
ETH-TXN FE28
2 FE28 G6
ETH-RXP FE29
3
FE30 3E65 (RES) PHYADD(1) = 1 FE29 G6
4 PHYADD(1) = 0
5 FE30 G6
ETH-RXN FE31
6
7 3E66 (RES) PHYADD(2) = 1 PHYADD(2) = 0 FE31 H6
8
FE32 I5
3E67 (RES) RMII mode selected MII mode selected
15p
15p
15p
15p
22n
FE33 I5
2E58
2E59
2E60
1551151-1
H FE34
H FE34 H6
RES 2E56
RES 2E57
RES
RES
3E68 (RES) Internal 1.2V reg. disabled Internal 1.2V reg. enabled FE56 A11
FE57 A11
3E69 (RES) MODE(0) = 0 MODE(0) = 1
FE58 B11
3E70 (RES) MODE(1) = 0 MODE(1) = 1 IE06 B4
IE07 A3
3E71 (RES) MODE(2) = 0 MODE(2) = 1 IE26 C2
FE32 IE32 B3
I 3E72 INTERRUPT FUNCTION INTERRUPT FUNCTION I IE33 B3
ETH-INTSEL
DISABLED ON ENABLED ON IE38 B4
ETH-REGOFF
FE33 nINT/TXER/TXD4 SIGNAL nINT/TXER/TXD4 SIGNAL IE39 D5
IE49 A10
IE50 A9
IE63 C6
IE64 D6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3 2010-03-05
2 2010-02-01
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 146
HDMI
HDMI
B04D B04D
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1P02 E2
1P03 C2
1P04 A2
I2C Address 2EC0 A9
2EC1 A8
5EC0 FEC0 FEC3 MICOM-VCC33
SII9187A = 0xB2 2EC2 A10
+3V3 30R 2EC3 B10
HDMI CONNECTOR 3
10u
1u0
10K
3ECH 2EC6 B9
100n
1P04
2EC0
2EC2
2ECV
1 ARX2+ 2EC7 B9
A A
220u 16V
RES 2EC1
2 FECB 2EC8 B9
3 ARX2-
4 ARX1+ 2ECC G8
5 RES 2ECM B8
6 ARX1- AIN-5V FEC7 5EC3 +3V3
7 ARX0+ +3V3-HDMI 2ECN D8
8 30R 2ECP E8
9 ARX0-
10u
100n
100n
100n
100n
2ECQ F8
2EC6
2EC7
2EC8
2EC3
10 ARXC+
11 2ECU I3
RES 2ECW
12 ARXC-
2ECV A9
47K
13 PCEC-HDMI
3 3EC1-3 6
14 7EC1 2ECW B10
9
27
64
37
38
FEC1 ARX-DDC-SCL ARX-DDC-SCL SII9287B
B 15 B 3E23 F4
16 FEC2 ARX-DDC-SDA ARX-DDC-SDA VCC33
17 ARX-HOTPLUG +5V-EDID 3EC1-1 B4
FEC4 1 8 31
AIN-5V
8
6
18 3ECM-4 IE42 (CBUS) HPD0 3EC1-3 B4
SBVCC33
19 FEC5 ARX-HOTPLUG 4 5 3ECN-1 100K 32
AIN-5V R0PWR5V
47K
FEC6 21 20 10R 3EC3 E10
10K
10K
1u0 2ECM 29
MICOM_VCC33
8 3EC1-1 1
23 22 ARX-DDC-SDA DSDA0
3ECP-1
3ECP-3
30 49
3EC5 E10
1
3
ARX-DDC-SCL DSCL0 R4PWR5V
3ECA-1 D4
ARXC- 65 48 VGA-SCL-EDID-HDMI 3ECA-2 D4
N DSCL4
ARXC+ 66 R0XC 47 VGA-SDA-EDID-HDMI
AIN-5V P DSDA4 3ECA-3 F4
HDMI CONNECTOR 2
1P03 ARX0- 67 51 9EC2 CEC-HDMI 3ECA-4 F4
N CEC_D
BRX2+ ARX0+ 68 R0X0 RES
1 P 3ECD G3
C 2 C
BRX2- ARX1- 69 3ECE H3
3 N
BRX1+ ARX1+ 70 R0X1
4 P 3ECF I3
5
BRX1- ARX2- 71 3ECG I3
6 BIN-5V N
BRX0+ ARX2+ 72 R0X2
7 P 3ECH A10
BRX-HOTPLUG 57 HDMIA-RX2-
8 N
BRX0- 2 7 35 TX2 56 HDMIA-RX2+ 3ECJ D10
9 IE43 (CBUS) HPD1 P
BRXC+ 3 3ECM-3 6 3ECN-2 100K 36
10 BIN-5V R1PWR5V
59
3ECK D11
11 10R N HDMIA-RX1-
BRXC- BRX-DDC-SDA 1u0 2ECN 33 TX1 58 HDMIA-RX1+ 3ECL E11
12 DSDA1 P
PCEC-HDMI BRX-DDC-SCL 34
47K
13 DSCL1 3ECM-1 F8
61
7 3ECA-2 2
14 N HDMIA-RX0-
FECC BRX-DDC-SCL BRX-DDC-SCL BRXC- 1 TX0 60 HDMIA-RX0+
3ECM-2 E8
15 N P
FECD BRX-DDC-SDA BRX-DDC-SDA BRXC+ 2 R1XC 3ECM-3 D8
D 16 P D
63 HDMIA-RXC-
17 FECE N 3ECM-4 B8
BIN-5V BRX0- 3 TXC 62 HDMIA-RXC+
18 N P
19 FECF BRX-HOTPLUG BRX0+ 4 R1X0 3ECN-1 B8
FECG 21 P 3ECJ RES RES
20
47K
3ECK MICOM-VCC33 3ECN-2 D8
5 55 4K7
1 3ECA-1 8
23 22 BRX1- N TPWR_CI2CA
BRX1+ 6 R1X1 IE12 4K7
3ECN-3 E8
P
FECR 3ECN-4 F8
BRX2- 7 50 9EC3 PCEC-HDMI
N CEC_A 3ECP-1 B10
BRX2+ 8 R1X2 RES
BIN-5V P
CRX-HOTPLUG FECY 3ECP-3 B10
3 6 41 52 3ECL RES
IE44 (CBUS) HPD2 INT +3V3
HDMI CONNECTOR 1 2 3ECM-2 7 3ECN-3 100K 42 3ECU-2 I8
CIN-5V R2PWR5V 4K7
1P02 10R 3ECU-4 I8
CRX2+ CRX-DDC-SDA 1u0 2ECP 39
E 1 DSDA2 E 5EC0 A8
CRX-DDC-SCL 40
2 DSCL2
3 CRX2- 5EC2 F7
CRX1+ CRXC- 11
4 N 5EC3 A11
CRXC+ 12 R2XC 54 SCL-SSB
5 P CSCL
CRX1- 53 3EC3 100R SDA-SSB 6EC1 H3
6 CIN-5V CSDA
CRX0+ CRX0- 13 3EC5 100R
7 N 7E02 G3
CRX0+ 14 R2X0
8 P 7EC0 G3
CRX0- 10
9
CRXC+ CRX1- 15 RSVDL 28 7EC1 B9
10 N
CRX1+ 16 R2X1
11 P 9EC0 G4
12 CRXC-
FECJ PCEC-HDMI CRX2- 17
47K
13 N 9EC2 C11
FECA 18 R2X2
5 3ECA-4 4
14 ARC-eHDMI+ CRX2+ P
FECK CRX-DDC-SCL CRX-DDC-SCL DRX-HOTPLUG
9EC3 E11
F 15 F
FECL CRX-DDC-SDA CRX-DDC-SDA 4 5 45 FEC0 A9
16 IE45 (CBUS) HPD3
1 3ECM-1 8 3ECN-4 100K 46 74
17 DIN-5V R3PWR5V FEC1 B2
FECM CIN-5V 10R 75
18 1u0
FECP19 FECN CRX-HOTPLUG DRX-DDC-SDA 2ECQ 43 76 FEC2 B2
DSDA3
21 20 DRX-DDC-SCL 44 77
47K
DSCL3 FEC3 A10
78
3 3ECA-3 6
23 22 5EC2
3E23 +3V3-STANDBY 19 79 FEC4 B2
eHDMI+ DRXC- N
RES 22K DRXC+ 20 R3XC 80 FEC5 B2
30R P
7E02 81
RES FEC6 B2
BC847BW ARC-eHDMI+ DRX0- 21 VIA 82
CIN-5V N
DRX0+ 22 R3X0 83 FEC7 A10
P
84
DRX1- 23 85 FECA F3
N
10p
24 R3X1 86
2ECC
7EC0 DRX1+ P
FECB A10
G BC847BW IEC6 87
G
3ECD 9EC0 25 88
FECC D2
PCEC-HDMI CEC-HDMI DRX2- N
IEC4 DRX2+ 26 R3X2 89 FECD D2
100R IEC5 P
FECE D2
EPAD FECF D2
73
FECG D2
IEC7
FECJ F2
FECW 7EC1 3ECN 3ECF FECK F2
22K
3ECE +3V3-STANDBY
FECL F2
NON-INSTAPORT 9187A 4X 3K3 3K3 FECM F2
H H FECN F2
INSTAPORT 9287B 4X 100K 100K FECP F2
6EC1
FECR E10
+5V +5V-VGA
FECW H9
BAT54 FECY E10
IE11
FECZ I3
IE11 I3
IE65 +3V3 IE12 D10
DDCA-SDA 2 3ECU-2 7
4R7
3ECG IE42 B8
10K
IE66 4 3ECU-4 5
IE43 D8
3ECF 2ECU DDCA-SCL
I FECZ I IE44 E8
10K
100K 1u0 IE45 F8
IE65 I7
IE66 I7
+5V-EDID
IEC4 G3
IEC5 G3
IEC6 G4
IEC7 H3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3 2010-03-05
2 2010-02-01
HDMI
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 147
Headphone
Headphone
B04E B04E
1 2 3 4 5 6 7 8 9
2EE0 C5
2EE1 D5
2EE2 E4
+3V3-STANDBY 2EE3 E2
A A 2EE4 E3
2EE5 D5
2EE6 E6
4
PUMD12 2EE7 E6
5 7EE0-2
A-PLOP
3EE0-1 E3
3
3EE0-3 F3
3EE0-4 E3
B B 3EE1-1 C5
6 A-STBY
3EE1-2 D8
FEE0 3EE1-3 D8
RESET-AUDIO 2 7EE0-1
PUMD12
1
3EE1-4 D5
3EE2-1 D7
3EE2-2 E7
3EE2-3 E7
C C 3EE2-4 E7
2EE0
7EE0-1 B5
47p
7EE0-2 B6
3EE1-1
1 8 7EE1 D4
7
6
22K
FE35 E7
3EE1-2
22K
22K
3EE1-3
3EE1-4 FE36 E7
4 5
2
3
22K FEE0 B4
2EE5
IEE0 E2
D 47p +3V3 D
IEE1 E2
IEE2 E2
7EE1 IEE3 E3
100n
2EE1
TPA6111A2DGN 3EE2-1
8
1 8
VDD
IEE4 E3
Φ 33R
IEE0 2EE3 IEE1 IEE3 2EE6 IEE7 FE36 IEE5 F3
3EE0-1 AMPLIFIER 3EE2-2
ADAC(3) 8 1 2 1 2 7 AMP1
1 1
IEE2 1u0 2EE4 10K 3EE0-4 IN- 4V 100u 33R IEE6 E4
ADAC(4) 5 4 6
2 VO
1u0 10K IEE4 2EE7 IEE8 3EE2-3 FE35 IEE7 E6
5 7 3 6 AMP2
E SHUTDOWN 2 E
2EE2 IEE6
3 10
4V 100u 33R IEE8 E6
BYPASS 3EE2-4
VIA 11 4 5
1u0
GND GND_HS 33R
4
9
3EE0-3
A-PLOP 3 6
10K IEE5
F F
1 2 3 4 5 6 7 8 9
3 2010-03-05
2 2010-02-01
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 148
DDR
B05A B05A
1 2 3 4 5 6 7 8 9 10 11 12 13
2B00 A2 3B02-1 C7
2B01 A3 3B02-2 B6
2B02 A3 3B02-3 C7
+1V8 DDR2-VREF-DDR +1V8 DDR2-VREF-DDR
2B03 A3 3B02-4 B6
2B04 A3 3B03 D9
2B05 A3 3B04-1 C12
A A
2B06 A4 3B04-2 B13
2B07 A4 3B04-3 B12
100p
100n
2B08
2B36
2B08 A6 3B04-4 C12
47u
100n
100n
100n
100n
100n
100n
100n
100n
2B40
2B00
2B01
2B02
2B03
2B04
2B05
2B06
2B07
100n
100p
2B17
2B37
47u
100n
100n
100n
100n
100n
100n
100n
100n
2B41
2B09
2B10
2B11
2B12
2B13
2B14
2B15
2B16
2B09 B8 3B05-1 C13
2B10 B8 3B05-2 C13
7B02
2B11 B9 3B05-3 B12
A1
E9
L1
H9
E1
A9
C1
C3
C7
C9
E2
EDE1108AGBG-1J-F 7B03
EDE1108AGBG-1J-F
A1
E9
L1
H9
E1
A9
C1
C3
C7
C9
E2
B VDD VDDL VDDQ VREF B 2B12 B9 3B05-4 C13
DDR2-A0 H8 VDDL VREF
0 VDD VDDQ 2B13 B9
AT T-POINT DDR2-A1 H3 DDR2-A0 H8 3B06 H3
1 Φ 3B00-2 0
DDR2-A2 H7 SDRAM C8 2 7 DDR2-D16 DDR2-A1 H3
3B22 2 0 1 Φ
DDR2-CLK_P DDR2-A3 J2 C23B02-4 4 5 33R DDR2-D17 DDR2-A2 H7 SDRAM C8 2 3B04-2 7 DDR2-D24 2B14 B9 3B07-1 G6
3 1 2 0
240R DDR2-A4 J8 D7 33R 3 6 3B00-3 DDR2-D18 DDR2-A3 J2 3B05-3
C2 3 6 33R DDR2-D25
4 2 3 1
DDR2-CLK_N DDR2-A5 J3 D33B02-2 2 7 33R DDR2-D19 DDR2-A4 J8 3B04-3
D7 3 6 33R DDR2-D26 2B15 B9 3B07-2 G7
5 3 4 2
DDR2-A6 J7 DQ D1 33R 1 8 3B02-1 DDR2-D20 DDR2-A5 J3 D3 33R 33R 2 7 3B05-2 DDR2-D27
3B27 6 A 4 5 3
DDR2-CLK_P DDR2-A7 K2 D93B00-4 4 5 33R DDR2-D21 DDR2-A6 J7 DQ D1 1 8 3B05-1 DDR2-D28 2B16 B10 3B07-3 G7
7 5 6 A 4 33R
240R DDR2-A8 K8 B1 33R 3 6 3B02-3 DDR2-D22 DDR2-A7 K2 D93B04-4 4 5 DDR2-D29
8 6 7 5
DDR2-CLK_N DDR2-A9 K3 B9 3B00-1 1 8 33R DDR2-D23 DDR2-A8 K8 B1 33R 4 5 3B05-4 DDR2-D30 2B17 A11 3B07-4 G6
9 7 8 6
DDR2-A10 H2 33R DDR2-A9 K3 B93B04-1 1 8 33R DDR2-D31
3B28 10 9 7
DDR2-CLK_P DDR2-A11 K7 DDR2-A10 H2 33R
11 10 2B18 F2 3B08-1 G7
DDR2-A12 L2 B7 3B12 DDR2-DQS2_P DDR2-A11 K7
240R 12 11
C DDR2-CLK_N DDR2-A13 L8 DQS A8 3B13 33R DDR2-DQS2_N DDR2-A12 L2 B7 3B14 DDR2-DQS3_P C
13 12 2B19 F3 3B08-2 G6
2B44 DDR2-A13 L8 DQS A8 3B15 33R DDR2-DQS3_N
33R 13
DDR2-BA0 G2 RES 2p2 2B45 RES 33R
0 2B20 F3 3B08-3 G7
DDR2-BA1 G3 A2 DDR2-BA0 G2 2p2
1 BA NU|RDQS 0
DDR2-BA2 G1 DDR2-BA1 G3 A2
2 1 BA NU|RDQS 2B21 F3 3B08-4 G6
DDR2-ODT DDR2-BA2 G1
2
3B01 RES F9 DDR2-ODT
ODT 2B22 F3
DDR2-CLK_P 240R E8 3B03 RES F9 3B09 H9
ODT
DDR2-CLK_N F8 CK DDR2-CLK_P 240R E8
DDR2-CKE F2 DDR2-CLK_N F8 CK 2B23 F3 3B10-1 G12
CKE
DDR2-CS G8 DDR2-CKE F2
CS CKE
DDR2-RAS F7 L3 DDR2-A14 DDR2-CS G8 2B24 F4 3B10-2 G13
RAS CS
DDR2-CAS G7 NC L7 DDR2-RAS F7 L3 DDR2-A14
CAS RAS
DDR2-WE F3 DDR2-CAS G7 NC L7 2B25 F4 3B10-3 G12
WE CAS
D DDR2-DQM2 3B23 B3 DDR2-WE F3 D
DM|RDQS WE
33R DDR2-DQM3 3B24 B3 2B26 F6 3B10-4 G12
VSS VSSQ DM|RDQS
VSSDL 33R VSS VSSDL VSSQ
J1
A3
E3
K9
E7
A7
B2
B8
D2
D8
2B27 F8 3B11-1 G12
J1
A3
E3
K9
E7
A7
B2
B8
D2
D8
2B28 F8 3B11-2 G13
2B29 F9 3B11-3 G12
2B30 F9 3B11-4 G13
2B31 F9 3B12 C7
E E 2B32 F9 3B13 C6
+1V8 +1V8 2B33 F9 3B14 C13
DDR2-VREF-DDR
2B34 F10 3B15 C12
DDR2-VREF-DDR
2B35 F11 3B16 H7
2B36 A6 3B17 H7
2B37 A11 3B18 H13
2B38 F6 3B19 H12
2B26
2B38
100n
100p
47u
100n
100n
100n
100n
100n
100n
100n
100n
2B42
2B18
2B19
2B20
2B21
2B22
2B23
2B24
2B25
F F
2B39
100p
2B35
100n
47u
2B39 F11 3B20 H1
100n
100n
100n
100n
100n
100n
100n
100n
2B43
2B27
2B28
2B29
2B30
2B31
2B32
2B33
2B34
2B40 A2 3B21 I1
2B41 B8 3B22 B1
7B00
A1
E9
L1
H9
E1
A9
C1
C3
C7
C9
E2
EDE1108AGBG-1J-F 7B01 2B42 F2 3B23 D3
EDE1108AGBG-1J-F
A1
E9
L1
H9
E1
A9
C1
C3
C7
C9
E2
VDDL VREF
VDD VDDQ
DDR2-A0 H8 VDD VDDL VDDQ VREF 2B43 F8 3B24 D9
0
DDR2-A1 H3 DDR2-A0 H8
1 Φ 0
DDR2-A2 H7 SDRAM C8 2 3B07-2 7 DDR2-D0 DDR2-A1 H3 2B44 C6 3B25 I3
2 0 1 Φ 3B10-2
DDR2-A3 J2 C23B08-4 4 5 33R DDR2-D1 DDR2-A2 H7 SDRAM C8 2 7 DDR2-D8
3 1 2 0
DDR2-A4 J8 D7 33R 3 6 3B07-3 DDR2-D3 DDR2-A3 J2 3B11-3 3
C2 6 33R DDR2-D9 2B45 C12 3B26 I9
4 2 3 1
G DDR2-A5 J3 D3 3B08-2 2 7 33R DDR2-D2 DDR2-A4 J8 3B10-3 33R 3
D7 6 33R DDR2-D10 G
5 3 4 2
DDR2-A6 J7 DQ D1 33R 1 8 3B08-1 DDR2-D4 DDR2-A5 J3 D3 2 7 3B11-2 DDR2-D11
6 A 4 33R 5 3 2B46 H6 3B27 C1
DDR2-A7 K2 D9 3B07-4 4 5 DDR2-D5 DDR2-A6 J7 DQ D1 1 8 33R DDR2-D12
7 5 6 A 4 33R
DDR2-A8 K8 B1 33R 3 6 3B08-3 DDR2-D6 DDR2-A7 K2 D93B10-4 4 5 3B11-1 DDR2-D13
8 6 7 5 2B47 H12 3B28 C1
DDR2-A9 K3 B9 3B07-1 1 8 33R DDR2-D7 DDR2-A8 K8 B1 33R 4 5 3B11-4 DDR2-D14
9 7 8 6
DDR2-A10 H2 33R DDR2-A9 K3 B93B10-1 1 8 33R DDR2-D15
10 9 7 3B00-1 C6 7B00 G4
DDR2-A11 K7 DDR2-A10 H2 33R
11 10
DDR2-A12 L2 B7 3B16 DDR2-DQS0_P DDR2-A11 K7
12 11 3B00-2 B7 7B01 G10
DDR2-A13 L8 DQS A8 3B17 33R DDR2-DQS0_N DDR2-A12 L2 B7 3B18 DDR2-DQS1_P
13 12
2B46 RES 33R DDR2-A13 L8 DQS A8 3B19 33R DDR2-DQS1_N
+1V8 13 3B00-3 B7
DDR2-BA0 G2 2p2 2B47 RES 33R
7B02 B4
0
DDR2-BA1 G3 A2 DDR2-BA0 G2 2p2
1 BA NU|RDQS 0
DDR2-BA2 G1 DDR2-BA1 G3 A2 3B00-4 C6 7B03 B10
2 1 BA NU|RDQS
DDR2-ODT DDR2-BA2 G1
2
H 3B06 RES F9 DDR2-ODT H 3B01 C3 FB00 H1
ODT
DDR2-CLK_P 240R E8 3B09 RES F9
ODT
DDR2-CLK_N F8 CK DDR2-CLK_P 240R E8
F2 F8 CK
3B20
DDR2-CKE CKE DDR2-CLK_N
180R 1%
DDR2-CS G8 DDR2-CKE F2
CS CKE
DDR2-RAS F7 L3 DDR2-A14 DDR2-CS G8
FB00 RAS CS
DDR2-CAS G7 NC L7 DDR2-RAS F7 L3 DDR2-A14
DDR2-VREF-DDR CAS RAS
DDR2-WE F3 DDR2-CAS G7 NC L7
WE CAS
DDR2-DQM0 3B25 B3 DDR2-WE F3
DM|RDQS WE
DDR2-DQM1 3B26 B3
33R VSS VSSQ DM|RDQS
VSSDL 33R VSS VSSQ
3B21
VSSDL
J1
A3
E3
K9
E7
A7
B2
B8
D2
D8
180R 1%
J1
A3
E3
K9
E7
A7
B2
B8
D2
D8
I I
1 2 3 4 5 6 7 8 9 10 11 12 13 5 2009-12-07
DDR 4
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 149
B 1G03 B
T 3.0A 32V
100n
2G43
5G02
30R RES
C C
22u
2G44
RES
3G28 IG11
6G00
2K2 LTST-C190KGKT
D D
E E
F F
1 2 3 4 5 6 7 8
2 2010-02-01
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 150
RES
RES
2G93 C4 FG1U F9
10K
3G34
2G94 D4 FG1V F9
8
7
6
5
FI-RE51S-HF
10p
10p
10p
10p
10p
10p
RES
RES
2G95 D4 FG1W F9
100p
100p
100p
100p
60 61
2G96 D4
10K
10K
C 3G33 3G35 58 59 C FG1Y D9
9G0K-1
9G0K-2
9G0K-3
9G0K-4
56 57
RES
RES
RES
RES
RES
RES
2G97 D4 FG1Z D9
RES
RES
1
2
3
4
2G77
2G75
2G76
2G78
2G79
2G24
2G25
2G26
2G27
2G7A
54 55
RES FG34
CTRL-DISP 3G32 52 53
RES FI-RE41S-HF SDA-DISP 100R 3G2W FG2H
51 2G98 D4 FG20 D9
10p 50 51 SCL-DISP 50
2G92 100R 3G2Y FG2G 2G99 D4 FG21 D9
RES 48 49 49
100R
10p 46 47 RES 3G2Z FG2K 48
2G93 3D-LR 3G2W C8 FG22 E9
FG2J 47
RES 44 45 BACKLIGHT-BOOST 100R 3G37 RES FG2R
10p 42 43 46
2G94 3D-VS-DISP 3G36 100R 3G2Y C8 FG23 E9
RES 45
FG30 41 100R RES 44
10p 2G95 FG31 CTRL-DISP FG04 3G30 FG2L 3G2Z D8 FG24 E9
40 43
FG32 CTRL-DISP 3G31 RES 100R
39 42 3G30 D9 FG25 E9
FG33 FG2M
RES 38 100R RES 41
D 37 PX1A- FG2E 40 D 3G31 D8 FG26 E9
10p 2G96 RES PX1A+ FG2F
RES 10p 36 39
2G99 PX1B- FG1Y 3G32 C8 FG27 E9
RES 10p 35 38
2G97 PX1B+ FG1Z
10p 34 37
2G98 PX1C- FG20 3G33 C9 FG28 E9
FG1C 33 36
PX3A- 32 PX1C+ FG21 35
PX3A+ FG1D 3G34 B9 FG29 E9
31 34
PX3B- FG1E PX1CLK- FG22
30 33 3G35 C9
PX3B+ FG1F 29 PX1CLK+ FG23 32
FG2A E9
PX3C- FG1G
28 FG24 31 3G36 D8 FG2B E9
PX3C+ FG1H PX1D-
27 30
PX1D+ FG25
FG11 26 29 3G37 D9 FG2C E9
PX3CLK- 25 PX1E- FG26 28
PX3CLK+ FG1J PX1E+ FG27
24 27 9G0G G11 FG2D F9
E FG1K
23 10p 2G28 26 E
PX3D- 22 25 9G0K-1 C4 FG2E D9
PX3D+ FG1L PX2A- FG28 10p 2G29
21 24
PX3E- FG1M PX2A+ FG29 9G0K-2 C4 FG2F D9
20 23
PX3E+ FG1N PX2B- FG2A
19 22
PX2B+ FG2B 9G0K-3 C4 FG2G C9
18 21
PX2C- FG2C
17 20
PX4A- FG12 PX2C+ FG2D 9G0K-4 C4 FG2H C9
16 19
PX4A+ FG13 15 FG1R 18
PX4B- FG14 PX2CLK-
FG04 D8 FG2J D5
14 17
PX4B+ FG15 13 PX2CLK+ FG1S 16
PX4C- FG16
FG11 E4 FG2K D9
12 15
PX4C+ FG17 PX2D- FG1T
11 14 FG12 F4 FG2L D10
10 PX2D+ FG1U 13
F PX4CLK- FG18 PX2E- FG1W F
9 12 FG13 F4 FG2M D10
PX4CLK+ FG19 8 PX2E+ FG1V 11
7 10 FG14 F4 FG2N G11
PX4D- FG1A
6 FG2P 9
PX4D+ FG1B FG15 F4 FG2P F11
5 8
PX4E- FG1Q
4 7
PX4E+ FG1P FG16 F4 FG2R D11
3 6
+VDISP RES 9G0G FG2N
2 5 FG17 F4 FG30 D5
1 4
3 FG18 F4 FG31 D5
1G50
2
1 FG19 F4 FG32 D5
TO DISPLAY 1G51 FG1A F4 FG33 D5
G G
TO DISPLAY FG1B F4 FG34 C11
1X05
EMC HOLE
H H
1 2 3 4 5 6 7 8 9 10 11 12
2 2010-02-01
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 151
AmbiLight CPLD
AmbiLight CPLD
B06C B06C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A A
DEBUG ONLY
5GA0 FGA0
+3V3 VINT
30R
1u0
100n
100n
2GA0
2GA1
2GA2
1G37
B +3V3 1 B
5GA1 2
FGA1 3GA5-4 4 5
+3V3 VIO GCK3 3
GTS1 3GA5-3 3 6 100R 4
30R
GTS2 3GA5-2 2 7 100R 5
GSR 3GA5-1 1 8 100R 6
1u0
100n
100R
2GA3
2GA5
SD51022
IGA1
CPLED2
C IGA2
C
CPLED3
15
35
26
XC9572XL-10VQG44C0100 3
VCCINT Φ VCCIO AMBI-SPI-CLK-OUT-R
PXCLK54 43 AMBI-SPI-SDI-OUT_G1-R GCK3 5 7GA1-2
IXO1_43|GCK1 BC847BS(COL)
GCK2 44 AMBI-SPI-SDO-OUT-R
IXO1_44|GCK2
GCK3 1 4
IXO1_1|GCK3
+3V3
2 5 PNX-SPI-CSBn
D IXO1_2 IXO3_5 D
PNX-SPI-CS-BLn 3 6 9GA1 BACKLIGHT-PWM 6
IXO1_3 IXO3_6
PNX-SPI-SDO 39 7 3D-LR
IXO1_39 IXO3_7
PNX-SPI-SDI 40 8 3D-VS-DISP GTS1 2 7GA1-1
IXO1_40 IXO3_8 BC847BS(COL)
PNX-SPI-CLK 41 IXO3_12 12 BL-SPI-SDO
IXO1_41
42 13 BL-SPI-SDI 1
IXO1_42 IXO3_13
14 BL-SPI-CSn +3V3
IXO3_14
GTS1 36 IXO3_16 16 3GA1 BACKLIGHT-PWM_BL-VS
IXO2_36|GTS1
GTS2 34 18 47R BL-SPI-CLK 3
IXO2_34|GTS2 IXO3_18
GSR 33
IXO2_33|GSR
AMBI-SPI-CS-OUTn_R2-R 19 3 6 AMBI-PROG_B1 GTS2 5 7GA2-2
IXO4_19 BC847BS(COL)
AMBI-PWM-CLK_B2 29 20 3G10-3 100R 2 7 AMBI-BLANK_R1
IXO2_29 IXO4_20
AMBI-SPI-CS-OUTn_R2 2 7 3G14 100R 30 21 1 8 3G10-2 100R AMBI-SPI-CS-EXTLAMPSn 4
IXO2_30 IXO4_21
AMBI-LATCH1_G2 3G11-2 100R 4 5 31 22 3G10-1 100R AMBI-SPI-CLK-OUT +3V3
IXO2_31 IXO4_22
AMBI-TEMP 3G11-4 100R 32 23 3G13 100R AMBI-SPI-SDI-OUT_G1
E IXO2_32 IXO4_23 E
CPLED3 37 27 3G12 10R 4 5 AMBI-SPI-SDO-OUT 6
IXO2_37 IXO4_27
CPLED2 38 28 8 1 3G10-4 100R AMBI-LATCH2_DIS
IXO2_38 IXO4_28
3G11-1 100R GSR 2 7GA2-1
11 BC847BS(COL)
TCK
9 1
RES
RES
TDI
24
TDO
10p
10p
10p
10p
10p
10p
10p
10p
10p
10p
10K
3G15 10
TMS
2G10
2G11 RES
2G12 RES
2G13
2G14 RES
2G15 RES
2G16 RES
2G17 RES
2G18 RES
2G19 RES
3GA6-4
3GA6-3
3GA6-2
3GA6-1
GND
5 330R 4
6 330R 3
7 330R 2
8 330R 1
+3V3
4
17
25
F F
6GA0
6GA1
6GA2
6GA3
LTST-C190KGKT
LTST-C190KGKT
LTST-C190KGKT
LTST-C190KGKT
DEBUG ONLY
1G36 1G35
1 1 3GA2-1 1 8 100R
2 2 3GA2-2 2 7 100R FGA6
3 3 3GA2-3 3 6 100R FGA4
4 4 3GA2-4 4 5 100R FGA5
5 5 FGA2 FGA3
6 6
+3V3
G 7 8 G
SD51022
2GA4
100n RES
BACKLIGHT-PWM 9GA0 BACKLIGHT-PWM_BL-VS
H H
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1G35 G2 2G10 F3 2G13 F7 2G16 F8 2G19 F9 2GA2 B4 2GA5 B3 3G10-3 E6 3G11-2 E3 3G13 E7 3GA1 E6 3GA2-3 G3 3GA5-2 B12 3GA6-1 F13 3GA6-4 F12 6GA0 F12 6GA3 F13 7GA1-2 D13 9GA0 H5 FGA1 B4 FGA4 G4 IGA0 C11 IGA3 C11
1G36 G2 2G11 F3 2G14 F8 2G17 F8 2GA0 B3 2GA3 B3 3G10-1 E6 3G10-4 E7 3G11-4 E4 3G14 E4 3GA2-1 G3 3GA2-4 G3 3GA5-3 B12 3GA6-2 F13 5GA0 A3 6GA1 F12 7GA0 D5 7GA2-1 E12 9GA1 D7 FGA2 G3 FGA5 G5 IGA1 C11
1G37 B13 2G12 F3 2G15 F8 2G18 F9 2GA1 B4 2GA4 G3 3G10-2 E7 3G11-1 E6 3G12 E6 3G15 E2 3GA2-2 G3 3GA5-1 B12 3GA5-4 B12 3GA6-3 F12 5GA1 B2 6GA2 F13 7GA1-1 D13 7GA2-2 E12 FGA0 A5 FGA3 G5 FGA6 G4 IGA2 C11
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 152
SPI-Buffer
SPI-Buffer
B06D B06D
2GE0 B2
1 2 3 4 5 6 3GE0-1 B4
3GE0-3 B4
3GE1-3 C3
3GE1-4 C4
3GE2 B4
3GE3 C4
3GE4 C3
7GE0 B3
7GE1 B4
A A 9GE0-2 C3
9GE0-3 D3
+3V3 9GE0-4 D3
+3V3 9GE1 D3
9GE2 D3
IGE0 B3
IGE1 D2
7GE1
10K
3GE2 PDTC114EU
100n
2GE0
7GE0 PNX-SPI-CSBn
20
74LVC245A
1
B 3EN1 B
3EN2 IGE0
19
G3
3GE0-3
PNX-SPI-CLK 18 2 3 6 BL-SPI-CLK
1
2 47R 3GE0-1
17 3 1 8 BL-SPI-SDO
PNX-SPI-SDO 16 4 3GE1-3 6 3 47R AMBI-SPI-CLK-OUT-R
15 5 47R RES 5 4 3GE1-4 AMBI-SPI-SDO-OUT-R
AMBI-SPI-SDI-OUT_G1-R 14 6 3GE3 47R RES PNX-SPI-SDI
BL-SPI-SDI 13 7 3GE4 47R RES
12 8 47R
11 9
10
C C
PNX-SPI-CLK 7 9GE0-2 2 BL-SPI-CLK
9GE2
D ∗ D
PNX-SPI-CS-BLn IGE1 5 9GE0-4
∗∗4 BL-SPI-CSn
Buffer
∗
E Direct E
∗∗
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 153
100n
2G43
5G02
30R RES
C C
22u
2G44
RES
3G28 IG11
6G00
2K2 LTST-C190KGKT
D D
E E
F F
1 2 3 4 5 6 7 8
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 154
RES
RES
2G79 C10 FG1R F9
10K
3G34
2G7A C10 FG1S F9
8
7
6
5
FI-RE51S-HF
10p
10p
10p
10p
10p
10p
RES
RES
100p
100p
100p
100p
60 61 2G92 C4 FG1T F9
10K
10K
C 3G33 3G35 58 59 C
9G0K-1
9G0K-2
9G0K-3
9G0K-4
56 57 2G93 C4 FG1U F9
RES
RES
RES
RES
RES
RES
RES
RES
1
2
3
4
2G77
2G75
2G76
2G78
2G79
2G24
2G25
2G26
2G27
2G7A
54 55
RES FG34
CTRL-DISP 3G32 52 53
RES FI-RE41S-HF SDA-DISP 100R 3G2W FG2H
51 2G94 D4 FG1V F9
10p 50 51 SCL-DISP 50
2G92 100R 3G2Y FG2G
RES 48 49 49 2G95 D4 FG1W F9
100R
10p 46 47 RES 3G2Z FG2K 48
2G93 3D-LR
FG2J 47
RES 44 45 BACKLIGHT-BOOST 100R 3G37 RES FG2R 2G96 D4 FG1Y D9
10p 42 43 46
2G94 3D-VS-DISP 3G36 100R
RES 45
FG30 41 100R RES 44
2G97 D4 FG1Z D9
10p 2G95 FG31 CTRL-DISP FG04 3G30 FG2L
40 43
FG32 CTRL-DISP 3G31 RES 100R 2G98 D4 FG20 D9
39 42
FG33 FG2M
RES 38 100R RES 41
D 37 PX1A- FG2E 40 D
10p 2G96 RES PX1A+ FG2F
2G99 D4 FG21 D9
RES 10p 36 39
2G99 PX1B- FG1Y
RES 10p 35 38 3G2W C8 FG22 E9
2G97 PX1B+ FG1Z
10p 34 37
2G98 PX1C- FG20
FG1C 33 36
PX3A- 32 PX1C+ FG21 35
3G2Y C8 FG23 E9
PX3A+ FG1D
31 34
PX3B- FG1E PX1CLK- FG22 3G2Z D8 FG24 E9
30 33
PX3B+ FG1F 29 PX1CLK+ FG23 32
PX3C- FG1G
28 FG24 31 3G30 D9 FG25 E9
PX3C+ FG1H PX1D-
27 30
PX1D+ FG25
FG11 26 29 3G31 D8 FG26 E9
PX3CLK- 25 PX1E- FG26 28
PX3CLK+ FG1J PX1E+ FG27
24 27
E FG1K
23 10p 2G28 26 E 3G32 C8 FG27 E9
PX3D- 22 25
PX3D+ FG1L PX2A- FG28 10p 2G29
21 24 3G33 C9 FG28 E9
PX3E- FG1M PX2A+ FG29
20 23
PX3E+ FG1N PX2B- FG2A
19 22 3G34 B9 FG29 E9
PX2B+ FG2B
18 21
PX2C- FG2C
17 20
PX4A- FG12 PX2C+ FG2D 3G35 C9 FG2A E9
16 19
PX4A+ FG13 15 FG1R 18
PX4B- FG14 PX2CLK- 3G36 D8 FG2B E9
14 17
PX4B+ FG15 13 PX2CLK+ FG1S 16
PX4C- FG16 12 15 3G37 D9 FG2C E9
PX4C+ FG17 PX2D- FG1T
11 14
10 PX2D+ FG1U 13
F PX4CLK- FG18 PX2E- FG1W F 9G0G G11 FG2D F9
9 12
PX4CLK+ FG19 8 PX2E+ FG1V 11
7 10
9G0K-1 C4 FG2E D9
PX4D- FG1A
6 FG2P 9
PX4D+ FG1B 9G0K-2 C4 FG2F D9
5 8
PX4E- FG1Q
4 7
PX4E+ FG1P
3 6 9G0K-3 C4 FG2G C9
+VDISP RES 9G0G FG2N
2 5
1 4 9G0K-4 C4 FG2H C9
3
1G50
2 FG04 D8 FG2J D5
1
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 155
AmbiLight CPLD
AmbiLight CPLD
B06C B06C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A A
DEBUG ONLY
5GA0 FGA0
+3V3 VINT
30R
1u0
100n
100n
2GA0
2GA1
2GA2
1G37
B +3V3 1 B
5GA1 2
FGA1 3GA5-4 4 5
+3V3 VIO GCK3 3
GTS1 3GA5-3 3 6 100R 4
30R
GTS2 3GA5-2 2 7 100R 5
GSR 3GA5-1 1 8 100R 6
1u0
100n
100R
2GA3
2GA5
SD51022
IGA1
CPLED2
C IGA2
C
CPLED3
15
35
26
XC9572XL-10VQG44C0100 3
VCCINT Φ VCCIO AMBI-SPI-CLK-OUT-R
PXCLK54 43 AMBI-SPI-SDI-OUT_G1-R GCK3 5 7GA1-2
IXO1_43|GCK1 BC847BS(COL)
GCK2 44 AMBI-SPI-SDO-OUT-R
IXO1_44|GCK2
GCK3 1 4
IXO1_1|GCK3
+3V3
2 5 PNX-SPI-CSBn
D IXO1_2 IXO3_5 D
PNX-SPI-CS-BLn 3 6 9GA1 BACKLIGHT-PWM 6
IXO1_3 IXO3_6
PNX-SPI-SDO 39 7 3D-LR
IXO1_39 IXO3_7
PNX-SPI-SDI 40 8 3D-VS-DISP GTS1 2 7GA1-1
IXO1_40 IXO3_8 BC847BS(COL)
PNX-SPI-CLK 41 IXO3_12 12 BL-SPI-SDO
IXO1_41
42 13 BL-SPI-SDI 1
IXO1_42 IXO3_13
14 BL-SPI-CSn +3V3
IXO3_14
GTS1 36 IXO3_16 16 3GA1 BACKLIGHT-PWM_BL-VS
IXO2_36|GTS1
GTS2 34 18 47R BL-SPI-CLK 3
IXO2_34|GTS2 IXO3_18
GSR 33
IXO2_33|GSR
AMBI-SPI-CS-OUTn_R2-R 19 3 6 AMBI-PROG_B1 GTS2 5 7GA2-2
IXO4_19 BC847BS(COL)
AMBI-PWM-CLK_B2 29 20 3G10-3 100R 2 7 AMBI-BLANK_R1
IXO2_29 IXO4_20
AMBI-SPI-CS-OUTn_R2 2 7 3G14 100R 30 21 1 8 3G10-2 100R AMBI-SPI-CS-EXTLAMPSn 4
IXO2_30 IXO4_21
AMBI-LATCH1_G2 3G11-2 100R 4 5 31 22 3G10-1 100R AMBI-SPI-CLK-OUT +3V3
IXO2_31 IXO4_22
AMBI-TEMP 3G11-4 100R 32 23 3G13 100R AMBI-SPI-SDI-OUT_G1
E IXO2_32 IXO4_23 E
CPLED3 37 27 3G12 10R 4 5 AMBI-SPI-SDO-OUT 6
IXO2_37 IXO4_27
CPLED2 38 28 8 1 3G10-4 100R AMBI-LATCH2_DIS
IXO2_38 IXO4_28
3G11-1 100R GSR 2 7GA2-1
11 BC847BS(COL)
TCK
9 1
RES
RES
TDI
24
TDO
10p
10p
10p
10p
10p
10p
10p
10p
10p
10p
10K
3G15 10
TMS
2G10
2G11 RES
2G12 RES
2G13
2G14 RES
2G15 RES
2G16 RES
2G17 RES
2G18 RES
2G19 RES
3GA6-4
3GA6-3
3GA6-2
3GA6-1
GND
5 330R 4
6 330R 3
7 330R 2
8 330R 1
+3V3
4
17
25
F F
6GA0
6GA1
6GA2
6GA3
LTST-C190KGKT
LTST-C190KGKT
LTST-C190KGKT
LTST-C190KGKT
DEBUG ONLY
1G36 1G35
1 1 3GA2-1 1 8 100R
2 2 3GA2-2 2 7 100R FGA6
3 3 3GA2-3 3 6 100R FGA4
4 4 3GA2-4 4 5 100R FGA5
5 5 FGA2 FGA3
6 6
+3V3
G 7 8 G
SD51022
2GA4
100n RES
BACKLIGHT-PWM 9GA0 BACKLIGHT-PWM_BL-VS
H H
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1G35 G2 2G10 F3 2G13 F7 2G16 F8 2G19 F9 2GA2 B4 2GA5 B3 3G10-3 E6 3G11-2 E3 3G13 E7 3GA1 E6 3GA2-3 G3 3GA5-2 B12 3GA6-1 F13 3GA6-4 F12 6GA0 F12 6GA3 F13 7GA1-2 D13 9GA0 H5 FGA1 B4 FGA4 G4 IGA0 C11 IGA3 C11
1G36 G2 2G11 F3 2G14 F8 2G17 F8 2GA0 B3 2GA3 B3 3G10-1 E6 3G10-4 E7 3G11-4 E4 3G14 E4 3GA2-1 G3 3GA2-4 G3 3GA5-3 B12 3GA6-2 F13 5GA0 A3 6GA1 F12 7GA0 D5 7GA2-1 E12 9GA1 D7 FGA2 G3 FGA5 G5 IGA1 C11
1G37 B13 2G12 F3 2G15 F8 2G18 F9 2GA1 B4 2GA4 G3 3G10-2 E7 3G11-1 E6 3G12 E6 3G15 E2 3GA2-2 G3 3GA5-1 B12 3GA5-4 B12 3GA6-3 F12 5GA1 B2 6GA2 F13 7GA1-1 D13 7GA2-2 E12 FGA0 A5 FGA3 G5 FGA6 G4 IGA2 C11
3 2010-03-09
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 156
SPI-Buffer
SPI-Buffer
B06D B06D
1 2 3 4 5 6
2GE0 B2
3GE0-1 B4
3GE0-3 B4
3GE1-3 C3
3GE1-4 C4
A A 3GE2 B4
3GE3 C4
+3V3
+3V3 3GE4 C3
7GE0 B3
7GE1 B4
7GE1
9GE0-2 C3
10K
3GE2 PDTC114EU
100n
2GE0
9GE0-3 D3
7GE0 PNX-SPI-CSBn 9GE0-4 D3
20
74LVC245A
1 9GE1 D3
B 3EN1 B
3EN2 IGE0 9GE2 D3
19
G3
3GE0-3 IGE0 B3
PNX-SPI-CLK 18 2 3 6 BL-SPI-CLK
1
2 47R 3GE0-1
IGE1 D2
17 3 1 8 BL-SPI-SDO
PNX-SPI-SDO 16 4 3GE1-3 6 3 47R AMBI-SPI-CLK-OUT-R
15 5 47R RES 5 4 3GE1-4 AMBI-SPI-SDO-OUT-R
AMBI-SPI-SDI-OUT_G1-R 14 6 3GE3 47R RES PNX-SPI-SDI
BL-SPI-SDI 13 7 3GE4 47R RES
12 8 47R
11 9
10
C C
PNX-SPI-CLK 7 9GE0-2 2 BL-SPI-CLK
9GE2
D * D
PNX-SPI-CS-BLn IGE1 5 9GE0-4 BL-SPI-CSn
** 4
Buffer
* Direct
E E
**
1 2 3 4 5 6
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 157
3T74
100K
AMBI-SPI-SDO-OUT FT71
2
AMBI-SPI-SDI-OUT_G1 FT72 1T85 F4 FT52 D8
A 3 2T76 A
4 1T86 B4 FT53 D8
AMBI-PWM-CLK_B2 FT73 FT87
5 3T75 100p
V-AMBI 6 LIGHT-SENSOR 2T70 B3 FT54 D8
AMBI-SPI-CS-OUTn_R2 FT74 100R
7 2T77 2T76 A7 FT55 D8
AMBI-LATCH1_G2 FT75
8
9 IT73 3T76 100p TO 2T77 A7 FT56 E8
AMBI-PROG_B1 FT76 RC
10 LED PANEL 2T78 B7 FT57 E8
AMBI-BLANK_R1 FT77 100R
11 2T78
V-AMBI 1M20 2T79 B7 FT58 E8
12 FT88
AMBI-LATCH2_DIS FT78 IT74
13 LED-2 3T77 100p 1 2T80 B7 FT59 F7
AMBI-SPI-CS-EXTLAMPSn FT80 FT89
14 2
AMBI-TEMP 3T70 FT79 100R FT90 2T81 B9 FT60 E8
15 3
100R FT91
16 4 2T82 C7 FT61 E8
+3V3-STANDBY FT92
B 17 5 B
FT81 2T79 FT93 2T83 E4 FT64 E7
18 6
100n
2T70
FT94
19 7 2T84 E4 FT68 D3
20 IT75 3T78 100p +5V 8
LED-1 2T85 F5 FT69 E3
21
FC83 FT82 100R
1T86 22 2T80 2T86 C7 FT70 A5
+24V 23 100n
2T81
10p
2T86
3T71 E7 FT78 B4
1M09 FT51 3T85 3T74 A6 FT79 B4
SCL-BL
1 3T75 A7 FT80 B5
100R
+24V 2 3T76 A7 FT81 B5
10p
2T87
3
4 3T77 B7 FT82 B5
6 5 3T86 3T78 B7 FT87 A7
* HOTEL TV BL-SPI-CLK
502382-0470 100R
3T79 C7 FT88 B9
3T90 3T80 D4 FT89 B9
10p
D D
2T88
+3V3 * RES
10K 1F53 3T81 E4 FT90 B9
3T91 FT52
FAN-CTRL1 RES 1 3T82 E4 FT91 B9
* 3T88-1
100R BL-SPI-SDO 8 1 2
FT68 100R FT53 3 3T83 E4 FT92 B9
3T80
TACH01 FT54 4 3T84 C7 FT93 B9
10p
FT55
2T89
5
100R FT94 B9
FT96
1M71 6 3T85 C7
RES 3T81 FT56
SCL-BL 7
1 3T86 D7 FT95 C7
FT69 FT97 8
3T82 100R 2 3T88-2 FT57
TACH02 FT98 2 7 9 3T87 F7 FT96 E4
3
100R 100R 10
4 3T88-1 D7 FT97 E4
FT58 11
RES 3T83
10p
2T90
100p
100p
2T83
2T84
100R FT60 13
14
3T88-4 F7 FT99 F5
3T92 TEMPERATURE 3T71
FAN-CTRL2 * RES BACKLIGHT-PWM-ANA-DISP FT64 15 16 3T90 D3 IT73 A7
3T93 100R SENSOR 100R 3T91 D4 IT74 B7
+3V3 * RES 502386-1470
9T50
1u0
2T85
30R RES
10p
2T91
1X03
REF EMC HOLE
F FT59 3T87 F
1T85
BACKLIGHT-PWM_BL-VS
T 1.0A 63V
5T53 100R
+12V IT78
10p
2T92
30R RES
1 2 3 4 5 6 7 8 9
2 2010-02-01
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Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 158
Example
Net Name Diagram 1.1. Introduction
+12V B03B (1 ×)
+12V B03C (1 ×)
+12VD B03C (1 ×) SRP (Service Reference Protocol) is a software tool that creates a list with all references to signal lines. The list contains
+12VD B03H (1 ×) references to the signals within all schematics of a PWB. It replaces the text references in the past printed next to the signal
+1V1 B03E (2 ×)
+1V2 B02H (1 ×) names in the schematics. These printed references were created manually and are therefore not guaranteed to be 100%
+1V2 B03D (1 ×) correct. In addition, in the current crowded schematics there is often none or very little place for these references.
+1V2-BRA-DR1 B01G (1 ×)
+1V2-BRA-VDDC B01G (1 ×)
+1V8 B02B (1 ×)
+1V8 B05A (5 ×) 1.2. Non-SRP Schematics
+24V B13 (2 ×)
+24V-AUDIO-POWER B02D (1 ×)
+24V-AUDIO-POWER B03A (2 ×)
+24V-AUDIO-POWER B03C (1 ×) There are several different signals available in a schematic:
+24V-AUDIO-VDD B02D (4 ×)
+2V5 B02D (1 ×)
+2V5 B03E (1 ×) 1.2.1. Power Supply Lines
+2V5-AUDIO B02D (1 ×)
+2V5-AUDIO B02H (2 ×)
+2V5-BRA B01K (3 ×)
+2V5-LVDS B02H (2 ×) All power supply lines are available in the supply line overview (see chapter 9). In the schematics (see chapter 10) is not
+2V5-LVDS B03D (1 ×) indicated where supplies are coming from or going to.
+2V5-REF B03D (3 ×)
+3V3 B04A (3 ×) It is however indicated if a supply is incoming (created elsewhere), or outgoing (created or adapted in the current schematic).
+3V3 B04C (8 ×)
+3V3 B04D (4 ×)
+3V3 B04E (1 ×)
+5V +5V
+3V3 B11D (2 ×)
+3V3 B13 (6 ×) Outgoing Incoming
+3V3-ARC B02D (4 ×)
+3V3-BRA B01K (2 ×)
+3V3-BRA-FLT B01K (3 ×)
+3V3-ET-ANA B04C (3 ×) 1.2.2. Normal Signals
+3V3-HDMI B04D (1 ×)
+3V3-SD B01D (2 ×)
+3V3-STANDBY B01E (4 ×) For normal signals, a schematic reference (e.g. B14b) is placed next to the signals.
+3V3-STANDBY B02E (1 ×)
+3V3-STANDBY B02G (7 ×)
+3V3-STANDBY B02H (1 ×)
+3V3-STANDBY B03A (3 ×) B14b signal_name
+3V3-STANDBY B03B (1 ×)
+3V3-STANDBY B03C (5 ×)
+3V3-STANDBY B03H (1 ×)
+3V3-STANDBY B04D (2 ×)
+3V3-STANDBY B04E (1 ×)
+3V3-STANDBY B11D (1 ×)
+5V B01A (1 ×) 1.2.3. Grounds
+5V B01C (3 ×)
+5V B04D (1 ×)
+5V B11D (2 ×) For normal and special grounds (e.g. GNDHOT or GND3V3 etc.), nothing is indicated.
+5V5-TUN B03D (2 ×)
+5V5-TUN B03E (1 ×)
+5VCA B01A (4 ×)
+5V-EDID B04D (2 ×)
+5V-TUN B01F (1 ×) 1.3. SRP Schematics
+5V-TUN B03D (2 ×)
+5V-TUN-PIN B01F (4 ×)
+5V-USB1 B01C (2 ×) SRP is a tool, which automatically creates a list with signal references, indicating on which schematic the signals are used.
+5V-USB2 B01C (2 ×)
+5V-VGA B01I (16 ×) A reference is created for all signals indicated with an SRP symbol, these symbols are:
+5V-VGA B04D (2 ×)
+AUDIO-L B02D (1 ×)
+AUDIO-L B03A (1 ×) +5V +5V
+AVCC B03A (2 ×) Power supply line.
+VDISP B11A (2 ×)
+VDISP B11B (7 ×)
+VDISP-INT B03H (1 ×)
+VDISP-INT B11B (1 ×)
ADAC(1) B02D (2 ×) name name
Stand alone signal or switching line (used as less as possible).
ADAC(2) B02D (2 ×)
ADAC(3) B02D (1 ×)
ADAC(3) B04E (1 ×)
name name
ADAC(4) B02D (1 ×)
ADAC(4) B04E (1 ×)
ADAC(5) B02D (2 ×) Signal line into a wire tree.
ADAC(6) B02D (2 ×)
AGND B01K (12 ×)
AIN-5V B04D (4 ×)
ALE B02G (2 ×) name name
AMBI-BLANK_R1 B13 (2 ×)
AMBI-LATCH1_G2 B13 (2 ×) Switching line into a wire tree.
AMBI-LATCH2_DIS B13 (2 ×)
AMBI-PROG_B1 B13 (2 ×)
AMBI-PWM-CLK_B2 B13 (2 ×)
AMBI-SPI-CLK-OUT B13 (2 ×) name
AMBI-SPI-CLK-OUT-R B13 (1 ×)
AMBI-SPI-SDO-OUT B13 (2 ×) Bi-directional line (e.g. SDA) into a wire tree.
AMBI-SPI-SDO-OUT-R B13 (1 ×)
AMBI-TEMP B13 (2 ×)
AMP1 B01J (1 ×) name
AMP1 B04E (1 ×)
AMP2 B01J (1 ×)
AMP2 B04E (1 ×) Signal line into a wire tree, its direction depends on the circuit (e.g. ingoing for PDP, outgoing for LCD sets).
A-PLOP B03A (1 ×)
A-PLOP B04E (2 ×)
AP-SCART-OUT-L B04A (3 ×) Remarks:
AP-SCART-OUT-R B04A (3 ×)
ARC-eHDMI+ B04D (2 ×) • When there is a black dot on the “signal direction arrow” it is an SRP symbol, so there will be a reference to the signal
ARX0- B04D (2 ×) name in the SRP list.
ARX0+ B04D (2 ×)
ARX1- B04D (2 ×) • All references to normal grounds (Ground symbols without additional text) are not listed in the reference list, this to keep
ARX1+ B04D (2 ×) it concise.
ARX2- B04D (2 ×)
ARX2+ B04D (2 ×) • Signals that are not used in multiple schematics, but only once or several times in the same schematic, are included
ARXC- B04D (2 ×)
ARXC+ B04D (2 ×) in the SRP reference list, but only with one reference.
ARX-DDC-SCL B04D (3 ×)
ARX-DDC-SDA B04D (3 ×) Additional Tip:
ARX-HOTPLUG B04D (2 ×)
A-STBY B03A (1 ×) When using the PDF service manual file, you can very easily search for signal names and follow the signal over all the
A-STBY B04E (1 ×)
AUDIO-IN1-L B02D (1 ×) schematics. In Adobe PDF reader:
AUDIO-IN1-L B04A (1 ×) • Select the signal name you want to search for, with the “Select text” tool.
AUDIO-IN1-R B02D (1 ×)
AUDIO-IN1-R B04A (1 ×) • Copy and paste the signal name in the “Search PDF” tool.
AUDIO-IN2-L B02D (1 ×)
AUDIO-IN2-L B04A (1 ×) • Search for all occurrences of the signal name.
AUDIO-IN2-R B02D (1 ×) • Now you can quickly jump between the different occurrences and follow the signal over all schematics. It is advised to
AUDIO-IN2-R B04A (1 ×)
AUDIO-IN3-L B02D (1 ×) “zoom in” to e.g. 150% to see clearly, which text is selected. Then you can zoom out, to get an overview of the complete
AUDIO-IN3-L B04B (1 ×) schematic.
AUDIO-IN3-R B02D (1 ×)
AUDIO-IN3-R B04B (1 ×)
AUDIO-IN4-L B02D (1 ×) 1 2010-04-09
AUDIO-IN4-L B04B (1 ×)
PS. It is recommended to use at least Adobe PDF (reader) version 6.x, due to better search possibilities in this version.
SRP LIST EXPLANATION
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10000_050_100409.eps
100409
2010-Oct-01 back to
div. table
Circuit Diagrams and PWB Layouts Q551.1L LA 10. EN 159
3T91
2G77
2G96
2G97
9G0K
2G28
2G29
3T81
3T80
2G24
2G75
2G76
2G27
2G26
2G7A
2T81
3T79
2T82
3T78
2T80
2T79
3T77
2T78
3T76
2T77
2T76
3T75
3T74
2T84
3T82
2T83
1T85
5T53
2T85
2G78 2G25 2G79
2G99
2G98
3G28
3T92 3T83
3T90 5T54 6G00
IT75
IT74
3T93
IG11
1M09
3B11
2G15
2G14
3G15
2G11
2G19 2G16 2G13
5UM1
3US2 2G12
3UU1
3G14
2G17
3G12
3G13
2G18
3G11 3G10
3U29
3GA1
3US3 2G10
9GA0
5UM0
2GA4
6GA0 1G35
2UU1
3B26
2U42
IUS4 3US7
7UU1
IUT2 7GA2
1UM0
3B18 6GA1
IUS3
2B47
3B19
3UU3
7UU3
2UU0
2U41 6GA2
3UU2
2UD6 IUT1
1G36
2US3
3US5
2U46
7UU0 7B01
3GA5
3U45
6GA3
7UU2
3UU0
1G37
3U81 IUS6
7US2
3B10
9UU0 9UU1
2U45
2U15
7GA1
2UE9
7US1
2UD5
2UD4
3U42
IU23
2UE6
2U44
1F24
3U43 2U18
2U43
9US0