ADC and DAC INTERFACE

ADC Interfacing
• Interfacing ADC In most of the cases, the PIO
8255 is used for interfacing the analog to
digital converters with microprocessor.
• The analog to digital converters is treaded as
an input device by the microprocessor
• The MPU sends an initializing signal to the
ADC to start the analog to digital data
conversation process.
• The start of conversation signal is a pulse of a
specific duration.
 ADC Interfacing
• Interfacing ADC The process of analog to digital
conversion is a slow process, and the
microprocessor has to wait for the digital data till
the conversion is over.
• After the conversion is over, the ADC sends end of
conversion EOC signal to inform the
microprocessor that the conversion is over and
the result is ready at the output buffer of the
ADC.
• These tasks of issuing an SOC pulse to ADC,
reading EOC signal from the ADC and reading the
digital output of the ADC are carried out by the
CPU using 8255 I/O ports.
 ADC Interfacing
• The time taken by the ADC from the active edge of SOC pulse
till the active edge of EOC signal is called as the conversion
delay of the ADC.

• General algorithm for ADC interfacing contains the following

steps
1. Ensure the stability of analog input, applied to the
ADC
2. Issue start of conversion SOC pulse to ADC
3. Read end of conversion EOC signal to mark the
end of conversion process
4. Read digital data output of the ADC as equivalent
digital output.
 ADC Interfacing Procedure
• Analog input voltage must be constant at the
input of the ADC right from the start of
conversion till the end of the conversion to get
correct results.
• This may be ensured by a sample and hold circuit
which samples the analog signal and holds it
constant for a specific time duration.
• The microprocessor may issue a hold signal to the
sample and hold circuit.
• If the applied input changes before the complete
conversion process is over, the digital equivalent
of the analog input calculated by the ADC may
not be correct.
 ADC 0808 / 0809
• The analog to digital converter chips 0808
and 0809 are 8- bit CMOS, successive
approximation converters.
• This technique is one of the fast techniques
for analog to digital conversion.
• The conversion delay is 100µs at a clock
frequency of 640 KHz, which is quite low as
compared to other converters.
• These converters do not need any external
zero or full scale adjustments as they are
already taken care of by internal circuits.
 Internal 3:8 Analog Multiplexers
• Using these address inputs, multichannel data
acquisition system can be designed using a
single ADC.
 ADC 0808/0809

• These are unipolar analog to digital

converters, i.e. they are able to convert only
positive analog input voltage to their digital
equivalent.
• These chips do no contain any internal sample
and hold circuit
Block Diagram of ADC 0808 / 0809
Pin Diagram of ADC 0808 / 0809
 Pin description of ADC 0808/0809
Pin No Signal Name Description
11 Vcc Supply pins +5V

13 GND GND

12 Vref+ Reference voltage positive

(+5 Volts maximum)

16 Vref - Reference voltage negative

(0 Volts minimum)
26 – 28 I/P0 –I/P7 Analog inputs
1-5
25, 24, 23 ADD A,B,C Address lines for selecting
analog inputs.
 Pin description of ADC 0808/0809
Pin No Signal Name Description
8, 14, 15, 17 - 21 O7 – O0 Digital 8-bit output with O7
MSB and O0 LSB
6 SOC Start of conversion signal
pin
7 EOC End of conversion signal
pin

9 OE Output latch enable pin, if

high enables output
10 CLK Clock input for ADC

22 ALE Address Load Enable. Once

loaded the multiplexer
sends the appropriate
channel to the converter
on the chip
 Interfacing between ADC to Microprocessor

Example:
Interfacing ADC 0808 with 8086 using 8255
ports. Use port A of 8255 for transferring
digital data output of ADC to the CPU and port
C for control signals. Assume that an analog
input is present at I/P2 of the ADC and a clock
input of suitable frequency is available for
ADC.
Interfacing of ADC 0808 to 8086 through 8255
Solution:-

•The analog input I/P2 is used & therefore address pins

A,B,C should be 0,1,0 respectively to select I/P2.
•The OE (Out put latch Enable) & ALE pins are already
kept at +5v to select the ADC and enable the outputs.
•Port C upper acts as the input port to receive the EOC
signal while Port C lower acts as the output port to
send SOC to ADC.
•Port A acts as a 8-bit input data port to receive the
digital data output from the ADC.
8255 Control Word:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 0 0 0 = 98H
Program:
MOV AL,98H ; Initialize 8255, send AL to control word (CWR)
OUT CWR, AL
MOV AL, 02H ;Select I/P2 as analog I/P
OUT Port B, AL ;Port B as output
MOV AL, 00H ; Give start of conversion pulse to the ADC
OUT Port C, AL
MOV AL, 01H
OUT Port C, AL
MOV AL, 00H
OUT Port C, AL
WAIT: IN AL, Port C ; check for EOC by reading Port C upper & rotating
RCL ; through carry.
JNC WAIT
IN AL, Port A ; if EOC, read digital equivalent in AC
HLT ; stop.
 Interfacing D/A Converters

• The Digital to Analog Converters (DAC) convert binary numbers

into their analog equivalent voltages.
• The DAC find applications in areas like
– Digitally controlled gains
– Motor speed controls
– Programmable gain amplifiers etc.
 AD 7523 - DAC
• DAC 8-bit DAC
• This 16 pin DIP, multiplying digital to analog converter,
containing R-2R ladder (R=10K) for digital to analog
conversion.
• Also contains single pole double thrown NMOS
switches to connect the digital inputs to the ladder.
 R – 2R Ladder Type DAC

• The R-2R resistor ladder network directly converts a

parallel digital symbol / word into an analog voltage.
Functional Block Diagram
Pin diagram AD 7523
 Pin description of AD 7523
Pin No Signal Name Description
14 Vcc Supply range is from +5V to
+15V

3 GND GND

15 Vref in vary between -10V to +10V

4 – 11 B1 – B8 Binary Input
1, 2 OUT1, OUT 2 Analog output

12, 13 NC No connection
16 RFB R Feedback (Feedback
resistor )(To be connected
with Op amp)
 Pin Description of AD 7523 DAC
• The maximum analog output voltage will be any
where between -10V to +10V, when all the digital
inputs are at logic high state.
• An operational amplifier is used as a current to
voltage converter at the output of DAC to convert
the current output of DAC to a proportional output
voltage.
• Usually a Zener is connected between OUT1 and
OUT2 to save the DAC from negative transients.
• An external feedback resistor acts to control the
gain. One may not connect any external feedback
resistor, if no gain control is required.
Interfacing of AD 7523 with 8086
Problem:--
Interface DAC AD7523 with the 8086 running at 8MHz & write ALP
to generate a saw tooth waveform of period 1ms with Vmax 5v.
Solution:--
Code segment
Assume cs:code
Start: MOV AL, 80H
OUT CWR, AL
AGAIN: MOV AL, 00H
BACK: OUT Port A, AL
INC AL
CMP AL, 0F2H
JB BACK
JMP AGAIN
Code ends
End Start
 Program Explanation
• In the above program, port A is initialized as the
output port for sending the digital data as input to
DAC. The ramp starts from the 0V (analog), hence
AL starts with 00H.
• To increment the ramp, the content of AL is
increased during each execution of loop till it
reaches F2H.
• After that the saw tooth wave again starts from
00H, i.e. 0V(analog) and the procedure is repeated.
• The ramp period given by this program is precisely
1.000625 ms.
 ALP Program to generate Triangular waveform
• 2000: RPT1: MOV CX, 0FF;
MOV AL, 00;
UP: INC AL;
MOV DX, 0FFE0 ;
OUT DX, AL;
MOV DX, 0FFE2 ;
OUT DX, AL;
LOOP UP
MOV CX, 0FF;
MOV AX, CX;
 ALP Program to generate Triangular waveform
• DOWN: DEC AL MOV DX, 0FFE0 ;
OUT DX, AL;
MOV DX, 0FFE2 ;
OUT DX, AL;
LOOP DOWN

JMP RPT1; Repeat the above Process

//Note: Initialization of Ports must be done through
initialization of CWR
 ADC Conversion Techniques

• Flash Conversion
• Successive Approximation Conversion
• Delta-encoded ADC (up-down counter type).
3-bit Flash type ADC
Successive Approximation type ADC
Successive Approximation type ADC
 DAC Conversion Techniques

• Weighted Resistors method

• R-2R ladder network method
• Serial DAC converter
• BCD DAC
• Bipolar DAC
Binary Weighted resistor based DAC
R-2R ladder network method based DAC
 R-2R ladder network method based DAC
• This network has some unique and interesting
properties.
– 1. Easily scalable to any desired number of bits
– 2. Uses only two values of resistors which make for
easy and accurate fabrication and integration
– 3. Output impedance is equal to R, regardless of the
number of bits, simplifying filtering and further
analog signal processing circuit design
– 4. The R-2R resistor ladder based digital-to-analog
converter (DAC) is a simple, effective, accurate and
inexpensive way to create analog voltages from
digital values.
 Display interface
Interface an 8255 with 8086 at 80h as an I/O address of port-A.
interface five 7 segment displays with the 8255. write a
sequence of instructions to display 1,2,3,4 and 5 over the five
displays continuously as per their positions starting with 1 at
the least significant position. CWR address is 86h.

Number to be PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Code
displayed dp a b c d e f g
1 1 1 0 0 1 1 1 1 CF

2 1 0 0 1 0 0 1 0 92

3 1 0 0 0 0 1 1 0 86

4 1 1 0 0 1 1 0 0 CC

5 1 0 1 0 0 1 0 0 A4

All these codes are stored in a look up table starting at 2000:0001.

Interfacing multiplexed 7-segment display to 8086 through 8255
 ALP for display interface

again: mov cl,05h ;count for displays

mov bx,2000h ;initialize the data segment for
mov ds,bx ; look-up table
mov ch,01h ;1st no. to be displayed
mov al,80h
out 86h,al ;load control word in the CWR
mov dl,01h ;enable code for least significant 7-seg
display

nxtdgt: mov bx,0000h ;set pointer to look-up table

mov al,ch ;store number to be display
xlat ;find code from table
out 80h,al
mov al,dl
out 82h,al ;enable the display
rol dl ;go for next digit display
inc ch
dec cl ;decrement counter
jnz nxtdgt ;go for next digit display
jmp again
 Stepper Motor Interfacing
• A stepper motor is a device used to obtain an accurate position
control of rotating shafts.
• It employs rotation of its shaft in terms of steps, rather than
continuous rotation as in case of AC or DC motors.
• In dot-matrix printer one small stepper motor which is used to
advance the paper to the next line position & another small stepper
motor which is used to move the print head to the next character
position.
• In floppy disk stepper motor is used to position the read/write head
over the desired track.
• To rotate the shaft of the stepper motor, a sequence of pulses is
needed to be applied to the windings of the stepper motor, in a
proper sequence.
• The no. of pulses required for one complete rotation of the shaft of
the stepper motor are equal to its number of internal teeth on its
rotor.
• The stator teeth the rotor teeth lock with each other to fix a
position of the shaft .
• With a pulse applied to the winding input, the rotor rotates by
one teeth position or an angle x. The angle x may be calculated
as:
x = 3600 / no. of rotor teeth
• The stepper motors have been designed to work with digital
circuits. Binary level pulses of 0-5v are required at its winding
inputs to obtain the rotation of shafts.
• The sequence of pulses can be decided, depending upon the
required motion of the shaft.
• The count for rotating the shaft of the stepper motor through a
specified angle may be calculated from the no. of rotor teeth
C = no. of rotor teeth / 3600 * θ0
 Motion Step A B C D
Clockwise 1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0

Anticlockwise 1 1 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 1 0 0
5 1 0 0 0

Excitation sequence for clockwise and anticlockwise rotation of a stepper

motor
 Problem

Design a stepper motor controller and write an ALP to rotate

shaft of a 4-phase stepper motor:
i. In clockwise 5 rotations
ii. In anticlockwise 5 rotations.
The 8255 port A address is 0740h. The stepper motor has 200
rotor teeth.
The port A bit PA0 drives winding Wa, PA1 drives winding Wb
and so on.
The stepper motor has an internal delay of 10msec. Assume that
the routine for this delay is already available.
Solution:

ALP:
Assume cs:Code
Code segment
Start: MOV AL, 80H
OUT CWR, AL
MOV AL, 88H; Bit pattern 10001000
MOV CX, 1000
Again1: OUT Port A, AL
CALL DELAY
ROL AL, 01
DEC CX
JNZ Again1
MOV AL, 88H
MOV CX, 1000
 Again2: OUT Port A, AL
CALL DELAY
ROR AL, 01
DEC CX
JNZ Again2
MOV AH, 4CH
INT 21H
Code ends
End start
 8254 - Programmable Interval Timer

This is a bus compatible digital timer / counter.

Usage
• real time clock,
• event counter,
• a digital one shot,
• a square wave generator,
• a complex wave form generator.
Pinout and block diagram
 Pin Definitions for 8254
A0 , A1
• The address inputs select one of four internal
registers within the 8254. See Table 11–4 for the
function of the A1 and A0 address bits.
CLK
• The clock input is the timing source for each of the
internal counters. This input is often connected to the
PCLK signal from the microprocessor system bus
controller.
 CS
• Chip select enables 8254 for programming and
reading or writing a counter.
G
• The gate input controls the operation of the
counter in some modes of operation
GND
• Ground connects to the system ground bus.
 OUT
• A counter output is where the waveform
generated by the timer is available.
RD
• Read causes data to be read from the 8254 and
often connects to the IORC signal.
Vcc
• Power connects to the +5.0 V power supply.
WR
• Write causes data to be written to the 8254 and
often connects to write strobe IOWC.
 Modes of function
Each of the three counters can be programmed as :
• Timer
1. Generate a required time delay to the
accuracy of one clock period,
2. Generate an one shot pulse (retriggerable
or non- retriggerable).
• Counter
1. Count the number of events occurred on its
input terminal during unit time,
2. Divide the input clock by any number.
 Working principle
8254 possesses three independent binary down counters 16
bits wide:
• A counter is loaded with a number proportional to
required time delay,
• The time required to empty the counter is the delay time,
• The time delay is programmable, delay can be changed
with instructions,
• Single or repetitive time delay can be generated.
• A count can be read by MPU while the counter is
decrementing,
8254: Mode of operations
Mode 0: Interrupt on terminal count
The output becomes a logic 0 when the control word is
written
and remains there until N plus the number of
programmed counts
 Mode 1- HW triggered / programmable
one shot.
The triggering must be done through the GATE input by sending
a 0-to-1 pulse to it.
Steps:
1. load the count register
2. a 0-to-1 pulse must be sent to the GATE input to trigger the
count.
3. after sending the 0-to-1 pulse to GATE, OUT becomes low and
stays low for a duration of N*T, then becomes high and stays
high until the GATE is triggered again.
4. If during the activation, a retriggered happened, then restart the
down counting.
Mode 1 (cont.)
 Mode 2: Rate Generator (Divide-by-N
counter
• If GATE=1, OUT will be high for N*T, goes low
only for one clock pulse, then counter is reloaded
automatically,
• The cycle is repeated until reprogrammed or Gate
pin set to 0.
Mode 3: Square wave rate generator
• Generates a continuous square-wave with G set to 1.
• If count is even, 50% duty cycle otherwise OUT is
high 1 cycle longer
Mode 4: Software triggered strobe
• If GATE=1, the output will go high when loading the
count, it will stay high for duration N*T.
• After the count reaches zero, it becomes low for one clock
pulse, then goes high again and stays high until a new
command word or new count is loaded
• To repeat the strobe, the count must be reloaded
 Mode 5: Hardware triggered strobe

• Similar to Mode4, except that the triggering

must be done with the GATE input
• The count starts only when a 0-to-1 pulse is
sent to the GATE input
• If GATE retriggered during the counting, it
will restart the down counting
8254: Addresses of internal registers
Addressing 8254
8254: Format of the control word
 8254: Steps of program codes

1. Write the control word to configure the 8254 into the

control register
2. Write the low order byte of count into a counter
register
3. Write the higher order byte of count into a counter
register
The corresponding Gate input must be high to start
down counting.
 8254: Steps of read value of the count

1. Write the control word to latch a count in the

output latch into the control register,
2. Perform two I/O read operations
 Example #1:

Write the instructions to configure the

counter # 2 of 8254 as counter (mode 0) ?
Given
• Chip select is enabled when address line A7 = 1,
• Address lines A1 and A0 are connected to the A1
and A0 pins of 8254,
• The 8254 chip is I/O mapped,
• The address of counter # 2 is 82H
• The address of control register is 83H
 Example #1: (cont.)
Control words
Control word to initialize the counter # 2 in mode 0 is B0h

Control word for latching (bits D5 and D4 equal to 0) is 80h

 Example #1: (cont.)
Instructions:
COUNTER: MOV AL, B0h ; control word to initialize counter # 2
OUT 83h,AL ; Write in the control register
MOV AL, COUNT_LOBYTE ; Low order byte of the count
OUT 82h,AL ;Load counter#2 with low order byte of the count
MOV AL, COUNT_HIBYTE ; High order byte of the count
OUT 82h,AL ;Load counter#2 with high order byte of the count

READ: MOV AL, 80h ; control word to latch a count

OUT 83h,AL ; Write in the control register
IN AL,82h ; read low order byte
MOV DL, AL ; store low order byte in reg. D
IN AL,82h ; read high order byte
OR AL,DL ; OR low and high order bytes to set Z flag
JNZ READ : if the counter is not 0 go back to read next count.
 Mode 3: Square Wave Generator
Description
A continuous square wave is generated whose
period is equal to the count.
• When a count is loaded, the OUT pin is high,
• The count is decremented by 2 at every clock
cycle,
• When the count reaches zero, the OUT pin
goes low,
• The count is reloaded again.
Example: Configure the counter # 1 as 1KHz
square wave generator (mode 3)

Given
• Chip select is enabled when address line A7=1,
• Address lines A1 and A0 are connected to the
A1 and A0 pins of 8254,
• The 8254 chip is I/O mapped,
• The clock frequency is 2MHz (0.5μs clock
period)
 Solution

From the address table determine

• The address of counter # 1 is 81H
• The address of control register is 83H

Determine the count

• The count is calculated by dividing clock
frequency by the square wave frequency
2MHz /1KHz =2000 = 07D0h.
 Solution (cont.)

From the bit pattern format determine

• Control word to initialize counter # 1 in
mode 0 is 76h
 Solution (cont.)
Instructions:
SQWAVE:
MOV AL, 76h ; control word mode3 and counter # 1
OUT 83h,AL ; Write in the control register
MOV AL, D0h ; Low order byte of the count
OUT 81h,AL ; Load counter#1 with low order byte of the count
MOV AL, 07h ; High order byte of the count
OUT 81h,AL ; Load counter#1 with high order byte of the count
HLT
 Timer exercise
(a) Identify the port address of the control register and counter 2
in figure.
(b) Write a subroutine to initialize counter 2 in mode 0 with a
count of 50,000. The subroutine should also include reading
counts on the fly; when count reaches zero, it should return to
the main program.
(c) Write a main
program to display
seconds by calling the
subroutine as many
times as necessary.
Solution (a):

Address of counter 2 = 8002H Address of

control register = 8003H
Solution (b):
We have to initialize counter 2 in Mode0.
Count=(50,000)10 = C350H
Control Word to initialize counter 2 in mode0 and to load 16-bit count

To read count 2 on the fly counter latch command is

Continued solution b:

Subroutine:
COUNTER PROC NEAR
CNT2 EQU 8002H
CNTR EQU 8003H
MOV AL, B0H
OUT CNTR, AL
MOV AL, 50H
OUT CNTR2, AL
MOV AL, C3H
OUT CNTR2, AL
READ: MOV AL, 80H
OUT CNTR, AL
IN AL, CNT2
MOV DL, AL
IN AL, CNT2
OR AL, DL
JNZ READ
RET
COUNTER ENDP
Solution (c) Clock frequency, fc = 2 MHz
Time period of each clock cycle: 𝑡𝑐 = (1/2𝑥106 )= 5𝑥10−7 sec
Every time subroutine is called then, 50000 × 5 × 10^(−7) = 25 𝑚𝑠= is counted.
To count 1 sec subroutine needed to be called, 1𝑠/ 25𝑚𝑠 = 40 𝑡𝑖𝑚𝑒𝑠 = 28𝐻 𝑡𝑖𝑚𝑒
Main Program:
Assuming segment registers are already initialized.
MOV BL, 00H
SECOND:
MOV CL, 28H
WAIT: CALL COUNTER
DEC CL
JNZ WAIT
MOV AL, BL
ADD AL, 01
DAA
OUT 25H, AL ; assuming 8 bit port 25H
MOV BL, AL
JMP SECOND
HLT
Ex2: Write instructions to generate a 1 KHz square wave
from Counter1. Assume the gate of counter1 is tied to +5V
through a 10K resistor. Explain the significance of connecting
the gate to +5V. (use figure of problem 1)
Ex3:Write a subroutine to generate an interrupt every 1sec.
Consider the figure of problem1.