National institute of Technology Silchar

End Sem (PG/PhD), Dec. 2020

Subject Code: EI 5045 Subject: Microelectronics & VLSI, EL-I
Semester: I Branch: EIE
Duration: 3 Hours Total Marks: 50

Note:
1. Attempt all parts of a question in sequence.
2. Assume suitable data wherever required.
3. Figure in the right hand margin indicates full marks for the question.

Part A: Mini Project:

Q1. Consider a CMOS inverter with the device parameters as
VT0,n = 0.8V, µ𝑛 Cox = 70µA/V2
VT0,p = -1V, µ𝑝 Cox = 40µA/V2
VDD = 5V, both transistors have equal channel length of 1 µm. The total output load capacitance is
Cout = 500fF + Cdb,n + Cdb,p
Where, the drain to body parasitic capacitances are functions of channel width as
Cdb,n = (100 + 9 Wn)fF
Cdb,p = (80 + 7Wp)fF
a) Determine the channel width of both the transistors such that the propagation delay is smaller
than 0.9ns and the switching threshold is designed to be 2.75V. Assume the input as an ideal
step signal. (10)
b) Assume the input as an ideal step signal and (W/L)n = 10 and (W/L)p = 30. Calculate and
compare the rise time and fall time of the output signal using both
b1) Average current method. (4+4)
b2) Differential equation method. (6+6)
c) For part (b), determine the maximum frequency of a periodic square-wave input signal so that
the output voltage have a full logic swing in each cycle. (6)
d) Calculate the dynamic power dissipation at maximum frequency obtained in (c). (4)

Part B:
Q2. A CMOS logic gate that implements the function
F = X . (Y+Z) + X . W
is needed in a control network. Design the logic circuit, schematic circuit and draw the stick
diagram using Euler’s method. (10)