EE671: VLSI DESIGN

ASSIGNMMENT-3
Name: M. Naresh Kumar
Roll no: 193070081

Q.1. Designed Dadda multiplier for unsigned 16x16 bit multiplication diagram.

In the figures below pp0 to pp15 represent partial products 00 to 15 for the first stage,for
2nd stage I assumed q0 to q12 as max. capacity of layer 2 is 13, similarly for all stages.
Simulated Results for various test vectors:
When inputs A=(65534)10 and B==(36856)10
When inputs A==(65534)10 and B==(65534)10

When inputs A=(65534)10 and B==(32769)10

Theoretically dada multiplier will take 2650ps time to take produce the final bits
and brent kung adder will take 3150ps to add final bits coming from the final layers
,so worse case delay will be 5800ps.so, 5800ps time i can guarantee that the
multiplication will be complete.