Format No:LP01

Issue No:01
Issue Date: 07/01/09

SRM INSTITUTE OF SCIENCE AND TECHNOLOGY

Ramapuram, Chennai-600089
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
LESSON PLAN- THEORY
ACADEMIC YEAR (2020-21 EVEN)
Degree/ Branch: B.Tech /CSE WITH SPECIALIZATION BDA - A
Subject Code: 18CSS201J Total no. of Hours given in syllabus: 105
Subject Name:ANALOG AND DIGITAL ELECTRONICS Lecture Hours: 75
Year /Sem : II / 3 Practical:30

Refere Date Date

Lecture Planned Actually Teaching
S.No Lesson /Topic Covered nce
Hours Taken Methodology
Books

UNIT I (9)

Characteristics of BJT (CB, CE and

1 CC 1
configurations) and DC biasing,

2 BJT Uses 1

Characteristics and uses of JFET (CS,

3 1
Common Drain and Common Gate)

4 Transistor Amplifier: CE amplifier 1

Transistor Amplifier: CC ,CB

5 1
amplifier

Power Amplifiers: Different classes of

6 Amplifiers and its operation-Class A, 1
Class B, AB and C

Operational Amplifiers: Ideal v/s

7 practical 1
Op-amp Performance Parameters

Applications: Peak detector, 1

8 Comparator,
Inverting, Non-Inverting Amplifiers

Effect of positive and Negative 1

Feedback
9 Amplifiers, Analysis of Practical
Feedback Amplifiers

Oscillator Operation, Crystal 1

Oscillator
 Overview of UJT, Relaxation 1
Oscillator,555
Timer
CLA-1

UNIT II (9)

Transistor as a Switch, Characteristics

1 2
of Digital ICs

2 DL, RTL, DTL,TTL 2

3 ECL, IIL, 2

Characteristics and uses of MOSFET

4 (CS, 2
Common drain and Common gate)

5 MOSFET Logic, PMOS,NMOS 2

6 CMOS Logic, Propagation delay 2

Tristate Logic, Tristate Logic

7 2
Applications

FPGA Basics, Introduction to HDL 2

8 and logic simulation

HDL System primitives, user defined 2

primitives, Stimulus to the design

UNIT III (9)

Quine-McCluskey minimization
1 technique
4

Combinational Circuits, Multiplexer, 4

2 Demultiplexer

3 Decoder, Encoder 4

Binary adder, Binary adder as 4

4 subtractor

Carry look ahead adder, Decimal 4

5 adder

Magnitude Comparator. Read Only 4

6 Memory

Arithmetic Logic Unit, Programmable 4

7 Logic Arrays

HDL Gate and Data Flow modeling, 4

8 HDL Behavioral modeling

9
CLA-2
 UNIT IV (9)

Sequential circuits, Latch and Flip- 5

1 Flops, RS Flip-Flops,

Gated Flip-Flops, Edge-triggered RS 5

2 FLIP-FLOP

Edge-triggered D FLIP-FLOPs, Edge- 5

3 triggered T FLIP-FLOPs

4 Edge-triggered JK FLIPFLOPs, 5

5 JK Master-slave FLIP-FLOP, 5

Analysis of Synchronous Sequential 5

Circuit,
6 State Equation, State table, State
Diagram

Synthesis of sequential circuit using 5

7 Flip-Flops

Asynchronous sequential circuit, 5

8 Transition Table, State table

9 Flow table 5

Analysis of asynchronous sequential 5

circuits

UNIT V (9)

Registers and Types of Registers- 6

1 Serial In -
Serial Out, Serial In - Parallel out

Parallel In - Serial Out, Parallel In - 6

2 Parallel
Out

Universal Shift Register, Applications 6

3 of Shift Registers

Synchronous Counters, Asynchronous 6

4 Counters Changing the Counter
Modulus

5 Decade Counters, Presettable counters 6

Counter Design as a Synthesis 6

6 problem Seven segment Display and
A Digital Clock.

D/A Conversion, Types of D/A 6

7 Converters
 Types of D/A Converters, Problems, 6
8 A/D Conversion

9 Types of A/D conversion 6

CLA-3

CLA-4(Assignments, Seminars, Tech

Talks, Mini-Projects, Case-Studies,
Self-Study, MOOCs, Certifications,
Conf. Paper etc.,)

REFERENCES:

1. Robert L. Boylestad& Louis Nashelsky, Electronic Devices & Circuit Theory, 11th ed., Pearson, 2013
2. Anil K Maini, Varsha Agarwal: Electronic Devices and Circuits, Wiley, 2012
3. Paul Tuinenga, SPICE: A Guide to Circuit Simulation and Analysis Using PSpice, 3rd ed., Prentice-
Hall,1995,
4. Douglas A, G.K. Kharate, Digital Electronics, Oxford university Press,2012
5. M. Morris R. Mano, Michael D. Ciletti, Digital Design: With an Introduction to the Verilog HDL,
VHDL, andSystemVerilog, 6th ed., Pearson, 2018
6. A.P. Malvino, Electronic Principles,7th Edition, Tata Mcgraw Hill Publications, 2013

COURSE CO-ORDINATOR HOD CSE