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Name:
Reg. No:
Slot:
Faculty Name:
Cycle – 1
S.No. Date Name of the Experiment Marks Remarks
Verification of DC circuit using Mesh and Nodal
1. 09-10-20
Analysis
2. Verification of Thevenin’s Theorem
Verification of Maximum Power Transfer theorem
3.
using DC Parametric Sweep Analysis
Resonance in a Series RLC Circuit using AC
4.
Parametric Sweep Analysis
Design of Uncontrolled Rectifier Circuit with
5.
Different loads
Cycle – 2
S.No. Date Name of the Experiment Marks Remarks
Binary Addition using Logic Gates - Verification of
6.
Half-Adder and Full adder Logic Circuits
7. Regulated Power Supply Using Zener Diode
Implementation of 4x1 multiplexer and 1x4
8.
demultiplexer using logic gates
Input and Output Characteristics of BJT using
9.
Pspice
Realization of logic functions with the help of
10.
universal gates NAND and NOR Gate.
Ex. No.: 01 Date:
1.1 Aim
Construct resistive circuits and analyse the circuits using Nodal Analysis and Mesh
Analysis
1.2 Circuit
8V VDC
1.4 Procedure
1. Create the given circuit diagram in new project file using the general procedure.
2. Replace the default component value and source value as per given circuit diagram.
3. Create the New simulation profile and set analysis type as Bias point
4. Run the simulation and note down the readings in tabulation.
5. Compare the simulated results with solved values.
1.9 Summary
Thus the given circuit is verified with mesh and nodal analysis using Pspice
simulation and theoretically verified.