GUJRAT TECHNOLOGICAL UNIVERSITY

Chandkheda, Ahmedabad

BIRLA VISHVAKARMA MAHAVIDYALAYA

Engineering College, V. V. Nagar, Anand

A Project Report
On

Video Graphics Array (VGA)

Under the subject of

Digital Design (2151007)

B. E. – III, SEMESTER: V

(Electronics Engineering)

Submitted by:

1) Harshvardhan Patel 130070110047

2) Parth Sarvaiya 130070110060

Prof. C. S. Patel Dr. T. D. Pawar

(Faculty Guide) (Head of the Dept.)

Academic Year: 2015-16

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 BIRLA VISHVAKARMA MAHAVIDYALAYA
Engineering College, V. V. Nagar, Anand

Department of Electronics Engineering

CERTIFICATE

This is to certify that the project entitled ‘Video Graphics Array (VGA)’ has
been carried out by Harshvardhan Patel (130070110047) and Parth Sarvaiya (130070110060)
under my guidance and supervise, on for the award of the degree of the Bachelor of Engineering
in Electronics Engineering (Semester: V) at Birla Vishvakarma Mahavidyalaya, Engineering
College during the academic year 2015 – 16.

Date:

Prof. C. S. Patel Dr. T. D. Pawar

(Faculty Guide) (Head of Dept)

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ACKNOWLEDGEMENT:

We take this opportunity to express our profound gratitude and deep regards to our Head of Dept.
Dr. T. D. Pawar for giving us opportunity to undertake this project work.

We would like to express our heartfelt gratitude to our faculty and Project guide Prof. C. S. Patel
for his exemplary guidance, monitor and constant encouragement throughout the term work. The
blessings, help and guidance given by him time to time shall carry us a long way in the academic journey
of our life.

We are obliged to the staff members of Electronics Dept. for their support. We are grateful to
Parth Parikh (Semester VII) for his cooperation during the project work.

Lastly, we thankful to almighty, our parents and classmates for constant support.

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Abstract:

Video Graphics Array (VGA) refers specifically to the

display hardware first introduced with the IBM PS/2 line of
computers in 1987, but through its widespread adoption has also
come to mean either an Amplitude Modulated computer display
standard, the 15-pin D-subminiature VGA connector or
the 640x480 resolution itself.
VGA was the last IBM graphics standard to which the
majority of PC clone manufacturers conformed, making it the lowest common denominator that
virtually all post-1990 PC graphics hardware can be expected to implement. It was officially
followed by IBM's Extended Graphics Array (XGA) standard.
Here, we try to interface the simple 8 bit image on desktop screen via Basys - 3 FPGA
(Field Programming Gate Array) board in VHDL language. Output of VGA project is 155*175
pixels image that consists of 8 bit color code.
As we define a VGA project as top module, it required bunch of sub modules and that
are….VHDL codes in XILINX Vivado software, generating block Ram for image which is
extracted in suitable form that can be recognized by FPGA board via MATLAB software and 15
pin VGA connector to show output on desktop.

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INDEX:

1) Introduction 6

2) Video Graphics Array 6

3) Field Programming Gate Array 8

4) VGA Controller 11

5) VHDL codes 13

6) Constraints file 7

7) Output 20

8) Reference 21

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Introduction:

Video Graphics Array (VGA):

Video Graphics Array (VGA) refers
specifically to the display hardware first
introduced with the IBM PS/2 line of
computers in 1987,[1] but through its
widespread adoption has also come to
mean either an Amplitude
Modulated computer display standard, the
15-pin D-subminiature VGA connector or
the 640x480 resolution itself.
VGA was the last IBM graphics standard
to which the majority of PC
clone manufacturers conformed, making it the lowest common denominator that virtually all
post-1990 PC graphics hardware can be expected to implement. It was officially followed by
IBM's Extended Graphics Array (XGA) standard, but was effectively superseded by numerous
slightly different extensions to VGA made by clone manufacturers, collectively known as Super
VGA.
Today, the VGA analog interface is used for high definition video, including resolutions
of 1080p and higher. While the transmission bandwidth of VGA is high enough to support even
higher resolution playback, there can be picture quality degradation depending on cable quality
and length. How discernible this degradation is depends on the individual's eyesight and the
display, though it is more noticeable when switching to and from digital inputs
like HDMI or DVI.

Technical Specification:

VGA is referred to as an "Array" instead of an "adapter" because it was implemented

from the start as a single chip—an application-specific integrated circuit which replaced both
the Motorola 6845 video address generator as well as dozens of discreet logic chips that covered
the full-length ISA boards of the MDA, CGA, and EGA. Its single-chip implementation allowed
the VGA to be placed directly on a PC′s motherboard with a minimum of difficulty, since it only
required video memory, timing crystals and an external RAMDAC. As a result, the first IBM
PS/2 models were equipped with VGA on the motherboard, in contrast to all of the "family one"

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IBM PC desktop models—the PC, PC/XT, and PC AT—which required a display adapter
installed in a slot in order to connect a monitor.

Specifications:
The original VGA specifications are as follows:

 256 kB Video RAM (The very first cards could be ordered with 64 kB or 128 kB of RAM, at
the cost of losing some or all high-resolution 16-color modes.)
 16-color and 256-color palette display modes.
 Selectable 25.175 MHz[4] or 28.322 MHz master pixel clock
 Usual line rate fixed at 31.469 kHz
 Maximum of 800 horizontal pixels[5]
 Maximum of 600 lines[5]
 Refresh rates at up to 70 Hz
 0.7 V peak-to-peak[7]
 75 ohm double-terminated impedance (18.7 mA, 13 mW)

Signal Timings:
All derived VGA timings can be varied widely by software that bypasses the VGA firmware
interface and communicates directly with the VGA hardware.

Parameter Value Unit

 Pixel clock frequency 25.175 MHz

 Horizontal frequency 31.469 kHz
 Horizontal pixels 640
 Horizontal sync polarity Negative
 Total time for each line 31.778 µs
 Front porch (A) 0.636 µs
 Sync pulse length (B) 3.813 µs
 Back porch (C) 1.907 µs
 Active video (D) 25.422 µs

Total horizontal sync and blanking time = 6.356 µs; equivalent to pixel widths of A = 16, B = 96,

C = 48, D = 640 and each complete line = 800

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Typical uses:

 640x400 @ 70 Hz is traditionally the video mode used for booting most VGA-
compatible x86 personal computers which show a graphical boot screen (text-mode boot
uses 720x400 @ 70 Hz).
 640x480 @ 60 Hz is the default Windows graphics mode (usually with 16 colors) up to
Windows 2000. It remains an option in XP and later versions via the boot menu "low
resolution video" option and per-application compatibility mode settings.
 320x200 @ 70 Hz is the most common mode for VGA-era PC games, using exactly the same
timings as the 640x400 mode, but halving the pixel rate (and, in 256 color mode, doubling
the bit-depth of each pixel) and displaying each line of pixels twice.
P. S.: In our application, we have used the 640*480 pixels VGA mode with 8 bit color code.

VGA Connectors:

VGA uses a DE-15 connector. This connector fits on the

mounting tab of an ISA expansion card.

An alternative method of connecting VGA devices that

maintains very high signal quality is the BNC connector,
typically used as a group of five connectors, one each for Red,
Green, Blue, Horizontal Sync, and Vertical Sync. With BNC,
the coaxial wires are fully shielded end-to-end and through the inter connect so that no crosstalk
or external interference is possible.

Field Programming Gate Array:

A field-programmable gate array (FPGA) is an integrated circuit designed to be
configured by a customer or a designer after manufacturing – hence "field-programmable". The
FPGA configuration is generally specified using
a hardware description language (HDL), similar to
that used for an application-specific integrated
circuit (ASIC). (Circuit diagrams were previously
used to specify the configuration, as they were for
ASICs, but this is increasingly rare.)
FPGAs contain an array
of programmable logic blocks, and a hierarchy of
reconfigurable interconnects that allow the blocks to
be "wired together", like many logic gates that can

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be inter-wired in different configurations. Logic blocks can be configured to perform
complex combinational functions, or merely simple logic gates like AND and XOR. In most
FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more
complete blocks of memory.
Here, the basic functionality of the project is to generate the image on screen via FPGA board
and for that we have selected XILINX BasysTM – 3 boards.

Overview:
The Basys3 board is a complete, ready-to-use digital circuit development platform based on the
latest Artix -7 Field Programmable Gate Array (FPGA) from Xilinx. With its high-capacity
FPGA, low overall cost, and collection of USB, VGA, and other ports, the Basys3 can host
designs ranging from introductory combinational circuits to complex sequential circuits like
embedded processors and controllers. It includes enough switches, LEDs, and other I/O devices
to allow a large number of designs to be completed without the need for any additional hardware,
and enough uncommitted FPGA I/O pins to allow designs to be expanded using Digilent Pmods
or other custom boards and circuits.
The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher
performance, and more resources than earlier designs. Artix-7 35T features include:

• 33,280 logic cells in 5200 slices (each slice contains four 6-input LUTs and 8 flip-flops)
• 1,800 Kbits of fast block RAM
• Five clock management tiles, each with a phase-locked loop (PLL)
• 90 DSP slices
• Internal clock speeds exceeding 450MHz
• On-chip analog-to-digital converter (XADC)

BasysTM – 3 Layouts:

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Callout Component Callout Component
Description Description
1 Power good LED 9 FPGA configuration
reset button
2 Pmod connector(s) 10 Programming mode
jumper
3 Analog signal Pmod 11 USB host connector
connector (XADC)
4 Four digit 7-segment 12 VGA connector
display
5 Slide switches (16) 13 Shared UART/ JTAG
USB port
6 LEDs (16) 14 External power
connector
7 Pushbuttons (5) 15 Power Switch
8 FPGA programming 16 Power Select Jumper
done LED

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VGA controller:

VGA (video graphics array) is a video display standard introduced in the late 1980s in
IBM PCs and is widely supported by PC graphics hardware and monitors. We discuss the design
of a basic eight-color 640-by-480 resolution interface for CRT (cathode ray tube) Monitors /
LCD monitor in this section. CRT synchronization and basic graphic processing are examined in
this part.

Basic operation of CRT:

The conceptual sketch of a monochrome CRT monitor is shown in fig.. The electron gun
(cathode) generates a focused electron beam, which traverses a vacuum tube and eventually hits
the phosphorescent screen; Light is emitted at the instant that electrons hit a phosphor dot on the
screen. The intensity of the electron beam and the brightness of the dot are determined by the
voltage level of the external video input signal, labeled mono in Figure 12.1. The mono signal is
an analog signal whose voltage level is between 0 and 0.7 V.

VGA Synchronization:

The video synchronization circuit generates the hsync signal, which specifies the required time to
traverse (scan) a row, and the vsync signal, which specifies the required time to traverse (scan)
the entire screen. Subsequent discussions are based on a 640-by-480 VGA screen with a 25-MHz
pixel rate, which means that 25M pixels are processed in a second.

Note that this resolution is also known as the VGA mode. The screen of a CRT monitor
usually includes a small black border. The middle rectangle is the visible portion. Note that the
co ordinate of the vertical axis increases downward. The coordinates of the top-left and bottom-
right corners are (0, 0) and (639,479), respectively.
Figure 3 illustrates the timing signals produced by the VGA controller. The controller contains
two counters. One counters increments on pixel clocks and controls the timing of

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the hsync (horizontal sync) signal. By setting it up such that the display time starts at counter
value 0, the counter value equals the pixel’s column coordinate during the display time. The
horizontal display time is followed by a blanking time, which includes a horizontal front porch,
the horizontal sync pulse itself, and the horizontal back porch, each of specified duration. At the
end of the row, the counter resets to start the next row.
The other counter increments as each row completes, therefore controlling the timing of
the vsync (vertical sync) signal. Again, this is set up such that the display time starts at counter
value 0, so the counter value equals the pixel’s row coordinate during the display time. As
before, the vertical display time is followed by a blanking time, with its corresponding front
porch, sync pulse, and back porch. Once the vertical blanking time completes, the counter resets
to begin the next screen refresh.
A display enable is defined by the logical AND of the horizontal and vertical display times.
Using these counters, the VGA controller outputs the horizontal sync, vertical sync, display
enable, and pixel coordinate signals. The sync pulses are specified as positive or negative
polarity for each VGA mode. The GENERIC parameters hpol (horizontal polarity)

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and vpol (vertical polarity) set the polarity of the VGA controller’s hsync and vsync outputs,
respectively

VGA color combinations:

VHDL Code:
Vivado Design Suite is a software suite produced by Xilinx for synthesis and analysis
of HDL designs, superseding Xilinx ISE with additional features for system on a
chip development and high-level synthesis.[3][4][5] Vivado represents a ground-up rewrite and re
thinking of the entire design flow (compared to ISE), and has been described by reviewers as
"well conceived, tightly integrated, blazing fast, scalable, maintainable, and intuitive".[6][7][8]
Unlike ISE which relied on ModelSim for simulation,[9][10] the Vivado System Edition includes
an in-built logic simulator.[11] Vivado also introduces high-level synthesis, with a toolchain that

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converts C code into programmable logic.[4] Vivado has been described as a "state-of-the-art
comprehensive EDA tool with all the latest bells and whistles in terms of data model, integration,
algorithms, and performance".

XILINX VIVADO _new project and parameters to select the BASYSTM – 3 FPGA board.

----------------------------------------------------------------------------------

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-- Design Name: VGA Controller
-- Module Name: VGA_sync - Behavioral
-- Project Name: VGA
-- Target Devices: XILINX BASYSTM - 3
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: Semester Project of Digital Design SEM: V
--
----------------------------------------------------------------------------------
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity VGA_sync is
Port ( clk : in STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
Red : out STD_LOGIC_VECTOR (2 downto 0);
Green : out STD_LOGIC_VECTOR (2 downto 0);
Blue : out STD_LOGIC_VECTOR (2 downto 1));
end VGA_sync;

architecture Behavioral of VGA_sync is

-- component clock port(CLK_IN: in std_logic;CLK_OUT:out std_logic);

signal hcount:integer range 0 to 1023 := 640;
signal vcount:integer range 0 to 1023 := 480;
signal v_clk:std_logic;

signal data: std_logic_vector(7 downto 0);

signal addr: std_logic_vector(15 downto 0);

component clkGen is
port(CLK_IN1:in std_logic;CLK_OUT1:out std_logic);
end component;

component ram
port(clka:in std_logic;

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 addra:in std_logic_vector(15 downto 0):=(others=>'0');
douta:out std_logic_vector(7 downto 0));
end component;

begin
clk1: clkGen port map(CLK_IN1 =>clk,CLK_OUT1=>v_clk);
pic_ram:ram port map(clka=>v_clk,addra=>addr,douta=>data);

--Frame Reset
process(v_clk)
begin
if v_clk'event and v_clk='0' then
if hcount = 799 then
hcount <= 0;
if vcount = 524 then
vcount <= 0;
else
vcount <= vcount + 1;
end if;
else
hcount<=hcount +1;
end if;
end if;
end process;

--Sync process
process(hcount,vcount)
begin
if hcount >= 656 and hcount <752 then
hsync <= '0';
else
hsync <= '1';
end if;

if vcount = 489 or vcount = 490 then

vsync<='0';
else
vsync<='1';
end if;

if hcount<640 and vcount<480 then

if hcount<255 and vcount<255 then
addr<= std_logic_vector(TO_UNSIGNED(hcount +
255*vcount,16));

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 Red<=data(7 downto 5);
Green<=data(4 downto 2);
Blue<=data(1 downto 0);
else
addr <= (others=>'Z');
Blue <= "11";
Green <="000";
Red <= "000";
end if;
else
Blue <= "11";
Green <="000";
Red <= "000";
end if;
end process;
end Behavioral;

---------------------------------------------------------------------------------------------------

Constraints file of Project:

It is very important to map your variables of code to I/O ports of FPGA board. It seems that
converting the high level language into machine level language. To generate the Constraints
file….it required to perform the following steps……

1) Write your VGA – synchronization and controller code in XILINX VIVADO software
and check it for probable error.
2) If code is logical and errorless then perform ‘ Run Synthesis ‘….It will check your code
and give three options…..
1) Open Synthesis Design
2) Run implementations
3) View Report

3) To generate the constraint file, perform the first step and Open I/O planning. Every FPGA
board has its unique I/O port that we have to assign it according to our application. In
BASYSTM – 3 board, Shown in below fig.

Map the variables of codes, add ‘VCCO’ and ‘CONFIG. VOLTAGE’ through ‘ EDIT DEVICE
PROPERTIES’ and save it as a Constraint file. It will convert the high level language to machine
level language.

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.XDC file:
set_property PACKAGE_PIN N18 [get_ports {Blue[1]}]
set_property PACKAGE_PIN L18 [get_ports {Blue[2]}]
set_property PACKAGE_PIN J17 [get_ports {Green[0]}]
set_property PACKAGE_PIN H17 [get_ports {Green[1]}]
set_property PACKAGE_PIN G17 [get_ports {Green[2]}]
set_property PACKAGE_PIN G19 [get_ports {Red[0]}]
set_property PACKAGE_PIN H19 [get_ports {Red[1]}]
set_property PACKAGE_PIN J19 [get_ports {Red[2]}]
set_property PACKAGE_PIN W5 [get_ports clk]
set_property PACKAGE_PIN P19 [get_ports hsync]
set_property PACKAGE_PIN R19 [get_ports vsync]
set_property IOSTANDARD LVCMOS33 [get_ports {Blue[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Blue[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Green[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Green[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Green[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Red[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Red[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Red[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports hsync]
set_property IOSTANDARD LVCMOS33 [get_ports vsync]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

After generating ‘constraint file’ , it is necessary to generate block ram and clock wizard for
image, and image must be in extracted form via ‘MATLAB’ or ‘PYTHON’ software to convert
VGA Controller BASYSTM - 3 Page 18
image into .COE file that can be understood by FPGA board, which will show as a output on
desktop screen.

XILINX Vivado block ram and clock wizard generator using Existing inbuilt IP.

After generating block ram and clock wizard, click on ‘ Run implementation’ and ‘ generate
bitstream’, it will give two options to user.

1) View reports
2) Open Hardware manager….

First option will give each and every specifications about project.

Second option will give access to interface the FPGA board with PC to check the output on
hardware through dump code via Mini USB port on FPGA board.

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Output:

155*175 pixels image of tiger with 8 bit color code is shown on LCD monitor

XILINX BASYSTM - 3 FPGA board is connected with VGA connector.

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Reference:

1) FPGA prototype by VHDL examples; Author: Pong P. Chu

2) WWW.xilinx.com
3) www.digilentinc.com

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