Vol. 1, No.

Circuit Monitors and Protects Against Power

Supply Overvoltage
Systems incorporating microprocessors, FPGA, ASICs and other
expensive devices can sustain costly damage if the power supply voltages
exceed the nominal values. Rather than hoping for the best, good design
practice says you should add circuitry that will indicate an overvoltage
(OV) condition, take corrective action, take protective action, or perform a
combination of all of these functions.

Electronic Load Achieves 0 Ω

The general approach to an electronic load is to use a transistor across
the input terminals so the current flows from drain (collector) to source
(emitter). A resistance is affected by causing a current flow in proportion
to the applied voltage in the manner of a resistor, I = V/R. A controller
monitors the applied voltage and adjusts the current in response. To
achieve 0 Ω, the terminal voltage must be 0 in the presence of a current.

Determine MOSFET Junction Temperature and

Switching Losses for Various Package Types
The junction temperature of power MOSFETs is one of the major criteria
used to obtain temperature derating curves for power converters. This
article describes an improved technique for determining MOSFET
junction temperature and switching losses more accurately based on
the given thermal resistances and lead and case (package) temperature
measurements.

Do you have Electronic Design is always on the lookout for new

an Idea for ideas. Do you have one? Our Ideas for Design
Design for articles are short and to the point, often with a single
Electronic figure or program listing to help explain the idea. If
Design? you would like to submit one, you can check out the
details at
https://www.electronicdesign.com/contribute.
We look forward to seeing your ideas.
 for Design
BRAD ALBING | INTERSIL CORP.

Circuit Monitors And Protects

balbing@intersil.com
Ideas
Against Power Supply Overvoltage
SYSTEMS INCORPORATING MICROPROCES- VIn VIn The divider resistors are R1 and R2
SORS, FPGAs, ASICs, and other expen- (3.40 V) (3.60 V) (upper and lower resistors, respectively),
sive devices can sustain costly damage which set the overvoltage trip-point for
if the power supply voltages exceed the R1 R3 the ISL6132’s OVMON_1 input, and
nominal values. Rather than hoping for 8.66k 9.38k R3 and R4, which set the overvoltage
the best, good design practice says you OVMON_1 OVMON_2 trip-point for OVMON_2 (Fig. 1). For
should add circuitry that will indicate an (633 mV) (633 mV) example, assume the system operates
overvoltage (OV) condition, take cor- R2 R4 with a 3.30-V dc bus. Then assume we
rective action, take protective action, or 2.00k 2.00k want an alarm indication to occur if the
perform a combination of all of these supply bus voltage rises to 3.40 V dc,
functions. and we want to take protective action if
The OV indicator can be an audible 1. The overvoltage protection circuit employs two the voltage rises to 3.60 V dc.
or visual alarm. Correction can take the voltage divider circuits that set the overvoltage The voltage dividers reduce the
form of additional active circuitry that trip points for the voltage monitoring/supervising applied voltage to match the ISL6132’s
adjusts or clamps the higher-than-nor- IC, inputs OVMON_1 and OVMON_2. internal reference voltage. The internal
mal voltage. Protection usually involves comparators act when the applied volt-
forcibly shutting down the power supply. age just exceeds the reference voltage. Assuming that the input
To decide if an OV condition exists, you will probably want current to the comparator is negligible, and the reference volt-
to use a separate, standalone detection circuit with an accurate age is typically 633 mV, the standard voltage divider formula
trip-point. The advantage of a standalone detector compared provides the resistor values:
to a power supply that detects its own overvoltage condition
becomes clear if a failure mode effects analysis is performed. VOut = VIn – R2/(R1 + R2)
With separate circuitry, a single-point failure can be prevented
from causing an overvoltage condition. where VOut is 633 mV, and VIn is 3.40 V or 3.60 V. If you select
To get an accurate trip-point, avoid using Zener diodes. R2 as some standard value, e.g., 2.00 kΩ, you can calculate R1.
They generally have poor initial accuracy, an undesirable For the 3.40-V detection circuitry, R1 is 8.74 kΩ. For the
temperature coefficient, and an undesirable voltage versus cur- 3.60-V detector, R1 is 9.38 kΩ. For practical purposes, pick the
rent characteristic (a soft knee). A voltage reference diode/IC nearest 1% values. To add some adjustment range in the trip-
or a voltage monitoring IC will provide better results. These points, insert a trimmer potentiometer between the upper and
devices usually feature an accurate, sta- lower resistors (Fig. 2).
VIn VIn
ble comparator and an accurate voltage For example, use a 500-Ω trim-pot
(3.40 V) (3.60 V)
reference, and they may include on-chip and subtract 250 Ω from each of the
voltage divider resistors. Designers can R1 R3
upper and lower resistor values. Then,
also add voltage divider resistors exter- 8.45k 9.09k pick the nearest standard value. The
nal to the IC. If so, they should be accu- result is 8.45 kΩ, 500 Ω, and 1.74 kΩ for
R5 OVMON_1 R6 OVMON_2
rate (1% tolerance or better) resistors 500 (633 mV) 500 (633 mV) the 3.40-V divider and 9.09 kΩ, 500 Ω,
with a low temperature coefficient. and 1.74 kΩ for the 3.60-V divider.
The Intersil ISL6132 is an easy to use, R2 R4 Those who would prefer to avoid
flexible voltage monitoring/supervising 1.74k 1.74k algebraic manipulation can use an alter-
IC. It has two comparators intended for native method for calculating the divider
undervoltage detection, two comparators resistor values. As before, assume you
for overvoltage detection, and an accu- 2. The addition of trimmer potentiometers to the want to get a specific output voltage,
rate reference voltage. This application divider circuits provides the ability to make makes VOut, from the divider with a specific
uses the two OV detectors to implement adjustments to the trip points. The divider resis- input voltage, V In, and that the input
two of the three previously described tors’ values should be modified to account for the current to the comparator is negligible
functions: indication and protection. potentiometers’ values. (Fig. 3).

ELECTRONIC DESIGN GO TO WWW.ELECTRONICDESIGN.COM

IdeasForDesign

Select the lower resistor, R1, as some
convenient value—1.0 kΩ, 10 kΩ, or
such. Using Ohm’s law, calculate the
current through that resistor: V In/R1.
This is also the current through the upper
resistor, R2. The voltage across R2 is
VIn less VOut. R2 can then be calculated
using Ohm’s law.
If you want to minimize the response
to very narrow voltage transients, you
can add small capacitors (C1 and C2)
between the potentiometers’ wipers
and the circuit’s common ground (Fig. (OVSTATUS_2) can be used to shut off
4). Typically, 1 nF to 0.1 µF is suf- the monitored power supply.
ficient. Since the circuit does not use The preferred implementation (which
the ISL6132’s undervoltage detection is usually called a crowbar circuit) con-
inputs (UVMON_1 and UVMON_2), sists of a silicon controlled rectifier
they should be connected to the circuit’s (SCR) that’s connected across the pow-
common ground. er supply bus being protected. OVSTA-
The device’s overvoltage 1 output TUS_2 triggers the SCR’s gate. The
(OVSTATUS_1) can be used to light gate should be bypassed with a 0.1-µF
an LED, energize an audible alarm, or capacitor so the SCR isn’t triggered
provide an input to an FPGA or micro- by the rapid dv/dt of the supply bus at
processor. The overvoltage 2 output power-up.

VIn To LED, audible alarm, FPGA, or microprocessor

From output
of regulator
being
monitored
OVSTATUS_1

OVSTATUS_2
R2 R1
UVSTATUS_1

UVSTATUS_2
8.45k
Alternate
VOut R5 connection:
500 raw dc
VDD input to
R1 regulator
R2 1.0k
UVMON_1 1.74k SCR1
GND
UVMON_2

OVMON_1
3. An alternative method of determining the PGOOD1 OVMON_2 1.0k 0.1 µF
voltage divider resistors involves using the PGOOD2 R3
9.09k
known voltages, VIn and VOut, and simple
Ohm’s law calculations. C1 R6
500

R4
C2
Brad alBing is a senior field 1.74k

applications engineer at intersil,

with almost 30 years experience
in electronic design. He holds a 4. The complete circuit includes two capacitors, C1 and C2, that minimize its response to very narrow
BSE from the University of akron. voltage transients. The IC’s OVSTATUS_2 output triggers the SCR connected across the power supply.

henry SanTana | hsantana@pacbell.net

Electronic Load Achieves 0 Ω

The general approach to an electronic load is to use a transis-
tor across the input terminals so the current flows from drain
(collector) to source (emitter). A resistance is effected by caus-
ing a current flow in proportion to the applied voltage in the
manner of a resistor, I = V/R. A controller monitors the applied
voltage and adjusts the current in response (Fig. 1).
To achieve 0 Ω, the terminal voltage must be 0 in the pres-
ence of a current. Under this condition the pass transistor suf-
fers a loss of operating voltage and cannot conduct a current.
To maintain conduction of the pass transistor, an auxiliary
power supply is connected (Fig. 2). The required voltage, VB
≥ IIn(max) × RS + VDS@I(max), is sufficient to maintain forward
conduction with VIn = 0 and 0 < IIn ≤ IIn(max). This condition
corresponds to an effective zero input resistance.
It can be shown that RIn = α × k × RS for 0 ≤ α ≤ 1 and
where k multiplies RS so it can be made small to reduce power
loss. If, for example, RS = 1.0 Ω, k = 100, then 0 ≤ RIn ≤ 100
Ω for 0 ≤ α ≤ 1. If IIn(max) = 1 A and VDS@I(max) = 2 V, then VB
≥ 3 V.
In virtually all applications, the pass transistor must be
heatsinked as the power dissipated is IIn(max) × (VIn(max) +
VB) – IIn(max)2 × RS. If in this example VIn(max) = 15 V, the pass

ElEctronic DEsign
IdeasForDesign

transistor would have a maximum dissipation of 17 W. This
would appear as a 15-W resistor adjustable over 0 to 100 Ω.
You may be wondering why an additional power source was
introduced between the source of the MOSFET and the current
sense resistor to achieve a “0-Ω load” condition (essentially a
short across input voltage) in Figure 2. After all, why would
you need an electronic load that can go down to 0 V (i.e., short
circuit) condition?
If you wanted to short an electronic load, you could always
use a relay directly across the input voltage. Or if you wanted
it to be all solid state, you could place another MOSFET that
has much higher current capacity (and very low RDS(on) that
approaches a few milliohms) directly across the input and turn
it on using a switch. This approach would be much simpler
(and cost effective) than adding a second power supply in
series with sense resistor. So, why would you use the addi-
tional power source?
Here’s the answer. This electronic load can check low-
voltage power supplies (i.e., 3.3 V and lower) where a voltage
burden (i.e., 1 V) would not permit testing under short-circuit
condition. This is useful in testing the short-circuit response of
power supplies, current trip level, and effectiveness of over-
load protection.
Furthermore, even with a low RDS(on), a MOSFET will not
conduct at 0 V (VDS). At high currents, a MOSFET requires
non-zero voltage (see note A) to sustain conduction. This cir-
cuit will maintain VDS right into a virtual short circuit.
Finally, a hard switch such as a relay does not permit a
smooth transition of resistance. The circuit described here
acts more like a rheostat but with the ability to be voltage con-
trolled (see note B) from a remote point. The controller does
not have to carry the load current. It would require multiple
relays to apply a range of loading. This circuit can provide
smooth (stepless) effective resistive loading over a large range
including 0 Ω.
The circuit can be scaled up to higher voltages and currents.
Figure 3 shows an application. For a derivation of the equa-
tions, e-mail the author at hsantana@pacbell.net.
Note A: For example, an RFP30N06 MOSFET has a specified RDS(on)
of 0.047 Ω. At 30 A this device requires at least 2 V VDS. This would
not be an effective short circuit on a 3.3-V, 30-A power supply. On a
1.8-V supply, it would not conduct this current.
Note B: The effective resistance can be controlled with a voltage-
controlled amplifier (see “Op Amp And Two JFETs Form A Voltage-
Controlled Amplifier” at electronicdesign.com).

IIn RIn = ȼ × k × RS
IIn
VIn
VIn
Q D A1 15 V max
0 < RIn ≤ a × k × RS +15 V
+ Q1 RFP12N10L LT1006 1.0 A max
Aż∞ 1.0 µF
A 7 3 C2
+
– G
I In 6 2 0 ≤ RIn ≤ 100
4 –
S
CW 3 RS –15 V
2 –
k
2.5 V
a 1 C1 0.1 µF
+
A2 +24 V R4
CW 10k
LT1006
1. An electronic load typically employs a transistor across the input termi- R1 RV1 3 7
+
nals so the current flows from drain (collector) to source (emitter). 1.0 100k 6
K = 100
2
– 4
5 R3
1 –15 V
VIn 10k
0≤a≤1
Adjust RV1 for required RIn
IIn
Q CW
0 < RIn ≤ a × k × RS 3
+ R2
2 RV2
Aż∞ A –5 V 100
10k
– 1
IIn
Maximum power
– VB
dissipated in Q1= 16.5 W Adjust RV2 for 0 VIn at IIn(max) and a = 0

+ Auxiliary power supply 3. An application circuit like this one achieves a zero-load condition for
CW 3 RS testing low-voltage power supplies.
2
k
a 1

Henry Santana is a former senior electronic engi-

2. To maintain conduction of the pass transistor for a zero-load condition, neer with CSt Corp. He has a BSee from Colorado State
the circuit uses an auxiliary power supply. University, Fort Collins.

ElEctronic DEsign Go To www.elecTronicdesiGn.com

 for Design
Ideas
ALEXANDER ASINOVSKI | MURATA POWER SOLUTIONS INC., MANSFIELD, MASS.

Determine MOSFET Junction Temperature And

aasinovski@murata-ps.com

Switching Losses For Various Package Types

THE JUNCTION TEMPERATURE of power MOSFETs is one of the
major criteria used to obtain temperature derating curves for
power converters. This article describes an improved technique
for determining MOSFET junction temperature and switching
losses more accurately based on the given thermal resistances
and lead and case (package) temperature measurements.
To keep the junction temperature (Tj) within specifications,
allowable drain (leads) temperature (TD) is often calculated as:
TD = Tj – (Pj ñ ĤJD) (1)
where Pj is the total heat power generated inside the package
(including conduction, switching, and gate losses), and ĤJD
is the junction-to-drain (leads) thermal resistance, which is a
package-related parameter provided in the MOSFET’s data
sheet. The table shows typical values of ĤJD for some standard
power MOSFET packages.
For example, if a MOSFET in an SO8 package (Ĥ JD =
15°C/W) dissipates a Pj of 1 W and must maintain a junction
temperature below 125°C, then the measured drain tempera-
ture must not exceed 110°C according to Equation 1:
TD = 125°C – (1 W ñ 15°C/W) = 110°C (2)
PjD ȏjD ȏDB
(+)
ȏBA
(+)
PjC ȏjC ȏCA
(+)
Using Equation 1 implies that Pj can be determined under
any operational condition and that the total power generated
inside the package is dissipated to ambient through the drain
leads. In reality, the accuracy of the Pj calculation is relatively
low because switching losses in the MOSFET cannot be calcu-
lated accurately enough. Also, since a portion of Pj is dissipat-
ed to ambient through the MOSFET package, the actual heat
flow through the drain leads is smaller than Pj, which presents
another source of error.
The more accurate technique starts by considering the MOS-
FET thermal model in the figure, which is a modification of the
model used in “Estimating TJ of SO-8 Power MOSFETs” at
www.irf.com/technical-info/designtp/dt99-2.pdf.
According to this model, the total heat generated in the
package, represented by current source Pj, flows to ambient
through two parallel branches. The first is the junction-drain
(leads)-to-PCB-to-ambient route (the “drain” or “lead” branch,
labeled P jD) with junction-to-drain thermal resistance ĤjD,
drain-to-PCB thermal resistance ĤDB, and PCB-to-ambient
thermal resistance ĤBA.
The second is junction-to-case (package)-to-ambient (the
“case” or “package” branch, labeled PjC) with junction-to-case
thermal resistance ĤjC and case-to-ambient thermal resistance
ĤCA. The model represents the case temperature as TC and the
ambient temperature TA by a voltage source.
Applying conventional electrical circuit analysis and Ohm’s
law to the model, we obtain the following equations for the
heat (PjD and PjC) flowing through the respective drain and
case branches:
PjD = Pj/(1 + ĤD/ĤC) (3)
PjC = Pj/(1 + ĤC/ĤD) (4)

where ĤD = ĤJD + ĤDB + ĤBA (total drain-branch thermal resis-

Tj
Pj + tance) and ĤC = ĤjC + ĤCA (total case branch thermal resis-
TD TC TA
tance). So, total heat flow Pj is:
–
Pj = PjD + PjC (5)

(–) (–) (–) Applying Ohm’s law to the combinations of thermal resis-
tances in each branch of the diagram in the figure, we get two
This modified thermal model of a MOSFET illustrates how the total heat equations for junction temperature:
Pj generated in the device is dissipated to ambient through two parallel
branches: junction-to-drain (leads)-to-PCB-to-ambient and junction-to-case Tj = TD + [(TD – TA) ñ ĤjD]/(ĤDB + ĤBA) =
(6)
(package)-to-ambient. TD + [(TD – TA) ñ
ĤjD/ĤDA]

ELECTRONIC DESIGN
IdeasForDesign
TYPICAL VALUES OF THERMAL RESISTANCE
Thermal
resistance
ºC/W DirectFET PowerPAKSO8 DPAK
1 1.5 1.5
Tj = TC + [(TC – TA) ñ ĤjC]/ĤCA (7)
Neither of these equations contains the troublesome heat pow-
er term, Pj, and either one can be used to calculate the junction
temperature, Tj, as long as the case, drain, and ambient tempera-
tures and the thermal resistances of the package are known.
Consider a typical SO8 power MOSFET with thermal resis-
tances ĤCA = 380°C/W, ĤJC = 18°C/W, ĤJD = 15°C/W, and ĤDA
= 20°C/W (given in “Estimating TJ of SO-8 Power MOSFETs,”
again). Substituting these values into Equations 3 and 4, we
obtain:
PjD/Pj = 1/[1 + (15 + 20)/(18 + 380)] = 0.92 (8)
PjC/Pj = 0.08 (9)
In other words, 92% of the total power generated in the sili-
con is dissipated to ambient through the drain, and the remain-
ing 8% is dissipated through the case.
Another important observation is that ĤCA is much greater
than any other thermal resistance in the system, which makes
the second term in Equation 7 relatively small. Assuming TC
= 125°C and TA = 85°C for the set of parameters given above,
Equation 7 gives a junction temperature of:
Tj = 125 + [(125 – 85) ñ 18]/380 = 126.9°C (10)
This is only 1.9°C greater than the case temperature. Using
Equation 6, the drain temperature is:
TD = {Tj + [(TA ñĤjD)/ĤDA)]}/(1+ ĤJD/ĤDA) =
(11)
{126.9 + [(85 ñ 15)/20)]}/(1 + 15/20) = 108.9°C
So, the drain temperature is 16.1°C lower than the case tem-
perature. This implies that for an SO8 power MOSFET with
a ĤjD on the same order as ĤDA and with a ĤCA much greater
than ĤJC, the drain temperature tends to be lower than the case
temperature. Also, the plastic case temperature is an accurate
representation of the junction temperature.
According to the measured results in “Estimating TJ of SO-8
Power MOSFETs,” the difference between Tj and TC for SO8
packages is typically 1°C to 3°C. If we use the same equations
for other MOSFET packages, like PPAKSO8, D2PAK, DPAK,
and LFPAK with low junction-to-drain thermal resistances
(see the table, again), both the drain and case temperatures are
close to the junction temperature. For DirectFET type MOS-
FETs with metal cases, ĤJD is even lower and, according to
Equation 6, the drain temperature is an accurate representation
of the junction temperature.
ELECTRONIC DESIGN GO TO WWW.ELECTRONICDESIGN.COM
Package type
D2PAK LFPAK SO8
1.5 2 15
For a more accurate Tj calculation based on Equation 6,
ĤDA, which is not available from MOSFET datasheets, can
be determined. According to the model, junction-to-ambient
thermal resistance, ĤjA, which is provided in datasheets, is a
parallel combination of ĤD and ĤC resistances and ĤDA = ĤD –
ĤjD. Applying this to the model, we can get:
ĤDA = ĤjA/(1 – ĤjA/ĤC) – ĤjD (12)
Taking into account that ĤC is approximately an order of
magnitude greater than ĤjA, Equation 12 can be simplified as:
ĤDA ≈ (1.1 ñ ĤjA) – ĤjD (13)
Substituting Equation 13 into Equation 6, we get:
Tj ≈ TD + [(TD – TA) ñ ĤjD]/[(1.1 ñ ĤjA) – ĤjD] (14)
where all the thermal resistance values are available from the
datasheets.
We calculated the junction temperature based on parameters
specified on a MOSFET’s datasheet and temperature mea-
surements taken from the component under test conditions. A
conventional measurement technique for the drain (lead) and
case (package) temperature uses thermocouples placed on the
package and on the lead areas.
This technique results in measured temperatures that are
lower than actual temperatures for two reasons. First, the
thermocouple itself works as a heatsink, cooling the device
down. Second, its physical placement is critical when trying
to determine the device’s hottest temperature. A more accurate
temperature measurement method uses an infrared camera to
determine the hottest temperature in the areas of interest (case
and lead) without interfering with the heat flow.
Once the junction temperature is determined, the total power
generated in the silicon, Pj, can be calculated:
Pj = (Tj – TA)/ĤjA (15)
where ĤjA is the junction-to-ambient thermal resistance avail-
able from the MOSFET’s datasheet. Pj also can be calculated
based on Equation 3 and the junction-to-drain thermal resis-
tance, which is also available from the datasheets:
Pj = [(1 + ĤD/ĤC) ñ (Tj – TD)]/ĤjD (16)
Although ĤD and ĤC are not available from the datasheets, ĤC
is approximately one order greater than ĤD, so Equation 16 can
be simplified as:
IdeasForDesign
Pj ≈ [1.1 ñ
(Tj – TD)]/ĤjD (17)
After Pj is determined, switching losses, PSW can be calcu-
lated in the conventional way:
PSW = Pj – Pdc – Pg =
(18)
Pj – [Irms2 ñ RDS(on)] – [Q ñ Vg ñ FSW]
where Pdc = conduction (dc) losses, Pg = gate drive losses, Irms
= the rms value of the drain current, RDS(on) = the MOSFET on
resistance, Q = total gate charge, Vg = peak gate voltage, and
FSW = switching frequency. For a square-wave drain current
with peak current of Ipk and duty cycle D, Irms2 = Ipk2 ñ D.
This analysis of the modified thermal model of the MOS-
FET demonstrates that the hottest spot on the lead and package
areas of a power MOSFET is typically a couple of degrees
Celsius less than the junction temperature. This hot-spot tem-
perature can be accurately measured by an infrared camera
without affecting the device’s heat flow, and the result can be
used with the thermal resistance values found in the datasheet
to calculate the MOSFET’s junction temperature. Finally, the
total power generated inside the silicon and the switching
losses can be calculated.
ALEXANDER ASINOVSKI, principal
engineer of Murata Power Solutions Inc.,
Manfield, Mass., holds BSEE and MSEE degrees
from State Technical University, St. Peteresburg,
Russia, and a PhD from the University of
Telecommunications, St. Petersburg.
IDEAS FOR DESIGN WANTED
Send us your Ideas For Design. We’ll pay you $150 for every Idea For
Design that we publish. In addition, this year’s top design as selected by
our readers will earn an additional $500, with two runners up each
receiving $250. You can submit your Ideas For Design via:
t
&NBJM
KPFEFTQPTJUP!QFOUPODPN
OR BY
t

1PTUBM
NBJM
UP
Ideas For Design
&MFDUSPOJD
%FTJHO
249 W. 17th Street,
New York, NY 10011
Go to www.electronicdesign.com for our submission guidelines.
ELECTRONIC DESIGN