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Arp Cache
Arp Cache
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN
THE SOFTWARE.
*/
/*
* ARP cache
*/
module arp_cache #(
parameter CACHE_ADDR_WIDTH = 9
)
(
input wire clk,
input wire rst,
/*
* Cache query
*/
input wire query_request_valid,
output wire query_request_ready,
input wire [31:0] query_request_ip,
/*
* Cache write
*/
input wire write_request_valid,
output wire write_request_ready,
input wire [31:0] write_request_ip,
input wire [47:0] write_request_mac,
/*
* Configuration
*/
input wire clear_cache
);
reg mem_write = 0;
reg store_query = 0;
reg store_write = 0;
reg valid_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg [31:0] ip_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg [47:0] mac_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
rd_hash (
.data_in(query_request_ip),
.state_in(32'hffffffff),
.data_out(),
.state_out(query_request_hash)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
wr_hash (
.data_in(write_request_ip),
.state_in(32'hffffffff),
.data_out(),
.state_out(write_request_hash)
);
integer i;
initial begin
for (i = 0; i < 2**CACHE_ADDR_WIDTH; i = i + 1) begin
valid_mem[i] = 1'b0;
ip_addr_mem[i] = 32'd0;
mac_addr_mem[i] = 48'd0;
end
end
always @* begin
mem_write = 1'b0;
store_query = 1'b0;
store_write = 1'b0;
wr_ptr_next = wr_ptr_reg;
rd_ptr_next = rd_ptr_reg;
clear_cache_next = clear_cache_reg | clear_cache;
query_ip_valid_next = query_ip_valid_reg;
write_ip_valid_next = write_ip_valid_reg;
write_request_ready_next = !clear_cache_next;
if (write_ip_valid_reg) begin
write_ip_valid_next = 0;
mem_write = 1;
end
if (clear_cache) begin
clear_cache_next = 1'b1;
wr_ptr_next = 0;
end else if (clear_cache_reg) begin
wr_ptr_next = wr_ptr_reg + 1;
clear_cache_next = wr_ptr_next != 0;
mem_write = 1;
end
end
always @(posedge clk) begin
if (rst) begin
query_ip_valid_reg <= 1'b0;
query_request_ready_reg <= 1'b0;
query_response_valid_reg <= 1'b0;
write_ip_valid_reg <= 1'b0;
write_request_ready_reg <= 1'b0;
clear_cache_reg <= 1'b1;
wr_ptr_reg <= 0;
end else begin
query_ip_valid_reg <= query_ip_valid_next;
query_request_ready_reg <= query_request_ready_next;
query_response_valid_reg <= query_response_valid_next;
write_ip_valid_reg <= write_ip_valid_next;
write_request_ready_reg <= write_request_ready_next;
clear_cache_reg <= clear_cache_next;
wr_ptr_reg <= wr_ptr_next;
end
if (store_query) begin
query_ip_reg <= query_request_ip;
end
if (store_write) begin
write_ip_reg <= write_request_ip;
write_mac_reg <= write_request_mac;
end
if (mem_write) begin
valid_mem[wr_ptr_reg] <= !clear_cache_reg;
ip_addr_mem[wr_ptr_reg] <= write_ip_reg;
mac_addr_mem[wr_ptr_reg] <= write_mac_reg;
end
end
endmodule