library ieee;

use ieee.std_logic_1164.all;
-- Descripcion en caja negra
entity control is
port(
a, b: in std_logic_vector(3 downto 0);
f: out std_logic_vector (4 downto 0);
);
end control;
-- Descripcion del circuito
architecture solucion of control is
begin
x <= a when (f = "00") else
a when (f = "01") else
a when (f = "10") else
b;
end solucion;