Efficient Implementation of CFAR Based Algorithms
Using The ADSP TigerSHARC 201S Processor
Ahcène BELLABAS and Boualem MAGAZ
Département Electronique
Ecole Nationale Polytechnique,
Algiers, Algeria
ahcene.bellabas@gmail.com, boualem.magaz@enp.edu.dz
Abstract— In this paper, we propose an efficient DSP
implementation of the CA-CFAR, the SO-CFAR, the GO-CFAR
and the OS-CFAR detectors using the ADSP TigerSHARC 201S
processor from Analog Devices and the VisualDSP++5.0
development tools. The main contribution of this paper involves
two parts. The first one concerns the extension of the GASW
technique developed initially for the CA-CFAR threshold
estimate implementation to the SO-CFAR and the GO-CFAR
detectors. In the second part, a new and efficient procedure for
the OS-CFAR detector implementation is investigated. The real-
time constraints are managed so as to satisfy the requirements of
the ASR-12 radar. It should be noticed that the developed
architectures are fully reconfigurable and can be extended to
other CFAR detectors easily. The DSP implementation results
are presented and discussed in this paper.
Key words: ADSP T201 processor , CFAR, Implementation.
I. INTRODUCTION
Detection of target in a background of clutter is a problem
of interest in radar field. In order to improve such system
detection, the designer usually prefers Constant False Alarm
Rate detection, CFAR, procedures.
Many different CFAR algorithms have been developed to
effectively deal with the various types of backgrounds that are
encountered. However, any single algorithm is likely to be
inadequate in a dynamically changing environment.
The most basic forms of the adaptive threshold processor
are the well-known cell-averaging CFAR (CA-CFAR) [2] for
homogeneous environment and the ordered statistics (OS-
CFAR) [3] in presence of interfering targets.
The application of digital signal processing in radar systems
began from signal detection in video frequency and is now
developing into signal processing in intermediate frequency. It
seems possible to process the RF signal directly owing to the
development of digital devices. The percentage of digitized
parts in radar system becomes larger since it is a cost-effective
way to improve the performance of the entire radar system.
Real-time performance of adaptive digital signal processing
algorithms is required in many applications but it often means a
high computational load for many conventional processors.
In this paper, we propose new and efficient DSP
implementation procedures of CFAR based detectors using the
ADSP TigerSHARC 201S processor. In section 2, we present
the considered detectors architecture. In section 3, we describe
the TS201S processor and the development tools
specifications. Section 4 deals with the real-time constraints
and the implementation results and finally we provide some
comments on the opportunity of the application of the proposed
procedures in a radar system.
II. THE DETECTION ALGORITHMS
Several kinds of CFAR techniques have been proposed in
the literature [1], based on the method to obtain the adaptive
threshold from the reference window or data set. The Cell-
Averaged CFAR (CA-CFAR) is the most common CFAR
detector used in adaptive signal processing for target
detection. In the CA-CFAR all the cells in the reference
window are summed up to compute their average, and hence
the adaptive threshold. There are other algorithms such as the
Order Statistics CFAR that computes an order statistic of the
reference cells to compute the threshold.
This work is focused in the CA-CFAR algorithm, two
versions of it, the Smallest Of CFAR and the Greatest Of
CFAR, and the OS-CFAR detectors.
For the GO-CFAR detector, the leading and the lagging
samples are separately summed and the larger of the two is
used to set the threshold. The GO-CFAR has been introduced
in [7] to alleviate the problem of increase in the false alarm
probability due to step discontinuity (clutter edge).
In the SO-CFAR detector, the estimate of the noise level is the
minimum of the sums of the outputs of the leading and the
lagging range cells. The SO-CFAR detector was proposed in
[6] in order to improve the resolution of closely spaced targets.
More details will be provided in the full paper.
III. THE ADSP-TS201S PROCESSOR AND
DEVELOPMENT TOOLS DESCRIPTION
The ADSP-TS201S TigerSHARC processor is an ultra-
high performance, static superscalar processor optimized for
large signal processing tasks and communications
infrastructure. The DSP combines very wide memory widths
with dual computation blocks supporting 32 and 40-bit
floating-point and supporting 8, 16, 32, and 64-bit fixed-point
processing to set a new standard of performance for digital
signal processors. The TigerSHARC static superscalar
architecture lets the DSP execute up to four instructions each GO-CFAR:
cycle, performing twenty four 16-bit fixed-point operations or
six floating-point operations [8].                                                                    5  
Four independent 128-bit wide internal data buses, each
connecting to the six 4M bit memory banks, enable quad-word
data, instruction, and I/O accesses and provide 33.6G bytes per                                                                   6  
second of internal memory bandwidth. Operating at 600 MHz,
the ADSP-TS201S processor’s core has a 1.67 ns instruction   ,                                                                      7  
cycle time. Using its Single-Instruction, Multiple-Data (SIMD)
features, the ADSP-TS201S processor can perform 4.8 billion OS-CFAR:
40-bit MACs or 1.2 billion 80-bit MACs per second [9,10]. ,… 1 ,
The VisualDSP++ development tools are used for code 1 ,…                             8  
generation, loading, debugging and evaluation of the proposed _                                                          9  
implementation procedures for the considered detectors. It 3
    _                                                      10  
includes all the tools needed to build and manage processor 2
Projects. The VisualDSP++ IDDE provides complete graphical
control of the edit, build, and debug process. In this integrated OS-CFAR   ):
environment, we can move easily between editing, building,
and debugging activities.   ,… 1 ,

It provides flexible project management for the development 1 ,…                      11  

of processor applications, including access to all the activities For     1:  1 
necessary to create, define, and build processor projects.                            12  
End 
IV. DSP IMPLEMENTATION
                                                                  13  
A. The Real Time Constraints
The period between two sweeps is the critical time for the For the optimized procedures, the corresponding expressions of
implementation of the proposed detectors, in case of one pulse the threshold estimates are given as follows:
processing. This means that these periods determine the
amount of time for acquisition, storage, threshold computation, CA-CFAR:
comparison and storage of the output decision. This critical
time depends on the size of the reference window of the CFAR                             14  
detector.
The real time considerations are managed so as to satisfy  
the requirements of the air surveillance radar, ASR-12, with a 1 1
pulse repetition frequency of 1200Hz, an angular resolution of 1    15  
1.4°, an antenna rotation speed of 12rpm and 1 microsecond
pulse width. The minimum critical time corresponds to 499000  
cycles for the ADSP-TS201S with a 1.67ns instruction cycle
time. SO-CFAR:
B. Implementation procedures
                                                          16  
The ordinary implementation procedures of the considered
detectors are computed according to the following expressions.
CA-CFAR:                                                           17  

 
                               1 1                  18  
1 1 1 19  
 
SO-CFAR:   1 1 , 1                              20  

                                                                  2   GO-CFAR:

                                                         21  
                                                                  3  

  ,                                                                       4  
 The evaluation of the processing time is in number of
                                                         22   cycles. The total time will be computed for a cycle time of
1.7ns.
  In table 1, we present the obtained execution time of the
1                  23   CA, the SO, the GO and the OS-CFAR detectors using
1 1 1 24   ordinary procedures for different sizes of the reference
1 1 , 1                              25   window, N.
For the OS-CFAR implementation, two procedures are
  considered, the classical ordering procedure and the direct
determination of the (N-k) maximum proposed in [4]. K is the
The OS-CFAR implementation procedure is illustrated in order of the OS-CFAR detector.
the following bloc diagram.
TABLE I. EXECUTION TIMES FOR ORDINARY PROCEDURES

N
Step k=0 Vect_sort Detector 8 16 32 40
CA 28 041 40 113 72 149 88 239
Step k k=k+1 SO 32 843 51 291 96 145 118 553
GO
32 843 51 291 96 145 118 553

k<kmax OS
END 579 756 1 847 491 6331925 9512051
(ordinary)
OS
264 304 657 209 1 923 233 2 792 278
(N-k)

_ , 1 It can be seen the limitation of these procedures for larger

number of reference cells. The increase of the number of
reference cells decreases the processed range.
_ 1 , Table II presents the execution times of the optimized
procedures for the considered detectors DSP implementation.

TABLE II. EXECUTION TIMES FOR THE OPTIMIZED PROCEDURES

_

k=k+1 Detector 8 16 32 40

Figure 1. Bloc diagram of the optimized OS-CFAR implementation CA 14 459 14 493 14 555 14 595

SO 16 040 16 082 16 122 16 144

Where q(.): is the output of the square law detector, m: the
number of cells in left/right reference window; and g: the GO 16 040 16 082 16 122 16 144
number of guard cells. OS 249 450 370 854 621 920 750 340
and are respectively the lagging and the leading
reference window and 1 is the estimate for the (k+1)th
range cell under test.
The numerical results presented in Table II show the real
_ is the sorted reference window samples.
time processing improvement compared to Table I presenting
C. Execution times the corresponding times for the ordinary procedures.
The software implementation of the CFAR algorithms was It can be pointed out that the application of the GASW
carried out in VisualDSP++ targeted to a personal computer technique for the CA-CFAR, the SO-CFAR and the GO-CFAR
with a Pentium IV processor running a 3 GHz and 1Gbytes of detectors reduces significantly the execution times and keep it
main memory. The proposed procedures are coded in quasi-constant whatever the reference window size and the
assembly language to optimize the execution times. number of guard cells is, for the entire radar range cells
For real-time application, we must consider the entire radar processing.
coverage range to determine the processing limitation. The For the OS-CFAR detector, the proposed procedure ensures
considered range corresponds to 800 cells. the real time processing for larger reference window sizes
compared to the (N-K) procedure.
 For practical application in the ASR-12 radar, the obtained
results are widely sufficient for a real-time processing.
D. Implementation results
The implemented procedures have been evaluated using
synthetic radar data. In order to demonstrate the behavior of the
CFAR detectors in different environments, the considered
signal contains eight targets and a clutter edge. The targets are
present in known positions to meet several radar situations,
namely the presence of interfering targets and clutter edge to
show the effectiveness of the implemented CFAR detectors.
Hence, the implementation results of the CA-CFAR, the
SO-CFAR and the GO-CFAR thresholding for Pfa=1E-6 and
N=16, are presented in Fig. 2.
Figure 2. Implementation results using the CA, SO and GO-CFAR
thresholding on the ADSP-TS201S Processor
The implementation results of the OS-CFAR thresholding,
for K=12, are presented in Fig. 3. We can observe the detection
of all the considered targets.
Figure 3. Implementation results using the OS-CFAR thresholding on the
ADSP-TS201S Processor
V. CONCLUSION
In this paper, efficient DSP implementation procedures for the
CA-CFAR, the SO-CFAR, the GO-CFAR and the OS-CFAR
detectors using the ADSP Tiger SHARC 201S processor have
been presented.
The proposed architecture exploits the parallel nature in
CFAR signal processing and it can be extended to more
complex CFAR algorithms.
The real-time constraints are managed so as to satisfy the
requirements of the ASR-12 radar. It should be noticed that the
developed architectures are fully reconfigurable and can be
easily extended to any other CFAR detector.
REFERENCES
[1] Skolnik, M. I., Radar HandBook , McGraw-Hill, 3rd edition, USA,
2008.
[2] H. M Finn and R. S. Johnson, Adaptive Detection Mode With Threshold
Control as a function of spatially sampled Clutter level Estimates, RCA
Review, Vol. 29, PP.414-464, September 1968.
[3] H. Rohling, Radar CFAR thresholding in clutter and multiple target
situations, IEEE Transactions on aerospace and electronic systems, Vol.
19, PP.608-621, july 1983.
[4] B. Magaz and M. L. Bencheikh, An Efficient FPGA Implementation of
the OS-CFAR Processor, Proceedings of the International Radar
Symposium, Wroclaw, Poland, pp. 143 - 146, May 2008
[5] B. Magaz, M..L Bencheikh, M. Hamadouche and A. Belouchrani,
Design And Real Time Implementation of a Novel Combined CA-
CFAR/SLB System On TMS320C67x Processor, Proc. International
Radar Symposium, pp. 697-700, Krakow, Poland, Mai 2006.
[6] Hansen, V. G. and Sawyers, J. H., Detectability loss due to greatest of
selection in a cell-averaging CFAR, IEEE Trans. Aerospace and
electronic Systems, Vol. AES-16, pp. 115-118, Jan. 1980.
[7] G. V. Trunk, Range Resolution of Target using Automatic Detectors,
IEEE Transaction on aerospace and Electronic Systems. Vol. 14, pp. 750
- 755, September, 1978.
[8] TigerSHARC Embedded processor Data Sheet, Analog Devices, 2003.
[9] TS201S DSP Processor Library Programmer’s Reference, Online
available.
[10] URL: http://www.analog.com/processors/tigersharc.