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wire referesh_clock;
clock_divider referesh_clock_generator(referesh_clock,clk);
refershcounter refereshcount_wrapper(referesh_clock,refereshcounter);
ancode_control anodecontrol_wrapper(refereshcounter,Anode);
BCd_control
BCDcontrol_wrapper(one_digit,switch[3:0],switch[7:4],button[3:0],button[3:0],refereshcounter);
//BCDto cathode wrapper
BCD_to_cathode bcdtocathode_wrapper(cathode,one_digit);
Endmodule
module clock_divider(newclk,clk);
input clk;
always@(posedge clk)
begin
count = count+1;
newclk =count[17];
end
endmodule
module refershcounter(refersh_clock,refersh_counter);
input refersh_clock;
begin
end
endmodule
module ancode_control(referesh_counter,anode);
always@(referesh_counter)
begin
case(referesh_counter)
endcase
end
endmodule
module BCd_control(one_digit,digit1,digit2,digit3,digit4,referesh_counter);
always@(referesh_counter)
begin
case(referesh_counter)
endcase
end
Endmodule
module BCD_to_cathode(cathode,digit);
always@(digit)
begin
case(digit)
endcase
end
endmodule