80 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO.

1, JANUARY 2012

A 104-GHz Phase-Locked Loop Using

a VCO at Second Pole Frequency
Kun-Hung Tsai, Student Member, IEEE, and Shen-Iuan Liu, Fellow, IEEE

Abstract—The design and implementation of a high-speed

voltage-controlled oscillator (VCO) in 65-nm CMOS technology is
presented. The proposed VCO oscillates at the secondary resonant
pole of its resonator and achieves a frequency enhancement
of 84.7% while compared with a conventional cross-coupled VCO.
The proposed VCO is also incorporated into a phase-locked loop
(PLL) to generate clock signals above 100 GHz. For a 1.2-V supply,
the measured tuning range of this VCO is from 103.057 to 104.581
GHz, and the measured phase noise of this VCO is 101 08
dBc/Hz at 10-MHz offset. The locking range of the PLL is from
103.058 to 104.58 GHz, and its measured in-band phase noise is Fig. 1. Fourth-order LC resonator.
80 41 dBc/Hz at 1-MHz offset. The measured reference spur
level of this PLL is less than 63 8 dBc while consuming 63 mW
from a 1.2-V supply.
103.058 to 104.58 GHz. The power dissipation of the proposed
Index Terms—CMOS, resonator, phase-locked loop (PLL), VCO and the PLL are 12 mW and 63 mW from a 1.2-V supply,
voltage-controlled oscillator (VCO). respectively. To the best of authors’ knowledge, the PLL in-
corporated with the proposed VCO is currently the first PLL
with fundamental frequencies higher than 100 GHz in CMOS
I. INTRODUCTION technology.
This paper is organized as follows. The analysis and design

S INCE semiconductor technologies continue to scale down,

high-speed communication systems are emerging by
using advanced CMOS processes. In recent years, high-speed
of the proposed VCO and the PLL are illustrated in Section II.
Section III summarizes the experimental results of the proposed
VCO and the PLL. Finally, Section IV concludes this work.
transceivers for 60-GHz indoor RF link [1] and 77/79-GHz
automotive radar [2] have been successfully realized in 90-nm II. CIRCUIT DESCRIPTION
CMOS. Moreover, the receivers for imaging applications
near 90 GHz are reported [3], [4] in 65-nm CMOS. In these A. Analysis of Fourth-Order LC Resonator
communication systems, a phase-locked loop (PLL) with an Fig. 1 shows a fourth-order resonator. Assuming that all
voltage-controlled oscillator (VCO) is widely used for of the passive components are ideal, the input impendence
clock generation or frequency synthesis. In [5]–[7], several between nodes and is calculated as
VCOs with fundamental frequencies near 100 GHz have been
demonstrated. However, circuit techniques are still developed
to improve the performance of VCOs. In this paper, a VCO (1)
incorporating a fourth-order resonator is introduced to
raise the oscillation frequency of the VCO. To compare with a The pole frequencies are found by equating the denomi-
conventional cross-coupled VCO, the proposed VCO improves nator of to zero. That is
the oscillation frequency by 84.7% according to analysis.
Moreover, the proposed VCO is integrated into a PLL to gen-
erate clock signals above 100 GHz. From experimental results,
the proposed VCO can be tuned from 103.057 to 104.581 GHz,
and the PLL with the proposed VCO successfully locks from (2)

Manuscript received May 31, 2010; revised September 01, 2010; accepted
October 07, 2010. Date of publication November 18, 2010; date of current ver-
From (2), the square of the first and second pole frequency (i.e.,
sion December 14, 2011. This work was supported in part by NTU-MediaTek and ) can be expressed as
lab and in part by NSC, Taiwan.
The authors are with the Graduate Institute of Electronics Engineering and
Department of Electrical Engineering, National Taiwan University, Taipei
10617, Taiwan (e-mail: lsi@cc.ee.ntu.edu.tw).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. (3)
Digital Object Identifier 10.1109/TVLSI.2010.2088144

1063-8210/$26.00 © 2010 IEEE

TSAI AND LIU: A 104-GHZ PHASE-LOCKED LOOP USING A VCO AT SECOND POLE FREQUENCY 81

(4)

To gain more insight about the pole frequencies, let us consider

the special case of and . Thus,
and are simplified as

(5)

Fig. 2. Simulated jZ j of Fig. 1 while V and V are in phase and out of

phase, respectively.

(6)

From (5) and (6), and are given by

(7)

(8)

Note that the magnitude of is much higher than that of

. Moreover, voltage ratios between nodes and at
and are derived as

(9) Fig. 3. Proposed VCO with the fourth-order LC resonator.

(10)
, loading inductors, and , varactors, , parasitic
From (9) and (10), the phases at nodes and are in phase and capacitances, and , common-source amplifiers, and
out of phase at and , respectively. Fig. 2 shows the , cross-coupled pair, and , and tail current sources,
simulated magnitude of to demonstrate this phenomenon. and . The fourth-order resonator is composed of
With pH and fF, the , and . Based on (10), nodes
upper figure shows that has a maximum value located at and should be out of phase to ensure the fourth-order
the first pole frequency of 41 GHz while and are in resonator to oscillate at . Thus, two common-source
phase. On the other hand, the lower figure of Fig. 2 shows that amplifiers, and , are adopted to provide 180 phase dif-
resonates at the second pole frequency of 100 GHz ference between and and satisfy the condition
while and are out of phase. As a comparison, a higher of (10). The cross-coupled pair formed by and has two
resonant frequency can be obtained at , and is functions. First, the cross-coupled pair produces a negative re-
about 144% higher than . Using this property, it is possible sistance (i.e., ) to compensate
for a VCO with the fourth-order resonator to oscillate at a the component loss of and . Second, it facilitates
high frequency of . the proposed VCO to operate differentially.
Fig. 4 shows the small-signal half-circuit of the proposed
B. Analysis of Proposed VCO With Fourth-Order VCO. With narrow band approximation, the loss of is mod-
LC Resonator eled to parallel with a resistor . Similarly, the losses of
Fig. 3 shows the circuit diagram of the proposed VCO, and and are modeled to parallel with a resistor . Consid-
the proposed VCO is composed of feedback inductors, and ering the case similar to previous section (i.e.,
82 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 1, JANUARY 2012

Fig. 4. Small-signal half-circuit of the proposed VCO.

and ), the input impedance be-

tween nodes and is given as (11) at the bottom of the Fig. 5. ! with different ratio of C =C .
page while assuming that is compensated by (i.e.,
). With typical values, [8], the
oscillation frequency of the proposed VCO . Therefore, the proposed VCO
is derived as would need more power consumption to oscillate at
because is larger than .
(12) From above discussion, one may think that the cross-coupled
VCO is superior to the proposed VCO if an inductor with small
value is employed and makes the cross-coupled VCO to op-
by equating the denominator of to zero. Moreover, the min-
erate at the frequency close to (12). Indeed, using such an in-
imum required transconductance of can be also ob-
ductor is a possible solution to increase the oscillation frequency
tained from (11) by equating the denominator of to zero.
of the cross-coupled VCO. However, the inductor with a small
That is
value usually leads to a VCO with serious frequency devia-
tion between post-simulation and measurement. For high-speed
(13) PLL design, the frequency deviation usually causes imperfect
frequency alignment between the VCO and divider so that a
for properly compensating the loss of and letting the pro- PLL may fail to work correctly. Under the same oscillation fre-
posed VCO steady oscillate at . quency, the proposed VCO may have a smaller frequency devi-
On the other hand, the oscillation frequency of a conventional ation than the cross-coupled VCO. In the consideration of fre-
cross-coupled VCO with a resonator of can be quency alignment between the VCO and divider, the proposed
approximated to . For fair comparison between VCO may be a better candidate for a high-speed PLL.
the proposed VCO and the cross-coupled VCO, we assume Furthermore, the readers may wonder what if the condition
that , and . Thus, the oscillation of cannot be exactly satisfied since
frequency and the minimum required the capacitive parasitics cause by transistors or layout routing
transconductance requirement of the cross-coupled VCO can are difficult to be precisely estimated at high-speed operation.
be given as Simulation shown in Fig. 5 demonstrates the impact of the ca-
pacitance uncertainty on . In Fig. 5, considering a fixed
value (e.g., in simulation), is gradually de-
(14)
creased with the ratio of , and therefore a small ratio
of facilitates to achieve a high for the proposed
(15)
VCO.

where is the transconductance of the cross-coupled tran-
sistors. To compare (12) with (14), the proposed VCO has a
higher oscillation frequency and achieve a frequency enhance-
ment of 84.7%. In the minimum required transcoductance for
reliable oscillation, the transconductance of the proposed VCO
is at
whereas that of the cross-coupled VCO is
C. Design Considerations of Passive Components
in Proposed VCO
Fig. 6(a) depicts the inductor in the proposed VCO. The in-
ductor is basically realized by a top metal line (the sixth metal
layer with m) with U-shape. Fig. 6(b)
, shows the folded structure in [9], and a brief comparison be-
at tween Fig. 6(a) and (b) will be discussed later. In the design of

(11)
TSAI AND LIU: A 104-GHZ PHASE-LOCKED LOOP USING A VCO AT SECOND POLE FREQUENCY 83

Fig. 6. (a) U-shape inductor in the proposed VCO. (b) Folded structure in [9].
(c) Simulated L and Q of the U-shape inductor with fixed length (100 m) but
different W and S . (d) Simulated L and Q of the U-shape inductor (hollow Fig. 7. (a) Varactor in the proposed VCO. (b) Simulated C-V curves and Q
circles) and the folded structure in [9] (solid circles). at 100 GHz with different dimension but fixed area (i.e., the same L2 W
value).

the U-shape inductor, it provides two design parameters to af-

fect the inductor performance with a fixed length: 1) the metal shorten drain and source. The simulated C-V curves and quality
width of the inductor and 2) the metal spacing between factors of the varactors with three different sizes are shown
two legs of the inductor. Using HFSS EM simulator, the induc- in Fig. 7(b). In Fig. 7(b), and denote the gate
tance value and quality factor of the U-shape inductor length, gate width, and quality factor of the varactor, respec-
near 100 GHz are presented in Fig. 6(c) with different and tively. The upper figure shows the simulated C-V curves of three
. In Fig. 6(c), gradually degenerates with increasing , and different but the same value. These C-V curves are
then the U-shape inductor with narrow results in large and monotonically decreased with VCO controlled voltage
a small silicon area for a given inductance value. has a trend so that the tuning curve of the proposed VCO will gradually in-
opposite to , and it enhances with increasing according to crease with . The simulated of these three varactors
the simulation on right-hand side of Fig. 6(c). Moreover, of at 100 GHz are shown in the lower figure, and the simulated
the U-shape inductor decreases with , and one of the possible of these three varactors are lower than 5 while operating
reasons is that the mutual magnetic coupling effect between two at 100 GHz. From the simulation results, a small facilitates
legs lowers the overall inductance. Opposite to the trend of to increase when varies from 0 to 0.8 V. In the pro-
with different of the inductor slightly decreases with . In posed VCO, nm is adopted in the varactors since
summary, it would be trade-off between and for different of nm is superior to that of nm and varies
and . In proposed VCO design, we finally choose m more slightly than that of nm for different .
and m for the U-shape inductor. To consider the tuning range of a VCO, a varactor with
Fig. 6(d) shows the simulated and of the U-shape large size is usually used to widen that. However, of
inductor and the folded structure in [9] with the same size. a varactor is inversely proportional to the capacitance value
From Fig. 6(d), the U-shape inductor has larger and than of the varactor and the operation frequency (i.e.,
the folded structure in [9]. One of the possible reasons for the ) [10]. The varactor with large size leads
smaller and lower of the folded structure is because the to a large and then results in a poor at high-speed
structure has larger capacitances contributed by the use of a operation [e.g., if a varactor size is larger than the
GND plane. In this work, the U-shape inductor (rather than varactor in Fig. 7(b) and operates near 100 GHz]. The poor
the folded structure in [9]) is chosen for the considerations of may deteriorate the quality factor of the resonator
silicon area and quality factor. as well as the phase noise of the VCO. Hence, the tuning range
A varactor is another critical component for the frequency of a VCO above 100 GHz may be limited because the varactor
tuning capability of a VCO. Fig. 7(a) shows the varactor in with large size is not suitable for a high-speed VCO. Referring
the proposed VCO. The varactor is an NMOS transistor with to the published VCOs [5]–[7], high-speed PLLs [11]–[13],
84 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 1, JANUARY 2012

Fig. 8. Floor plan of the proposed VCO.

and the simulated in Fig. 7(b), the tuning range of the
proposed VCO is finally designed within 2 GHz while consid-
ering the trade-off among the poor of varactors, VCO
performance above 100 GHz, and integration into a PLL.
Four inductors in the proposed VCO may lead to difficulties
in the layout and need long interconnects. Using three U-shape
inductors with identical size, the floor plan of Fig. 8 is adopted
to improve this layout issue of the proposed VCO. The vertical
inductor in Fig. 8 has a center tap which is connected to
Because the proposed VCO operates differentially, the center
tap is AC grounded, and therefore the inductance of this ver-
tical inductor is equally divided. Such a characteristic results
in and satisfies the require-
ment of inductance value in (11) and (12). With this layout style,
, and are closed to each other, and then the par-
asitics of layout routing among these nodes can be reduced.
Moreover, the opposite placement between and can also
diminish the mutual coupling effect of inductors.
D. PLL Design
To measure a free running VCO above 100 GHz is a chal-
lenging work since VCO spectra are sensitive to external per-
turbation such as supply and temperature variations. Therefore,
the proposed VCO is integrated into a PLL to generate stable
spectra for measurement. Furthermore, the PLL with the pro-
posed VCO also demonstrates the possibility for clock genera-
tion above 100 GHz.
Fig. 9 shows the block diagram of the PLL, and the PLL is
composed of the proposed VCO, a phase-frequency detector
(PFD) [14], a charge pump (CP), an integrated second-order
loop filter (2nd LF), and a divider chain with three different
kinds of divider circuits. Because the proposed VCO is designed
to oscillate above 100 GHz, an injection-locked frequency di-
vider (ILFD) [11] is utilized as the first divider for the trade-off
between power consumption and operation speed. Following the
ILFD, the divide-by-16 dividers in Fig. 9 are realized by four
current-mode-logic (CML) dividers. The first and second stages
of the divide-by-16 dividers adopt inductive-peaking technique
[15] to improve their operation speed. Behind the divide-by-16
dividers, the divide-by-8 stage in the PLL is realized by true-
single-phase-clocking (TSPC) logics [16] to further save the
power consumption of the divider chain. Fig. 10 shows the PFD
in the PLL. The PFD consists of 11 NAND gates which are
realized by static logics. In Fig. 10, a delay cell is inserted at
Fig. 9. Block diagram of the PLL integrated with the proposed VCO.
.
Fig. 10. PFD [14] in the PLL.
the output of the 4-input NAND gate to reduce the dead zone
problem of the PFD. However, one of the disadvantages of using
the delay cell in a PFD is that the degeneration of PFD opera-
tion speed. Fortunately, as discussed in [14], the operation speed
of the PFD in Fig. 10 is unaffected by the delay cell, and then
the PFD operation speed can be improved. Designed in 1.2-V
65-nm CMOS process, the simulated operation speed of this
PFD is up to 600 MHz. In PLL integration, the digital noise
of PFD would be an issue because the noise may affect the sen-
sitive circuits (e.g., VCO and ILFD) in a PLL through the sil-
icon substrate. In the consideration of digital noise, some guard
rings are adopted to reduce the effect of the digital noise caused
by PFD. The second-order loop filter is fully integrated into the
PLL, and it is composed of two capacitors ( and ) and
one resistor . and are implemented by metal-insu-
lator-metal (MIM) capacitors, and is a polysilicon resistor
with large size to alleviate process variations. The design pa-
rameters of the PLL are listed in Table I. The simulated loop
bandwidth and the phase margin of the PLL are 2 MHz and 65 ,
respectively.
III. EXPERIMENTAL RESULTS
Fig. 11 shows the die photo of the PLL integrated with the
proposed VCO. Fabricated in 1.2-V 65-nm CMOS process, the
chip area of the PLL is 0.84 mm with pads. For a 1.2-V supply,
the power consumption of the PLL is 63 mW, of which 12 mW
TSAI AND LIU: A 104-GHZ PHASE-LOCKED LOOP USING A VCO AT SECOND POLE FREQUENCY 85

TABLE I
DESIGN PARAMETERS OF THE PLL

Fig. 12. Test setup of the PLL.

Fig. 13. Measured and post-simulated tuning curves of the proposed VCO.

Fig. 11. Die photo of the PLL integrated with the proposed VCO.

is dissipated in the VCO, 35.4 mW in the high-speed dividers

(CML dividers ILFD), 13.2 mW in the output buffers, and
2.4 mW in the low-speed circuits (PFD CP TSPC dividers).
Fig. 12 shows the test setup of the PLL. The PLL chip is
mounted on an RF probe station, and the output spectra of the
PLL are measured through a W-band (75–110 GHz) waveguide
probe. To observe spectra above 100 GHz, a spectrum analyzer
combined with an external W-band harmonic mixer [17] is
applied to the test setup. Moreover, time domain measurement
including the frequency-hopping characteristic and the jitter
performance of the PLL are presented to further verify the
locking behavior of the PLL. In the frequency-hopping test, Fig. 14. Closed-loop spectrum of the PLL at f = 103:936 GHz.
a signal generator is used to provide a frequency modulation
(FM) signal with square-wave shape so that the PLL can period-
ically lock between two reference frequencies. Since the output when is between 0.5 to 0.9 V. To compare with post-simu-
signal of the PLL exceeds the frequency limitation of lation results, the maximum frequency deviation between mea-
FSUP signal source analyzer, the hopping behavior is captured surement and post-simulation is about 0.76 GHz. The measured
from , which is the signal divided by dividers. In closed-loop spectrum of the PLL is shown in Fig. 14, and the
the jitter measurement, the jitter performance of is locking range of the PLL is from 103.058 to 104.58 GHz by
measured because exceeds the frequency limitation of altering reference frequency . When is 406 MHz,
the oscilloscope. of the PLL is locked at 103.936 GHz. The measured ref-
Fig. 13 shows the measured and post-simulated tuning curves erence spur level is shown in Fig. 15. For MHz,
of the proposed VCO. The measured tuning range of the VCO the reference spurs are located near MHz,
is from 103.057 to 104.581 GHz when is changed from 0 and the maximum power level of reference spur is about
to 1.2 V. The measured VCO gain is about 2.6 GHz/V 63.8 dB lower than . Fig. 16 shows the closed-loop
86 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 1, JANUARY 2012

Fig. 15. Reference spur measurement of the PLL at f
= 103:936 GHz for f = 406 MHz.
phase noise measurement of the PLL. According to Fig. 16,
the measured loop bandwidth of the PLL is about 1.8 MHz
at GHz, and the measured loop bandwidth
is slightly lower than the simulated value. One of the pos-
sible reasons for the bandwidth deviation is that the measured
VCO gain ( GHz/V) is lower than the simulated
value ( GHz/V) listed in Table I. The in-band and
out-band phase noise of the PLL are dBc/Hz (at 1-MHz
offset) and dBc/Hz (at 10-MHz offset), respectively.
Because the out-band phase noise of a PLL is usually con-
tributed by the VCO, the phase noise of the proposed VCO can
be also obtained from Fig. 16, which is about dBc/Hz
at 10-MHz offset. Fig. 17 presents frequency-hopping mea-
surement of the PLL. The hopping property is measured from
(about 3.248 GHz). When periodically varies
between 405.5 MHz and 406.5 MHz, is able to lock
between 3.244 GHz and 3.252 GHz. The hopping time of the
PLL is about 50 s when the frequency error is less than 4 ppm.
The jitter performance of the PLL at
is shown in Fig. 18, and the rms jitter and peak-to-peak jitter
are 2.44 ps and 18 ps, respectively. Finally, the measured per-
formance of the proposed VCO and PLL are summarized in
Tables II and III and compared with previous work imple-
mented by nanoscale CMOS technology.

IV. CONCLUSION
The design and implementation of a high-speed VCO above
100 GHz has been presented. Oscillating at secondary resonant
pole, the output frequency of the proposed VCO can be im-
proved. The proposed VCO is also incorporated into a fully in-
tegrated PLL for the purposes of measurement and stable clock
signal generation. For a 1.2-V supply, the tuning range of the
proposed VCO is from 103.057 to 104.581 GHz. The measured
phase noise of the proposed VCO is about dBc/Hz at
10-MHz offset. In the PLL, the locking range of the PLL is from
103.058 to 104.58 GHz by changing reference frequency, and
Fig. 16. Closed-loop phase noise measurement of the PLL at f =
103 936
: GHz. (a) In-band phase noise at 1-MHz offset. (b) Out-band phase the in-band phase noise of the PLL is dBc/Hz at 1-MHz
noise at 10-MHz offset. offset.
TSAI AND LIU: A 104-GHZ PHASE-LOCKED LOOP USING A VCO AT SECOND POLE FREQUENCY 87

Fig. 17. Frequency-hopping measurement of the PLL.

TABLE III
SUMMARY OF THE PLL AND COMPARISON WITH PREVIOUS WORK

Fig. 18. Jitter performance at f =32(= 3:248 GHz).

TABLE II
SUMMARY OF THE PROPOSED VCO AND COMPARISON WITH PRIOR VCOS
NEAR 100 GHZ

ACKNOWLEDGMENT
The authors would like to thank TSMC Co., Hsinchu, Taiwan,
for fabricating this chip through the TSMC university shuttle
program, and Prof. H.-W. Tsao of National Taiwan University
for help in the measurement.
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Kun-Hung Tsai (S’07) was born in Taipei, Taiwan,
in 1981. He received the B.S. degree in electrical en-
gineering from National Central University, Jhongli,
Taiwan, in 2003 and the M.S. degree in electronics
engineering from National Chiao-Tung University,
Hsinchu, Taiwan, in 2005. He is currently working
toward the Ph.D. degree in electronics engineering,
National Taiwan University, Taipei, Taiwan.
His research interests include phase-locked system
and millimeter-wave circuit design.
Shen-Iuan Liu (S’88–M’93–SM’03–F’10) was born
in Keelung, Taiwan, in 1965. He received the B.S.
and Ph.D. degrees in electrical engineering from Na-
tional Taiwan University (NTU), Taipei, Taiwan, in
1987 and 1991, respectively.
During 1991–1993, he served as a Second Lieu-
tenant in the Chinese Air Force. During 1991–1994,
he was an Associate Professor in the Department of
Electronic Engineering, National Taiwan Institute of
Technology. He joined the Department of Electrical
Engineering, NTU, in 1994, where he has been a Pro-
fessor since 1998. Now, he has been an NTU Distinguished Professor since Au-
gust 2010. His research interests are in analog and digital integrated circuits and
systems.
Dr. Liu has served in 2004–2008 as chair of the IEEE SSCS Taipei Chapter,
which achieved the Best Chapter Award in 2009. He has served as general
chair of the 15th VLSI Design/CAD Symposium, Taiwan (2004) and as
Program Co-Chair of the Fourth IEEE Asia-Pacific Conference on Advanced
System Integrated Circuits, Fukuoka, Japan (2004). He was the recipient
of the Engineering Paper Award from the Chinese Institute of Engineers in
2003, the Young Professor Teaching Award from MXIC Inc., the Research
Achievement Award from NTU, and the Outstanding Research Award from
National Science Council in 2004. He has served as a technical program
committee member for ISSCC in 2006–2008, IEEE VLSI-DAT in 2008–2010,
and A-SSCC in 2005–2010. He was an Associate Editor for IEEE JOURNAL OF
SOLID-STATE CIRCUITS in 2006–2009 and a Guest Editor for a IEEE JOURNAL
OF SOLID-STATE CIRCUITS Special Issue in December 2008. He was an Asso-
ciate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS
BRIEFS in 2006–2007. He was an Associate Editor for IEEE TRANSACTIONS
ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS in 2008–2009. He was on the
Editorial Board of Research Letters in Electronics in 2008–2009. He also has
been an Associate Editor for IEICE (The Institute of Electronics, Information
and Communication Engineers) Transactions on Electronics since 2008. He
is an Associate Editor for ETRI Journal, and also an Associate Editor for the
Journal of Semiconductor Technology and Science, Korea, since 2009. He is
a member of IEICE.