BLOCK DIAGRAM

Combo Jack Audio Codec DDR3L 4Gbit x4

ALC5640
Bay Trail-T CR D2516EC4BXGGB
H5TC4G63AFR-PBA
SPK CONN 17mm x 17mm
Bei Ruier Z3735F/G
XHB160905B08-01 x2
0.6W, 8ohm I2S_0 eMMC 16G
I2C_1 KE4CN4K6A-A58
MMC1 H26M52103FMR
DMIC KLMAG2WEMB-B031
GoerTek
SD07OT263-010

SPI (8MB)
Level Shift W25Q64FWZPIG
DDIO_DDC_HPD

XDP Debug CONN

uHDMI CONN DDIO UART3
I2C_1

Rear CAM MCSI_1 SD3 uSD CONN

OV5693
I2C_1

Front CAM MDSI_A LCD CONN

GC2155 D2HD K&D
OV2722 D2W MCSI_2 KD080D10-31NA-A7
I2C_2 MIPI, 1280x800

22.8V FB1~3
USB PHY USB_ULPI
USB SWITCH TUSB1210
uUSB CONN AOZ6184 Vibrator BKLT DRV
TPS61176
USB2_P1
I2C_0

Charger I2C_3 Touch CONN

BQ24297 I2C_0 FocalTech
BATTHERM Sensor FT5506
5V Boost +VBUS_CONN

I2C_2 Gyro/G Combo

MPU-6515
PMIC I2C_4
Gauge
SYSTHERM Sensor
SND9039ABTRSK SD2 WIFI/BT/FM

SOC Rails & UART1 BCM43340 COB

BAT CONN Supply to all other IOs
I2S_1
LGC Polymer
Springpower
4600mAh
1S1P UART2 GPS
BCM4752
HDMI 5V To HDMI
TPS60151
PWR & Volume
GPIOs
25MHz
Button x3
Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
32.768KHz Ducati2 BAYt_CR OrCAD Lib Ver
Title: 01_BLOCK DIAGRAM

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 1 of 39
TABLE OF CONTENTS & NOTES

TABLE OF CONTENTS I2C MAP

SHEET NO. SHEET NAME INTERFACE PART I2C_0 I2C_1 I2C_2 I2C_3 I2C_4

1 BLOCK DIAGRAM TOUCH CONTROLLER FT5506 0x70

2 TABLE OF CONTENTS & NOTES
AUDIO CODEC ALC5640 0x38
3 SOC: MEMORY

4 SOC: DISPLAY & CAMERA PMIC SND9039ABTRSK 0x5C~5F

5 SOC: STORAGE & I2S
GYRO/G SENSOR MPU-6515 0x69
6 SOC: USB & I2C

7 SOC: PMU/DFX/CLK/UART/SUS FRONT CAMERA GC2155 (D2HD) 0x3C/0x78/0x79

OV2722 (D2W) 0x36/0x6D/0x6C
8 SOC: POWER 1

9 SOC: POWER 2 REAR CAMERA OV5693 0x10/0x21/0x20

0x0C/0x19/0x18
10 SOC: GND

11 SOC: DECOUPLING LCD (NC in LCM) KD080D10-31NA-A7 0xXX

12 PMIC: SWITCHING REGULATORS
XDP CONNECTOR 0xXX
13 PMIC: LDOS

14 PMIC: HOST & MISC INTERFACES Charger BQ24297 0x6B

15 PMIC: EXTERNAL REGULATORS

16 MEMORY DEVICE 0 & 1

17 MEMORY DEVICE 2 & 3

18 MEMORY TERMINATION

19 SPI NOR FLASH

20 USB PHY & MUX

21 EMMC

22 BLANK PAGE

23 CAMERA CONNECTOR

24 TOUCH CONNCTOR & SHIELDS & HOLES

25 MIPI-DISPLAY CONNECTOR

26 SENSORS

27 AUDIO ALC5640

28 SPEAKER & DMIC & JACK

29 LCM LED BOOST

30 USB CONNECTOR

31 HDMI LEVEL SHIFTERS

32 HDMI CONNECTOR

33 MICRO-SD CONNECTOR

34 WIFI-BT

35 GPS

36 BATTERY & DEBUG CONNECTOR

37 POWER SEQUENCE

38 CHANGE LIST

39 POWER TREE

40

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 02_TABLE OF CONTENTS & NOTES

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 2 of 39
SOC: MEMORY

?
U1A
M24 D18
16,18 M0_MA0 DRAM0_MA[00] DRAM0_DQ[00] M0_DATA0 16
L23 B18
16,18 M0_MA1 DRAM0_MA[01] DRAM0_DQ[01] M0_DATA1 16
N23 A21
16,18 M0_MA2 DRAM0_MA[02] DRAM0_DQ[02] M0_DATA2 16
M20 C18
16,18 M0_MA3 DRAM0_MA[03] DRAM0_DQ[03] M0_DATA3 16
M22 A22
16,18 M0_MA4 DRAM0_MA[04] DRAM0_DQ[04] M0_DATA4 16
L22 B20
16,18 M0_MA5 DRAM0_MA[05] DRAM0_DQ[05] M0_DATA5 16
K24 A18
16,18 M0_MA6 DRAM0_MA[06] DRAM0_DQ[06] M0_DATA6 16
N25 B22
16,18 M0_MA7 DRAM0_MA[07] DRAM0_DQ[07] M0_DATA7 16
J25 C20
16,18 M0_MA8 DRAM0_MA[08] DRAM0_DQ[08] M0_DATA8 16
H24 D23
16,18 M0_MA9 DRAM0_MA[09] DRAM0_DQ[09] M0_DATA9 16
N20 E19
16,18 M0_MA10 DRAM0_MA[10] DRAM0_DQ[10] M0_DATA10 16
K25 E23
16,18 M0_MA11 DRAM0_MA[11] DRAM0_DQ[11] M0_DATA11 16
M25 D22
16,18 M0_MA12 DRAM0_MA[12] DRAM0_DQ[12] M0_DATA12 16
M23 E22
16,18 M0_MA13 DRAM0_MA[13] DRAM0_DQ[13] M0_DATA13 16
H25 E20
16,18 M0_MA14 DRAM0_MA[14] DRAM0_DQ[14] M0_DATA14 16
K23 D20
DRAM0_MA[15] DRAM0_DQ[15] M0_DATA15 16
E25
DRAM0_DQ[16] M0_DATA16 16
A20 A23
16 M0_DM0 DRAM0_DM[0] DRAM0_DQ[17] M0_DATA17 16
D21 C23
16 M0_DM1 DRAM0_DM[1] DRAM0_DQ[18] M0_DATA18 16
D25 F25
16 M0_DM2 DRAM0_DM[2] DRAM0_DQ[19] M0_DATA19 16
F19 B24
16 M0_DM3 DRAM0_DM[3] DRAM0_DQ[20] M0_DATA20 16
AC24 D24
17 M0_DM4 DRAM0_DM[4] DRAM0_DQ[21] M0_DATA21 16
V24 B23
17 M0_DM5 DRAM0_DM[5] DRAM0_DQ[22] M0_DATA22 16
Y22 F24
17 M0_DM6 DRAM0_DM[6] DRAM0_DQ[23] M0_DATA23 16
T23 F20
17 M0_DM7 DRAM0_DM[7] DRAM0_DQ[24] M0_DATA24 16
F21
DRAM0_DQ[25] M0_DATA25 16
N22 G20
16,18 M0_RASB DRAM0_RAS# DRAM0_DQ[26] M0_DATA26 16
P20 H23
16,18 M0_CASB DRAM0_CAS# DRAM0_DQ[27] M0_DATA27 16
P21 G21
16,18 M0_WEB DRAM0_WE# DRAM0_DQ[28] M0_DATA28 16
J21
DRAM0_DQ[29] M0_DATA29 16
M21 J20
16,18 M0_BS0 DRAM0_BS[0] DRAM0_DQ[30] M0_DATA30 16
N19 H22
16,18 M0_BS1 DRAM0_BS[1] DRAM0_DQ[31] M0_DATA31 16
K22 AD24
16,18 M0_BS2 DRAM0_BS[2] DRAM0_DQ[32] M0_DATA32 17
AB25
DRAM0_DQ[33] M0_DATA33 17
P22 Y24
16,18 M0_CS0_B DRAM0_CS[0]# DRAM0_DQ[34] M0_DATA34 17
1 OF 9 AE23
DRAM0_DQ[35] M0_DATA35 17
P23 AA25
DRAM0_CS[2]# DRAM0_DQ[36] M0_DATA36 17
VLV2_CR AC23
DRAM0_DQ[37] M0_DATA37 17
AD23
DRAM0_DQ[38] M0_DATA38 17
G22 Y25
16,18 M0_CKE0 DRAM0_CKE[0] DRAM0_DQ[39] M0_DATA39 17
G23 V23
DRAM0_CKE[1] DRAM0_DQ[40] M0_DATA40 17
F23 T24
DRAM0_CKE[2] DRAM0_DQ[41] M0_DATA41 17
F22 W22
DRAM0_CKE[3] DRAM0_DQ[42] M0_DATA42 17
W23
DRAM0_DQ[43] M0_DATA43 17
P24 R23
16,18 M0_ODT0 DRAM0_ODT[0] DRAM0_DQ[44] M0_DATA44 17
R22
DRAM0_DQ[45] M0_DATA45 17
P25 V22
DRAM0_ODT[2] DRAM0_DQ[46] M0_DATA46 17
T25
DRAM0_DQ[47] M0_DATA47 17
AB22
DRAM0_DQ[48] M0_DATA48 17
J23 AC22
16,18 M0_CLK0_DP DRAM0_CKP[0] DRAM0_DQ[49] M0_DATA49 17
J22 Y19
PLACE CLOSE TO SOC 16,18 M0_CLK0_DN DRAM0_CKN[0] DRAM0_DQ[50]
DRAM0_DQ[51]
AD22
M0_DATA50
M0_DATA51
17
17
AA22
+VDDQ_DDR DRAM0_DQ[52] M0_DATA52 17
K20 Y23
DRAM0_CKP[2] DRAM0_DQ[53] M0_DATA53 17
K21 Y20
DRAM0_CKN[2] DRAM0_DQ[54] M0_DATA54 17
R301 Y21
DRAM0_DQ[55] M0_DATA55 17
T22
4.7K PR 0402

DRAM0_DQ[56] M0_DATA56 17
T20
DRAM0_DQ[57] M0_DATA57 17
U19 W20
16,18 M0_DRAMRSTB DRAM0_DRAMRST# DRAM0_DQ[58] M0_DATA58 17
V20
DRAM0_DQ[59] M0_DATA59 17
U21
DRAM0_DQ[60] M0_DATA60 17
AD20 W21
DRAM_VREF DRAM0_DQ[61] M0_DATA61 17
U20
DRAM0_DQ[62] M0_DATA62 17
R302 C301 T21
DRAM0_DQ[63] M0_DATA63 17
4.7K PR 0402

0.1UF C 0402 10V

D19
DRAM0_DQSP[0] M0_DQS0_DP 16
C19
DRAM0_DQSN[0] M0_DQS0_DN 16
C22
DRAM0_DQSP[1] M0_DQS1_DP 16
AC20 C21
13 DDR3_DRAM_PWROK DRAM_VDD_S4_PWROK DRAM0_DQSN[1] M0_DQS1_DN 16
AB20 C24
13 DDR3_VCCA_PWROK DRAM_CORE_PWROK DRAM0_DQSP[2] M0_DQS2_DP 16
C25
DRAM0_DQSN[2] M0_DQS2_DN 16
H20
DRAM0_DQSP[3] M0_DQS3_DP 16
H19
DRAM0_DQSN[3] M0_DQS3_DN 16
DDR3_SOC_ODTPU AE22 AC25
DRAM_RCOMP[2] DRAM0_DQSP[4] M0_DQS4_DP 17
DDR3_SOC_DQPU AE20 AB24
DRAM_RCOMP[1] DRAM0_DQSN[4] M0_DQS4_DN 17
DDR3_SOC_CMDPU AE21 V25
DRAM_RCOMP[0] DRAM0_DQSP[5] M0_DQS5_DP 17
U25
DRAM0_DQSN[5] M0_DQS5_DN 17
R303 R304 R305 AB23
DRAM0_DQSP[6] M0_DQS6_DP 17
AA23
162ohm 1% R 0402

29.4ohm 1% R 0402

23.2ohm 1% R 0402

DRAM0_DQSN[6] M0_DQS6_DN 17
U22
DRAM0_DQSP[7] M0_DQS7_DP 17
U23
DRAM0_DQSN[7] M0_DQS7_DN 17

Z3735F
REV = 2.0

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 03_SOC_ MEMORY

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 3 of 39
SOC: DISPLAY & CAMERA

? +V1P8A_SOC
U1B
AB4 U7
32 DDI0_TX0_DP DDI0_TXP[0] DDI1_TXP[0]
AB3 U6
32 DDI0_TX0_DN DDI0_TXN[0] DDI1_TXN[0]
AB2 V5 R402
32 DDI0_TX1_DP DDI0_TXP[1] DDI1_TXP[1]
AA1 V4

100K R 0402
32 DDI0_TX1_DN DDI0_TXN[1] DDI1_TXN[1]
Y2 T1
32 DDI0_TX2_DP DDI0_TXP[2] DDI1_TXP[2]
Y1 U1
32 DDI0_TX2_DN DDI0_TXN[2] DDI1_TXN[2]
Y4 U4
32 DDI0_TX3_DP DDI0_TXP[3] DDI1_TXP[3]
Y3 U5
HDMI 32 DDI0_TX3_DN DDI0_TXN[3] DDI1_TXN[3]
Y5
DDI1_AUXP W6
DDI1_AUXN B12 DDI1_HPD
E14 DDI1_HPD
32 DDI0_HPD_N DDI0_HPD
D13
32 DDI0_DDC_SDA DDI0_DDCDATA
C13 B14
32 DDI0_DDC_SCL DDI0_DDCCLK DDI1_VDDEN LCM_RST_N 25
A14 DDI1_BKLTEN 1 TP3650 TEST_POINT_20
DDI1_BKLTEN A13
DDI1_BKLTCTL DDI1_BKLTCTL 25

R401
2 OF 9
402 PR 0402

DDI0_PLLOBS_DP AA3
DDI0_PLLOBS_DN AA4 DDI_RCOMP_P VLV2_CR
DDI_RCOMP

M5
MCSI1_CLKN MCSI_1_CLK_DN 23
P5 M6
25 MDSI_A_CLKN MDSI_A_CLKN MCSI1_CLKP MCSI_1_CLK_DP 23
P4
25 MDSI_A_CLKP MDSI_A_CLKP P3
T4 MCSI1_DN[0] P2
MCSI_1_DATA0_DN 23 5M CAMERA
25 MDSI_A_DN_0 MDSI_A_DN[0] MCSI1_DP[0] MCSI_1_DATA0_DP 23
T3 M1
25 MDSI_A_DP_0 MDSI_A_DP[0] MCSI1_DN[1] MCSI_1_DATA1_DN 23
R4 N1
MIPI DSI 25 MDSI_A_DN_1
R3 MDSI_A_DN[1] MCSI1_DP[1] M4
MCSI_1_DATA1_DP 23
25 MDSI_A_DP_1 MDSI_A_DP[1] MCSI1_DN[2]
T6 M3
25 MDSI_A_DN_2 MDSI_A_DN[2] MCSI1_DP[2]
T5 L3
25 MDSI_A_DP_2 MDSI_A_DP[2] MCSI1_DN[3]
P6 L4
25 MDSI_A_DN_3 MDSI_A_DN[3] MCSI1_DP[3]
N6 K4
25 MDSI_A_DP_3 MDSI_A_DP[3] MCSI2_CLKN MCSI_2_CLK_DN 23
K5
MCSI2_CLKP MCSI_2_CLK_DP 23
K6 2M CAMERA
MCSI2_DN[0] MCSI_2_DATA_DN 23
J6
MCSI2_DP[0] MCSI_2_DATA_DP 23

K1 MCSI_COMP
MCSI_RCOMP R403
D17

150 PR 0402
GPIO_S0_NC[15] CHG_DISABLE 14
B16
GPIO_S0_NC[16] MEMORY_SEL0 5
C15
GPIO_S0_NC[17] CAM1_RESET_N 23
C14
GPIO_S0_NC[18] CAM2_RESET_N 23
C17
GPIO_S0_NC[19] CODEC_RESET 27
MDSI_COMP P1 C16
MDSI_RCOMP GPIO_S0_NC[20] CAMERA_1_VCM_PD_N 23
F17 D16
MDSI_A_TE GPIO_S0_NC[21] CAMERA_1_PD_N 23
R404 D15
GPIO_S0_NC[22] CAMERA_2_PD 23
D14
150 PR 0402

GPIO_S0_NC[23] F18
GPIO_S0_NC[24] BT_DEV_WAKE 34
E17
GPIO_S0_NC[25] BT_REG_ON 34
E16
GPIO_S0_NC[26] TOUCH_RESET_N 24

Z3735F
REV = 2.0

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 04_SOC_ DISPLAY & CAMERA

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 4 of 39
SOC: STORAGE & I2S
+V1P8A_SOC +V1P8A_SOC
A Build: sku1 & sku4
B/C Build: sku1 & sku2
Pre-MP Build: sku1 & sku2
R502 R503

10K PR 0402

10K PR 0402
1G Hynix 1G Kingston 2G Hynix 2G Kingston @
(sku1) (sku2) (sku3) (sku4)

MEMORY_SEL0 Low Low High High 4 MEMORY_SEL0

5 MEMORY_SEL1
R504 R505
MEMORY_SEL1 High Low High Low

10K PR 0402

10K PR 0402
@

?
U1C Vendor SOE O-Film
AB6
31 GPI_VOLUMEDOWN GPIO_S0_SC[00]
AA6
31 GPI_VOLUMEUP GPIO_S0_SC[01]
Y6 TOUCH_ID 1 0
5 MEMORY_SEL1 GPIO_S0_SC[02] +V1P8A_SOC

R3682

100K PR 0402
AE8
21 EMMC_CLK MMC1_CLK
AB7
21 EMMC_DATA_0 MMC1_D[0]
AC7 AC5 TOUCH_ID
21 EMMC_DATA_1 MMC1_D[1] GPIO_S0_SC[03] TOUCH_ID 24
AC8
21 EMMC_DATA_2 MMC1_D[2]
AB9 3 OF 9
21 EMMC_DATA_3 MMC1_D[3]
AA9
21 EMMC_DATA_4 MMC1_D[4]
AA8 VLV2_CR AA5
eMMC 21 EMMC_DATA_5
Y8 MMC1_D[5] GPIO_S0_SC[07] SDMMC3_CD_N 5,33
21 EMMC_DATA_6 MMC1_D[6]
Y7
21 EMMC_DATA_7 MMC1_D[7]
AB8
21 EMMC_CMD MMC1_CMD
AD8
21 EMMC_RESET_N MMC1_RST# AE14 AUDIO_RCOMP
EMMC_RCOMP AE6 AUDIO_RCOMP Y16 R506
MMC1_RCOMP I2S0_CLK I2S_0_CLK 27
Y14

49.9 PR 0402
I2S0_L_R I2S_0_FS 27
R501 AE9 AA14
SDIO2_CLK SD2_CLK I2S0_DATAOUT Y13
I2S_0_TXD 27 CODEC
49.9 PR 0402

I2S0_DATAIN I2S_0_RXD 27
AB11
34 SDIO2_DATA_0 SD2_D[0]
AB10 AC13
WLAN 34 SDIO2_DATA_1
AC10 SD2_D[1] I2S1_CLK AC14
I2S_1_CLK 34
34 SDIO2_DATA_2 SD2_D[2] I2S1_L_R I2S_1_FS 34
AD10 AB14
34 SDIO2_DATA_3
AC9 SD2_D[3]_CD# I2S1_DATAOUT Y10
I2S_1_TXD 34 WLAN
34 SDIO2_CMD SD2_CMD I2S1_DATAIN I2S_1_RXD 34
U17 1 TP3642 TEST_POINT_20
GPIO_S0_SC[65]
AC12
33 SDMMC3_CLK SD3_CLK
TP on bottom side
AC11
33 SDMMC3_D0 SD3_D[0]
AB13
33 SDMMC3_D1 SD3_D[1]
AA12
33 SDMMC3_D2 SD3_D[2]
AA13
33 SDMMC3_D3 SD3_D[3]
SD CARD Y12
5,33 SDMMC3_CD_N SD3_CD#
AB12
33 SDMMC3_CMD SD3_CMD
Y9 F16
AA10 SD3_1P8EN PROCHOT#
SD3_PWREN#
SDMMC3_RCOMP AE10
SD3_RCOMP
R507
49.9 PR 0402

Z3735F
REV = 2.0

SDIO2_CLK SDIO2_CLK_S Drawing Rule

R3619 0 R 0402

C3632
SDIO2_CLK_S 34
Acer Inc. Allegro Lib Ver
Project:
22pF C 0402 50V
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 05_SOC_ STORAGE & I2S

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 5 of 39
SOC: USB & I2C

?
U1D
A8 USB3_REXT_P1
N3 USB_REXT[1]
20 USB_ULPI_0_CLK USB_ULPI_CLK C1 USB3_REXT_P0
J5 USB_REXT[0]
20 USB_ULPI_0_DATA0 USB_ULPI_DATA[0]
H5 A4 GPIO_RCOMP
20 USB_ULPI_0_DATA1 USB_ULPI_DATA[1] GPIO_RCOMP
J4
20 USB_ULPI_0_DATA2 USB_ULPI_DATA[2]
H1 R602 R603 R604
20 USB_ULPI_0_DATA3 USB_ULPI_DATA[3]
H2

49.9 PR 0402

1.24K PR 0402

1.24K PR 0402
20 USB_ULPI_0_DATA4 USB_ULPI_DATA[4]
J3 AC6
20 USB_ULPI_0_DATA5 USB_ULPI_DATA[5] GPIO_S0_SC[57] UART3_DEBUG_TXD 28,36
J1
20 USB_ULPI_0_DATA6 USB_ULPI_DATA[6]
K2
20 USB_ULPI_0_DATA7 USB_ULPI_DATA[7]
K3 AD6
20 USB_ULPI_0_DIR USB_ULPI_DIR GPIO_S0_SC[61] UART3_DEBUG_RXD 28,36
N4
20 USB_ULPI_0_NXT USB_ULPI_NXT
M2 AE5
20 USB_ULPI_0_STP USB_ULPI_STP GPIO_S0_SC[54] USB_ULPI_0_CS 20
F10
20 USB_ULPI_0_REFCLK USB_ULPI_REFCLK
G4 AE12
USB_DP[0] SIO_I2C0_DATA I2C_0_SDA 14
G3 AD12 Charger, USB Switch
USB_DN[0] SIO_I2C0_CLK I2C_0_SCL 14
H4 AE13
20 USB2_P1_DP USB_DP[1] SIO_I2C1_DATA I2C_1_SDA 23,27,36
Micro USB H3 AD14 Codec, Front/Rear Camera, XDP
20 USB2_P1_DN USB_DN[1] 4 OF 9 SIO_I2C1_CLK I2C_1_SCL 23,27,36
+V1P8A_SOC AB15
SIO_I2C2_DATA I2C_2_SDA 25,26
VLV2_CR AC15 Gyro/G Sensor, LCD (reserved)
SIO_I2C2_CLK I2C_2_SCL 25,26
R3642 AB16
SIO_I2C3_DATA I2C_3_SDA 24
AC16 Touch
10K R 0402

SIO_I2C3_CLK I2C_3_SCL 24
AD16
SIO_I2C4_DATA I2C_4_SDA 13
AE16 PMIC
SIO_I2C4_CLK I2C_4_SCL 13
F13
F14 USB_OC[0]# AA17
34 WL_REG_ON USB_OC[1]# D1_I2C_DATA AB17
USB_RCOMP F1 D1_I2C_CLK
USB_RCOMPO
USB_ULPI_0_CS
R601
R605
45.3 PR 0402

Z3735F

10K R 0402
REV = 2.0

RCOMP: PLACE AS CLOSE AS POSSIBLE TO SOC. PREFERABLY TRACE RESISTANCE < 0.5OHM

+V1P8A_SOC

R606 R607 R608 R609 R610 R611 R612 R613 R614 R615
1K PR 0402

1K PR 0402
2.2K PR 0402

2.2K PR 0402

2.2K PR 0402

2.2K PR 0402

2.2K PR 0402

2.2K PR 0402

2.2K PR 0402

2.2K PR 0402
I2C_0_SCL
I2C_0_SDA
I2C_1_SCL
I2C_1_SDA
I2C_2_SCL
I2C_2_SDA
I2C_3_SCL
I2C_3_SDA
I2C_4_SCL
I2C_4_SDA

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 06_SOC_ USB & I2C

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 6 of 39
SOC: PMU & DFX & CLOCK & UART & SUS

?
U1E
XTAL25_IN V3 AB19
ICLK_OSCIN SIO_UART1_RXD UART_1_BT_RXD 34
XTAL25_OUT V2 AC19
1 G 4
ICLK_OSCOUT SIO_UART1_TXD AC18
UART_1_BT_TXD 34 WLAN
SIO_UART1_RTS# UART_1_BT_RTS 34
AB18
SIO_UART1_CTS# UART_1_BT_CTS 34
2 3
G ICLK_ICOMP V1 AD18
ICLK_ICOMP SIO_UART2_RXD UART_2_GPS_RXD 35
X701 AE18
25MHz 10pF SIO_UART2_TXD AC17
UART_2_GPS_TXD 35 GPS
SIO_UART2_RTS# UART_2_GPS_RTS 35
AE17
SIO_UART2_CTS# UART_2_GPS_CTS 35
R702
R701 1M PR 0402 D10

4.02K PR 0402
PMC_SUSPWRDNACK SUSPWRDNACK 13
A9 1 TP702 TEST_POINT_20
C701 C3707 PMC_SUSCLK_0 C7
PMC_SLP_S0IX# PMU_SLP_S0IX_N 13,15,18,32
D8 1
15pF C 0402 50V

15pF C 0402 50V

PMC_SLP_S4# TP706 TEST_POINT_20 USB_ID_CONN 20,30

C8 1 TP707 TEST_POINT_20
PMC_SLP_S3# C6
USB_ULPI_RST# USB_ULPI_RESET_N 20 +VRTC
B8
PMC_ACPRESENT B10
GPIO_S5[15] COMBO_WLAN_IRQ 34
C9
PMC_PWRBTN# must have internal pull-up PMC_BATLOW# A10 1 TP705 TEST_POINT_20
PMC_PWRBTN# R703
B6

20K PR 0402
PMC_PLTRST# PLTRST_N 13,36
AB5 D9
23 PLT_CLK0_CAM1 PMC_PLT_CLK[0] GPIO_S5[17] BT_HOST_WAKE 34
AE4 E10 PMC_SUS_STAT# R704 0 R 0402
23 PLT_CLK1_CAM2 PMC_PLT_CLK[1] 5 OF 9 PMC_SUS_STAT#
AD4
27 CODEC_MCLK PMC_PLT_CLK[3]
XDP_H_TRST_N AD2 VLV2_CR E3 RTEST_N
HW_BOARD_ID2 PMC_PLT_CLK[4] ILB_RTC_TEST#
F3 C703
PMC_RSMRST# RSMRST_N 13,36
R705 F2

1uF C 0402 10V

PMC_CORE_PWROK COREPWROK 13,36
E5
51 PR 0402

36 XDP_H_TCK TAP_TCK
G6 E4
36 XDP_H_TRST_N TAP_TRST# ILB_RTC_RST# SRTCRST_N 36
H6 D1 RTC_X1
36 XDP_H_TMS TAP_TMS ILB_RTC_X1
F4 E1 RTC_X2
XDP 36 XDP_H_TDI
F6 TAP_TDI ILB_RTC_X2 D2 BVCCRTC_EXTPAD
36 XDP_H_TDO TAP_TDO ILB_RTC_EXTPAD X702
F7 C704
36 XDP_H_PRDY_N TAP_PRDY#
F5 2 1 Changed to Q-SC20S0322070AAAF

0.1uF C 0402 16V

36 XDP_H_PREQ_N TAP_PREQ# (follow FHD)
C10
SVID_ALERT# C11
SVID_DATA D11 32.768KHz 7pF
C12 SVID_CLK R706 10M PR 0402 RSMRST_N
19 SPI_NOR_CS0_N PCU_SPI_CS[0]#
+V1P8A_SOC
D12 AA16
28 UART3_DEBUG_SW PCU_SPI_CS[1]# SIO_PWM[0] MIPI_PWM_BKLT_EN 29
E13 Y17
19 SPI_NOR_MISO PCU_SPI_MISO SIO_PWM[1] SOC_VIBRA_PWM 31
E12 R3644
19 SPI_NOR_MOSI PCU_SPI_MOSI
F12 C706 C705

100K R 0402
19 SPI_NOR_CLK PCU_SPI_CLK
R707 Changed to 8pF (follow FHD) 8pF C 0402 50V 7pF C 0402 50V
A6
51 PR 0402

GPIO_S5[22] GPS_WAKEUP 35
@ E9 B4
13 PMIC_INT GPIO_S5[00] GPIO_S5[23] LCM_ID1 25
GPIO_SUS1 D7 A3
GPIO_S5[01] GPIO_S5[24] LCM_ID 25
GPIO_SUS2 F9 B3 Changed to 7pF (follow FHD)
GPIO_S5[02] GPIO_S5[25] GYRO_INT1 26
GPIO_SUS3 E8 B2
GPIO_SUS4 F8 GPIO_S5[03] GPIO_S5[26] C2
XDP_H_TDO GPIO_S5[04] GPIO_S5[27] JACK_DET_N_R2 28
D6 C3
34 WIFI_32K_CLK GPIO_S5[05] GPIO_S5[28] LCM_3P3V_EN 25
TEST_POINT_20TP3613 1 D4 C4
PLACE WITHIN 0.25' 35 GPS_32K_CLK
D5 GPIO_S5[06]
GPIO_S5[07]
GPIO_S5[29]
GPIO_S5[30]
A5
LCM_1P8V_EN
BUCK_3P3V_EN
25

FROM XDP CONN

D3
HW_BOARD_ID0 GPIO_S5[08]
E6
HW_BOARD_ID1 GPIO_S5[09]
R708 51 PR 0402 XDP_H_TCK C5 +V1P8A_SOC
14 CHG_STAT GPIO_S5[10]

Z3735F
REV = 2.0
+V1P8A_SOC +V1P8A_SOC +V1P8A_SOC +V1P8A_SOC R730 R713 +VRTC

100K PR 0402

100K PR 0402
@

+V1P8A_SOC
R3680 R709 R710
R3683 R712 R714

10K PR 0402

10K PR 0402

10K PR 0402
@ @ LCM_ID
10K PR 0402

10K R 0402

20K PR 0402
CHG_INT_N requires 10K pull-up

R715 R716 LCM_ID1

JTAG2_TMS HW_BOARD_ID0
51 PR 0402

51 PR 0402

GPIO_SUS2 R717 0 R 0402 HW_BOARD_ID1 SRTCRST_N

CHG_INT_N 14
HW_BOARD_ID2
JTAG2_TDI C707
GPIO_SUS3 R718 0 R 0402 R3681 R719 R720

1uF C 0402 10V

TOUCH_INT_N 24
10K PR 0402

10K PR 0402

10K PR 0402
XDP_H_TDI JTAG2_TDO @
GPIO_SUS4 R721 0 R 0402
AUDIO_INT 27
XDP_H_TMS
JTAG2_TCK
GPIO_SUS1 R722 0 R 0402
USBMUX_SEL 20
R723
51 PR 0402

Drawing Rule

@
V0.1
A/B
V0.2 V0.3
C Pre-MP
V0.4
Android Windows
Acer Inc. Allegro Lib Ver
Project:
Ducati2 BAYt_CR
HW_Board_ID0 Low High Low High HW_Board_ID2 Low High Title: OrCAD Lib Ver
07_SOC_ PMU_DFX_CLK_UART_SUS

HW_Board_ID1 Low Low High High Approved: Size: Document Number: Rev
POPOLATE ONLY FOR DEBUG VERSION C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 7 of 39
SOC: POWER 1

+V_VNN
+V_VCC
?
U1F +V1P2SX +V1P2SX_SOC
A12 U12
G15 CORE_VCC_S0IX_1 UNCORE_VNN_S4_26 K12 SH701
H14 CORE_VCC_S0IX_3 UNCORE_VNN_S4_2 L11 1 2
H15 CORE_VCC_S0IX_4 UNCORE_VNN_S4_3 L12
H16 CORE_VCC_S0IX_5 UNCORE_VNN_S4_4 L13 SHORT-0402
K13 CORE_VCC_S0IX_6 UNCORE_VNN_S4_5 M11
K14 CORE_VCC_S0IX_8 UNCORE_VNN_S4_8 M12
CORE_VCC_S0IX_9 UNCORE_VNN_S4_9 +VDDQ +VDDQ_SOC
K15 M9
K16 CORE_VCC_S0IX_10 UNCORE_VNN_S4_11 N10 SH3636
L14 CORE_VCC_S0IX_11 UNCORE_VNN_S4_12 N11 1 2
L15 CORE_VCC_S0IX_12 UNCORE_VNN_S4_13 N12
L16 CORE_VCC_S0IX_13 UNCORE_VNN_S4_14 M10 SHORT-0603
M14 CORE_VCC_S0IX_14 UNCORE_VNN_S4_7 R13
F15 CORE_VCC_S0IX_15 UNCORE_VNN_S4_15 L9
M15 CORE_VCC_S0IX_2 UNCORE_VNN_S4_6 T11
N14 CORE_VCC_S0IX_16 UNCORE_VNN_S4_17 T12
N15 CORE_VCC_S0IX_17 UNCORE_VNN_S4_18 T13
P13 CORE_VCC_S0IX_18 UNCORE_VNN_S4_19 T14
P14 CORE_VCC_S0IX_19 UNCORE_VNN_S4_20 T15
P15 CORE_VCC_S0IX_20 UNCORE_VNN_S4_21 T16
P16 CORE_VCC_S0IX_21 UNCORE_VNN_S4_22 T17
J17 CORE_VCC_S0IX_22 UNCORE_VNN_S4_23 U10
CORE_VCC_S0IX_7 UNCORE_VNN_S4_24 U11
6 OF 9 UNCORE_VNN_S4_25 U13
UNCORE_VNN_S4_27 U14
+VDDQ_SOC UNCORE_VNN_S4_28
VLV2_CR U15
W19 UNCORE_VNN_S4_29 U16
+V1P2SX_SOC +VDDQ_SOC DRAM_VDD_S4_7 UNCORE_VNN_S4_30
L18 V10
L19 DRAM_VDD_S4_2 UNCORE_VNN_S4_31 V11
M19 DRAM_VDD_S4_3 UNCORE_VNN_S4_32 V13
L20 DRAM_VDD_S4_5 UNCORE_VNN_S4_33 V17
K18 DRAM_VDD_S4_4 UNCORE_VNN_S4_34 R8
DRAM_VDD_S4_1 UNCORE_VNN_S4_16 V18
T19 UNCORE_VNN_S4_35 W18
DRAM_VDD_S4_6 UNCORE_VNN_S4_36 AB1
P19 UNCORE_VNN_S4_1 M8
DRAM_V1P24_S0IX_F1 UNCORE_VNN_S4_10

Z3735F
REV = 2.0

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 08_SOC_ POWER 1

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 8 of 39
SOC: POWER 2

+V1P0A +V1P0A_SOC
SH901
1 2

SHORT-0603

+V1P2A +V1P2A_SOC
SH902
1 2
+V1P0A_SOC
SHORT-0402

+V1P0A_SOC
?
U1G
J16 L17
M16 CORE_V1P05_S4_5 CORE_V1P05_S4_7 K17
CORE_V1P05_S4_8 CORE_V1P05_S4_6 G18
CORE_V1P05_S4_4 R18
J7 CORE_V1P05_S4_10 R17
K8 UNCORE_V1P0_G3_1 CORE_V1P05_S4_9 A17
L7 UNCORE_V1P0_G3_4 CORE_V1P05_S4_2 G17
K7 UNCORE_V1P0_G3_6 CORE_V1P05_S4_3 A16 +V1P0SX
W10 UNCORE_V1P0_G3_3 CORE_V1P05_S4_1
GPIO_V1P0_S4 7 OF 9

VLV2_CR R11
G8 UNCORE_V1P0_S0IX_4 R10
USB_V1P0_S4_1 UNCORE_V1P0_S0IX_3 +V1P2A_SOC
T10
UNCORE_V1P0_S0IX_5 H11
UNCORE_V1P0_S0IX_1 H12
UNCORE_V1P0_S0IX_2 N7
H7 MIPI_V1P24_S4_1 P7
USB_V1P0_S4_2 MIPI_V1P24_S4_2 +V1P8A_SOC
H8
UNCORE_V1P0_S4 W16
UNCORE_V1P8_S4_3 W12
UNCORE_V1P8_S4_1 Y15
UNCORE_V1P8_S4_4 +V1P8A_SOC
+V1P0SX
W13
UNCORE_V1P8_S4_2 J15
MIPI_V1P8_S4
V15 G11
W15 UNCORE_V1P0_S0IX_6 UNCORE_V1P8_G3
V16 UNCORE_V1P0_S0IX_8 J10 +VSDIO
UNCORE_V1P0_S0IX_7 PMC_V1P8_G3_2 +VRTC +V3P3A_SOC
H10
PMC_V1P8_G3_1 K10
K9 PMC_V1P8_G3_3
J9 UNCORE_V1P0_G3_5 F11
UNCORE_V1P0_G3_2 RTC_VCC H9
+V1P0SX USB_V3P3_S0IX G12
T7 PCU_V3P3_G3
U8 DDI_V1P0_S0IX_1 W14
T8 DDI_V1P0_S0IX_3 SD3_V1P8V3P3_S4
DDI_V1P0_S0IX_2 +V1P2A_SOC +V1P2SX_SOC
M7
AE24 ICLK_V1P24_S4_F1 N8
H18 DRAM_V1P0_S4_1 ICLK_V1P24_S4_F2 P12
G19 DRAM_V1P0_S4_3 UNCORE_V1P24_S0IX_F5 H13
U18 DRAM_V1P0_S4_2 UNCORE_V1P24_S0IX_F4_2 G13
N18 DRAM_V1P0_S4_6 UNCORE_V1P24_S0IX_F4_1
M18 DRAM_V1P0_S4_5 P9
DRAM_V1P0_S4_4 UNCORE_V1P24_S0IX_F1

Z3735F
REV = 2.0

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 09_SOC_ POWER 2

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 9 of 39
SOC: GND & RESERVED PINS

?
U1H
V8 W8
V7 VSS86 VSS92 W7
E7 VSS85 VSS91
E24 VSS28 W9
E21 VSS27 VSS93 V12
E2 VSS26 VSS80 Y11 ?
E18 VSS25 VSS94 W5
VSS24 VSS90 U1I
E15 V6 AC4
E11 VSS23 VSS84 V21 AC3 RESERVED9
B9 VSS22 VSS83 V14 AE3 RESERVED8 9 OF 9
B5 VSS21 VSS81 U9 AD3 RESERVED13
B21 VSS20 VSS79 U24 AC2 RESERVED11 VLV2_CR
B17 VSS19 VSS78 U2 AC1 RESERVED6
B13 VSS18 VSS77 T9 RESERVED5
B1 VSS17 VSS76 T18 T2
AE2 VSS16 VSS75 R9 N5 RESERVED17
AD9 VSS15 VSS74 R6 RESERVED14 A25
AD5 VSS14 VSS72 R5 A2 PWR_RSVD_OBS1
AD21 VSS13 VSS71 R21 RESERVED1
AD17 VSS11 VSS70 R20 U3
AD13 VSS10 VSS69 R16 RESERVED18 B25
AA7 VSS9 VSS67 R14 Y18 PWR_RSVD_OBS3
AA24 VSS8 VSS65 R12 RESERVED21
AA21 VSS7 VSS64 P18 P10 AE25
AA2 VSS6 VSS62 N24 P11 RESERVED15 PWR_RSVD_OBS2
AA18 VSS5 8 OF 9 VSS59 N21 RESERVED16
AA15 VSS4 VSS58 N2 AD1
AA11 VSS3 VLV2_CR VSS57 N17 AE1 RESERVED10
W17 VSS2 VSS56 N16 W4 RESERVED12
L8 VSS89 VSS55 N13 W3 RESERVED20
W11 VSS51 VSS54 M17 RESERVED19
P8 VSS88 VSS53 M13
J11 VSS63 VSS52 L6 AA19
J8 VSS36 VSS50 L5 AA20 RESERVED2
G9 VSS44 VSS49 L21 AC21 RESERVED3
V9 VSS33 VSS48 L10 AB21 RESERVED7
N9 VSS87 VSS47 J24 RESERVED4
R7 VSS60 VSS43 J2
A24 VSS73 VSS42 J18
V19 VSS1 VSS40 J14 Z3735F
K11 VSS82 VSS39 J13 REV = 2.0
K19 VSS45 VSS38 H21
J19 VSS46 VSS35 H17
AD25 VSS41 VSS34 G5
R19 VSS12 VSS32 G16
P17 VSS68 VSS31 G10
G14 VSS61 VSS29 R15
J12 VSS30 VSS66 G7
VSS37 USB_VSSA

Z3735F
REV = 2.0

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 10_SOC_ GND & RESERVED PINS

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 10 of 39
SOC: DECOUPLING

+V_VCC
+V1P0SX +V1P0A_SOC +V1P2A_SOC

C1101 C1102 C1103 C1104 C1105 C1106 C1107 C1108 C1109

1uF C 0402 10V @ @

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

ESC ESC
BSC BSC ESC ESC ESC ESC ESC

C1105 AND C1106 ARE STUFFED FOR

+V1P0A_SOC
+V_VNN VALIDATION WHEN BSC'S ARE UNSTUFFED
+V1P0A_SOC +V1P2A_SOC

C1110 C1111 C1112 C1113 C1114 C1115 C1116 C1117

@ @ @ @ @
1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

BSC
ESC
BSC ESC ESC BSC ESC ESC

+VDDQ_DDR
+V1P0A_SOC
+VSDIO +V1P8A_SOC
C1118
1uF C 0402 10V

C1119 C1120 C1121 C1122

@

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

ESC

+VDDQ_DDR ESC ESC

ESC ESC

+V1P0A_SOC +V1P8A_SOC +V3P3A_SOC

C1123 C1124 C1125
@
1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

C1126 C1127 C1128

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

BSC ESC ESC
ESC
ESC ESC

+V1P2SX_SOC
+V1P0A_SOC

C1129
1uF C 0402 10V

C1130 C1131 C1132

@
1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

ESC

+V1P0SX
BSC ESC ESC

C1133 C1134
@
1uF C 0402 10V

1uF C 0402 10V

BSC ESC

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 11_SOC_ DECOUPLING

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 11 of 39
 +V_VSYS_PMIC U2A +V_VSYS_PMIC

48 BUCK1VIN BUCK5VIN1 27
C3679 BUCK5VIN2 28 C3642 C3643

10uF C 0603 6.3V

10uF C 0603 6.3V

10uF C 0603 6.3V

45 BUCK1FB
+V_VCC_PMIC BUCK5FB1 31
+V_VNN_PMIC
L3214 1uH L 4040 +V_VCC_LX 47 BUCK1LX
C3683 C3680 C3681 C3635 (1V/3A) BUCK5LX1 26 +V_VNN_LX1 L3218 0.47uH L 2520
1uH±20%, 4.2A, 43mohm (1V, 5A) C3644 C3645 C3646
22uF C 0603 6.3V

22uF C 0603 6.3V

22uF C 0603 6.3V

22uF C 0603 6.3V

0.47uH+/-20%, 3.9A, 30mohm

22uF C 0603 6.3V

22uF C 0603 6.3V

22uF C 0603 6.3V

Changed to 4040 package in C build

+V_VSYS_PMIC
BUCK5LX2 29 +V_VNN_LX2 L3219 0.47uH L 2520

40 BUCK2VIN 0.47uH+/-20%, 3.9A, 30mohm

C3637
4.7uF C 0603 6.3V

38 BUCK2FB
+V1P0SX +V_VSYS_PMIC
SH3616
1 2 +V1P0SX_BUCK2 L3215 1.5uH L 2520 +V1P0SX_LX 39 BUCK2LX BUCK6VIN 19
C3636 (1V/1.8A) C3647
SHORT-0603 1.5uH+/-20%, 3.1A, 66mohm
22uF C 0603 6.3V

4.7uF C 0603 6.3V

BUCK6FB 18
+V1P8A
+V_VSYS_PMIC
SH3637
BUCK6LX 20 +V1P8A_LX L3220 1.5uH L 2520 +V1P8A_BUCK6 1 2
54 BUCK3VIN (1.8V/1A) C3648
C3638 1.5uH+/-20%, 3.1A, 66mohm SHORT-0603

22uF C 0603 6.3V

4.7uF C 0603 6.3V

56 BUCK3FB
+V1P0A

L3216 1.5uH L 2520 +V1P0A_LX 55 BUCK3LX

C3639 (1.05V/2A)
1.5uH+/-20%, 3.1A, 66mohm
22uF C 0603 6.3V

+V_VSYS +V_VSYS_PMIC
SH1203
1 2
PLACE AT V_SYS OUTPUT FROM PMIC TO MEASURE REST OF SYSTEM V_SYS PWR
SHORT-0805
+V_VSYS_PMIC
+V1P8A +V1P8A_SOC
61 BUCK4VIN SH1202 PLACE RESISTOR FOR V1P8A RAIL TO SOC, CLOSE TO SOC (POWER #2)
C3640 1 2
4.7uF C 0603 6.3V

SHORT-0603
63 BUCK4FB
+VDDQ +VDDQ +VDDQ_DDR
SH1204
L3217 1.5uH L 2520 +VDDQ_LX 62 BUCK4LX 1 2 PLACE RESISTOR AT INPUT TO MEMORY ICS
C3641 (1.25V/2A)
1.5uH+/-20%, 3.1A, 66mohm 1/2 SHORT-0603
22uF C 0603 6.3V

PSND9039ABTRSK +V_VNN_PMIC +V_VNN

SH1206
1 2 PLACE RESISTOR AT OUTPUT OF PMIC (PMIC #3)

SHORT-0805

+V_VCC_PMIC +V_VCC

SH1207
1 2 PLACE RESISTOR AT OUTPUT OF PMIC (PMIC #3)
SHORT-0603

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 12_DOLLARCOVE TI_ SWITCHERS

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 12 of 39
 U2B +VBATTERY_SENSE
+VBUS

64 VBUS VBATSENSE 52
C3649

2.2uF C 0402 16V

IBATSENSEP 16 LOADSENSE
BAT_AGND V_VREFT
Change to 29.4K in C build by Intel
R3631
0.01 PR 2512 R3630

29.4K PR 0402
Add 0R in C build by power team 2512, 1%, 2W
IBATSENSEN 15 BATSENSE 10mR,TCR=75ppm OPTIONAL: USE FOR SYSTEM THERMISTOR
R3688 0 R 0402 24 I2CSDA OR BATTERY ID RESISTOR
6 I2C_4_SDA
R3689 0 R 0402 23 I2CSCL For System Thermal
6 I2C_4_SCL
32 IRQ BPTHERM 21 SYS_THERM R3692 0 R 0402
7 PMIC_INT
35 COREPWROK
7,36 COREPWROK V_VREFT
34 VCCAPWROK
3 DDR3_VCCA_PWROK
33 RSMRSTB GPADC 53 R3694 @ 0 R 0402 R3639 NTC1304
7,36 RSMRST_N
36 DRAMPWROK 47Kohm 1% NTC 0603 B=3380

29.4K PR 0402
3 DDR3_DRAM_PWROK
49 SLPS0IXB
7,15,18,32 PMU_SLP_S0IX_N
51 SUSPWRDNACK R3695 @ 0 R 0402
7 SUSPWRDNACK
50 PLTRSTB
7,36 PLTRST_N
37 PWRBTNB
31,36 PMU_PWRBTN_N
V_VREFT
R3693 0 R 0402
BATT_ID 36
22 VREFT
CAD NOTE: PLACE FOR BATTRY PACK THERMAL DETECTION
V1P25_VREF 14 VREF1P25 For Battery ID
C3650 C3651 13 VSSREF
1uF C 0402 6.3V

1uF C 0402 6.3V

Reserve possibility to swap 2 ADCs for Windows SKU

by Intel

+V1P8A

42 VINLDO1_2_5 (1.25V/300mA) LDO1 41 +V1P2SX

(1.25V/50mA) LDO2 43 +V1P2A
+V_VSYS_PMIC
(0.62V/20mA) LDO5 44 +VREFDQ
5 VINLDO3_6 (3.3V/200mA) LDO3 6 +V3P3A_PMIC
(2.85V/500mA) LDO6 4 +V2P85S_MMC
11 VSYS1 (3V/2mA) VRTC 17 +VRTC
(2.85V/250mA) LDO9 7 +AVDD_CAM
(1.8V/250mA) LDO10 9 +V1P8S_CAM1
(1.8V/250mA) LDO11 10 +V1P8S_CAM2
(3.3V/150mA) LDO13 12 +V3P3A_TCH
2 VSYS2 (2.85V/200mA) LDO7 3 +VSDIO
8 VSYS3 (2.85V/400mA) LDO8 1 +V3P3A_SD
59 VSYS4 (2.85V/200mA) LDO12 60 +V3P3A_SEN
(3.3V/500mA) LDO14 58 +V3P3S_DISP

C3661 C3660 C3664 C3665 C3668 C3669

PGND_BUCK1 46

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

PGND1_BUCK5 25
PGND2_BUCK5 30

C3652 C3653 C3654 C3655 C3656 C3657 AGND 57

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

EPAD SH1

2/2
C3659 C3658 C3662 C3663 C3666 C3667 C3670 C3671
PSND9039ABTRSK

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

2.2uF C 0402 6.3V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

PLACE RESISTOR FOR V3P3A RAIL TO SOC, CLOSE TO SOC (POWER #2)
PLACE RESISTOR AT OUTPUT OF PMIC (PMIC #2)

Drawing Rule
+V3P3A +V3P3A_PMIC +V3P3A_SOC +V3P3A
Acer Inc. Allegro Lib Ver
SH3620 SH3618
Project:
1 2 1 2 Ducati2 BAYt_CR OrCAD Lib Ver
SHORT-0603 SHORT-0603
Title: 13_DOLLARCOVE TI_ LDO_CTRL

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 13 of 39
Output 5V @ USB OTG
+VBUS_CONN
SH3635
1 2 CHG_VBUS

SHORT-0603 C3672 +V1P8A_SOC

1uF C 0603 25V SH3688 reserved for fast charging To be changed to 4.5A if implementing fast charging
1uH±20%, 3.5A, 45mohm
U3 +V_VSYS
R3623 SH3688 1 VBUS_1 SW_19 19 +V_VSYS_SW L3221 1uH L 2520
1 2 24 VBUS_24 SW_20 20 C3675 C3674 C3706 C3705

10K R 0402

10uF C0603 10V

10uF C0603 10V

10uF C0603 10V

10uF C0603 10V

+VREGN
C3673 10uF C0603 10V PMID SHORT-0603 23 PMID BTST 21 +V_VSYS_BTST C3678 0.047uF C 0402 16V

Add 0R in C build by power team 4 STAT REGN 22 C3677 4.7uF C 0402 10V
7 CHG_STAT
R3690 0 R 0402 6 SDA SYS_15 15
6 I2C_0_SDA +V_BATTERY
I2C_0_SDA/SCL & CHG_INT_N R3691 0 R 0402 5 SCL SYS_16 16 AGND
pull-up 2.2K & 10K to +V1P8A_SOC at SOC side 6 I2C_0_SCL
7 INT
7 CHG_INT_N
+V_VSYS
9 CE_N BAT 13 +V_BATTERY_BAT
4 CHG_DISABLE
CHG_OTG 8 OTG_IUSB BAT 14 C3676
+VREGN

10uF C0603 10V

R3626 4.7K R 0402 2 D+ TS 11 CHG_TS R3628 2.94K PR 0402 10V
30 USB2_P1_CHG_DP
3 D-
30 USB2_P1_CHG_DN ILIM 10 CHG_ILIM
From USB connector, for adaptor detection 17 PGND_17
BATT_THERM 36
18 PGND_18 R3627
NC 12
1 R3629

191 PR 0402
TP3612TEST_POINT_20
SH1 EPAD
From battery pack, for battery thermal 0~60C

11.8K PR 0402
BQ24297RGET R2628/R3629: 2.98K/11.84K (TI suggestion)

AGND
Ilim = 1V/Rlim * Klim
= 1/191 * 435
Reserved for fast charging SH3630 = 2.277A
1 2 AGND
CHG_VBUS
SHORT-0402
AGND
R3687
0 R 0402

R2 +VBUS

R3686
110K PR 0402

@
R1

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 14_DOLLARCOVE TI_ CHARGER

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 14 of 39
EXTERNAL REGULATORS

+VHDMI_OUT +VHDMI
SH1502
1 2

SHORT-0402

+VHDMI_OUT
+V_VSYS
U5

1/1
C1503 2 VIN VOUT 3
4.7uF C 0402 6.3V

C1504 C1505
@

2.2uF C 0402 6.3V

2.2uF C 0402 6.3V

CP_P 4

C1506
PMU_SLP_S0IX_N 6 ENA

2.2uF C 0402 6.3V

7,13,18,32 PMU_SLP_S0IX_N
1 GND CP* 5
7 THERMAL

TPS60151

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 15_EXTERNAL REGULATORS

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 15 of 39
 PLACE +V_VTT
BETWEEN DRAM DEVICES
MEMORY DEVICE 0 & 1 +V_VTT +VDDQ_DDR +V_VTT

C1601 C1602 C1603 C1604

0.47uF C 0402 10V

0.47uF C 0402 10V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

U7 U8

N4 E4 N4 E4
3,16,18 M0_MA0 A0 DQL0 M0_DATA12 3 3,16,18 M0_MA0 A0 DQL0 M0_DATA31 3
P8 F8 P8 F8
3,16,18 M0_MA1 A1 DQL1 M0_DATA8 3 3,16,18 M0_MA1 A1 DQL1 M0_DATA26 3
P4 F3 P4 F3
3,16,18 M0_MA2 A2 DQL2 M0_DATA13 3 3,16,18 M0_MA2 A2 DQL2 M0_DATA27 3
N3 F9 N3 F9
3,16,18 M0_MA3 A3 DQL3 M0_DATA15 3 3,16,18 M0_MA3 A3 DQL3 M0_DATA25 3
P9 H4 P9 H4
3,16,18 M0_MA4 A4 DQL4 M0_DATA9 3 3,16,18 M0_MA4 A4 DQL4 M0_DATA30 3
P3 H9 P3 H9
3,16,18 M0_MA5 A5 DQL5 M0_DATA10 3 3,16,18 M0_MA5 A5 DQL5 M0_DATA24 3
R9 G3 R9 G3
3,16,18 M0_MA6 A6 DQL6 M0_DATA11 3 3,16,18 M0_MA6 A6 DQL6 M0_DATA29 3
R3 H8 R3 H8
3,16,18 M0_MA7 A7 DQL7 M0_DATA14 3 3,16,18 M0_MA7 A7 DQL7 M0_DATA28 3
T9 T9
3,16,18 M0_MA8 A8 3,16,18 M0_MA8 A8
R4 D8 R4 D8
3,16,18 M0_MA9 A9 DQU0 M0_DATA0 3 3,16,18 M0_MA9 A9 DQU0 M0_DATA17 3
L8 C4 L8 C4
3,16,18 M0_MA10 A10(AP) DQU1 M0_DATA2 3 3,16,18 M0_MA10 A10(AP) DQU1 M0_DATA16 3
R8 C9 R8 C9
3,16,18 M0_MA11 A11 DQU2 M0_DATA6 3 3,16,18 M0_MA11 A11 DQU2 M0_DATA22 3
N8 C3 N8 C3
3,16,18 M0_MA12 A12(nBC) DQU3 M0_DATA5 3 3,16,18 M0_MA12 A12(nBC) DQU3 M0_DATA21 3
T4 A8 T4 A8
3,16,18 M0_MA13 A13 DQU4 M0_DATA3 3 3,16,18 M0_MA13 A13 DQU4 M0_DATA18 3
T8 A3 T8 A3
3,16,18 M0_MA14 A14 DQU5 M0_DATA7 3 3,16,18 M0_MA14 A14 DQU5 M0_DATA23 3
B9 B9
DQU6 M0_DATA1 3 DQU6 M0_DATA20 3
A4 A4
DQU7 M0_DATA4 3 DQU7 M0_DATA19 3

+VDDQ_DDR +VDDQ_DDR
J4 B3 J4 B3
3,16,18 M0_RASB nRAS VDD1 3,16,18 M0_RASB nRAS VDD1
K4 D10 K4 D10
3,16,18 M0_CASB nCAS VDD2 3,16,18 M0_CASB nCAS VDD2
L4 G8 M0_CLK0_DP L4 G8
3,16,18 M0_WEB nWE VDD3 3,16,18 M0_WEB nWE VDD3
L3 K3 L3 K3
3,16,18 M0_CS0_B nCS VDD4 3,16,18 M0_CS0_B nCS VDD4
K9 R1602 K9
VDD5 N2 VDD5 N2

1.24K PR 0402
M3 VDD6 N10 M3 VDD6 N10
3,16,18 M0_BS0 BA0 VDD7 3,16,18 M0_BS0 BA0 VDD7
N9 R2 N9 R2
3,16,18 M0_BS1 BA1 VDD8 3,16,18 M0_BS1 BA1 VDD8
M4 R10 M4 R10
3,16,18 M0_BS2 BA2 VDD9 3,16,18 M0_BS2 BA2 VDD9
H10 H10
VDDQ1 M0_CLK0_DN VDDQ1
K10 H3 K10 H3
3,16,18 M0_CKE0 CKE VDDQ2 3,16,18 M0_CKE0 CKE VDDQ2
J8 F2 J8 F2
3,16,18 M0_CLK0_DP CK VDDQ3 3,16,18 M0_CLK0_DP CK VDDQ3
K8 E10 K8 E10
3,16,18 M0_CLK0_DN nCK VDDQ4 3,16,18 M0_CLK0_DN nCK VDDQ4
D3 D3
VDDQ5 C10 VDDQ5 C10
E8 VDDQ6 C2 E8 VDDQ6 C2
3 M0_DM1 DML VDDQ7 3 M0_DM3 DML VDDQ7
D4 A9 D4 A9
3 M0_DM0 DMU VDDQ8 3 M0_DM2 DMU VDDQ8
A2 A2
VDDQ9 VDDQ9
+VREFDQL
F4 F4
3 M0_DQS1_DP DQSL +VDDQ_DDR 3 M0_DQS3_DP DQSL
G4 G4
3 M0_DQS1_DN nDQSL 3 M0_DQS3_DN nDQSL
H2 H2
VREFDQ M9 R1603 VREFDQ M9 C1605
VREFCA VREFCA +VREFCAL
C8 C8

4.7K PR 0402

0.1UF C 0402 10V

3 M0_DQS0_DP DQSU 3 M0_DQS2_DP DQSU
B8 B8
3 M0_DQS0_DN nDQSU 3 M0_DQS2_DN nDQSU
+VREFDQL
B2 B2 C1606
VSSQ1 B10 VSSQ1 B10

0.1UF C 0402 10V

K2 VSSQ2 D2 K2 VSSQ2 D2
3,16,18 M0_ODT0 ODT VSSQ3 3,16,18 M0_ODT0 ODT VSSQ3
D9 D9
T3 VSSQ4 E3 T3 VSSQ4 E3
3,16,18 M0_DRAMRSTB nRESET VSSQ5 3,16,18 M0_DRAMRSTB nRESET VSSQ5
E9 C1607 R1604 E9
DDR3L_ZQ_L9_A L9 VSSQ6 F10 DDR3L_ZQ_L9_B L9 VSSQ6 F10
4.7K PR 0402
0.1UF C 0402 10V

ZQ VSSQ7 G2 ZQ VSSQ7 G2
R1601 VSSQ8 G10 R1605 VSSQ8 G10
VSSQ9 A10 VSSQ9 A10
240 PR 0402

240 PR 0402
VSS1 ONE DECOUPLING CAP EACH FOR VSS1
M8 B4 M8 B4
L10 NC1 VSS2 E2 VREFDQ OF DRAM MODULES, L10 NC1 VSS2 E2
L2 NC2 VSS3 G9 L2 NC2 VSS3 G9
J10 NC3 VSS4 J3 J10 NC3 VSS4 J3
NC4 VSS5 +VDDQ_DDR NC4 VSS5
J2 J9 J2 J9
NC5 VSS6 M2 NC5 VSS6 M2
VSS7 M10 R1606 VSS7 M10
VSS8 P2 VSS8 P2
4.7K PR 0402

VSS9 P10 VSS9 P10

VSS10 +VREFCAL VSS10
T2 T2
VSS11 T10 VSS11 T10
VSS12 VSS12

H5TC4G63MFR-PBA_FBGA96 C1608 R1607 ONE DECOUPLING CAP EACH FOR H5TC4G63MFR-PBA_FBGA96

4.7K PR 0402
0.1UF C 0402 10V

VREFCA OF DRAM MODULES,

+VDDQ_DDR

C1609 C1610 C1611 C1612 C1613 C1614 C1615 C1616

Drawing Rule
1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 16_MEMORY DEVICE 0 & 1

MEMORY DEVICE 1&2 DECAPS Approved: Size: Document Number: Rev

C {Doc} 0.1
4 CAPS FOR EACH MODULE.PLACE CLOSE TO EACH MODULE Designer:
Date: Friday, July 25, 2014 Sheet: 16 of 39
 PLACE BETWEEN DRAM DEVICES
MEMORY DEVICE 2 & 3 +V_VTT +V_VTT +VDDQ_DDR +V_VTT

C1701 C1702 C1703 C1704

0.47uF C 0402 10V

0.47uF C 0402 10V

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

U9 U10

N4 E4 N4 E4
17,18 M0_MA0_R A0 DQL0 M0_DATA59 3 17,18 M0_MA0_R A0 DQL0 M0_DATA48 3
P8 F8 P8 F8
17,18 M0_MA1_R A1 DQL1 M0_DATA57 3 17,18 M0_MA1_R A1 DQL1 M0_DATA55 3
P4 F3 P4 F3
17,18 M0_MA2_R A2 DQL2 M0_DATA58 3 17,18 M0_MA2_R A2 DQL2 M0_DATA49 3
N3 F9 N3 F9
17,18 M0_MA3_R A3 DQL3 M0_DATA63 3 17,18 M0_MA3_R A3 DQL3 M0_DATA54 3
P9 H4 P9 H4
17,18 M0_MA4_R A4 DQL4 M0_DATA60 3 17,18 M0_MA4_R A4 DQL4 M0_DATA52 3
P3 H9 P3 H9
17,18 M0_MA5_R A5 DQL5 M0_DATA62 3 17,18 M0_MA5_R A5 DQL5 M0_DATA50 3
R9 G3 R9 G3
17,18 M0_MA6_R A6 DQL6 M0_DATA61 3 17,18 M0_MA6_R A6 DQL6 M0_DATA51 3
R3 H8 R3 H8
17,18 M0_MA7_R A7 DQL7 M0_DATA56 3 17,18 M0_MA7_R A7 DQL7 M0_DATA53 3
T9 T9
17,18 M0_MA8_R A8 17,18 M0_MA8_R A8
R4 D8 R4 D8
17,18 M0_MA9_R A9 DQU0 M0_DATA44 3 17,18 M0_MA9_R A9 DQU0 M0_DATA39 3
L8 C4 L8 C4
17,18 M0_MA10_R A10(AP) DQU1 M0_DATA40 3 17,18 M0_MA10_R A10(AP) DQU1 M0_DATA37 3
R8 C9 R8 C9
17,18 M0_MA11_R A11 DQU2 M0_DATA45 3 17,18 M0_MA11_R A11 DQU2 M0_DATA34 3
N8 C3 N8 C3
17,18 M0_MA12_R A12(nBC) DQU3 M0_DATA46 3 17,18 M0_MA12_R A12(nBC) DQU3 M0_DATA32 3
T4 A8 T4 A8
17,18 M0_MA13_R A13 DQU4 M0_DATA41 3 17,18 M0_MA13_R A13 DQU4 M0_DATA33 3
T8 A3 T8 A3
17,18 M0_MA14_R A14 DQU5 M0_DATA42 3 17,18 M0_MA14_R A14 DQU5 M0_DATA35 3
B9 B9
DQU6 M0_DATA47 3 DQU6 M0_DATA36 3
A4 A4
DQU7 M0_DATA43 3 DQU7 M0_DATA38 3

+VDDQ_DDR +VDDQ_DDR
J4 B3 J4 B3
17,18 M0_RASB_R nRAS VDD1 17,18 M0_RASB_R nRAS VDD1
K4 D10 K4 D10
17,18 M0_CASB_R nCAS VDD2 17,18 M0_CASB_R nCAS VDD2
L4 G8 L4 G8
17,18 M0_WEB_R nWE VDD3 17,18 M0_WEB_R nWE VDD3
L3 K3 L3 K3
17,18 M0_CS0_B_R nCS VDD4 17,18 M0_CS0_B_R nCS VDD4
K9 K9
VDD5 N2 VDD5 N2
M3 VDD6 N10 M3 VDD6 N10
17,18 M0_BS0_R BA0 VDD7 17,18 M0_BS0_R BA0 VDD7
N9 R2 N9 R2
17,18 M0_BS1_R BA1 VDD8 17,18 M0_BS1_R BA1 VDD8
M4 R10 M4 R10
17,18 M0_BS2_R BA2 VDD9 17,18 M0_BS2_R BA2 VDD9
H10 H10
K10 VDDQ1 H3 K10 VDDQ1 H3
17,18 M0_CKE0_R CKE VDDQ2 17,18 M0_CKE0_R CKE VDDQ2
J8 F2 J8 F2
17,18 M0_CLK0_DP_R CK VDDQ3 17,18 M0_CLK0_DP_R CK VDDQ3
K8 E10 K8 E10
17,18 M0_CLK0_DN_R nCK VDDQ4 17,18 M0_CLK0_DN_R nCK VDDQ4
D3 D3
VDDQ5 C10 VDDQ5 C10
E8 VDDQ6 C2 E8 VDDQ6 C2
3 M0_DM7 DML VDDQ7 3 M0_DM6 DML VDDQ7
D4 A9 D4 A9
3 M0_DM5 DMU VDDQ8 3 M0_DM4 DMU VDDQ8
A2 A2
VDDQ9 VDDQ9
+VREFDQU
F4 F4
3 M0_DQS7_DP DQSL 3 M0_DQS6_DP DQSL
G4 +VDDQ_DDR
G4
3 M0_DQS7_DN nDQSL 3 M0_DQS6_DN nDQSL
H2 H2
VREFDQ M9 VREFDQ M9 C1705
VREFCA VREFCA +VREFCAU
C8 R1702 C8

0.1UF C 0402 10V

3 M0_DQS5_DP DQSU 3 M0_DQS4_DP DQSU
B8 B8

4.7K PR 0402
3 M0_DQS5_DN nDQSU 3 M0_DQS4_DN nDQSU
+VREFDQU
B2 B2 C1706
VSSQ1 B10 VSSQ1 B10

0.1UF C 0402 10V

K2 VSSQ2 D2 K2 VSSQ2 D2
17,18 M0_ODT0_R ODT VSSQ3 17,18 M0_ODT0_R ODT VSSQ3
D9 D9
T3 VSSQ4 E3 T3 VSSQ4 E3
17,18 M0_DRAMRSTB_R nRESET VSSQ5 17,18 M0_DRAMRSTB_R nRESET VSSQ5
E9 C1707 R1703 E9
DDR3L_ZQ_L9_C L9 VSSQ6 F10 DDR3L_ZQ_L9_D L9 VSSQ6 F10
4.7K PR 0402
0.1UF C 0402 10V

ZQ VSSQ7 G2 ZQ VSSQ7 G2
R1701 VSSQ8 G10 R1704 VSSQ8 G10
VSSQ9 A10 VSSQ9 A10
240 PR 0402

240 PR 0402
VSS1 ONE DECOUPLING CAP EACH FOR VSS1
M8 B4 M8 B4
L10 NC1 VSS2 E2 VREFDQ OF DRAM MODULES, L10 NC1 VSS2 E2
L2 NC2 VSS3 G9 L2 NC2 VSS3 G9
J10 NC3 VSS4 J3 J10 NC3 VSS4 J3
NC4 VSS5 +VDDQ_DDR NC4 VSS5
J2 J9 J2 J9
NC5 VSS6 M2 NC5 VSS6 M2
VSS7 M10 R1705 VSS7 M10
VSS8 P2 VSS8 P2
4.7K PR 0402

VSS9 P10 VSS9 P10

VSS10 +VREFCAU VSS10
T2 T2
VSS11 T10 VSS11 T10
VSS12 VSS12

H5TC4G63MFR-PBA_FBGA96 C1708 R1706 H5TC4G63MFR-PBA_FBGA96

4.7K PR 0402
0.1UF C 0402 10V

ONE DECOUPLING CAP EACH FOR

VREFCA OF DRAM MODULES,

+VDDQ_DDR

C1709 C1710 C1711 C1712 C1713 C1714 C1715 C1716

Drawing Rule
1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 17_MEMORY DEVICE 2 & 3

MEMORY DEVICE 1&2 DECAPS Approved: Size: Document Number: Rev

C {Doc} 0.1
4 CAPS FOR EACH MODULE.PLACE CLOSE TO EACH MODULE Designer:
Date: Friday, July 25, 2014 Sheet: 17 of 39
MEMORY: TERMINATION & X32/64 SCALABLE OPTIONS
UNSTUFF FOR X32 OPTION

+V_VTT

+V_VTT
R1801

300 PR 0402 R1802 0 R 0402

3,16 M0_DRAMRSTB M0_DRAMRSTB_R 17
R1803 R1804 R1805 R1806 R1807 R1808 R1809 R1810 R1811 R1812 R1813 R1814 R1815 R3679 R1817 R1816 0 R 0402
3,16 M0_CLK0_DP M0_CLK0_DP_R 17

300 PR 0402

300 PR 0402

300 PR 0402

300 PR 0402

300 PR 0402

300 PR 0402

300 PR 0402

300 PR 0402

300 PR 0402

300 PR 0402

300 PR 0402

300 PR 0402

300 PR 0402

300 PR 0402

300 PR 0402
R1818 0 R 0402
3,16,18 M0_CKE0 3,16 M0_CLK0_DN M0_CLK0_DN_R 17
R1819 0 R 0402
3,16,18 M0_CKE0 M0_CKE0_R 17
DD3L CKE TERMINATION R1820 0 R 0402
3,16,18 M0_MA0 3,16,18 M0_CS0_B M0_CS0_B_R 17
3,16,18 M0_MA1
R1821 0 R 0402
3,16,18 M0_MA2 3,16,18 M0_CASB M0_CASB_R 17
3,16,18 M0_MA3
+V_VTT
R1822 0 R 0402
3,16,18 M0_MA4 3,16,18 M0_RASB M0_RASB_R 17
3,16,18 M0_MA5
R1823 0 R 0402
3,16,18 M0_MA6 3,16,18 M0_WEB M0_WEB_R 17
3,16,18 M0_MA7
R1824 0 R 0402
3,16,18 M0_MA8 3,16,18 M0_MA0 M0_MA0_R 17
R1825 R1826 R1827
3,16,18 M0_MA9
R1828 0 R 0402
300 PR 0402

300 PR 0402

300 PR 0402

3,16,18 M0_MA10 3,16,18 M0_MA1 M0_MA1_R 17

3,16,18 M0_MA11
R1829 0 R 0402
3,16,18 M0_MA12 3,16,18 M0_MA2 M0_MA2_R 17
3,16,18 M0_MA13
R1830 0 R 0402
3,16,18 M0_MA14 3,16,18 M0_MA3 M0_MA3_R 17
3,16,18 M0_BS0
R1831 0 R 0402
3,16,18 M0_BS1 3,16,18 M0_MA4 M0_MA4_R 17
3,16,18 M0_BS2 DD3L MA TERMINATION R1832 0 R 0402
3,16,18 M0_MA5 M0_MA5_R 17
R1833 0 R 0402
3,16,18 M0_MA6 M0_MA6_R 17
R1834 0 R 0402
DD3L BS TERMINATION 3,16,18 M0_MA7 M0_MA7_R 17
R1835 0 R 0402
3,16,18 M0_MA8 M0_MA8_R 17
R1836 0 R 0402
3,16,18 M0_MA9 M0_MA9_R 17

+V_VTT
R1837 0 R 0402
3,16,18 M0_MA10 M0_MA10_R 17
R1838 0 R 0402
3,16,18 M0_MA11 M0_MA11_R 17
R1839 0 R 0402
3,16,18 M0_MA12 M0_MA12_R 17
R1840 R1841 R1842
R1843 0 R 0402
300 PR 0402

300 PR 0402

300 PR 0402

+VDDQ +V3P3A_PMIC 3,16,18 M0_MA13 M0_MA13_R 17

U11 R1844 0 R 0402
3,16,18 M0_MA14 M0_MA14_R 17
2 10
C1801 VIN VCNTL R1847 C1802 R1846 0 R 0402
3,16,18 M0_BS0 M0_BS0_R 17
R1845

100K R 0402
10uF C 0402 6.3V

4.7uF C 0402 6.3V

3,16,18 M0_RASB
10K PR 0402 R1848 0 R 0402
3,16,18 M0_CASB 3,16,18 M0_BS1 M0_BS1_R 17
1
3,16,18 M0_WEB REFIN
R1850 C1803 R1849 0 R 0402
3,16,18 M0_BS2 M0_BS2_R 17
10K PR 0402

100pF C 0402 50V

+V_VTT
9 R1851 0 R 0402
PGOOD 3,16,18 M0_ODT0 M0_ODT0_R 17
3
DD3L RAS, CAS, WEB TERMINATION VOUT
6 5
C3704 REFOUT SENSE X32/64 RESISTOR OPTIONS
C1804
0.1UF C 0402 10V

10uF C 0402 6.3V

+V_VTT
7
EN 4
PGND
R1852
8
300 PR 0402

GND 11
EXP_GND
RT9040
7,13,15,32 PMU_SLP_S0IX_N
3,16,18 M0_ODT0

+V_VTT

R1853
300 PR 0402

Drawing Rule
3,16,18 M0_CS0_B
Acer Inc.
DD3L CS & ODT TERMINATION Project: Allegro Lib Ver

Ducati2 BAYt_CR OrCAD Lib Ver

Title: 18_MEMORY TERMINATION

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 18 of 39
 5 4 3 2 1

SPI NOR FLASH

+V1P8A_SPI
+V1P8A
R1901 0 R 0402
7 SPI_NOR_CS0_N SPI_CS_N 19,36
SH1901
R1902 0 R 0402 1 2
7 SPI_NOR_MISO SPI_MISO 19,36
D R1903 0 R 0402 SHORT-0402 D
7 SPI_NOR_MOSI SPI_MOSI 19,36
R1904 0 R 0402
7 SPI_NOR_CLK SPI_CLK 19,36

+V1P8A_SPI

1 TP1901 TEST_POINT_20
SPI_NOR_CLK 1 TP1902 TEST_POINT_20
SPI_NOR_MOSI 1 TP1903 TEST_POINT_20
SPI_NOR_CS0_N 1 TP1904 TEST_POINT_20
SPI_NOR_MISO 1 TP1905 TEST_POINT_20
1 TP1906 TEST_POINT_20

+V1P8A_SPI +V1P8A_SPI

C C
R1905 R1906
R1907 C1901

10K PR 0402

10K PR 0402

10K PR 0402

0.1UF C 0402 10V

U12

1 SH1
19,36 SPI_CS_N CS# E-PAD
2 8
19,36 SPI_MISO DO/IO1 VCC
WP_N_FLASH 3 7 HOLD_N_FLASH
4 WP#/IO2 HOLD#/RESET/IO3 6
GND CLK SPI_CLK 19,36
5
DI/IO0 SPI_MOSI 19,36
C1902
W25Q64FWZPIG @

10pF C 0402 50V

B B

A A

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 19_SPI NOR FLASH

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 19 of 39
5 4 3 2 1
USB PHY & MUX
+V1P8A +V1P8A_ULPI +V_VSYS +VSYS_ULPI

SH2001 SH2002
1 2 1 2

SHORT-0402 SHORT-0402

+V1P8A_ULPI +VSYS_ULPI +V3P3_ULPI_0_INT +V1P5_ULPI_0_INT

C2002 C2003 C2004 C2005 C2006

0.1UF C 0402 10V

0.1UF C 0402 10V

2.2uF C 0402 6.3V

2.2uF C 0402 6.3V

2.2uF C 0402 6.3V

+V1P8A_ULPI
U13
26 CLOCK VDDIO 32
6 USB_ULPI_0_CLK
3 DATA0
6 USB_ULPI_0_DATA0
R2001 4 DATA1 VBAT 21
6 USB_ULPI_0_DATA1
5 DATA2

2.2K PR 0402
6 USB_ULPI_0_DATA2
@ 6 DATA3
6 USB_ULPI_0_DATA3
7 DATA4 VDD33 20
6 USB_ULPI_0_DATA4
9 DATA5
6 USB_ULPI_0_DATA5
10 DATA6
6 USB_ULPI_0_DATA6
13 DATA7 VDD15 12
6 USB_ULPI_0_DATA7
USB_ULPI_RESET_N 27 RESET_N
7 USB_ULPI_RESET_N VDD18_1 28
USB_ID_CONN R2002 @ 0 R 0402 USB_ID_CONN_R 23 ID VDD18_2 30
7,20,30 USB_ID_CONN
11 CS
6 USB_ULPI_0_CS DP 18
USB2_ULPI_OTG_DP 20
29 STP DM 19
6 USB_ULPI_0_STP USB2_ULPI_OTG_DN 20
+V1P8A_ULPI +V3P3_ULPI_0_INT
NXT 2
USB_ULPI_0_NXT 6
8 NC_1 DIR 31
USB_ULPI_0_DIR 6
C2001 C2007 15 NC_2
+VBUS
16 NC_3 CPEN 17
0.1UF C 0402 10V

0.1UF C 0402 10V

24 NC_4
U14 25 NC_5 VBUS 22
A2 VCCB VCCA A1 33 EP_GND

C2 B A C1 USB_ULPI_0_REFCLK_3P3 1 REFCLK CFG 14

6 USB_ULPI_0_REFCLK
B1 GND DIR B2
LevelShifter TUSB1210
SN74AVC1T45YZPR

+V3P3A_PMIC

C2008

0.1UF C 0402 10V

U15

VCC 9

R2003 0 R 0402

5 HSD1+ @ L2001
6 USB2_P1_DP
4 HSD1- D+ 1 USB2_MUX_DP A1 A2 USB2_OTG_CONN_DP
6 USB2_P1_DN USB2_OTG_CONN_DP 30
D- 2 USB2_MUX_DN
7 HSD2+ B1 B2 USB2_OTG_CONN_DN
20 USB2_ULPI_OTG_DP USB2_OTG_CONN_DN 30
6 HSD2- SDCW2012C-2-900TF
20 USB2_ULPI_OTG_DN
OE 8 R2004 0 R 0402
3 GND S 10 +V1P8A_SOC
AOZ6184

R2005
R3654 @ 0 R 0402

10K R 0402
R3655 @ 0 R 0402

USBMUX_SEL 7
R3677 0 R 0402
R3654, R3655 @
PLACE CLOSE TO MUX R3678 0 R 0402
USB_ID_CONN 7,20,30

Default Device Mode Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 20_USB PHY & MUX

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 20 of 39
EMMC

TEST_POINT_20 TP2101 1 EMMC_DATA0

TEST_POINT_20 TP2102 1 EMMC_RESET_N

TEST_POINT_20 TP2103 1 EMMC_CMD

U16B 2 OF 2

A4 R1
A6 NC#A4 NC#R1 R2
A9 NC#A6 NC#R2 R3
A11 NC#A9 NC#R3 R5
B2 NC#A11 NC#R5 R12
B13 NC#B2 NC#R12 R13
D1 NC#B13 NC#R13 R14
D14 NC#D1 NC#R14 T1
H1 NC#D14 NC#T1 T2
H2 NC#H1 NC#T2 T3
H6 NC#H2 NC#T3 T5
H7 NC#H6 NC#T5 T12
+V2P85S_EMMC_VCC H8 NC#H7 NC#T12 T13
+V2P85S_MMC NC#H8 NC#T13
H9 T14
H10 NC#H9 NC#T14 U1
SH2101 H11 NC#H10 NC#U1 U2
1 2 H12 NC#H11 NC#U2 U3
H13 NC#H12 NC#U3 U6
SHORT-0603 C2101 C2102 C2103 H14 NC#H13 NC#U6 U7
@ J1 NC#H14 NC#U7 U10

0.1UF C 0402 10V

0.1UF C 0402 10V

4.7uF C 0402 6.3V
J7 NC#J1 NC#U10 U12
J8 NC#J7 NC#U12 U13
J9 NC#J8 NC#U13 U14
+V1P8A J10 NC#J9 NC#U14 V1
GND NC#J10 NC#V1
J11 V2
J12 NC#J11 NC#V2 V3
U16A 1 OF 2 J13 NC#J12 NC#V3 V12
J14 NC#J13 NC#V12 V13
M6 W5 K1 NC#J14 NC#V13 V14
VCC CMD EMMC_CMD 5 NC#K1 NC#V14
N5 K3 W1
C2106 C2104 C2105 T10 VCC K5 NC#K3 NC#W1 W2
@ U9 VCC W6 K7 NC#K5 NC#W2 W3
1uF C 0402 10V
0.1UF C 0402 10V

4.7uF C 0402 6.3V

VCC CLK EMMC_CLK 5 NC#K7 NC#W3
C2107 K8 W7
K6 @ K9 NC#K8 NC#W7 W8
PLACE CLOSE TO EMMC

10pF C 0402 50V

W4 VCCQ K10 NC#K9 NC#W8 W9
Y4 VCCQ K11 NC#K10 NC#W9 W10
AA3 VCCQ K12 NC#K11 NC#W10 W11
AA5 VCCQ U5 K13 NC#K12 NC#W11 W12
VCCQ RST# EMMC_RESET_N 5 NC#K13 NC#W12
K14 W13
C2108 1uF C 0402 10V EMMC_VDDI K2 L1 NC#K14 NC#W13 W14
VDDI M7 L2 NC#L1 NC#W14 Y1
VSS P5 L3 NC#L2 NC#Y1 Y3
EMMC_DATA0 H3 VSS R10 L4 NC#L3 NC#Y3 Y6
5 EMMC_DATA_0 DATA0 VSS NC#L4 NC#Y6
H4 U8 L12 Y7
5 EMMC_DATA_1 DATA1 VSS NC#L12 NC#Y7
H5 L13 Y8
5 EMMC_DATA_2 DATA2 NC#L13 NC#Y8
J2 K4 L14 Y9
5 EMMC_DATA_3 DATA3 VSSQ NC#L14 NC#Y9
J3 Y2 M1 Y10
5 EMMC_DATA_4 DATA4 VSSQ NC#M1 NC#Y10
J4 Y5 M2 Y11
5 EMMC_DATA_5 DATA5 VSSQ NC#M2 NC#Y11
J5 AA4 M3 Y12
5 EMMC_DATA_6 DATA6 VSSQ NC#M3 NC#Y12
J6 AA6 M5 Y13
5 EMMC_DATA_7 DATA7 VSSQ NC#M5 NC#Y13
M8 Y14
M9 NC#M8 NC#Y14 AA1
KE4CN3K6A-A58 M10 NC#M9 NC#AA1 AA2
M12 NC#M10 NC#AA2 AA7
M13 NC#M12 NC#AA7 AA8
M14 NC#M13 NC#AA8 AA9
N1 NC#M14 NC#AA9 AA10
N2 NC#N1 NC#AA10 AA11
N3 NC#N2 NC#AA11 AA12
N10 NC#N3 NC#AA12 AA13
N12 NC#N10 NC#AA13 AA14
N13 NC#N12 NC#AA14 AE1
N14 NC#N13 NC#AE1 AE14
P1 NC#N14 NC#AE14 AG2
P2 NC#P1 NC#AG2 AG13
P3 NC#P2 NC#AG13 AH4
P10 NC#P3 NC#AH4 AH6
P12 NC#P10 NC#AH6 AH9
P13 NC#P12 NC#AH9 AH11
P14 NC#P13 NC#AH11
NC#P14

KE4CN3K6A-A58

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 20_EMMC

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 21 of 39
THIS PAGE IS LEFT BLANK INTENTIONALLY

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: BLANK PAGE

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 22 of 39
 5 4 3 2 1

CAMERA CONNECTOR
+V2P8_CAM +AVDD_CAM

6
EMI2301 EMI2303 ESD2302 @

MCSI_2_CLK_DP_C 1 10 MCSI_2_CLK_DP_C SH2301

1 10 1 2
MCSI_2_CLK_DN_C 2 9 MCSI_2_CLK_DN_C
2 9 SHORT-0402
2 4 MCSI_1_DATA0_DP_CN 2 4 MCSI_1_CLK_DP_CN 3
4 MCSI_1_DATA0_DP 4 MCSI_1_CLK_DP 3
MCSI_2_DATA_DP 4 7 MCSI_2_DATA_DP
4 7
D +V1P8_CAM +V1P8S_CAM1 D
1 3 MCSI_1_DATA0_DN_CN 1 3 MCSI_1_CLK_DN_CN MCSI_2_DATA_DN 5 6 MCSI_2_DATA_DN
4 MCSI_1_DATA0_DN 4 MCSI_1_CLK_DN 5 6
SH2302
BDFN10A054U 1 2

SHORT-0402

ICMEF062P750MFR ICMEF062P750MFR

5
6

EMI2302
PLACE CLOSE TO J1_CAM1 PLACE CLOSE TO J1_CAM2 +V2P8_CAM +V1P8_CAM
MCSI_1_CLK_DN_C MCSI_2_CLK_DN_C
MCSI_1_CLK_DP_C MCSI_2_CLK_DP_C

2 4 MCSI_1_DATA1_DP_CN C2305 C2306

4 MCSI_1_DATA1_DP
C2301 C2302 C2303 C2304

4.7uF C 0402 6.3V

4.7uF C 0402 6.3V

@ @ @ @

12pF C 0402 50V

12pF C 0402 50V

12pF C 0402 50V

12pF C 0402 50V

1 3 MCSI_1_DATA1_DN_CN
4 MCSI_1_DATA1_DN

C C

ICMEF062P750MFR Add common mode choke by RF in Pre-MP

5

MCSI_1 Rear Camera (5M) MCSI_2 Front Camera (2M)

OV5693 D2 FHD: Pin4_V1P8SX = 240mA
GC2235
D2 HD: Pin4_+V1P_CAM = 250mA
+V1P8_CAM +V2P8_CAM +V1P8_CAM +V2P8_CAM

C2307 C2308 C2309 C2310

0.1UF C 0402 10V

0.1UF C 0402 10V

0.1UF C 0402 10V

4.7uF C 0402 6.3V

J1_CAM1 J2_CAM2

SH1 SH1
GND1 GND1

1 1
B +V2P8_CAM 2 1 2 1 B
2 3 2 3
4 3 4 3
TEST_POINT_20 TP3639 1 4 5 TEST_POINT_20 TP3638 1 4 5
6 5 6 5
7 PLT_CLK0_CAM1 6 7 PLT_CLK1_CAM2 6
7 7
8 7 8 7
4 CAM1_RESET_N 8 4 CAM2_RESET_N 8
TEST_POINT_20 TP2301 1 9 TEST_POINT_20 TP2302 1 9
9 I2C_1_SDA 6,23,27,36 9 I2C_1_SDA 6,23,27,36
10 10
6,23,27,36 I2C_1_SCL 10 6,23,27,36 I2C_1_SCL 10
11 11
11 CAMERA_1_PD_N 4 11 CAMERA_2_PD 4
12 12 1
MCSI_1_DATA1_DP_CN 12 12
13 13 TP2303 TEST_POINT_20
13 MCSI_1_DATA1_DN_CN 13
14 14
14 15 MCSI_1_CLK_DP_C 14 15 MCSI_2_CLK_DP_C
15 MCSI_1_CLK_DP_CN 15 MCSI_2_CLK_DP 4
MCSI_1_CLK_DN_C 16 R2302 0 R 0402 MCSI_2_CLK_DN_C 16 R2303 0 R 0402
MCSI_1_CLK_DN_CN 16 4 MCSI_2_CLK_DN 16
R2301 0 R 0402 17 R2304 0 R 0402 17
18 17 1 TP3615 TEST_POINT_20 18 17
MCSI_1_DATA0_DP_CN 18 4 MCSI_2_DATA_DP 18
19 19
19 MCSI_1_DATA0_DN_CN 19 MCSI_2_DATA_DN 4
TEST_POINT_20 TP3614 1 20 TEST_POINT_20 TP3616 1 20
20 21 20 21 1 TP3617 TEST_POINT_20
21 CAMERA_1_VCM_PD_N 4 21

TP3614, TP3615 GND2

SH2
GND2
SH2

PLACE CLOSE TO J1_CAM1 TP3616, TP3617

FH35C-21S-0.3SHW_[ZR]
FH35C-21S-0.3SHW_[SR] PLACE CLOSE TO J2_CAM2
A A

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 23_CAMERA CONNECTOR

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 23 of 39
5 4 3 2 1
 5 4 3 2 1

TOUCH CONNCTOR & SHIELDS & HOLES

Touch Connector
+V3P3SX_TOUCH
+V3P3SX_TOUCH
+V3P3A_TCH
D D
SH2401
1 2
C2402
1 TP3624 TEST_POINT_40 SHORT-0402

1uF C 0402 10V

1 TP3625 TEST_POINT_40
1 TP3626 TEST_POINT_40 C2401
1 TP3627 TEST_POINT_40 @

0.1UF C 0402 10V

J3_TCH1 1 TP3628 TEST_POINT_40
1 TP3629 TEST_POINT_40
SH1 1 TP3631 TEST_POINT_40

1
2
I2C_3_SCL 6
3
I2C_3_SDA 6 +V1P8A_TOUCH +V1P8A +V1P8A_TOUCH
4
TOUCH_INT_N 7
5
TOUCH_RESET_N 4
6 SH2402
7 1 2
TOUCH_ID 5
8
C2403 SHORT-0402 C2404
SH2 1 TP3630 TEST_POINT_40 @

1uF C 0402 10V

0.1UF C 0402 10V
F0560-0801_[Z]

C C

Shields Changed to D2 FHD clips (Z000-4G7U1-11000) Holes

HOLE1 HOLE2 HOLE4 HOLE5

PTH PTH PTH PTH

SHIELD1 SHIELD2 SHIELD3 SHIELD4

Clip_0.17 Clip_0.17 Clip_0.17 Clip_0.17

1

PIN_6D4 PIN_6D4 PIN_6D2.4 PIN_6D2.4

1
SHIELD5 SHIELD13 SHIELD15 SHIELD7
HOLE3 HOLE6
B Clip_0.17 Clip_0.17 Clip_0.17 Clip_0.17 B
NPTH
1

NPTH

NPTH_2 NPTH_2X1.5

1
HOLE7 HOLE8 HOLE9 HOLE10
SHIELD8 SHIELD9 SHIELD10 SHIELD11
NPTH NPTH NPTH NPTH
Clip_0.17 Clip_0.17 Clip_0.17 Clip_0.17
1

NPTH_1.1x0.3 NPTH_1.1x0.3 NPTH_1.1x0.3 NPTH_1.1x0.3

1
SHIELD12 SHIELD14
Optical Points
Clip_0.17 Clip_0.17
1

FID1 FID2 FID3 FID4 FID5 FID6

1 1 1 1 1 1

FID40 FID40 FID40 FID40 FID40 FID40

A A

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 24_TOUCH CONN & SHIELDS & HOLES

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 24 of 39
5 4 3 2 1
 5 4 3 2 1

MIPI-DISPLAY CONNECTOR +V3P3S_DISP LCM_3D3V

MDSI_A_DP_1_CN
MDSI_A_DN_1_CN
MDSI_A_DP_2_CN MDSI_A_DP_0_CN R2523 @ 0 R 0603
MDSI_A_DN_2_CN MDSI_A_DN_0_CN

U17 SH2501
A2 A1 1 2
VIN1 VOUT1

A2

B2

A2

B2

A2

B2
Fine-tune K&D/ O-Filem panel power sequence (1.8V on first) B2 B1 SHORT-0603
@ L2501 @ L2504 L2505 @ VIN2 VOUT2
D SDCW2012C-2-900TF SDCW2012C-2-900TF SDCW2012C-2-900TF D

A1

B1

A1

B1

A1

B1
R2529 R2502 1.05K PR 0402 C2 C1
4,25 DDI1_BKLTCTL ON GND
0 R 0402
C2502 C2503 C2504
MDSI_A_DN_2 MDSI_A_DN_0

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

MDSI_A_DP_2 MDSI_A_DP_0 R2503 @ TPS22964
7 LCM_3P3V_EN
MDSI_A_DN_1 0 R 0402
MDSI_A_DP_1

+V1P8A LCM_1D8V
MDSI_A_CLKP_CN
MDSI_A_CLKN_CN
R2528 @ 0 R 0603
MDSI_A_DN_3_CN MDSI_A_CLKN_CN
MDSI_A_DP_3_CN MDSI_A_CLKP_CN
U18 SH2502
A2 A1 1 2
C2501 C2505 VIN1 VOUT1
B2 B1 SHORT-0603
B2

A2

B1

A1

10pF C 0402 50V

10pF C 0402 50V

VIN2 VOUT2
@
L2506 L2507 @ @ @
SDCW2012C-2-900TF SDCW2012C-2-900TF
R2530 R2504 0 R 0402 C2 C1
4,25 DDI1_BKLTCTL
B1

A1

B2

A2

0 R 0402 ON GND
C2506 C2507 C2508
C C

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

MDSI_A_DP_3 R2505 @ TPS22964
7 LCM_1P8V_EN
MDSI_A_DN_3 0 R 0402

MDSI_A_CLKN
MDSI_A_CLKP PLACE CLOSE TO J4_LCD1
+V1P8A
LCM_1D8V LCM_3D3V

LCM_3D3V R2506

100K PR 0402
C2511 C2512
C2509 C2510 @

1uF C 0603 16V

0.1UF C 0402 10V
@
0.1UF C 0402 10V
2.2uF C 0402 6.3V

@ J4_LCD1
4,25 LCM_RST_N LCM_RST_3P3V# 25
SH1
GND1

3
LCM_3D3V
1 @

D
1 2 Q2501
R2508 0 R 0402 EDID_3V3 3 2 NMOS NTK3043N Onsemi

(N)
3 4

G
5 4

1
5 6 LCM_RST_N_R R2509 0 R 0402
6 LCM_RST_N 4,25
7
7 LCM_ID 7 8 LCD_SDA2 R2513
R2512 0 R 0402 MDSI_A_DP_2_CN 9 8

100K PR 0402
4 MDSI_A_DP_2 9 +V1P8A
10 LCD_SCL2 @ LCM_3D3V
B R2514 0 R 0402 MDSI_A_DN_2_CN 11 10 B
4 MDSI_A_DN_2 11 12
13 12 R2510 R2511
13 14 MDSI_A_DP_1_CN R2515 0 R 0402

4.7K R 0402

4.7K R 0402
14 MDSI_A_DP_1 4
R2516 0 R 0402 MDSI_A_CLKP_CN 15
4 MDSI_A_CLKP 15 16 MDSI_A_DN_1_CN R2517 0 R 0402
16 MDSI_A_DN_1 4
R2518 0 R 0402 MDSI_A_CLKN_CN 17
4 MDSI_A_CLKN 17 18
19 18
19 20 MDSI_A_DP_0_CN R2519 0 R 0402
20 MDSI_A_DP_0 4
R2520 0 R 0402 MDSI_A_DP_3_CN 21 LCD_SCL2
4 MDSI_A_DP_3 21 6,26 I2C_2_SCL
22 MDSI_A_DN_0_CN R2521 0 R 0402
22 MDSI_A_DN_0 4

3
R2522 0 R 0402 MDSI_A_DN_3_CN 23
4 MDSI_A_DN_3 23 24
R3684 @ 0 R 0402 25 24 @ Q2502

D
7 LCM_ID1 25 26 NMOS NTK3043N Onsemi
26 BL_LED1 29
27

(N)
29 BL_LED2 27 28 VLCD: 19.6/21.7/23.8

G
28 BL_LED3 29
29
25 LCM_RST_3P3V#

1
29 30
31 30 +VBKLT_EDP LCD_SDA2
31 6,26 I2C_2_SDA

3
SH2 @ Q2503

D
GND2 NMOS NTK3043N Onsemi
C2513

(N)
FH35C-31S-0.3SHW_[SR]

G
1uF C 1206 50V

1
A A

Drawing Rule
Replaced by low profile 1uF 1206 50V in C build
Acer Inc. Allegro Lib Ver
Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 25_MIPI-DISPLAY CONNECTOR

Approved: Size: Document Number: Rev

<Approve> C {Doc} 0.1
Table update on 5/9 Designer:
<Designer> Date: Friday, July 25, 2014 Sheet: 25 of 39
5 4 3 2 1
SENSORS: Gyro & G-sensor Combo

+V1P8A +V1P8A_SENSOR

SH2601
1 2

SHORT-0402

+V1P8A_SENSOR

+V1P8A_SENSOR

C2601 C2604 C2605

1uF C 0402 10V

10nF C 0402 10V

0.1UF C 0402 10V

R2602

100K R 0402
@

14
15
16
17
1
2
3
4
5
6
U20
GND GND GND

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
+V1P8A_SENSOR
13
VDD
12
INT GYRO_INT1 7
8
VDDIO
C2606 23
SCL I2C_2_SCL 6,25
C2607
1uF C 0402 10V

24

10nF C 0402 10V

SDA I2C_2_SDA 6,25

7 GYRO_AUX_CL 1 TP2601 TEST_POINT_20

AUX_CL
GND GND 11 21 GYRO_AUX_DA 1 TP2602 TEST_POINT_20 +V1P8A_SENSOR
FSYNC AUX_DA

22
R2601 0 R 0402 9 nCS
SDO/AD0

REGOUT
R2604

RESV1

RESV2
0 R 0402

GND
@
MPU-6515
10

18

19

20
C2608
0.1UF C 0402 10V

I2C Address: 0x69 (AD0=1)

Power Consumption: 1.8V/3.4mA Normal Mode

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 26_SENSORS

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 26 of 39
 5 4 3 2 1

+V1P8A +V1P8A_AUDIO
CPVDD
DBVDD +V1P8A_AUDIO
SH2701
AVDD DACREF 1 2

VL3 SHORT-0402

600ohm FB 0402 +V3P3A +V3P3A_AUDIO

0.1uF C 0402 16V

0.1uF C 0402 16V

10uF C 0603 6.3V

0.1uF C 0402 16V

10uF C 0603 6.3V

0.1uF C 0402 16V

10uF C 0603 6.3V

2.2uF C 0402 6.3V
VC24 VC6 VC7 VC14 SH2702
VC23 VC11 VC12 VC13 1 2

SHORT-0402
D D

+V_VSYS +VSYS_AUDIO
AGND AGND AGND
GND SH2703
1 2

SPKVDD DCVDD SHORT-0603

+VSYS_AUDIO
MICVDD

+1V2
VC25
VC38 VC17 VC37 VC18

0.1uF C 0402 16V

2.2uF C 0402 6.3V

10uF C0603 10V

10uF C0603 10V

0.1uF C 0402 16V

0.1uF C 0402 16V

VC27

VC29
VC30

Power GND
0.1uF C 0402 16V
2.2uF C 0402 6.3V

GND
AGND

DACREF

SPKVDD
SPKVDD
MICVDD

DCVDD
DBVDD
CPVDD
AVDD
C C

10
15

46

42
43
23
3

2
U28
19 2.2uF C 0402 6.3V
DACREF

SPKVDDL
AVDD
MICVDD
SPKVDDR

DCVDD
DBVDD
CPVDD
CPP2 18 VC1
VC8 MIC_BIAS1 4 CPN2 20 2.2uF C 0402 6.3V
MICBIAS1 CPP1 21 VC9
4.7uF C 0402 6.3V CPN1 2.2uF C 0402 6.3V
24 CPVPP VC2
AGND CPVPP 27 CPVEE VC10 0.1uF C 0201 10V 20 R 0402 AGND
DMIC_DAT 5 CPVEE VC3 VR6
28 DMIC_DAT 6 IN1P/DMIC1_DAT 2.2uF C 0402 6.3V
HP_MIC 1uF C 0402 10V VC5 IN2P 7 IN1N/DMIC2_DAT/JD1 28 AGND AGND HP_L
1uF C 0402 10V VC40 8 IN2P HPO_L 26 HP_R HP_L 28
IN2N/JD2 HPO_R 25 HP_AGND HP_R 28
HPOFB HP_AGND 28
28 JACK_DET_N_R1
AGND VC15 VR10 AGND
0.1uF C 0201 10V 20 R 0402
1 SPK_L_P_L
Reserve for Windows SKU by Intel VC19 4.7uF C 0402 6.3V 12 SPO_LP 48 SPK_L_N_L SPK_L_P_L 28
VC20 4.7uF C 0402 6.3V 11 VREF2 SPO_LN 45 SPK_R_P_L SPK_L_N_L 28
VREF1 SPO_RP 47 SPK_R_N_L SPK_R_P_L 28
SPO_RN SPK_R_N_L 28 MIC_BIAS1

AGND AGND
13
TP3609 TEST_POINT_20 MONOP/IN3P 14
1 MONON/IN3N DBVDD R1961
37
7 CODEC_MCLK MCLK
36 17 0 R 0402 VC46
5 I2S_0_CLK 35 BCLK1 LOUTR 16
5 I2S_0_FS LRCK1 LOUTL 4.7uF C 0402 4V
33 VR82
5 I2S_0_TXD DACDAT1 HP_MIC_BIAS
34

10K R 0402
5 I2S_0_RXD ADCDAT1
VR34
30 2.2K R 0201
B
29 BCLK2 B
31 LRCK2 41 DMIC_SCL
32 DACDAT2 GPIO2/DMIC_SCL 40 DMIC_SCL 28 VR36 1K R 0201

上/下/左/右右右GND
ADCDAT2 GPIO1/IRQ 44 AUDIO_INT 7 HP_MIC HEADSET_MIC
LDO1_EN VR83 @ 0 R 0402 HEADSET_MIC 28
1 CODEC_RESET 4
1
TP3610 VC53
TEST_POINT_20 TP3611 100pF C 0201 25V
DGNDSPKGND

TEST_POINT_20
CODEC_MCLK

38
22pF C 0201 25V

22pF C 0201 25V

22pF C 0201 25V

22pF C 0201 25V

22pF C 0201 25V

SCL I2C_1_SCL 6,23,36

I2S_0_RXD

39
I2S_0_TXD

AGND
I2S_0_CLK

CPGND

SDA
I2S_0_FS

AGND

I2C_1_SDA 6,23,36

ALC5640
9
49

22
VC33
VC31

VC32

VC34

VC35

@ @ @ @ @

SH2707 SH2704 SH2705 SH2706

1 2 1 2 1 2 1 2

GND GND GND GND GND SHORT-0402 SHORT-0402 SHORT-0402 SHORT-0402

AGND GND AGND
AGND GND AGND GND AGND GND AGND GND
I2S1 Interface

A A

Drawing Rule
Acer Inc. Allegro Lib Ver
Project:
Ducati2 BAYt_CR
Title: OrCAD Lib Ver
27 AUDIO ALC5640

Approved: Size: Document Number: Rev

<Approve> C {Doc} {RevCode}
Designer:
<Designer> Date: Friday, July 25, 2014 Sheet: 27 of 39
5 4 3 2 1
 5 4 3 2 1

上/下AGND)
上 下 左 右右右
HP_Headset L/R (AGND/L/AGND/R/AGND
JACK DET EMI/RF
HP_MIC / / / AGND
Audio Jack +V1P8A_AUDIO
EJ-36959-GP VR50 0 R 0201 @ HP_AGND
D D
1 HEADSET_MIC_R VR45 0 R 0201 HEADSET_MIC
3 HP_right VR17 33 R 0402 HP_OUT_R HEADSET_MIC 27

HEADSET_MIC
5 HP_left VR18 33 R 0402 HP_OUT_L

22pF C 0201 25V

22pF C 0201 25V

22pF C 0201 25V

22pF C 0201 25V

HP_OUT_R

HP_OUT_R
VR52

HP_DET
4 HP_DET 100K R 0201
2 HP_AGND_R VR40 0 R 0201 HP_AGND
VR44 0 R 0201 @ HEADSET_MIC
AJ3 To Codec VR80

10K R 0201

10K R 0201
HP_AGND 27

ESD11B5.0ST5G VF24

ESD11B5.0ST5G VF22

ESD11B5.0ST5G VF26
VR85 @ 0 R 0201 JACK_DET_N HP_DET
27 JACK_DET_N_R1

ESD11B5.0ST5G VF25

ESD11B5.0ST5G VF23
@ @ @ @

HP_AGND

VC55

VC56

VC62

VC60
10K R 0201
To SOC From phone Jack
7 JACK_DET_N_R2 VR86 0 R 0201

VR78

VR79
VC61
0.1uF C 0201 6.3V
VR68 GND GND GND GND
@ @ @ @ @
0 R 0201

Reserve for Windows SKU by Intel

AGND AGND AGND

GND
close to Audio Jack

GND
C C

左右右右GND 680pF C 0402 50V

UART SWITCH
VC67 HP_L VR51 0 R 0201 @ HP_OUT_L
20mil @
CM1282-01D1 HP_R VR41 0 R 0201 HP_OUT_R

SH1
+V3P3A_AUDIO

SPK_L_P_L SPK_L_P VF5 W1256-04R_[Z]

27 SPK_L_P_L @
GND
VR31 0 R 0402

0.1uF C 0402 16V

CM1282-01D1 SPK_L_P 1
SPK_L_N_L SPK_L_N VF8 GND
27 SPK_L_N_L @ 2
VR32 0 R 0402 SPK_L_N
Close to Codec SPK_R_P 3 VC26
Close to conn U35
VC65 SPK_R_N 4
680pF C 0402 50V A2 A1
GND V+ NO2 UART3_DEBUG_RXD 6,36
TEST_POINT_40 TP3620 1 A3 B1 HP_OUT_L

SH2
TEST_POINT_40 TP3621 1 AJ2 6,36 UART3_DEBUG_TXD NO1 COM2
TEST_POINT_40 TP3622 1 HP_OUT_R B3 C1 HP_L
TEST_POINT_40 TP3623 1 COM1 NC2 HP_L 27
GND HP_R C3 D1
27 HP_R NC1 IN2
GND D3 D2
GND 7 UART3_DEBUG_SW NI1 GND

左右右右GND
TS5A22362YZPR
680pF C 0402 50V
VC63
20mil

10K R 0201
CM1282-01D1
GND

VR81
SPK_R_P_L SPK_R_P VF6 GND
27 SPK_R_P_L @
VR30 0 R 0402
CM1282-01D1
SPK_R_N_L SPK_R_N VF7 GND
B 27 SPK_R_N_L @ B
VR29 0 R 0402
Close to Codec
Close to conn GND
VC64
680pF C 0402 50V
Speaker
GND

DMIC +V1P8A_AUDIO
MIC1 VL15
DMIC_SCL VR47 0 R 0201 3 1 VDD_1V8_MIC
27 DMIC_SCL
DMIC_DAT VR48 0 R 0201 4 CLOCK VDD 2 10K R 0201 VR46 0 R 0402
27 DMIC_DAT
VC59

VC66

VC22

DATA SELECT 0506

1uF C 0402 10V

1uF C 0402 10V

0.1uF C 0402 16V

A A
ESD11B5.0ST5G VF28

ESD11B5.0ST5G VF27

7 5
8 GND GND 6
GND GND
SD07OT263-010 @

Drawing Rule
@ @
GND
GND GND GND
Acer Inc. Allegro Lib Ver
Project:
GND
Ducati2 BAYt_CR
Title: OrCAD Lib Ver
28 SPK/DMIC/JACK

Approved: Size: Document Number: Rev

<Approve> C {Doc} {RevCode}
Designer:
<Designer> Date: Friday, July 25, 2014 Sheet: 28 of 39
5 4 3 2 1
 5 4 3 2 1

LCM LED BOOST Change from RichTek to TI on 6/20

D D

+V_VSYS
Q2901 +VBKLT_EDP_1 +VBKLT_EDP
1 S D
SH2901 2 S D
1 2 3 S D SH2902
D 5 L2901 10uH L 2520 BKLT_LX D2901 A C 1N5819HW-7-F 1 2
SHORT-0805 C3719 C3718 R3701 C3717 G
1M PR 0402 AON7407 D3205 C3716 R2903 C2902 SHORT-0603
10uF C 0805 25V

1uF C 0402 10V

100pF C 0402 50V

C
4

348K PR 0402
1N5819HW-7-F

10uF C 0805 25V

10uF C 1206 50V

R2

A
R3702 U21
300K PR 0402
16 14
MODE/FAULT SW R2904
12 BKLT_OVP

20K PR 0402
+V_SYS_PANEL OVP
C R1 C
11
IFB1 BL_LED1 25
C3720
10
1uF C 0402 10V

IFB2 BL_LED2 25
15 9
VIN IFB3 BL_LED3 25
BKLT_VLDO 2 7
VLDO IFB4
6
C3724 IFB5
1uF C 0402 10V 5 VOCP=1.5*(1+(R2/R1))
IFB6
4
=1.5*(1+(348K/20K))
COMP =27.6V
1 13 C2906
7 MIPI_PWM_BKLT_EN PWM/EN PGND 8

0.47uF C 0603 25V

BKLT_ISET 3 GND 17
ISET PWPD K&D Spec.: IF=60mA, 21V~24.5V
(21pcs LED Circuit)
TPS61176
R2914

53.6K PR 0402
B B
IFB=(1.04/53.6K)*1024*100%
Change to 53.6K
=19.8mA (53K is not a standard part)

A A

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: LCM LED BOOST

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 29 of 39
5 4 3 2 1
 5 4 3 2 1

USB CONNECTOR

D D

R3652, R3653
+VBUS_CONN
PLACE CLOSE TO CONNECTOR
Change to 300ohm to pass USB host eye, requested by Intel on 7/25

MH1
MH3
SH1
C3001 C ESD3001 R3652 300 PR 0402 J5_USB1
14 USB2_P1_CHG_DN
D3001 1 MUC4B-536207
4.7uF C 0603 10V

TVM0G260M330R
UDZ5V6B @ R3659 0 R 0402 2
20 USB2_OTG_CONN_DN
3
R3653 300 PR 0402 4
14 USB2_P1_CHG_DP
A

5
R3660 0 R 0402
20 USB2_OTG_CONN_DP

7,20 USB_ID_CONN

MH2
MH4
SH2
C C
ESD3002 ESD3003 ESD3004

IECS0305C040

IECS0305C040

TVMAG5R5M330
@ @ @

B B

A A

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 30_USB CONNECTOR

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 30 of 39
5 4 3 2 1
 5 4 3 2 1

VIBRATOR & BUTTONS

Vibrator TP3632
+V3P3A_SEN +V3P3A_VIB

TEST_POINT_40 SH2602
1 2
+V3P3A_VIB
+V3P3S_VIB SHORT-0603

1
D D

SH1
U24 MOTOR_CN3101
5
VIN 1 1
2 OUT
GND C3106 C3104 2 Vibrator rated currenr = 75mA Max
4 3

10uF C 0402 6.3V

0.1UF C 0402 10V

7 SOC_VIBRA_PWM EN /OC
W0801-0202N_[Z]

SH2
G5250M
R3109 C3105

100K PR 0402

1uF C 0402 10V

1
GND

TP3633
GND GND TEST_POINT_40

C C

Power & Volume & Home Key

+V1P8A
J7_BUTTON1

SH2

R3102 0 R 0402 SW_PWR

PWR 4 R3103 @ 10K PR 0402
B 13,36 PMU_PWRBTN_N 5,31 GPI_VOLUMEUP B
C3101 3
Volume+ 2
1000pF C 0402 50V

ESD3101 @ 1
ESDL0402-05
Volume- SH1 R3104 @ 10K PR 0402
5,31 GPI_VOLUMEDOWN

F0560-0401_[Z] Pull-up by SW

R3105 0 R 0402 SW_VOL+

5,31 GPI_VOLUMEUP
C3102
1000pF C 0402 50V

ESD3102 @
ESDL0402-05

1 TP3634 TEST_POINT_40
1 TP3635 TEST_POINT_40
1 TP3636 TEST_POINT_40
1 TP3637 TEST_POINT_40
R3106 0 R 0402 SW_VOL-
5,31 GPI_VOLUMEDOWN
C3103
1000pF C 0402 50V

ESD3103 @
ESDL0402-05

A A

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 31_VIBRATOR & BUTTONS

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 31 of 39
5 4 3 2 1
 5 4 3 2 1

HDMI CONNECTOR for EMI Co-lay

HDMI_TX2_CMC_DP
R3201 @ 0 R 0402
HDMI_TX2_CMC_DN
L3201
DDI0_TX0_DP C3201 0.1UF C 0402 10V HDMI_TX2_CMC_DP A1 A2 HDMI_TX2_DP HDMI_TX1_CMC_DP
4 DDI0_TX0_DP
DDI0_TX0_DN C3202 0.1UF C 0402 10V HDMI_TX2_CMC_DN B1 B2 HDMI_TX2_DN HDMI_TX1_CMC_DN
4 DDI0_TX0_DN
SDCW2012C-2-900TF
HDMI_TX0_CMC_DP
@
D R3202 0 R 0402 HDMI_TX0_CMC_DN D
R3204 R3205 R3206 R3207
HDMI_CLK_CMC_DP

680 PR 0402

680 PR 0402

680 PR 0402

680 PR 0402
R3203 @ 0 R 0402
L3202 HDMI_CLK_CMC_DN
DDI0_TX1_DP C3203 0.1UF C 0402 10V HDMI_TX1_CMC_DP B1 B2 HDMI_TX1_DP
4 DDI0_TX1_DP
DDI0_TX1_DN C3204 0.1UF C 0402 10V HDMI_TX1_CMC_DN A1 A2 HDMI_TX1_DN
4 DDI0_TX1_DN
SDCW2012C-2-900TF R3208 R3209 R3211 R3212

680 PR 0402

680 PR 0402

680 PR 0402

680 PR 0402
@
R3210 0 R 0402

HDMI_PLS_FET
R3213 @ 0 R 0402

L3203
DDI0_TX2_DP C3205 0.1UF C 0402 10V HDMI_TX0_CMC_DP A1 A2 HDMI_TX0_DP
4 DDI0_TX2_DP
Q3201
DDI0_TX2_DN C3206 0.1UF C 0402 10V HDMI_TX0_CMC_DN B1 B2 HDMI_TX0_DN (N) 3
4 DDI0_TX2_DN D
SDCW2012C-2-900TF
G
@ PLS_FET 1
7,13,15,18 PMU_SLP_S0IX_N
R3214 0 R 0402
S
2

R3216 @ 0 R 0402 NMOS NTK3043N Onsemi

L3204
C DDI0_TX3_DP C3207 0.1UF C 0402 10V HDMI_CLK_CMC_DP B1 B2 HDMI_CLK_DP C
4 DDI0_TX3_DP
DDI0_TX3_DN C3208 0.1UF C 0402 10V HDMI_CLK_CMC_DN A1 A2 HDMI_CLK_DN
4 DDI0_TX3_DN
SDCW2012C-2-900TF

@ J8_HDMI1
R3217 0 R 0402 MH1
SHELL1 MH2
1 SHELL2
HDMI_HPD HP DET
2
3 Utility
HDMI_TX2_DP D2+
4
5 D2 Shield
HDMI_TX2_DN D2-
6
HDMI_TX1_DP D1+
ESD3201 @ ESD3202 @ 7
8 D1 Shield
HDMI_TX1_DN D1-
HDMI_TX0_DN 1 10 HDMI_TX0_DN HDMI_TX1_DN 1 10 HDMI_TX1_DN 9
1 10 1 10 HDMI_TX0_DP D0+
10
HDMI_TX0_DP 2 9 HDMI_TX0_DP HDMI_TX1_DP 2 9 HDMI_TX1_DP 11 D0 Shield
2 9 2 9 HDMI_TX0_DN D0-
12
HDMI_CLK_DP CK+
3 3 13
3 3 14 CK Shield
+VHDMI HDMI_CLK_DN CK-
HDMI_TX2_DN 4 7 HDMI_TX2_DN HDMI_CLK_DN 4 7 HDMI_CLK_DN 1 HDMI_CEC_1 15
4 7 4 7 TEST_POINT_20 TP3201 16 CEC
HDMI_TX2_DP 5 6 HDMI_TX2_DP HDMI_CLK_DP 5 6 HDMI_CLK_DP 17 GND
5 6 5 6 HDMI_DDC_SCL DDC CLK
18
HDMI_DDC_SDA DDC DATA
19
BDFN10A054U BDFN10A054U +5V MH3
SHELL3 MH4
B SHELL4 B
AHR48-AK1203
+VHDMI
C3209 C3210

1uF C 0402 10V

22pF C 0402 50V

+V1P8A +V1P8A

Change from AHR48-AK1200 to AHR48-AK1203

A

+V1P8A
D3201
MMSD301T1G
C

R3218 R3219
RN_+VHDMI R3220
10K PR 0402

10K PR 0402

C3211
1K PR 0402
1uF C 0402 10V

R3221 R3222
10K PR 0402

10K PR 0402
2

Q3202
4 DDI0_HPD_N
Q3203
S

3 (N)
D
DDI0_DDC_SCL HDMI_DDC_SCL
(N)

4 DDI0_DDC_SCL
G

G
NMOS NTK3043N Onsemi 1 HDMI_HPD
1

S
2 C3212 R3223

100K PR 0402
1uF C 0402 10V
NMOS NTK3043N Onsemi

DDI0_DDC_SDA HDMI_DDC_SDA
A 4 DDI0_DDC_SDA A
2

Q3204 Drawing Rule

Acer Inc.
S

PLACE CLOSE TO J8_HDMI1 Project: Allegro Lib Ver

(N)

Ducati2 BAYt_CR
G

NMOS NTK3043N Onsemi Title: OrCAD Lib Ver

1

32_HDMI CONNECTOR

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 32 of 39
5 4 3 2 1
MICRO-SD CONNECTOR

+V3P3A_SD +VSD

SH3301
1 2 Layout 20 mil
Remove power switch
(Power enabled by SW from SOC to PMIC SHORT-0603
through I2C register after system boot up) C3302 C3303 C3304 C3305

22pF C 0402 50V

1uF C 0402 10V

1uF C 0402 10V

1uF C 0402 10V

J9_SD1

4 9
VDD 9 10
CD# SDMMC3_CD_N 5
12
7 12 13
5 SDMMC3_D0 DAT0 13
8 14
5 SDMMC3_D1 DAT1 14
1 15
5 SDMMC3_D2 DAT2 VSS1
2
5 SDMMC3_D3 CD/DAT3
5 6
5 SDMMC3_CLK CLK VSS
3 11
5 SDMMC3_CMD CMD 11

TF-0029

Change from TF-0024 to TF-0029 on 5/21

SDMMC3_D0 C3306 22pF C 0402 50V

SDMMC3_D1 C3307 22pF C 0402 50V
SDMMC3_D2 C3308 22pF C 0402 50V
SDMMC3_D3 C3309 22pF C 0402 50V
SDMMC3_CMD C3310 22pF C 0402 50V
SDMMC3_CLK C3311 22pF C 0402 50V
SDMMC3_CD_N @ C3312 22pF C 0402 50V

PLACE CLOSE TO J9_SD1

Drawing Rule
Acer Inc. Allegro Lib Ver
Project:
Ducati2 BAYt_CR
Title: OrCAD Lib Ver
33_MICRO-SD CONNECTOR

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 33 of 39
 50 Ohm trace
WIFI-BT +V1P8A

SH3632
+V1P8A_WIFI_BT +V_VSYS

SH3631
+V3P3A_WIFI_BT

1 2 1 2

SHORT-0402 SHORT-0603
PCB Antenna
@

Stuff 1.5pF in B/C build R3647 0 R 0402

U2516-1
C2545 1.5pF C 50V 0402 U2515 R3615 0 R 0402 U2512
2 1 1 3 A5 A4
Ant RF in
IN OUT WRF_RFIN_2G WRF_RFOUT_2G

G
A2

C2544 0.5pF C 50V 0402

C2543 1pF C 0402 50V

3 4 TBF-1608-245-V3 C3701 10pF C 0402 50V C1 WRF_RFOUT_5G

2
WRF_RFIN_5G

C2541 1pF C 0402 50V

C2542 1pF C 0402 50V

@ @
@ @ L3225
MM8030-2610 4.7nH L 0402 A10 A7
FM_RFIN BT_RF
GND GND
D2
co-layout WRF_GPIO_OUT
G1 P9
WRF_XTAL_CAB_XOP VSS_P9
N8
X1 VSS_N8
1 H1 P8
G 4 WRF_XTAL_CAB_XON VSS_P8
Stuff 0.5pF in B/C build
2 3 R3646 220 PR 0402
G J3
WRF_TCXO_CKIN2V
37.4MHz 18pF
C3699 C3700 F11 H8
22pF C 0402 50V 7 WIFI_32K_CLK LPO_IN RF_SW_Ctrl_4
27pF C 0402 50V NPO G8
RF_SW_Ctrl_3 G6
C3698 220pF C 0402 50V RF_SW_Ctrl_2
D11 H6
C11 FM_AOUT1 RF_SW_Ctrl_1 L6
FM_AOUT2 RF_SW_Ctrl_0
+V1P8A_WIFI_BT +V3P3A_WIFI_BT
Update CIS part description from 34.7MHz to 37.4MHz on 5/21
VIN_LDO
BCM43340XKUBG
L3224 2.2uH L 0603 6/13 Add TP
C3684 2.2uF C 0402 6.3V Update CIS part description from 4.47*5.67 to 5.67*4.47mm
U2516-3
C3693
N2 N1 keep small loop 4.7uF C 0402 6.3V 1 TP3644 TEST_POINT_20
C3685 4.7uF C 0402 6.3V P2 SR_VDDBATA5V SR_VLX P1
SR_VDDBATP5V SR_PVSS 1 TP3643 TEST_POINT_20
U2516-2
A1 VOUT_3P3
WRF_PAPMU_VBAT_VDD5P0 R3650 4.7K R 0402
H9 A3 6 WL_REG_ON
J1 M4
J4 VDDIO_H9 WRF_PAPMU_VOUT_LDO3P3 J2 WL_REG_ON JTAG_SEL
VDDIO_J4 4 BT_REG_ON BT_REG_ON
VIN_LDO VOUT_2P5 6/13 Add TP E11
C3686 0.22uF C 0402 16V F4 C3694 4.7uF C 0402 6.3V 1 CLK_REQ
WRF_BUCK_VDD1P5 TP3645 TEST_POINT_20
P3 N4 TP3646 TEST_POINT_20
1 E7 F10
LDO_VDD1P5 VOUT_2P5 BT_I2S_DO BT_HOST_WAKE BT_HOST_WAKE 7
B3 TP3647 TEST_POINT_20 1 D7 E10
WRF_CBUCK_PAVDD1P5 BT_I2S_CLK BT_DEV_WAKE BT_DEV_WAKE 4
TP3648 TEST_POINT_20
1 D8
C3687 10pF C 0402 50V C3695 2.2uF C 0402 6.3V BT_I2S_WS
VOUT_3P3 L3
B5 HSIC_DVDD1P2_OUT H11 J5
WRF_PA2G_VBAT_VDD3P3 7 UART_1_BT_CTS BT_UART_RTS_N WL_GPIO_12
VOUT_3P3 D4 C3702 1000pF C 0402 50V VDD_CORE 7 UART_1_BT_RTS
G11 G5
J6 WRF_PADRV_VBAT_VDD3P3 G10 BT_UART_CTS_N WL_GPIO_6 H5
VDDIO_RF 7 UART_1_BT_RXD BT_UART_TXD WL_GPIO_5
N3 7 UART_1_BT_TXD H10 J7
VOUT_2P5 VOUT_CLDO BT_UART_RXD WL_GPIO_4 H4
C3688 10pF C 0402 50V A6 VDD_LN WL_GPIO_3 G4
BT_PAVDD WL_GPIO_2 COMBO_WLAN_IRQ 7
C3696 1uF C 0402 16V 5 I2S_1_RXD E8 F3
P4 F9 BT_PCM_OUT WL_GPIO_1 G3
VOUT_LNLDO 5 I2S_1_TXD BT_PCM_IN WL_GPIO_0
VDD_CORE C3689 10pF C 0402 50V E9 5 I2S_1_CLK F8
H7 VDDC_E9 F7 BT_PCM_CLK
VDDC_H7 5 I2S_1_FS BT_PCM_SYNC
K1 F5 C3697 1uF C 0402 16V K7
P5 VDDC_K1 WRF_AFE_GND1P2 D5 NC_K7 J10
VDDC_P5 WRF_LNA_2G_GND1P2 D1 VSS_J10 J11
WRF_LNA_5G_GND1P2 E5 L2 NC_J11
H3 WRF_RX_GND1P2 G2 HSIC_STROBE L7 1
WRF_TCXO_VDD1P8 WRF_SYNTH_GND1P2 NC_L7 TP3649 TEST_POINT_20
Change to H2 G9
BLM15EG121SN1D MURATA C3690 0.1uF C 0402 16V F2 WRF_XTAL_CAB_GND1P2 E1 K2 NC_G9 J9
WRF_SYNTH_VDD1P2 WRF_VCO_GND1P2 E4 HSIC_DATA NC_J9 M7 6/13 Add TP
VDD_LN WRF_TX_GND1P2 D3 K3 NC_M7 K9
WRF_PADRV_VBAT_GND3P3 RREFHSIC NC_K9
L3223 C3691 0.1uF C 0402 16V F1 C7
120ohm FB 0402 WRF_XTAL_CAB_VDD1P2 BT_PLLVSS B6 L1
VDD_LN BT_IFVSS B9 HSIC_AGND12PLL M9
BT_VCOVSS B7 VSS_M9 N10
C8 BT_PAVSS K4 VSS_N10 L8
BT_IFVDD 5 SDIO2_DATA_3 SDIO_DATA_3 VSS_L8
B8 C9 5 SDIO2_DATA_2
K5 N11
A9 BT_PLLVDD FM_PLLVSS B11 L4 SDIO_DATA_2 VSS_N11 P10
BT_VCOVDD FM_VCOVSS 5 SDIO2_DATA_1 SDIO_DATA_1 VSS_P10
C3692 0.1uF C 0402 16V A8 B10 5 SDIO2_DATA_0
L5 P11
BT_LNAVDD FM_LNAVSS M5 SDIO_DATA_0 VSS_P11 J8
5 SDIO2_CMD SDIO_CMD VSS_J8
5 SDIO2_CLK_S
M6 K8
G7 SDIO_CLK VSS_K8
D10 VSSC_G7 D6
FM_PLLVDD VSSC_D6 N6 SDIO0/SDIO1/SDIO2/SDIO3/SDIO_CMD need to pull
A11 VSSC_N6 M2 high. (Intel SOC default 20K pull high) BCM43340XKUBG
FM_LNAVCOVDD VSSC_M2 L9
VSS_L9
C4
WRF_PA2G_VBAT_GND3P3 C3
WRF_PA5G_VBAT_GND3P3_C3 C2
P6 WRF_PA5G_VBAT_GND3P3_C2
Drawing Rule
N7
M11
K11
VSS_P6
VSS_N7
VSS_M11
WRF_PAPMU_GND
PMU_AVSS
B1
M1 Acer Inc. Allegro Lib Ver
L11 VSS_K11 Project:
P7
N9
VSS_L11
VSS_P7 VSS_M10
M10
M8
Ducati2 BAYt_CR OrCAD Lib Ver
VSS_N9 VSS_M8 L10
Title: 34_WIFI-BT
VSS_L10 K10
VCO_K10
Approved: Size: Document Number: Rev
C {Doc} 0.1
BCM43340XKUBG
Designer:
Date: Friday, July 25, 2014 Sheet: 34 of 39
 50 Ohm trace
GPS

+V_VSYS +VSYS_GPS +V1P8A +V1P8A_GPS

@ J11_GPSCLIP1
SH3633 SH3634
1 2 1 2
Clip_0.66

1
SHORT-0603 SHORT-0402

V_GPS_LNA

3
X2

VCC

OUT
26MHz 10pF U2501
C2519
0.1uF C 0402 16V GPS_RF_IN D6 D4

GND

GND
GPS_RFIN GPS_TEST_OUT
1 TP3641 TEST_POINT_20

2
GPS_TCXO E4 A2
GPS_TCXO UART_TXD/SCL A1 UART_2_GPS_RXD 7
UART_RXD/SDA UART_2_GPS_TXD 7
A6 B1
7 GPS_32K_CLK CLK32 UART_NRTS/HOST_REQ UART_2_GPS_CTS 7
B2
UART_NCTS/ANT_SEL UART_2_GPS_RTS 7
R2527 0 R 0402 A5
C2526 GPS_CAL
@
10pF C 0402 50V GPS_WAKEUP_R B3 B6 GPS_LNA_EN_R R2526 0 R 0402 GPS_LNA_EN
B5 NSTANDBY LNA_EN/CAL_REQ
C3682 A3 SYNC/PPS
100nF C 0402 16V C3 IF_VALID
CLK_REQ VDD_GPS_GRF
E2
VDD1P2_GRF E5
A4 VDD_GPS_IF E6
VDD_IO VDD_GPS_LNA C2516 C2514
R2525 0 R 0402 47pF C 0402 50V 1uF C 0402 6.3V
7 GPS_WAKEUP E1 D1 VDD1P1_CORE
R2524 0 R 0402 VDD_3P3_IN VDD1P1_CORE C1
VDD_CORE
E3 D3 Closed to IC's pin
+V1P8A_GPS VDD_AUX_IN VDD1P8_AUX
C2518
REF_CAP C2 D5 1uF C 0402 6.3V
REF_CAP VSS_GPS_LNA C6 Closed to IC's pin
VSS_GPS_IF

C2524 0.01uF C 0402 50V

B4
C2521 C5 VSS_CORE C4 V_GPS_LNA
1uF C 0402 10V 1G TM0 VSS_CORE D2
2G BGA_LOCATE_1 VSS_PMU
BGA_LOCATE_2
BCM4752IUB2G
+VSYS_GPS
C2527
1uF C 0402 10V

Closed to IC's pin

C2523
1uF C 0402 10V

V_GPS_LNA
L2512 600ohm FB 0402

C2533
C2534 39pF C 0402 50V @
0.047uF X5R 0201 10V

Change to HI10056N8JT DARFON GPS_LNA_EN

C2532 Change to HI10056N8JT DARFON
J2 47pF C 0402 50V L2511
2 U2505 6.8nH L 0402 MAX2659
Ground

3 1 RFIN_B8401_CONN_2 1 RFIN_2657_L RFIN_2657 3 4

4 Input 4 RFIN VCC L2510
2 Output C2535 2 5 6.8nH L 0402
GND1 GND2 SHDN
C2537 1pF C 0402 50V

C2538 1pF C 0402 50V

20369-001E 5 470pF C 0402 25V U2506
GND3 GPS_RF_IN
C2531 2.7pF C 0402 50V

C2530 2.7pF C 0402 50V

3 1 6 1 GPS_RF_IN_1
@ @ GND2 GND1 RFOUT Input 4
@ @ U2514 2 Output
B9482
GND1 5 C2536
3 GND3 1pF C 0402 50V
GND2
B9482 close to u2501

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 35_GPS

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 35 of 39
BATTERY & DEBUG CONNECTOR

Debug Connector

+V1P8A J10_XDP1
Socket
SH2 SH1

2 1
4 3
XDP_H_TDI 7
6 5
XDP_H_TDO 7
8 7
XDP_H_TMS 7
10 9
6,23,27 I2C_1_SDA XDP_H_TRST_N 7
12 11
6,23,27 I2C_1_SCL XDP_H_TCK 7
14 13
XDP_H_PREQ_N 7
16 15
XDP_H_PRDY_N 7
18 17
20 19
19 SPI_MOSI RSMRST_N 7,13
22 21
19 SPI_MISO PMU_PWRBTN_N 13,31
24 23
19 SPI_CS_N COREPWROK 7,13
26 25
19 SPI_CLK
28 27
7 SRTCRST_N UART3_DEBUG_TXD 6,28
30 29
7,13 PLTRST_N UART3_DEBUG_RXD 6,28
Add SRTCRST_N on 5/21 32 31

TP3640
1 SH4 SH3
TEST_POINT_20
L R
AXE532127_[Y]

Battery Connector

TP3605
TEST_POINT_40

+V_BATTERY
1

C3601 C3602 C3603

Change from WB1202H-060GN_[Z] to
33pF C 0402 50V

10uF C 0402 6.3V

0.1uF C 0402 16V

WH6C-1B7D1-11006_[Z] C build
(pay attention to footprint)
SH1

J11_BATTERY1
+VBATTERY_SENSE
1
R3604 0 R 0402
2
TEST_POINT_40 TP3619 1
3
13 BATT_ID
14 BATT_THERM
4
TEST_POINT_40 TP3618 1
5

TEST_POINT_40 TP3606 1 6

WH6C-1B7D1-11006_[Z]
SH2

Drawing Rule

BAT_AGND
Acer Inc. Allegro Lib Ver
BAT_AGND
Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 36_BATTERY & DEBUG CONNECTOR

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 36 of 39
POWER SEQUENCE - DOLLARCOVE TI

Drawing Rule
Acer Inc. Allegro Lib Ver
Project:
Ducati2 BAYt_CR
Title: OrCAD Lib Ver
37_POWER SEQUENCE

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 37 of 39
 +V3P3A_WIFI_BT
U2516 WIFI/BT
U7 U8 U9 U10 DDR3L
POWER TREE SH3631 10m PR 0603 384mA SR_VDDBATA5V +VDDQ_DDR (H5TC4G63MFR-PBA)
+V1P8A SH3632 0.01 PR 0402 20mA WRF_PAPMU_VBAT_VDD5P0 SH1204 10m PR 0603 680mA VDD
U21 TPS61176 +V1P8A_WIFI_BT VDDIO 325mA
RT8567_VIN +VBKLT_EDP_1 VTT
4.3V~3.4V/1000mA SH2901 0.01 PR 0805 1000mA SH2902 10m PR 0603 +VBKLT_EDP
U11 Ext LDO RT9040 40mA
LCM BOOST VREFDQ
325mA 40mA
USB Charger With Adjustable U5 TPS60151 J8 HDMI1 (AHR48-AK1200)
VDDQ_VTT LDO VREFCA
Voltage USB OTG 4.3V~3.4V/229mA
+VHDMI_OUT +VHDMI
SH1502 0.01 PR 0402 140mA
+VDDQ_DDR
J5 USB U3 Charger IC CHARGE PUMP +5V Voltage Divider +VREFDQL
+VREFDQU
MUC4B-536207+VBUS_CONN (BQ24297RGET) +VDDQ_DDR
U2 TI PMIC
AC 5V/2000mA +5V SH3635 10m PR 0603 2000mA (PSND9039ABTRSK) Voltage Divider +VREFCAL
+VREFCAU
U1 SOC (Z3735F)
adapter VBUS +V_VSYS SH1203 10m +V_VSYS_PMIC +V_VCC_PMIC +V_VCC
4.3V~3.4V/2000mA PR 0603 4.3V~3.4V/980mA SH1207 10m PR 0603 3000mA CORE_VCC_S0IX
BUCK1 (1V/3A)
SYS +V1P0SX_BUCK2 +V1P0SX DDI_V1P0_S0IX,
+V_BATTERY SH3616 10m PR 0603 900mA
4.3V~3.4V/2000mA 4.3V~3.4V/588mA UNCORE_V1P0_S0IX
Battery BAT BUCK2 (1V/1.8A) 225mA UNCORE_V1P0_G3,
+V1P0A +V1P0A_SOC 175mA UNCORE_V1P0_S4,
U2 TI PMIC 4.3V~3.4V/686mA
BUCK3 (1.05V/2A) SH901 10m PR 0603 1900mA USB_V1P0_S4,
+VBATTERY_SENSE GPIO_V1P0_S4,
600mA
VBATSENSE +VDDQ 900mA CORE_V1P05_S4,
R3604 0 R 0402 4.3V~3.4V/817mA
BUCK4 (VDDQ 1.25V/2A) 1605mA +VDDQ_SOC DRAM_V1P0_S4
SH3636 10m PR 0603 600mA DRAM_VDD_S4
IBATSENSEP IBATSENSEN +V_VNN_PMIC +V_VNN
SH1206 10m PR 0603 5000mA UNCORE_VNN_S4
4.3V~3.4V/1634mA
LOADSENSE BATSENSE BUCK5 (1V/5A) PMC_V1P8_G3,
+V1P8A_BUCK6 +V1P8A +V1P8A +V1P8A_SOC 70mA
R3631 0.01 PR 2512 SH3637 10m PR 0603 SH1202 10m PR 0603 80mA UNCORE_V1P8_G3
4.3V~3.4V/588mA 10mA MIPI_V1P8_S4,
BAT_AGND BUCK6 (1.8V/1A)
+V1P2SX +V1P2SX_SOC UNCORE_V1P8_S4
SH701 0.01 PR 0402 225mA UNCORE_V1P24_S0IX_F
LDO1
(1.25V/300mA) DRAM_V1P24_S0ix_F1
+V1P2A +V1P2A_SOC ICLK_V1P24_S4_F,
Remove +V1P8A SH902 0.01 PR 0402 45mA
U4 TPS61253 370mA LDO2 MIPI_V1P24_S4
+V_VSYS VINLDO1_2_5 (1.25V/100mA) +V3P3A_SOC 45mA PCU_V3P3_G3
4.3V~3.4V/2451mA SH3618 10m PR 0603 70mA 25mA
5.0V 1.5A Boost +VREFDQ USB_V3P3_S0IX
LDO5 +VSDIO 5mA SD3_V1P8V3P3_S4
U6 TPS62063DSGT (0.62V/20mA) Not use
+V_VSYS U35 TS5A22362YZPR +VRTC 0.1mA RTC_VCC
4.3V~3.4V/1725mA +V3P3A_PMIC +V3P3A +V3P3A_AUDIO
3.3V BUCK LDO3 SH3620 10m PR 0603 SH2702 0.01 PR 0402 100mA
(3.3V/200mA) UART Switch U16 EMMC
U22 TPS22910 4.3V~3.4V/700mA
+V3P3A_SD VINLDO3_6 +V2P85S_MMC +V2P85S_EMMC_VCC (KE4CN3K6A-A58)
500mA LDO6 SH2101 10m PR 0603 200mA VCC
FET Switch (2.85V/500mA) +V1P8A 10mA VCCQ
+VSDIO
LDO7
4.3V~3.4V/600mA
(2.85V/200mA) +V3P3A_SD +VSD
J9 SD Conn. (TF-0024)
VSYS2 SH3301 10m PR 0603 500mA VDD
LDO8
(2.85V/400mA) +AVDD_CAM +V2P8_CAM
J1 Rear Camera (5M)
SH2301 0.01 PR 0402 273.4mA 136.7mA V2P85SX
LDO9 50mA
(2.85V/250mA) V1P8SX
4.3V~3.4V/500mA J2 Front Camera (2M)
VSYS1
LDO10 +V1P8S_CAM1 +V1P8_CAM 136.7mA V2P85SX
(1.8V/250mA) SH2302 0.01 PR 0402 100mA 50mA
V1P8SX
LDO12 +V3P3A_SEN
U24 G5250M +V3P3S_VIB CN3101 Vibrator Conn.

4.3V~3.4V/700mA
(2.85V/200mA) 120mA
FET Switch 120mA Vibrator
VSYS4 U17 TPS22964 +V3P3A_SENSOR J4 MIPI DISPLAY
LDO14 +V3P3S_DISP SH2602 10m PR 0603
(3.3V/500mA) 133mA Not use (FH35C-31S-0.3SHW_[SR])
FET Switch LCM_3D3V 133mA V3P3A
+V1P8S_CAM2 10mA
LDO11 U18 TPS22964 SH2501 10m PR 0603 V1P8S
(1.8V/250mA) Not use +VBKLT_EDP VBacklight
+V1P8A SH2502 10m PR 0603 LCM_1D8V J3 Touch Conn.
FET Switch
4.3V~3.4V/402mA LDO13 +V3P3A_TCH +V3P3SX_TOUCH (F0560-0801_[Z])
VSYS3 (3.3V/150mA) SH2401 0.01 PR 0402 15mA V3P3A
15mA
+VRTC +V1P8A +V1P8A_TOUCH V1P8S
LDO4 VRTC SH2402 0.01 PR 0402 U12 SPI NOR
(3V/2mA) +V1P8A +V1P8A_SPI (W25Q64FWZPIG)
U13 USB PHY (TUSB1210) SH1901 0.01 PR 0402 25mA VCC
+V1P8A +V1P8A_ULPI
SH2001 0.01 PR 0402 (60+100)mA VDDIO,VDD18,VCCB U20 Gyro&Gsensor(MPU-6515)
MIC1 DMIC +V1P8A +V1P8A_SENSOR
4.3V~3.4V/46mA +VSYS_ULPI VBAT SH2601 0.01 PR 0402 5mA VDD,VDDIO
SH2002 0.01 PR 0402 5mA VDD
U28 CODEC (ALC5640) Drawing Rule
+V1P8A
SH2701 0.01 PR 0402
+V1P8A_AUDIO
111mA DBVDD,AVDDD,CPVDD Acer Inc. Allegro Lib Ver
4.3V~3.4V/15mA SPKVDD Project:
SH2703 10m PR 0603 +VSYS_AUDIO Ducati2 BAYt_CR
+V1P8A +V1P8A_GPS
U2501 GPS (BCM4752IUB2G) Title: 38_POWER TREE
OrCAD Lib Ver

SH3634 0.01 PR 0402 55mA VDD_IO,VDD_3P3_IN

VDD_AUX_IN Approved: Size: Document Number: Rev
4.3V~3.4V/55mA C {Doc} 0.1
SH3633 10m PR 0603 +VSYS_GPS Designer:
Date: Friday, July 25, 2014 Sheet: 38 of 39
CHANGE LIST
Item Issue Root Cause Corrective Action Date Phase

10

11

12

13

Drawing Rule

Acer Inc. Allegro Lib Ver

Project:
Ducati2 BAYt_CR OrCAD Lib Ver
Title: 37_CHANGE LIST

Approved: Size: Document Number: Rev

C {Doc} 0.1
Designer:
Date: Friday, July 25, 2014 Sheet: 39 of 39