R9 - 280X Shematic

8 7 6 5 4 3 2 1
(1) PCI-E INTERFACE
+3.3V_BUS +3.3V_BUS
2
PERST#_buf 1 1 13 14
OUT 13 14
16 15 14 13 INPUT_RAILS_UP 3 D100
PCIE1 IN BAT54S U1
+12V_BUS R101 R102 +0.94V
45.3K 45.3K PCIE
Part 2 of 20
A2 A11 R115 BJ55 BE50
1
+12V PERST_ PERST# 1K PERST#_buf PERSTB PCIE_CALRP PCIE_CALRP R104 1K
A3 +0.94V
1
+12V Q100
C102 C103 C104 B1 +12V
D 10uF 0.15uF 0.15uF B2 +12V SMCLK B5 SMCLK 3 2
BSH111
DNI
GPUSMCLK BF46 SMBCLK PCIE_CALRN BE49 PCIE_CALRN R105 1.69K D
B3 GPUSMCLK
1
+12V 19
1 19 1 IN
+3.3V_BUS Q101 GPUSMDAT
BSH111 19 1 1 BI
SMDAT B6 SMDATA 3 2 DNI 19 GPUSMDAT BF47 SMBDAT PX_EN AK44 PX_EN_R R109 1K PX_EN 13 14 19
A9
OUT
+3.3V
A10 +3.3V
C105 C106 C107 C108 B8 +3.3V REFCLK+ A13 PCIE_REFCLKP BE53 PCIE_REFCLKP PCIE_REFCLKP_OUT0 BF52 PCIE_REFCLKOUT0_P
TP100
0.1uF
10uF 1uF 0.01uF
REFCLK- A14 PCIE_REFCLKN BE52 PCIE_REFCLKN PCIE_REFCLKN_OUT0 BF53 PCIE_REFCLKOUT0_N
TP101
B10 3.3Vaux TP102 PCIE_REFCLKP_OUT1 BJ58 PCIE_REFCLKOUT1_P
TP103
PETp0 B14 PETp0_GFXRp0 BH55 PCIE_RX0P PCIE_REFCLKN_OUT1 BH57 PCIE_REFCLKOUT1_N
TP104
PETn0 B15 PETn0_GFXRn0 BG55 PCIE_RX0N
A4 GND TP105
A12 GND PETp1 B19 PETp1_GFXRp1 BG58 PCIE_RX1P
A15 GND PETn1 B20 PETn1_GFXRn1 BG56 PCIE_RX1N
A18 GND TP106
A20 GND PETp2 B23 PETp2_GFXRp2 BF57 PCIE_RX2P
A23 GND PETn2 B24 PETn2_GFXRn2 BE56 PCIE_RX2N
A24
00
GND TP107 TP108
A27 GND PETp3 B27 PETp3_GFXRp3 BE58 PCIE_RX3P
A28 GND PETn3 B28 PETn3_GFXRn3 BD57 PCIE_RX3N
A31 GND TP109
A34 GND PETp4 B33 BD55 PCIE_RX4P
07
PETp4_GFXRp4
A37 GND PETn4 B34 PETn4_GFXRn4 BC55 PCIE_RX4N
A38 GND TP110 U1
A41 GND PETp5 B37 PETp5_GFXRp5 BC58 PCIE_RX5P
A42 GND PETn5 B38 PETn5_GFXRn5 BC56 PCIE_RX5N JTAG
74
Part 1 of 20
A45 GND
M
TP111 TP112 JTAG_TDO BC44 JTAG_TDO 19
A46 GND PETp6 B41 PETp6_GFXRp6 BB57 PCIE_RX6P BC45 JTAG_TDI
OUT
JTAG_TDI IN 19
A49 GND PETn6 B42 BA56 PCIE_RX6N
65 SI　
PETn6_GFXRn6
JTAG_TMS BC46 JTAG_TMS 19
A51 GND TP113 BB44 JTAG_TCK
OUT
JTAG_TCK OUT 19
A54 GND PETp7 B45 PETp7_GFXRp7 BA58 PCIE_RX7P BIF_VDDC AL48 BB46 TESTEN +3.3V_BUS
TESTEN IN 19
A55 GND PETn7 B46 PETn7_GFXRn7 AY57 PCIE_RX7N BIF_VDDC AL47 BB45 JTAG_TRSTB
JTAG_TRSTB
A58 GND BIF_VDDC AL49 C109 C110 C111 MR106 DNI 1K
TP114
A59 GND PETp8 B50 PETp8_GFXRp8 AY55 PCIE_RX8P BIF_VDDC AN47 10uF 1uF 1uF
R106 1K
　
+0.94V Tahiti
A62 GND PETn8 B51 AW55 PCIE_RX8N
C A63 GND TP115 TP116
PETn8_GFXRn8
R107 1K
C
A66 GND PETp9 B54 PETp9_GFXRp9 AW58 PCIE_RX9P PCIE_VDDC BE47 MR107 DNI 1K
張 CON
A67 GND PETn9 B55 PETn9_GFXRn9 AW56 PCIE_RX9N PCIE_VDDC AU51
A70 GND TP117 PCIE_VDDC AL50 C112 C113 C114 C115 C116
A71 GND PETp10 B58 PETp10_GFXRp10 AV57 PCIE_RX10P PCIE_VDDC AY47 10uF 10uF 1uF 1uF 1uF
A74 GND PETn10 B59 PETn10_GFXRn10 AU56 PCIE_RX10N PCIE_VDDC AY51
A75 GND TP118 PCIE_VDDC AP55
文
A78 GND PETp11 B62 PETp11_GFXRp11 AU58 PCIE_RX11P PCIE_VDDC AW47
F
A79 GND PETn11 B63 PETn11_GFXRn11 AT57 PCIE_RX11N PCIE_VDDC BC47 C117 C118 C119 C120 C161
A82 GND TP119 PCIE_VDDC AP51 1uF 1uF 1uF 1uF 1uF
TP120
RM 　 ID
B4 GND PETp12 B66 PETp12_GFXRp12 AT55 PCIE_RX12P PCIE_VDDC AP47
B7 GND PETn12 B67 PETn12_GFXRn12 AR55 PCIE_RX12N PCIE_VDDC AT47
B13 GND TP121 PCIE_VDDC BC51
B16 GND PETp13 B70 PETp13_GFXRp13 AR58 PCIE_RX13P PCIE_VDDC AV55 C121 C122 C123 C124 C162
A( RD EN
B18 GND PETn13 B71 PETn13_GFXRn13 AR56 PCIE_RX13N PCIE_VDDC BF55 1uF 1uF 0.1uF 0.1uF 0.1uF
+3.3V_BUS
B21 GND TP122 PCIE_VDDC BB55
B22 GND PETp14 B74 PETp14_GFXRp14 AP57 PCIE_RX14P PCIE_VDDC AL51
B25 GND PETn14 B75 PETn14_GFXRn14 AN56 PCIE_RX14N PCIE_VDDC AU47
5
吳 (C TI
B26 GND TP123 PCIE_VDDC BB47
TP124 U100 C101
B29 GND PETp15 B78 PETp15_GFXRp15 AN58 PCIE_RX15P PCIE_VDDC AT43 0.1uF
B32 GND PETn15 B79 PETn15_GFXRn15 AM57 PCIE_RX15N DNI
B35 GND TP125
積 )2 AL
B36 GND
B39 GND PERp0 A16 PERp0 C125 0.22uF 6.3V PCIE_TX0P BC50 PCIE_TX0P NC7SZ08P5X_NL
B40 A17 C126 0.22uF 6.3V BC49 DNI
GND PERn0 PERn0 PCIE_TX0N PCIE_TX0N
3
+1.8V
B43 GND R100 DNI 10K
+3.3V_BUS
B44 GND PERp1 A21 PERp1 C127 0.22uF 6.3V PCIE_TX1P BC53 PCIE_TX1P PCIE_PVDD BH51
源 01
DNI
B47 GND PERn1 A22 PERn1 C128 0.22uF 6.3V PCIE_TX1N BC52 PCIE_TX1N PCIE_PVDD BH52 C100 0.1uF
B49 GND C129 C130 C131 C132
B52 GND PERp2 A25 PERp2 C133 0.22uF 6.3V PCIE_TX2P BB50 PCIE_TX2P 0.01uF 0.1uF 1uF 4.7uF
4V
B53 A26 C134 0.22uF 6.3V BB49 U100
GND PERn2 PERn2 PCIE_TX2N PCIE_TX2N INPUT_RAILS_UP R103 DNI 0R 1
)
B56 GND 4 PERST#_buf
20
B57 GND PERp3 A29 PERp3 C135 0.22uF 6.3V PCIE_TX3P BB53 PCIE_TX3P PERST# 2
B60 GND Mechanical Key PERn3 A30 PERn3 C136 0.22uF 6.3V PCIE_TX3N BB52 PCIE_TX3N NC7SZ08P5X_NL
B61 GND PCIE_VSS BH53 DNI
B64 GND PERp4 A35 C137 0.22uF 6.3V AY50 PCIE_TX4P PCIE_VSS BB48
B PERp4 PCIE_TX4P
B
6
B65 GND PERn4 A36 PERn4 C138 0.22uF 6.3V PCIE_TX4N AY49 PCIE_TX4N PCIE_VSS AT48
B68 GND PCIE_VSS AL56
05
B69 GND PERp5 A39 PERp5 C139 0.22uF 6.3V PCIE_TX5P AY53 PCIE_TX5P PCIE_VSS AL55
B72 GND PERn5 A40 PERn5 C140 0.22uF 6.3V PCIE_TX5N AY52 PCIE_TX5N PCIE_VSS AL53
B73 GND PCIE_VSS AL52
B76 GND PERp6 A43 PERp6 C141 0.22uF 6.3V PCIE_TX6P AW50 PCIE_TX6P PCIE_VSS AM55
00
B77 GND PERn6 A44 PERn6 C142 0.22uF 6.3V PCIE_TX6N AW49 PCIE_TX6N PCIE_VSS AL58
B80 GND PCIE_VSS BH59
PERp7 A47 PERp7 C143 0.22uF 6.3V PCIE_TX7P AW53 PCIE_TX7P PCIE_VSS BF59
PERn7 A48 PERn7 C144 0.22uF 6.3V PCIE_TX7N AW52 PCIE_TX7N PCIE_VSS BF51
1
B9 JTAG1 PCIE_VSS BE55
A5 JTAG2 PERp8 A52 PERp8 C145 0.22uF 6.3V PCIE_TX8P AU50 PCIE_TX8P PCIE_VSS BE51
JTDIO_LOOP A6 JTAG3 PERn8 A53 PERn8 C146 0.22uF 6.3V PCIE_TX8N AU49 PCIE_TX8N PCIE_VSS BE48
A7 JTAG4 PCIE_VSS BD59
A8 JTAG5 PERp9 A56 PERp9 C147 0.22uF 6.3V PCIE_TX9P AU53 PCIE_TX9P PCIE_VSS BC48
PERn9 A57 PERn9 C148 0.22uF 6.3V PCIE_TX9N AU52 PCIE_TX9N PCIE_VSS BB59
PCIE_VSS BB51
PRESENCE A1 PRSNT1_A1 PERp10 A60 PERp10 C149 0.22uF 6.3V PCIE_TX10P AT50 PCIE_TX10P PCIE_VSS BA55
B17 PRSNT2_B17 PERn10 A61 PERn10 C150 0.22uF 6.3V PCIE_TX10N AT49 PCIE_TX10N PCIE_VSS AY59
B31 PRSNT2_B31 PCIE_VSS AY48
B48 PRSNT2_B48 PERp11 A64 PERp11 C151 0.22uF 6.3V PCIE_TX11P AT53 PCIE_TX11P PCIE_VSS AW51
B81 PRSNT2_B81 PERn11 A65 PERn11 C152 0.22uF 6.3V PCIE_TX11N AT52 PCIE_TX11N PCIE_VSS AW48
PCIE_VSS AV59
PERp12 A68 PERp12 C153 0.22uF 6.3V PCIE_TX12P AP50 PCIE_TX12P PCIE_VSS AU55
B11 WAKE_ PERn12 A69 PERn12 C154 0.22uF 6.3V PCIE_TX12N AP49 PCIE_TX12N PCIE_VSS AU48
PCIE_VSS AT59
PERp13 A72 PERp13 C155 0.22uF 6.3V PCIE_TX13P AP53 PCIE_TX13P PCIE_VSS AT51
A19 RSVD_A19 PERn13 A73 PERn13 C156 0.22uF 6.3V PCIE_TX13N AP52 PCIE_TX13N PCIE_VSS AP59
A32 RSVD_A32 PCIE_VSS AP48
A33 RSVD_A33 PERp14 A76 PERp14 C157 0.22uF 6.3V PCIE_TX14P AN50 PCIE_TX14P PCIE_VSS AN55
A50 RSVD_A50 PERn14 A77 PERn14 C158 0.22uF 6.3V PCIE_TX14N AN49 PCIE_TX14N PCIE_VSS AN51
B12 RSVD_B12 PCIE_VSS AN48
B30 A80 C159 0.22uF 6.3V AN53 BJ56 CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
RSVD_B30 PERp15 PERp15 PCIE_TX15P PCIE_TX15P PCIE_VSS
B82 RSVD_B82 PERn15 A81 PERn15 C160 0.22uF 6.3V PCIE_TX15N AN52 PCIE_TX15N PCIE_VSS AM59 AMD - GRAPHICS C 2010 Advanced Micro Devices
x16 PCIe Tahiti

1 COMMERCE VALLEY This AMD Board schematic and design is the exclusive property of AMD, and
A MARKHAM, ONTARIO, L3T 7X6 is provided only to entities under a non-disclosure agreement with AMD A
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
SHEET: TAHITI PCIE schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
DATE: Wed Nov 02 15:28:37 2011 REV: 1.0 information included herein.
SHEET NUMBER: 1 OF 21 TITLE:

TITLE
DOCUMENT NUMBER: 105-C38600-00
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(2) TAHITI Memory Channel A&B
U1 U1
BANK A DQA1_<31..0>
BI 3 3 BI DQB0_<31..0> BANK B
3 DQA0_<31..0> Part 3 of 20 Part 4 of 20 DQB1_<31..0> 3
BI AG53 AG44 U50 N39
BI
0 DQA0_<0> DQA0_0 DQA1_0 DQA1_<0> 0 0 DQB0_<0> DQB0_0 DQB1_0 DQB1_<0> 0
1 DQA0_<1> AF50 DQA0_1 DQA1_1 AD46 DQA1_<1> 1 1 DQB0_<1> M51 DQB0_1 DQB1_1 K40 DQB1_<1> 1
2 DQA0_<2> AJ50 DQA0_2 DQA1_2 AC48 DQA1_<2> 2 2 DQB0_<2> U53 DQB0_2 DQB1_2 L39 DQB1_<2> 2
D 3 DQA0_<3> AF51 DQA0_3 DQA1_3 AG46 DQA1_<3> 3 3 DQB0_<3> L53 DQB0_3 DQB1_3 H42 DQB1_<3> 3 D
4 DQA0_<4> AJ51 DQA0_4 DQA1_4 AD47 DQA1_<4> 4 4 DQB0_<4> P51 DQB0_4 DQB1_4 K42 DQB1_<4> 4
5 DQA0_<5> AD52 DQA0_5 DQA1_5 AF44 DQA1_<5> 5 5 DQB0_<5> M53 DQB0_5 DQB1_5 G42 DQB1_<5> 5
6 DQA0_<6> AG52 DQA0_6 DQA1_6 AJ45 DQA1_<6> 6 6 DQB0_<6> U51 DQB0_6 DQB1_6 M40 DQB1_<6> 6
7 DQA0_<7> AD53 DQA0_7 DQA1_7 AC45 DQA1_<7> 7 7 DQB0_<7> R53 DQB0_7 DQB1_7 K39 DQB1_<7> 7
8 DQA0_<8> AH57 DQA0_8 DQA1_8 V47 DQA1_<8> 8 8 DQB0_<8> D49 DQB0_8 DQB1_8 N31 DQB1_<8> 8
9 DQA0_<9> AF57 DQA0_9 DQA1_9 P48 DQA1_<9> 9 9 DQB0_<9> A50 DQB0_9 DQB1_9 T29 DQB1_<9> 9
10 DQA0_<10> AJ55 DQA0_10 DQA1_10 U48 DQA1_<10> 10 10 DQB0_<10> C52 DQB0_10 DQB1_10 T33 DQB1_<10> 10
11 DQA0_<11> AG55 DQA0_11 DQA1_11 R49 DQA1_<11> 11 11 DQB0_<11> D53 DQB0_11 DQB1_11 T30 DQB1_<11> 11
12 DQA0_<12> AK59 DQA0_12 DQA1_12 V49 DQA1_<12> 12 12 DQB0_<12> A54 DQB0_12 DQB1_12 P33 DQB1_<12> 12
13 DQA0_<13> AE55 DQA0_13 DQA1_13 P50 DQA1_<13> 13 13 DQB0_<13> E53 DQB0_13 DQB1_13 P30 DQB1_<13> 13
14 DQA0_<14> AJ56 DQA0_14 DQA1_14 Y47 DQA1_<14> 14 14 DQB0_<14> E51 DQB0_14 DQB1_14 T34 DQB1_<14> 14
15 DQA0_<15> AF59 DQA0_15 DQA1_15 M50 DQA1_<15> 15 15 DQB0_<15> C50 DQB0_15 DQB1_15 R29 DQB1_<15> 15
16 DQA0_<16> AK52 DQA0_16 DQA1_16 K51 DQA1_<16> 16 16 DQB0_<16> J48 DQB0_16 DQB1_16 M37 DQB1_<16> 16
17 DQA0_<17> AF47 DQA0_17 DQA1_17 N43 DQA1_<17> 17 17 DQB0_<17> G46 DQB0_17 DQB1_17 G39 DQB1_<17> 17
18 DQA0_<18> AK49 DQA0_18 DQA1_18 L45 DQA1_<18> 18 18 DQB0_<18> J46 DQB0_18 DQB1_18 H39 DQB1_<18> 18
19 DQA0_<19> AG47 DQA0_19 DQA1_19 P42 DQA1_<19> 19 19 DQB0_<19> H45 DQB0_19 DQB1_19 N36 DQB1_<19> 19
20 DQA0_<20> AK50 DQA0_20 DQA1_20 G50 DQA1_<20> 20 20 DQB0_<20> K45 DQB0_20 DQB1_20 M34 DQB1_<20> 20
AF48 T42 G49 N34
00
21 DQA0_<21> DQA0_21 DQA1_21 DQA1_<21> 21 21 DQB0_<21> DQB0_21 DQB1_21 DQB1_<21> 21
22 DQA0_<22> AG49 DQA0_22 DQA1_22 J50 DQA1_<22> 22 22 DQB0_<22> H49 DQB0_22 DQB1_22 K37 DQB1_<22> 22
23 DQA0_<23> AK53 DQA0_23 DQA1_23 M46 DQA1_<23> 23 23 DQB0_<23> K48 DQB0_23 DQB1_23 L36 DQB1_<23> 23
24 DQA0_<24> AA50 DQA0_24 DQA1_24 R47 DQA1_<24> 24 24 DQB0_<24> R37 DQB0_24 DQB1_24 L27 DQB1_<24> 24
V50 DQA0_25 DQA1_25 AA45 M43 DQB0_25 DQB1_25 N23 DQB1_<25>
07
25 DQA0_<25> DQA1_<25> 25 25 DQB0_<25> 25
26 DQA0_<26> AC53 DQA0_26 DQA1_26 U44 DQA1_<26> 26 26 DQB0_<26> N40 DQB0_26 DQB1_26 M26 DQB1_<26> 26
27 DQA0_<27> V53 DQA0_27 DQA1_27 R43 DQA1_<27> 27 27 DQB0_<27> N42 DQB0_27 DQB1_27 N30 DQB1_<27> 27
28 DQA0_<28> AA52 DQA0_28 DQA1_28 R46 DQA1_<28> 28 28 DQB0_<28> P39 DQB0_28 DQB1_28 M29 DQB1_<28> 28
29 DQA0_<29> AA53 DQA0_29 DQA1_29 Y45 DQA1_<29> 29 29 DQB0_<29> L42 DQB0_29 DQB1_29 N26 DQB1_<29> 29
74
Y50 DQA0_30 DQA1_30 V46 T39 DQB0_30 DQB1_30 N29
M
30 DQA0_<30> DQA1_<30> 30 30 DQB0_<30> DQB1_<30> 30
31 DQA0_<31> V52 DQA0_31 DQA1_31 AA44 DQA1_<31> 31 31 DQB0_<31> N37 DQB0_31 DQB1_31 N24 DQB1_<31> 31
MAA1_<8..0> MAB0_<8..0>
65 SI　
3 OUT MAA0_<8..0>
OUT 3 3 OUT MAB1_<8..0>
OUT 3
0 MAA0_<0> U56 MAA0_0 MAA1_0 K57 MAA1_<0> 0 0 MAB0_<0> E43 MAB0_0 MAB1_0 D35 MAB1_<0> 0
1 MAA0_<1> V57 MAA0_1 MAA1_1 J56 MAA1_<1> 1 1 MAB0_<1> D43 MAB0_1 MAB1_1 E35 MAB1_<1> 1
2 MAA0_<2> W55 MAA0_2 MAA1_2 H59 MAA1_<2> 2 2 MAB0_<2> A44 MAB0_2 MAB1_2 C34 MAB1_<2> 2
3 MAA0_<3> V59 MAA0_3 MAA1_3 J55 MAA1_<3> 3 3 MAB0_<3> C44 MAB0_3 MAB1_3 A34 MAB1_<3> 3
4 MAA0_<4> Y57 MAA0_4 MAA1_4 G56 MAA1_<4> 4 4 MAB0_<4> D45 MAB0_4 MAB1_4 E33 MAB1_<4> 4
　
5 MAA0_<5> W56 MAA0_5 MAA1_5 H57 MAA1_<5> 5 5 MAB0_<5> E45 MAB0_5 MAB1_5 D33 MAB1_<5> 5
C 6 MAA0_<6> T57 MAA0_6 MAA1_6 L56 MAA1_<6> 6 6 MAB0_<6> D41 MAB0_6 MAB1_6 E37 MAB1_<6> 6 C
7 MAA0_<7> T59 MAA0_7 MAA1_7 L55 MAA1_<7> 7 7 MAB0_<7> C42 MAB0_7 MAB1_7 A36 MAB1_<7> 7
張 CON
8 MAA0_<8> U55 MAA0_8 MAA1_8 K59 MAA1_<8> 8 8 MAB0_<8> A42 MAB0_8 MAB1_8 C36 MAB1_<8> 8
AB57 MAA0_9 MAA1_9 F55 E47 MAB0_9 MAB1_9 E31
3 WCKA0_0 AD57 WCKA0_0 WCKA1_0 AA47 WCKA1_0 3 3 WCKB0_0 J53 WCKB0_0 WCKB1_0 R36 WCKB1_0 3
OUT AD59 AA48
OUT OUT K53 T36
OUT
3 OUT WCKA0b_0 WCKA0B_0 WCKA1B_0 WCKA1b_0
OUT 3 3 OUT WCKB0b_0 WCKB0B_0 WCKB1B_0 WCKB1b_0
OUT 3
文 F
3 WCKA0_1 AC51 WCKA0_1 WCKA1_1 H51 WCKA1_1 3 3 WCKB0_1 K43 WCKB0_1 WCKB1_1 L33 WCKB1_1 3
OUT AD50 G52
OUT OUT J43 K33
OUT
3 OUT WCKA0b_1 WCKA0B_1 WCKA1B_1 WCKA1b_1
OUT 3 3 OUT WCKB0b_1 WCKB0B_1 WCKB1B_1 WCKB1b_1
OUT 3
RM 　 ID
3 EDCA0_0 AF53 EDCA0_0 EDCA1_0 AD44 EDCA1_0 3 3 EDCB0_0 P53 EDCB0_0 EDCB1_0 G40 EDCB1_0 3
IN AG56 U47
IN IN D51 R31
IN
3 IN EDCA0_1 EDCA0_1 EDCA1_1 EDCA1_1
IN 3 3 IN EDCB0_1 EDCB0_1 EDCB1_1 EDCB1_1
IN 3
3 EDCA0_2 AJ48 EDCA0_2 EDCA1_2 P45 EDCA1_2 3 3 EDCB0_2 K46 EDCB0_2 EDCB1_2 G37 EDCB1_2 3
IN IN IN IN
A( RD EN
3 EDCA0_3 Y53 EDCA0_3 EDCA1_3 U45 EDCA1_3 3 3 EDCB0_3 T40 EDCB0_3 EDCB1_3 N27 EDCB1_3 3
IN IN IN IN
3 DDBIA0_0 AG50 DDBIA0_0 DDBIA1_0 AF45 DDBIA1_0 3 3 DDBIB0_0 R52 DDBIB0_0 DDBIB1_0 J40 DDBIB1_0 3
BI AH59 R50
BI BI A52 T31
BI
3 BI DDBIA0_1 DDBIA0_1 DDBIA1_1 DDBIA1_1
BI 3 3 BI DDBIB0_1 DDBIB0_1 DDBIB1_1 DDBIB1_1
BI 3
吳 (C TI
3 DDBIA0_2 AJ47 DDBIA0_2 DDBIA1_2 N45 DDBIA1_2 3 3 DDBIB0_2 G48 DDBIB0_2 DDBIB1_2 J37 DDBIB1_2 3
BI Y51 V44
BI BI R40 P27
BI
3 BI DDBIA0_3 DDBIA0_3 DDBIA1_3 DDBIA1_3
BI 3 3 BI DDBIB0_3 DDBIB0_3 DDBIB1_3 DDBIB1_3
BI 3
AC56 WCDRA0_0 WCDRA1_0 AC47 L52 WCDRB0_0 WCDRB1_0 T37
積 )2 AL
AE56 WCDRA0_1 WCDRA1_1 Y48 H53 WCDRB0_1 WCDRB1_1 R34
AD49 WCDRA0_2 WCDRA1_2 G51 G45 WCDRB0_2 WCDRB1_2 N33
AC50 WCDRA0_3 WCDRA1_3 J52 G43 WCDRB0_3 WCDRB1_3 M31
3 ADBIA0 R55 ADBIA0 ADBIA1 M59 ADBIA1 3 3 ADBIB0 A40 ADBIB0 ADBIB1 C38 ADBIB1 3
OUT OUT OUT OUT
3 OUT CSA0b_0 AB59
AC55
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1
C55
E54
CSA1b_0
OUT 3
源 01 3 OUT CSB0b_0 A48

C48
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
A30
C30
CSB1b_0
OUT 3
)
3 CASA0b R56 CASA0B CASA1B M57 CASA1b 3 3 CASB0b E41 CASB0B CASB1B D37 CASB1b 3
OUT OUT OUT OUT
20
3 RASA0b P57 RASA0B RASA1B N56 RASA1b 3 3 RASB0b D39 RASB0B RASB1B E39 RASB1b 3
OUT Y59 G55
OUT OUT C46 A32
OUT
3 OUT WEA0b WEA0B WEA1B WEA1b
OUT 3 3 OUT WEB0b WEB0B WEB1B WEB1b
OUT 3
+MVDD
P59 N55 C40 A38 +MVDD
3 CKEA0 CKEA0 CKEA1 CKEA1 3 3 CKEB0 CKEB0 CKEB1 CKEB1 3
B OUT OUT OUT OUT B
R3607
3
3
OUT
OUT
120R
CLKA0
CLKA0b
MEM_CALRP0
AA56
AA55
AL43
CLKA0
CLKA0B
MEM_CALRP0
CLKA1
CLKA1B
MVREFDA
F59
E57
AC42
CLKA1
CLKA1b
MVREFD_A
OUT
OUT
3
3 R3601
40.2R
6 3 OUT DRAM_RST1 R3618 51R DRAM_RST1_R R3605 10R
05
3
3
OUT
OUT
CLKB0
CLKB0b
DRAM_RST1_RR
D47
A46
AJ43
CLKB0
CLKB0B
DRAM_RST_1
CLKB1
CLKB1B
MVREFDB
C32
D31
V34
CLKB1
CLKB1b
MVREFD_B
OUT
OUT
3
3
R3611
40.2R
00
C3605 120pF R3606 5.1K
R3608 120R V27 +MVDD
MEM_CALRP1 MEM_CALRP1 MVREFD/S =0.7*
R3612 +MVDD
C3602 R3602 C3612 100R
R3609 120R MEM_CALRP2 AG18 MEM_CALRP2
1uF 100R
5 DRAM_RST2 R3617 51R DRAM_RST2_R R3615 10R DRAM_RST2_RR U27 DRAM_RST_2 1uF
DNI OUT DNI
1
C3615 120pF R3616 5.1K
BC31 MVREFD/S =0.7*
R3610 120R MEM_CALRP3 MEM_CALRP3 R3603
40.2R R3613
40.2R
7 OUT DRAM_RST3 R3627 51R DRAM_RST3_R R3625 10R DRAM_RST3_RR AG17 DRAM_RST_3
MVREFSA AD42 MVREFS_A C3625 120pF R3626 5.1K MVREFSB V36 MVREFS_B
BD30 R3614
C3604 R3604 DRAM_RST_4 C3614 100R
1uF 100R 1uF
DNI DNI
Tahiti Tahiti
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

AMD - GRAPHICS C 2010 Advanced Micro Devices
SHEET: TAHITI MEM AB schematic and design, including, not limited to, any implied warranty

TITLE
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(3) GDDR5 Memory Channel A&B
+MVDD +MVDD +MVDD +MVDD
2 DQA0_<31..0> U2000 PATH=I19
2 DQA1_<31..0> U2100 PATH=I38
2 DQB0_<31..0> U2200 PATH=I186
2 DQB1_<31..0> U2300 PATH=I329
BI M2 B1
BI M2 B1
BI M2 B1
BI M2 B1
3 DQA0_<3> DQ31__DQ7 VDDQ_B1 26 DQA1_<26> DQ31__DQ7 VDDQ_B1 8 DQB0_<8> DQ31__DQ7 VDDQ_B1 1 DQB1_<1> DQ31__DQ7 VDDQ_B1
1 DQA0_<1> M4 DQ30__DQ6 VDDQ_B3 B3 24 DQA1_<24> M4 DQ30__DQ6 VDDQ_B3 B3 12 DQB0_<12> M4 DQ30__DQ6 VDDQ_B3 B3 2 DQB1_<2> M4 DQ30__DQ6 VDDQ_B3 B3
5 DQA0_<5> N2 DQ29__DQ5 VDDQ_B12 B12 31 DQA1_<31> N2 DQ29__DQ5 VDDQ_B12 B12 15 DQB0_<15> N2 DQ29__DQ5 VDDQ_B12 B12 7 DQB1_<7> N2 DQ29__DQ5 VDDQ_B12 B12
7 DQA0_<7> N4 DQ28__DQ4 VDDQ_B14 B14 28 DQA1_<28> N4 DQ28__DQ4 VDDQ_B14 B14 13 DQB0_<13> N4 DQ28__DQ4 VDDQ_B14 B14 0 DQB1_<0> N4 DQ28__DQ4 VDDQ_B14 B14
2 DQA0_<2> T2 DQ27__DQ3 VDDQ_D1 D1 25 DQA1_<25> T2 DQ27__DQ3 VDDQ_D1 D1 9 DQB0_<9> T2 DQ27__DQ3 VDDQ_D1 D1 5 DQB1_<5> T2 DQ27__DQ3 VDDQ_D1 D1
4 DQA0_<4> T4 DQ26__DQ2 VDDQ_D3 D3 30 DQA1_<30> T4 DQ26__DQ2 VDDQ_D3 D3 10 DQB0_<10> T4 DQ26__DQ2 VDDQ_D3 D3 6 DQB1_<6> T4 DQ26__DQ2 VDDQ_D3 D3
6 DQA0_<6> V2 DQ25__DQ1 VDDQ_D12 D12 29 DQA1_<29> V2 DQ25__DQ1 VDDQ_D12 D12 14 DQB0_<14> V2 DQ25__DQ1 VDDQ_D12 D12 3 DQB1_<3> V2 DQ25__DQ1 VDDQ_D12 D12
0 DQA0_<0> V4 DQ24__DQ0 VDDQ_D14 D14 27 DQA1_<27> V4 DQ24__DQ0 VDDQ_D14 D14 11 DQB0_<11> V4 DQ24__DQ0 VDDQ_D14 D14 4 DQB1_<4> V4 DQ24__DQ0 VDDQ_D14 D14
10 DQA0_<10> M13 DQ23__DQ15 VDDQ_E5 E5 22 DQA1_<22> M13 DQ23__DQ15 VDDQ_E5 E5 6 DQB0_<6> M13 DQ23__DQ15 VDDQ_E5 E5 11 DQB1_<11> M13 DQ23__DQ15 VDDQ_E5 E5
13 DQA0_<13> M11 DQ22__DQ14 VDDQ_E10 E10 16 DQA1_<16> M11 DQ22__DQ14 VDDQ_E10 E10 2 DQB0_<2> M11 DQ22__DQ14 VDDQ_E10 E10 8 DQB1_<8> M11 DQ22__DQ14 VDDQ_E10 E10
9 DQA0_<9> N13 DQ21__DQ13 VDDQ_F1 F1 23 DQA1_<23> N13 DQ21__DQ13 VDDQ_F1 F1 0 DQB0_<0> N13 DQ21__DQ13 VDDQ_F1 F1 13 DQB1_<13> N13 DQ21__DQ13 VDDQ_F1 F1
D 15 DQA0_<15> N11
T13
DQ20__DQ12 VDDQ_F3 F3
F12
20 DQA1_<20> N11
T13
F12
7 DQB0_<7> N11
T13
F12
10 DQB1_<10> N11
T13
F12
D
12 DQA0_<12> DQ19__DQ11 VDDQ_F12 18 DQA1_<18> DQ19__DQ11 VDDQ_F12 5 DQB0_<5> DQ19__DQ11 VDDQ_F12 15 DQB1_<15> DQ19__DQ11 VDDQ_F12
8 DQA0_<8> T11 DQ18__DQ10 VDDQ_F14 F14 17 DQA1_<17> T11 DQ18__DQ10 VDDQ_F14 F14 1 DQB0_<1> T11 DQ18__DQ10 VDDQ_F14 F14 12 DQB1_<12> T11 DQ18__DQ10 VDDQ_F14 F14
14 DQA0_<14> V13 DQ17__DQ9 VDDQ_G2 G2 21 DQA1_<21> V13 DQ17__DQ9 VDDQ_G2 G2 4 DQB0_<4> V13 DQ17__DQ9 VDDQ_G2 G2 9 DQB1_<9> V13 DQ17__DQ9 VDDQ_G2 G2
11 DQA0_<11> V11 DQ16__DQ8 VDDQ_G13 G13 19 DQA1_<19> V11 DQ16__DQ8 VDDQ_G13 G13 3 DQB0_<3> V11 DQ16__DQ8 VDDQ_G13 G13 14 DQB1_<14> V11 DQ16__DQ8 VDDQ_G13 G13
22 DQA0_<22> F13 DQ15__DQ23 VDDQ_H3 H3 9 DQA1_<9> F13 DQ15__DQ23 VDDQ_H3 H3 21 DQB0_<21> F13 DQ15__DQ23 VDDQ_H3 H3 31 DQB1_<31> F13 DQ15__DQ23 VDDQ_H3 H3
21 DQA0_<21> F11 DQ14__DQ22 VDDQ_H12 H12 15 DQA1_<15> F11 DQ14__DQ22 VDDQ_H12 H12 18 DQB0_<18> F11 DQ14__DQ22 VDDQ_H12 H12 25 DQB1_<25> F11 DQ14__DQ22 VDDQ_H12 H12
19 DQA0_<19> E13 DQ13__DQ21 VDDQ_K3 K3 13 DQA1_<13> E13 DQ13__DQ21 VDDQ_K3 K3 22 DQB0_<22> E13 DQ13__DQ21 VDDQ_K3 K3 29 DQB1_<29> E13 DQ13__DQ21 VDDQ_K3 K3
17 DQA0_<17> E11 DQ12__DQ20 VDDQ_K12 K12 11 DQA1_<11> E11 DQ12__DQ20 VDDQ_K12 K12 17 DQB0_<17> E11 DQ12__DQ20 VDDQ_K12 K12 26 DQB1_<26> E11 DQ12__DQ20 VDDQ_K12 K12
16 DQA0_<16> B13 DQ11__DQ19 VDDQ_L2 L2 8 DQA1_<8> B13 DQ11__DQ19 VDDQ_L2 L2 16 DQB0_<16> B13 DQ11__DQ19 VDDQ_L2 L2 30 DQB1_<30> B13 DQ11__DQ19 VDDQ_L2 L2
20 DQA0_<20> B11 DQ10__DQ18 VDDQ_L13 L13 14 DQA1_<14> B11 DQ10__DQ18 VDDQ_L13 L13 20 DQB0_<20> B11 DQ10__DQ18 VDDQ_L13 L13 27 DQB1_<27> B11 DQ10__DQ18 VDDQ_L13 L13
23 DQA0_<23> A13 DQ9__DQ17 VDDQ_M1 M1 10 DQA1_<10> A13 DQ9__DQ17 VDDQ_M1 M1 23 DQB0_<23> A13 DQ9__DQ17 VDDQ_M1 M1 24 DQB1_<24> A13 DQ9__DQ17 VDDQ_M1 M1
18 DQA0_<18> A11 DQ8__DQ16 VDDQ_M3 M3 12 DQA1_<12> A11 DQ8__DQ16 VDDQ_M3 M3 19 DQB0_<19> A11 DQ8__DQ16 VDDQ_M3 M3 28 DQB1_<28> A11 DQ8__DQ16 VDDQ_M3 M3
28 DQA0_<28> F2 DQ7__DQ31 VDDQ_M12 M12 6 DQA1_<6> F2 DQ7__DQ31 VDDQ_M12 M12 28 DQB0_<28> F2 DQ7__DQ31 VDDQ_M12 M12 17 DQB1_<17> F2 DQ7__DQ31 VDDQ_M12 M12
24 DQA0_<24> F4 DQ6__DQ30 VDDQ_M14 M14 0 DQA1_<0> F4 DQ6__DQ30 VDDQ_M14 M14 26 DQB0_<26> F4 DQ6__DQ30 VDDQ_M14 M14 18 DQB1_<18> F4 DQ6__DQ30 VDDQ_M14 M14
29 DQA0_<29> E2 DQ5__DQ29 VDDQ_N5 N5 3 DQA1_<3> E2 DQ5__DQ29 VDDQ_N5 N5 30 DQB0_<30> E2 DQ5__DQ29 VDDQ_N5 N5 16 DQB1_<16> E2 DQ5__DQ29 VDDQ_N5 N5
26 DQA0_<26> E4 DQ4__DQ28 VDDQ_N10 N10 5 DQA1_<5> E4 DQ4__DQ28 VDDQ_N10 N10 27 DQB0_<27> E4 DQ4__DQ28 VDDQ_N10 N10 22 DQB1_<22> E4 DQ4__DQ28 VDDQ_N10 N10
25 DQA0_<25> B2 DQ3__DQ27 VDDQ_P1 P1 4 DQA1_<4> B2 DQ3__DQ27 VDDQ_P1 P1 31 DQB0_<31> B2 DQ3__DQ27 VDDQ_P1 P1 23 DQB1_<23> B2 DQ3__DQ27 VDDQ_P1 P1
30 DQA0_<30> B4 DQ2__DQ26 VDDQ_P3 P3 7 DQA1_<7> B4 DQ2__DQ26 VDDQ_P3 P3 25 DQB0_<25> B4 DQ2__DQ26 VDDQ_P3 P3 21 DQB1_<21> B4 DQ2__DQ26 VDDQ_P3 P3
00
27 DQA0_<27> A2 DQ1__DQ25 VDDQ_P12 P12 1 DQA1_<1> A2 DQ1__DQ25 VDDQ_P12 P12 24 DQB0_<24> A2 DQ1__DQ25 VDDQ_P12 P12 19 DQB1_<19> A2 DQ1__DQ25 VDDQ_P12 P12
31 DQA0_<31> A4 DQ0__DQ24 VDDQ_P14 P14 2 DQA1_<2> A4 DQ0__DQ24 VDDQ_P14 P14 29 DQB0_<29> A4 DQ0__DQ24 VDDQ_P14 P14 20 DQB1_<20> A4 DQ0__DQ24 VDDQ_P14 P14
VDDQ_T1 T1 VDDQ_T1 T1 VDDQ_T1 T1 VDDQ_T1 T1
07
2 MAA0_<8..0> +MVDD 2 MAA1_<8..0> +MVDD 2 MAB0_<8..0> +MVDD 2 MAB1_<8..0> +MVDD
IN J5
IN J5
IN J5
IN J5
8 MAA0_<8> RFU_A12_NC 8 MAA1_<8> RFU_A12_NC 8 MAB0_<8> RFU_A12_NC 8 MAB1_<8> RFU_A12_NC
74
7 MAA0_<7> K4 A7_A8__A0_A10 VDD_C5 C5 0 MAA1_<0> K4 A7_A8__A0_A10 VDD_C5 C5 7 MAB0_<7> K4 A7_A8__A0_A10 VDD_C5 C5 0 MAB1_<0> K4 A7_A8__A0_A10 VDD_C5 C5
M
6 MAA0_<6> K5 A6_A11__A1_A9 VDD_C10 C10 1 MAA1_<1> K5 A6_A11__A1_A9 VDD_C10 C10 6 MAB0_<6> K5 A6_A11__A1_A9 VDD_C10 C10 1 MAB1_<1> K5 A6_A11__A1_A9 VDD_C10 C10
5 MAA0_<5> K10 A5_BA1__A3_BA3 VDD_D11 D11 3 MAA1_<3> K10 A5_BA1__A3_BA3 VDD_D11 D11 5 MAB0_<5> K10 A5_BA1__A3_BA3 VDD_D11 D11 3 MAB1_<3> K10 A5_BA1__A3_BA3 VDD_D11 D11
65 SI　
4 MAA0_<4> K11 A4_BA2__A2_BA0 VDD_G1 G1 2 MAA1_<2> K11 A4_BA2__A2_BA0 VDD_G1 G1 4 MAB0_<4> K11 A4_BA2__A2_BA0 VDD_G1 G1 2 MAB1_<2> K11 A4_BA2__A2_BA0 VDD_G1 G1
3 MAA0_<3> H10 A3_BA3__A5_BA1 VDD_G4 G4 5 MAA1_<5> H10 A3_BA3__A5_BA1 VDD_G4 G4 3 MAB0_<3> H10 A3_BA3__A5_BA1 VDD_G4 G4 5 MAB1_<5> H10 A3_BA3__A5_BA1 VDD_G4 G4
2 MAA0_<2> H11 A2_BA0__A4_BA2 VDD_G11 G11 4 MAA1_<4> H11 A2_BA0__A4_BA2 VDD_G11 G11 2 MAB0_<2> H11 A2_BA0__A4_BA2 VDD_G11 G11 4 MAB1_<4> H11 A2_BA0__A4_BA2 VDD_G11 G11
1 MAA0_<1> H5 A1_A9__A6_A11 VDD_G14 G14 6 MAA1_<6> H5 A1_A9__A6_A11 VDD_G14 G14 1 MAB0_<1> H5 A1_A9__A6_A11 VDD_G14 G14 6 MAB1_<6> H5 A1_A9__A6_A11 VDD_G14 G14
0 MAA0_<0> H4 A0_A10__A7_A8 VDD_L1 L1 7 MAA1_<7> H4 A0_A10__A7_A8 VDD_L1 L1 0 MAB0_<0> H4 A0_A10__A7_A8 VDD_L1 L1 7 MAB1_<7> H4 A0_A10__A7_A8 VDD_L1 L1
L4 L4 L4 L4
　
VDD_L4 VDD_L4 VDD_L4 VDD_L4
C VDD_L11 L11
L14
VDD_L11 L11
L14
VDD_L11 L11
L14
VDD_L11 L11
L14
C
張 CON
2 WCKA0_1 D4 WCK01__WCK23 VDD_P11 P11 2 WCKA1_0 D4 WCK01__WCK23 VDD_P11 P11 2 WCKB0_1 D4 WCK01__WCK23 VDD_P11 P11 2 WCKB1_1 D4 WCK01__WCK23 VDD_P11 P11
IN D5 R5
IN D5 R5
IN D5 R5
IN D5 R5
2 IN WCKA0b_1 WCK01#__WCK23# VDD_R5 2 IN WCKA1b_0 WCK01#__WCK23# VDD_R5 2 IN WCKB0b_1 WCK01#__WCK23# VDD_R5 2 IN WCKB1b_1 WCK01#__WCK23# VDD_R5
VDD_R10 R10 VDD_R10 R10 VDD_R10 R10 VDD_R10 R10
2 WCKA0_0 P4 WCK23__WCK01 2 WCKA1_1 P4 WCK23__WCK01 2 WCKB0_0 P4 WCK23__WCK01 2 WCKB1_0 P4 WCK23__WCK01
IN P5
IN P5
IN P5
IN P5
2 IN WCKA0b_0 WCK23#__WCK01# 2 IN WCKA1b_1 WCK23#__WCK01# 2 IN WCKB0b_0 WCK23#__WCK01# 2 IN WCKB1b_0 WCK23#__WCK01#
VSSQ_A1 A1 VSSQ_A1 A1 VSSQ_A1 A1 VSSQ_A1 A1
文
R2 A3 R2 A3 R2 A3 R2 A3
F
2 OUT EDCA0_0 EDC3__EDC0 VSSQ_A3 2 OUT EDCA1_3 EDC3__EDC0 VSSQ_A3 2 OUT EDCB0_1 EDC3__EDC0 VSSQ_A3 2 OUT EDCB1_0 EDC3__EDC0 VSSQ_A3
2 EDCA0_1 R13 EDC2__EDC1 VSSQ_A12 A12 2 EDCA1_2 R13 EDC2__EDC1 VSSQ_A12 A12 2 EDCB0_0 R13 EDC2__EDC1 VSSQ_A12 A12 2 EDCB1_1 R13 EDC2__EDC1 VSSQ_A12 A12
OUT C13 A14
OUT C13 A14
OUT C13 A14
OUT C13 A14
RM 　 ID
2 OUT EDCA0_2 EDC1__EDC2 VSSQ_A14 2 OUT EDCA1_1 EDC1__EDC2 VSSQ_A14 2 OUT EDCB0_2 EDC1__EDC2 VSSQ_A14 2 OUT EDCB1_3 EDC1__EDC2 VSSQ_A14
2 EDCA0_3 C2 EDC0__EDC3 VSSQ_C1 C1 2 EDCA1_0 C2 EDC0__EDC3 VSSQ_C1 C1 2 EDCB0_3 C2 EDC0__EDC3 VSSQ_C1 C1 2 EDCB1_2 C2 EDC0__EDC3 VSSQ_C1 C1
OUT C3
OUT C3
OUT C3
OUT C3
VSSQ_C3 VSSQ_C3 VSSQ_C3 VSSQ_C3
2 DDBIA0_0 P2 DBI3#__DBI0# VSSQ_C4 C4 2 DDBIA1_3 P2 DBI3#__DBI0# VSSQ_C4 C4 2 DDBIB0_1 P2 DBI3#__DBI0# VSSQ_C4 C4 2 DDBIB1_0 P2 DBI3#__DBI0# VSSQ_C4 C4
BI P13 C11
BI P13 C11
BI P13 C11
BI P13 C11
2 DDBIA0_1 DBI2#__DBI1# VSSQ_C11 2 DDBIA1_2 DBI2#__DBI1# VSSQ_C11 2 DDBIB0_0 DBI2#__DBI1# VSSQ_C11 2 DDBIB1_1 DBI2#__DBI1# VSSQ_C11
A( RD EN
BI D13 C12
BI D13 C12
BI D13 C12
BI D13 C12
2 BI DDBIA0_2 DBI1#__DBI2# VSSQ_C12 2 BI DDBIA1_1 DBI1#__DBI2# VSSQ_C12 2 BI DDBIB0_2 DBI1#__DBI2# VSSQ_C12 2 BI DDBIB1_3 DBI1#__DBI2# VSSQ_C12
2 DDBIA0_3 D2 DBI0#__DBI3# VSSQ_C14 C14 2 DDBIA1_0 D2 DBI0#__DBI3# VSSQ_C14 C14 2 DDBIB0_3 D2 DBI0#__DBI3# VSSQ_C14 C14 2 DDBIB1_2 D2 DBI0#__DBI3# VSSQ_C14 C14
BI E1
BI E1
BI E1
BI E1
VSSQ_E1 VSSQ_E1 VSSQ_E1 VSSQ_E1
VSSQ_E3 E3 VSSQ_E3 E3 VSSQ_E3 E3 VSSQ_E3 E3
吳 (C TI
G3 E14 +MVDD G3 E14 G3 E14 G3 E14
+MVDD 2 IN RASA0b RAS#__CAS# VSSQ_E14 2 IN CASA1b RAS#__CAS# VSSQ_E14 +MVDD 2 IN RASB0b RAS#__CAS# VSSQ_E14 +MVDD 2 IN CASB1b RAS#__CAS# VSSQ_E14
2 CASA0b L3 CAS#__RAS# VSSQ_F5 F5 2 RASA1b L3 CAS#__RAS# VSSQ_F5 F5 2 CASB0b L3 CAS#__RAS# VSSQ_F5 F5 2 RASB1b L3 CAS#__RAS# VSSQ_F5 F5
IN F10
IN F10
IN F10
IN F10
R2001 60.4R CLKA0b VSSQ_F10 R2101 60.4R CLKA1b VSSQ_F10 R2201 60.4R CLKB0b VSSQ_F10 R2301 60.4R CLKB1b VSSQ_F10
積 )2 AL
R2000 60.4R CLKA0 VSSQ_H2 H2 R2100 60.4R CLKA1 VSSQ_H2 H2 R2200 60.4R CLKB0 VSSQ_H2 H2 R2300 60.4R CLKB1 VSSQ_H2 H2
2 CKEA0 J3 CKE# VSSQ_H13 H13 2 CKEA1 J3 CKE# VSSQ_H13 H13 2 CKEB0 J3 CKE# VSSQ_H13 H13 2 CKEB1 J3 CKE# VSSQ_H13 H13
IN J11 K2
IN J11 K2
IN J11 K2
IN J11 K2
2 IN CK# VSSQ_K2 2 IN CK# VSSQ_K2 2 IN CK# VSSQ_K2 2 IN CK# VSSQ_K2
2 J12 CK VSSQ_K13 K13 2 J12 CK VSSQ_K13 K13 2 J12 CK VSSQ_K13 K13 2 J12 CK VSSQ_K13 K13
IN IN IN IN
源 01
VSSQ_M5 M5 VSSQ_M5 M5 VSSQ_M5 M5 VSSQ_M5 M5
VSSQ_M10 M10 VSSQ_M10 M10 VSSQ_M10 M10 VSSQ_M10 M10
2 CSA0b_0 G12 CS#__WE# VSSQ_N1 N1 2 WEA1b G12 CS#__WE# VSSQ_N1 N1 2 CSB0b_0 G12 CS#__WE# VSSQ_N1 N1 2 WEB1b G12 CS#__WE# VSSQ_N1 N1
IN L12 N3
IN L12 N3
IN L12 N3
IN L12 N3
2 IN WEA0b WE#__CS# VSSQ_N3 2 IN CSA1b_0 WE#__CS# VSSQ_N3 2 IN WEB0b WE#__CS# VSSQ_N3 2 IN CSB1b_0 WE#__CS# VSSQ_N3
)
VSSQ_N12 N12 VSSQ_N12 N12 VSSQ_N12 N12 VSSQ_N12 N12
20
R2002 120R J13 ZQ VSSQ_R1 R1 R2102 120R J13 ZQ VSSQ_R1 R1 R2202 120R J13 ZQ VSSQ_R1 R1 R2302 120R J13 ZQ VSSQ_R1 R1
J10 SEN VSSQ_R3 R3 J10 SEN VSSQ_R3 R3 J10 SEN VSSQ_R3 R3 J10 SEN VSSQ_R3 R3
VSSQ_R4 R4 VSSQ_R4 R4 VSSQ_R4 R4 VSSQ_R4 R4
B B
6
3 2 DRAM_RST1 J2 RESET# VSSQ_R12 R12 3 2 DRAM_RST1 J2 RESET# VSSQ_R12 R12 3 2 DRAM_RST1 J2 RESET# VSSQ_R12 R12 3 2 DRAM_RST1 J2 RESET# VSSQ_R12 R12
IN J1 R14
IN J1 R14
IN J1 R14
IN J1 R14
05
MF VSSQ_R14 +MVDD MF VSSQ_R14 MF VSSQ_R14 +MVDD MF VSSQ_R14
VSSQ_V1 V1 VSSQ_V1 V1 VSSQ_V1 V1 VSSQ_V1 V1
V14 V14 V14 V14
00
VSSQ_V14 VSSQ_V14 VSSQ_V14 VSSQ_V14
R2005 2.37K A5 Vpp_NC +MVDD R2105 2.37K A5 Vpp_NC R2205 2.37K A5 Vpp_NC +MVDD R2305 2.37K A5 Vpp_NC
+MVDD +MVDD
R2006 5.49K V5 Vpp_NC1 R2106 5.49K V5 Vpp_NC1 R2206 5.49K V5 Vpp_NC1 R2306 5.49K V5 Vpp_NC1
C2001 1uF VSS_B5 B5 C2101 1uF VSS_B5 B5 C2201 1uF VSS_B5 B5 C2301 1uF VSS_B5 B5
A10 VREFD1 VSS_B10 B10 A10 VREFD1 VSS_B10 B10 A10 VREFD1 VSS_B10 B10 A10 VREFD1 VSS_B10 B10
1
+MVDD R2007 2.37K V10 VREFD2 VSS_D10 D10 R2107 2.37K V10 VREFD2 VSS_D10 D10 R2207 2.37K V10 VREFD2 VSS_D10 D10 +MVDD R2307 2.37K V10 VREFD2 VSS_D10 D10
+MVDD +MVDD
R2008 5.49K VSS_G5 G5 R2108 5.49K VSS_G5 G5 R2208 5.49K VSS_G5 G5 R2308 5.49K VSS_G5 G5
C2003 1uF VSS_G10 G10 C2103 1uF VSS_G10 G10 C2203 1uF VSS_G10 G10 C2303 1uF VSS_G10 G10
VSS_H1 H1 VSS_H1 H1 VSS_H1 H1 VSS_H1 H1
R2009 2.37K VSS_H14 H14 R2109 2.37K VSS_H14 H14 +MVDD R2209 2.37K VSS_H14 H14 +MVDD R2309 2.37K VSS_H14 H14
+MVDD +MVDD
R2010 5.49K VSS_K1 K1 R2110 5.49K VSS_K1 K1 R2210 5.49K VSS_K1 K1 R2310 5.49K VSS_K1 K1
C2005 1uF J14 VREFC VSS_K14 K14 C2105 1uF J14 VREFC VSS_K14 K14 C2205 1uF J14 VREFC VSS_K14 K14 C2305 1uF J14 VREFC VSS_K14 K14
VSS_L5 L5 VSS_L5 L5 VSS_L5 L5 VSS_L5 L5
VSS_P10 P10 VSS_P10 P10 VSS_P10 P10 VSS_P10 P10
2 ADBIA0 J4 ABI# VSS_T5 T5 2 ADBIA1 J4 ABI# VSS_T5 T5 2 ADBIB0 J4 ABI# VSS_T5 T5 2 ADBIB1 J4 ABI# VSS_T5 T5
IN T10
IN T10
IN T10
IN T10
VSS_T10 VSS_T10 VSS_T10 VSS_T10
GDDR5 GDDR5 GDDR5 GDDR5
+MVDD +MVDD +MVDD

+MVDD
C2010
C2011
C2012
C2013
C2014
C2015
C2016
C2017
C2018
C2019
C2110
C2111
C2112
C2113
C2114
C2115
C2116
C2117
C2118
C2119
C2210
C2211
C2212
C2213
C2214
C2215
C2216
C2217
C2218
C2219
C2310
C2311
C2312
C2313
C2314
C2315
C2316
C2317
C2318
C2319

0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
1 COMMERCE VALLEY
10uF
10uF
10uF
10uF
10uF
10uF
10uF
10uF
This AMD Board schematic and design is the exclusive property of AMD, and
+MVDD +MVDD +MVDD +MVDD AMD makes no representations or warranties of any kind regarding this
SHEET: MEMORY CH AB schematic and design, including, not limited to, any implied warranty
C2029
DATE: Wed Nov 02 15:28:39 2011 REV: 1.0

C2020
C2021
C2022
C2023
C2024
C2025
C2026
C2027
C2028
C2120
C2121
C2122
C2123
C2124
C2125
C2126
C2127
C2128
C2220
C2221
C2222
C2223
C2224
C2225
C2226
C2227
C2228
C2320
C2321
C2322
C2323
C2324
C2325
C2326
C2327
C2328
C2129
information included herein.

10uF
10uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
10uF
10uF
10uF
TITLE
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(4) TAHITI Memory Channel C&D
U1 U1
DQC1_<31..0>
5 DQC0_<31..0> BANK C 5 5 DQD0_<31..0> BANK D DQD1_<31..0> 5
BI Part 5 of 20 BI BI Part 6 of 20 BI
0 DQC0_<0> H36 DQC0_0 DQC1_0 K24 DQC1_<0> 0 0 DQD0_<0> G4 DQD0_0 DQD1_0 M10 DQD1_<0> 0
1 DQC0_<1> G34 DQC0_1 DQC1_1 H21 DQC1_<1> 1 1 DQD0_<1> E3 DQD0_1 DQD1_1 U13 DQD1_<1> 1
2 DQC0_<2> G31 DQC0_2 DQC1_2 H24 DQC1_<2> 2 2 DQD0_<2> F5 DQD0_2 DQD1_2 P12 DQD1_<2> 2
3 DQC0_<3> G36 DQC0_3 DQC1_3 M23 DQC1_<3> 3 3 DQD0_<3> F1 DQD0_3 DQD1_3 U12 DQD1_<3> 3
D 4 DQC0_<4> G33 DQC0_4 DQC1_4 G24 DQC1_<4> 4 4 DQD0_<4> H3 DQD0_4 DQD1_4 R14 DQD1_<4> 4 D
5 DQC0_<5> K31 DQC0_5 DQC1_5 G21 DQC1_<5> 5 5 DQD0_<5> J5 DQD0_5 DQD1_5 V14 DQD1_<5> 5
6 DQC0_<6> H33 DQC0_6 DQC1_6 K23 DQC1_<6> 6 6 DQD0_<6> K1 DQD0_6 DQD1_6 V16 DQD1_<6> 6
7 DQC0_<7> K36 DQC0_7 DQC1_7 L24 DQC1_<7> 7 7 DQD0_<7> J4 DQD0_7 DQD1_7 P13 DQD1_<7> 7
8 DQC0_<8> K29 DQC0_8 DQC1_8 K14 DQC1_<8> 8 8 DQD0_<8> L8 DQD0_8 DQD1_8 AA14 DQD1_<8> 8
9 DQC0_<9> K26 DQC0_9 DQC1_9 K20 DQC1_<9> 9 9 DQD0_<9> L10 DQD0_9 DQD1_9 AA16 DQD1_<9> 9
10 DQC0_<10> G29 DQC0_10 DQC1_10 K15 DQC1_<10> 10 10 DQD0_<10> L7 DQD0_10 DQD1_10 AD16 DQD1_<10> 10
11 DQC0_<11> J29 DQC0_11 DQC1_11 K18 DQC1_<11> 11 11 DQD0_<11> P9 DQD0_11 DQD1_11 AF16 DQD1_<11> 11
12 DQC0_<12> G27 DQC0_12 DQC1_12 K17 DQC1_<12> 12 12 DQD0_<12> U7 DQD0_12 DQD1_12 AF15 DQD1_<12> 12
13 DQC0_<13> G26 DQC0_13 DQC1_13 L15 DQC1_<13> 13 13 DQD0_<13> R7 DQD0_13 DQD1_13 AG16 DQD1_<13> 13
14 DQC0_<14> G30 DQC0_14 DQC1_14 G18 DQC1_<14> 14 14 DQD0_<14> M7 DQD0_14 DQD1_14 AC15 DQD1_<14> 14
15 DQC0_<15> J26 DQC0_15 DQC1_15 H18 DQC1_<15> 15 15 DQD0_<15> R8 DQD0_15 DQD1_15 AA13 DQD1_<15> 15
16 DQC0_<16> N21 DQC0_16 DQC1_16 H15 DQC1_<16> 16 16 DQD0_<16> V8 DQD0_16 DQD1_16 AF9 DQD1_<16> 16
17 DQC0_<17> R23 DQC0_17 DQC1_17 G12 DQC1_<17> 17 17 DQD0_<17> V7 DQD0_17 DQD1_17 AK7 DQD1_<17> 17
18 DQC0_<18> T27 DQC0_18 DQC1_18 G15 DQC1_<18> 18 18 DQD0_<18> R11 DQD0_18 DQD1_18 AF7 DQD1_<18> 18
19 DQC0_<19> R26 DQC0_19 DQC1_19 G17 DQC1_<19> 19 19 DQD0_<19> U10 DQD0_19 DQD1_19 AG7 DQD1_<19> 19
20 DQC0_<20> T26 DQC0_20 DQC1_20 J14 DQC1_<20> 20 20 DQD0_<20> V10 DQD0_20 DQD1_20 AJ9 DQD1_<20> 20
21 DQC0_<21> T24 DQC0_21 DQC1_21 G11 DQC1_<21> 21 21 DQD0_<21> R10 DQD0_21 DQD1_21 AJ7 DQD1_<21> 21
T21 K11 Y10 AF10
00
22 DQC0_<22> DQC0_22 DQC1_22 DQC1_<22> 22 22 DQD0_<22> DQD0_22 DQD1_22 DQD1_<22> 22
23 DQC0_<23> P21 DQC0_23 DQC1_23 H11 DQC1_<23> 23 23 DQD0_<23> P10 DQD0_23 DQD1_23 AJ10 DQD1_<23> 23
24 DQC0_<24> N14 DQC0_24 DQC1_24 D9 DQC1_<24> 24 24 DQD0_<24> AD11 DQD0_24 DQD1_24 AT10 DQD1_<24> 24
25 DQC0_<25> T18 DQC0_25 DQC1_25 A10 DQC1_<25> 25 25 DQD0_<25> AC10 DQD0_25 DQD1_25 AN8 DQD1_<25> 25
DQC0_<26> P18 DQC0_26 DQC1_26 E9 DQC1_<26> DQD0_<26> AA7 DQD0_26 DQD1_26 AL10
07
26 26 26 DQD1_<26> 26
27 DQC0_<27> P15 DQC0_27 DQC1_27 C8 DQC1_<27> 27 27 DQD0_<27> AD7 DQD0_27 DQD1_27 AN7 DQD1_<27> 27
28 DQC0_<28> M17 DQC0_28 DQC1_28 A6 DQC1_<28> 28 28 DQD0_<28> AC12 DQD0_28 DQD1_28 AT7 DQD1_<28> 28
29 DQC0_<29> M14 DQC0_29 DQC1_29 E6 DQC1_<29> 29 29 DQD0_<29> AD8 DQD0_29 DQD1_29 AL7 DQD1_<29> 29
30 DQC0_<30> N17 DQC0_30 DQC1_30 C5 DQC1_<30> 30 30 DQD0_<30> AA8 DQD0_30 DQD1_30 AP7 DQD1_<30> 30
74
K12 DQC0_31 DQC1_31 D7 AD10 DQD0_31 DQD1_31 AT8
M
31 DQC0_<31> DQC1_<31> 31 31 DQD0_<31> DQD1_<31> 31
5 MAC0_<8..0> MAC1_<8..0> 5 5 MAD0_<8..0> MAD1_<8..0> 5
OUT A24 A16
OUT OUT T1 AD1
OUT
0 MAC0_<0> MAC0_0 MAC1_0 MAC1_<0> 0 0 MAD0_<0> MAD0_0 MAD1_0 MAD1_<0> 0
65 SI　
1 MAC0_<1> C24 MAC0_1 MAC1_1 C16 MAC1_<1> 1 1 MAD0_<1> T3 MAD0_1 MAD1_1 AD3 MAD1_<1> 1
2 MAC0_<2> E25 MAC0_2 MAC1_2 D15 MAC1_<2> 2 2 MAD0_<2> R4 MAD0_2 MAD1_2 AE5 MAD1_<2> 2
3 MAC0_<3> D25 MAC0_3 MAC1_3 E15 MAC1_<3> 3 3 MAD0_<3> R5 MAD0_3 MAD1_3 AE4 MAD1_<3> 3
4 MAC0_<4> C26 MAC0_4 MAC1_4 A14 MAC1_<4> 4 4 MAD0_<4> P1 MAD0_4 MAD1_4 AF3 MAD1_<4> 4
5 MAC0_<5> A26 MAC0_5 MAC1_5 C14 MAC1_<5> 5 5 MAD0_<5> P3 MAD0_5 MAD1_5 AF1 MAD1_<5> 5
　
6 MAC0_<6> C22 MAC0_6 MAC1_6 A18 MAC1_<6> 6 6 MAD0_<6> V1 MAD0_6 MAD1_6 AB3 MAD1_<6> 6
C 7 MAC0_<7> D23 MAC0_7 MAC1_7 E17 MAC1_<7> 7 7 MAD0_<7> U5 MAD0_7 MAD1_7 AC4 MAD1_<7> 7 C
8 MAC0_<8> E23 MAC0_8 MAC1_8 D17 MAC1_<8> 8 8 MAD0_<8> U4 MAD0_8 MAD1_8 AC5 MAD1_<8> 8
張 CON
A28 MAC0_9 MAC1_9 C12 M3 MAD0_9 MAD1_9 AH1
5 WCKC0_0 K30 WCKC0_0 WCKC1_0 G20 WCKC1_0 5 5 WCKD0_0 K7 WCKD0_0 WCKD1_0 Y12 WCKD1_0 5
OUT L30 H20
OUT OUT J7 Y13
OUT
5 OUT WCKC0b_0 WCKC0B_0 WCKC1B_0 WCKC1b_0
OUT 5 5 OUT WCKD0b_0 WCKD0B_0 WCKD1B_0 WCKD1b_0
OUT 5
文
5 WCKC0_1 M20 WCKC0_1 WCKC1_1 G10 WCKC1_1 5 5 WCKD0_1 Y7 WCKD0_1 WCKD1_1 AK10 WCKD1_1 5
OUT OUT OUT OUT
F
5 WCKC0b_1 N20 WCKC0B_1 WCKC1B_1 G9 WCKC1b_1 5 5 WCKD0b_1 Y8 WCKD0B_1 WCKD1B_1 AK11 WCKD1b_1 5
OUT OUT OUT OUT
RM 　 ID
5 EDCC0_0 J34 EDCC0_0 EDCC1_0 G23 EDCC1_0 5 5 EDCD0_0 H1 EDCD0_0 EDCD1_0 U15 EDCD1_0 5
IN H27 J17
IN IN M9 AC16
IN
5 IN EDCC0_1 EDCC0_1 EDCC1_1 EDCC1_1
IN 5 5 IN EDCD0_1 EDCD0_1 EDCD1_1 EDCD1_1
IN 5
5 EDCC0_2 T23 EDCC0_2 EDCC1_2 J12 EDCC1_2 5 5 EDCD0_2 U9 EDCD0_2 EDCD1_2 AG8 EDCD1_2 5
IN R17 A8
IN IN AC7 AP9
IN
5 IN EDCC0_3 EDCC0_3 EDCC1_3 EDCC1_3
IN 5 5 IN EDCD0_3 EDCD0_3 EDCD1_3 EDCD1_3
IN 5
A( RD EN
5 DDBIC0_0 K34 DDBIC0_0 DDBIC1_0 J23 DDBIC1_0 5 5 DDBID0_0 G5 DDBID0_0 DDBID1_0 R13 DDBID1_0 5
BI K27 L18
BI BI P7 AD14
BI
5 BI DDBIC0_1 DDBIC0_1 DDBIC1_1 DDBIC1_1
BI 5 5 BI DDBID0_1 DDBID0_1 DDBID1_1 DDBID1_1
BI 5
5 DDBIC0_2 P24 DDBIC0_2 DDBIC1_2 G14 DDBIC1_2 5 5 DDBID0_2 V11 DDBID0_2 DDBID1_2 AG10 DDBID1_2 5
BI BI BI BI
吳 (C TI
5 DDBIC0_3 N15 DDBIC0_3 DDBIC1_3 E7 DDBIC1_3 5 5 DDBID0_3 AC9 DDBID0_3 DDBID1_3 AP10 DDBID1_3 5
BI BI BI BI
J31 WCDRC0_0 WCDRC1_0 K21 J8 WCDRD0_0 WCDRD1_0 V13
H30 WCDRC0_1 WCDRC1_1 L21 K9 WCDRD0_1 WCDRD1_1 Y15
積 )2 AL
R20 WCDRC0_2 WCDRC1_2 J10 AA11 WCDRD0_2 WCDRD1_2 AK8
N18 WCDRC0_3 WCDRC1_3 H9 AA10 WCDRD0_3 WCDRD1_3 AL9
5 ADBIC0 E21 ADBIC0 ADBIC1 D19 ADBIC1 5 5 ADBID0 W4 ADBID0 ADBID1 AA5 ADBID1 5
OUT OUT OUT OUT
源 01
5 CSC0b_0 D29 CSC0B_0 CSC1B_0 E11 CSC1b_0 5 5 CSD0b_0 L5 CSD0B_0 CSD1B_0 AJ4 CSD1b_0 5
OUT E29 D11
OUT OUT L4 AJ5
OUT
CSC0B_1 CSC1B_1 CSD0B_1 CSD1B_1
5 CASC0b A22 CASC0B CASC1B C18 CASC1b 5 5 CASD0b V3 CASD0B CASD1B AB1 CASD1b 5
OUT OUT OUT OUT
)
5 RASC0b C20 RASC0B RASC1B A20 RASC1b 5 5 RASD0b Y1 RASD0B RASD1B Y3 RASD1b 5
OUT OUT OUT OUT
20
5 WEC0b E27 WEC0B WEC1B E13 WEC1b 5 5 WED0b N5 WED0B WED1B AG5 WED1b 5
OUT OUT OUT OUT
D21 E19 +MVDD W5 AA4 +MVDD
5 OUT CKEC0 CKEC0 CKEC1 CKEC1
OUT 5 5 OUT CKED0 CKED0 CKED1 CKED1
OUT 5
B B
6
5 CLKC0 C28 CLKC0 CLKC1 D13 CLKC1 5 5 CLKD0 N4 CLKD0 CLKD1 AH3 CLKD1 5
OUT D27 A12
OUT OUT M1 AG4
OUT
5 OUT CLKC0b CLKC0B CLKC1B CLKC1b
OUT 5 5 OUT CLKD0b CLKD0B CLKD1B CLKD1b
OUT 5
05
R3621 R3631
40.2R 40.2R
MVREFDC V24 MVREFD_C MVREFDD AD18 MVREFD_D
00
C3622 R3622 +MVDD C3632 R3632 +MVDD
1uF 100R 1uF 100R
MVREFD/S =0.7* MVREFD/S =0.7*
DNI DNI
1
R3623 R3633
40.2R 40.2R
MVREFSC V26 MVREFS_C MVREFSD AF18 MVREFS_D
C3624 R3624 R3634

1uF 100R C3634 100R
1uF
DNI
DNI
Tahiti Tahiti

SHEET: TAHITI MEM CD schematic and design, including, not limited to, any implied warranty

TITLE
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(5) GDDR5 Memory Channel C&D

4 DQC0_<31..0> U2400 PATH=I21
4 DQC1_<31..0> U2500 PATH=I43
U2600 U2700
BI M2 B1
BI M2 B1 4 BI DQD0_<31..0> PATH=I193
4 BI DQD1_<31..0> PATH=I338
27 DQC0_<27> DQ31__DQ7 VDDQ_B1 6 DQC1_<6> DQ31__DQ7 VDDQ_B1 13 DQD0_<13> M2 DQ31__DQ7 VDDQ_B1 B1 21 DQD1_<21> M2 DQ31__DQ7 VDDQ_B1 B1
24 DQC0_<24> M4 DQ30__DQ6 VDDQ_B3 B3 5 DQC1_<5> M4 DQ30__DQ6 VDDQ_B3 B3 M4 B3 M4 B3
N2 B12 N2 B12
12 DQD0_<12> DQ30__DQ6 VDDQ_B3 23 DQD1_<23> DQ30__DQ6 VDDQ_B3
31 DQC0_<31> DQ29__DQ5 VDDQ_B12 3 DQC1_<3> DQ29__DQ5 VDDQ_B12 11 DQD0_<11> N2 DQ29__DQ5 VDDQ_B12 B12 20 DQD1_<20> N2 DQ29__DQ5 VDDQ_B12 B12
29 DQC0_<29> N4 DQ28__DQ4 VDDQ_B14 B14 1 DQC1_<1> N4 DQ28__DQ4 VDDQ_B14 B14 N4 B14 N4 B14
T2 D1 T2 D1
15 DQD0_<15> DQ28__DQ4 VDDQ_B14 17 DQD1_<17> DQ28__DQ4 VDDQ_B14
30 DQC0_<30> DQ27__DQ3 VDDQ_D1 4 DQC1_<4> DQ27__DQ3 VDDQ_D1 9 DQD0_<9> T2 DQ27__DQ3 VDDQ_D1 D1 22 DQD1_<22> T2 DQ27__DQ3 VDDQ_D1 D1
26 DQC0_<26> T4 DQ26__DQ2 VDDQ_D3 D3 7 DQC1_<7> T4 DQ26__DQ2 VDDQ_D3 D3 T4 D3 T4 D3
V2 D12 V2 D12
8 DQD0_<8> DQ26__DQ2 VDDQ_D3 19 DQD1_<19> DQ26__DQ2 VDDQ_D3
25 DQC0_<25> DQ25__DQ1 VDDQ_D12 2 DQC1_<2> DQ25__DQ1 VDDQ_D12 14 DQD0_<14> V2 DQ25__DQ1 VDDQ_D12 D12 16 DQD1_<16> V2 DQ25__DQ1 VDDQ_D12 D12
28 DQC0_<28> V4 DQ24__DQ0 VDDQ_D14 D14 0 DQC1_<0> V4 DQ24__DQ0 VDDQ_D14 D14 V4 D14 V4 D14
M13 E5 M13 E5
10 DQD0_<10> DQ24__DQ0 VDDQ_D14 18 DQD1_<18> DQ24__DQ0 VDDQ_D14
20 DQC0_<20> DQ23__DQ15 VDDQ_E5 12 DQC1_<12> DQ23__DQ15 VDDQ_E5 6 DQD0_<6> M13 DQ23__DQ15 VDDQ_E5 E5 25 DQD1_<25> M13 DQ23__DQ15 VDDQ_E5 E5
18 DQC0_<18> M11 DQ22__DQ14 VDDQ_E10 E10 11 DQC1_<11> M11 DQ22__DQ14 VDDQ_E10 E10 M11 E10 M11 E10
N13 F1 N13 F1
5 DQD0_<5> DQ22__DQ14 VDDQ_E10 29 DQD1_<29> DQ22__DQ14 VDDQ_E10
19 DQC0_<19> DQ21__DQ13 VDDQ_F1 10 DQC1_<10> DQ21__DQ13 VDDQ_F1 7 DQD0_<7> N13 DQ21__DQ13 VDDQ_F1 F1 27 DQD1_<27> N13 DQ21__DQ13 VDDQ_F1 F1
N11 F3 N11 F3
D 21
22
DQC0_<21>
DQC0_<22> T13
DQ20__DQ12
DQ19__DQ11
VDDQ_F3
VDDQ_F12 F12
9
8
DQC1_<9>
DQC1_<8> T13
DQ20__DQ12
DQ19__DQ11
VDDQ_F3
VDDQ_F12 F12
4 DQD0_<4> N11
T13
F12
26 DQD1_<26> N11
T13
F12
D
T11 F14 T11 F14
2 DQD0_<2> DQ19__DQ11 VDDQ_F12 30 DQD1_<30> DQ19__DQ11 VDDQ_F12
16 DQC0_<16> DQ18__DQ10 VDDQ_F14 15 DQC1_<15> DQ18__DQ10 VDDQ_F14 3 DQD0_<3> T11 DQ18__DQ10 VDDQ_F14 F14 31 DQD1_<31> T11 DQ18__DQ10 VDDQ_F14 F14
17 DQC0_<17> V13 DQ17__DQ9 VDDQ_G2 G2 13 DQC1_<13> V13 DQ17__DQ9 VDDQ_G2 G2 V13 G2 V13 G2
V11 G13 V11 G13
1 DQD0_<1> DQ17__DQ9 VDDQ_G2 24 DQD1_<24> DQ17__DQ9 VDDQ_G2
23 DQC0_<23> DQ16__DQ8 VDDQ_G13 14 DQC1_<14> DQ16__DQ8 VDDQ_G13 0 DQD0_<0> V11 DQ16__DQ8 VDDQ_G13 G13 28 DQD1_<28> V11 DQ16__DQ8 VDDQ_G13 G13
6 DQC0_<6> F13 DQ15__DQ23 VDDQ_H3 H3 29 DQC1_<29> F13 DQ15__DQ23 VDDQ_H3 H3 F13 H3 F13 H3
F11 H12 F11 H12
19 DQD0_<19> DQ15__DQ23 VDDQ_H3 13 DQD1_<13> DQ15__DQ23 VDDQ_H3
5 DQC0_<5> DQ14__DQ22 VDDQ_H12 30 DQC1_<30> DQ14__DQ22 VDDQ_H12 20 DQD0_<20> F11 DQ14__DQ22 VDDQ_H12 H12 15 DQD1_<15> F11 DQ14__DQ22 VDDQ_H12 H12
4 DQC0_<4> E13 DQ13__DQ21 VDDQ_K3 K3 28 DQC1_<28> E13 DQ13__DQ21 VDDQ_K3 K3 E13 K3 E13 K3
E11 K12 E11 K12
21 DQD0_<21> DQ13__DQ21 VDDQ_K3 11 DQD1_<11> DQ13__DQ21 VDDQ_K3
2 DQC0_<2> DQ12__DQ20 VDDQ_K12 31 DQC1_<31> DQ12__DQ20 VDDQ_K12 22 DQD0_<22> E11 DQ12__DQ20 VDDQ_K12 K12 8 DQD1_<8> E11 DQ12__DQ20 VDDQ_K12 K12
1 DQC0_<1> B13 DQ11__DQ19 VDDQ_L2 L2 24 DQC1_<24> B13 DQ11__DQ19 VDDQ_L2 L2 B13 L2 B13 L2
B11 L13 B11 L13
23 DQD0_<23> DQ11__DQ19 VDDQ_L2 12 DQD1_<12> DQ11__DQ19 VDDQ_L2
7 DQC0_<7> DQ10__DQ18 VDDQ_L13 25 DQC1_<25> DQ10__DQ18 VDDQ_L13 16 DQD0_<16> B11 DQ10__DQ18 VDDQ_L13 L13 9 DQD1_<9> B11 DQ10__DQ18 VDDQ_L13 L13
0 DQC0_<0> A13 DQ9__DQ17 VDDQ_M1 M1 27 DQC1_<27> A13 DQ9__DQ17 VDDQ_M1 M1 A13 M1 A13 M1
A11 M3 A11 M3
18 DQD0_<18> DQ9__DQ17 VDDQ_M1 10 DQD1_<10> DQ9__DQ17 VDDQ_M1
3 DQC0_<3> DQ8__DQ16 VDDQ_M3 26 DQC1_<26> DQ8__DQ16 VDDQ_M3 17 DQD0_<17> A11 DQ8__DQ16 VDDQ_M3 M3 14 DQD1_<14> A11 DQ8__DQ16 VDDQ_M3 M3
12 DQC0_<12> F2 DQ7__DQ31 VDDQ_M12 M12 18 DQC1_<18> F2 DQ7__DQ31 VDDQ_M12 M12 F2 M12 F2 M12
F4 M14 F4 M14
31 DQD0_<31> DQ7__DQ31 VDDQ_M12 4 DQD1_<4> DQ7__DQ31 VDDQ_M12
10 DQC0_<10> DQ6__DQ30 VDDQ_M14 19 DQC1_<19> DQ6__DQ30 VDDQ_M14 25 DQD0_<25> F4 DQ6__DQ30 VDDQ_M14 M14 7 DQD1_<7> F4 DQ6__DQ30 VDDQ_M14 M14
9 DQC0_<9> E2 DQ5__DQ29 VDDQ_N5 N5 16 DQC1_<16> E2 DQ5__DQ29 VDDQ_N5 N5 E2 N5 E2 N5
E4 N10 E4 N10
27 DQD0_<27> DQ5__DQ29 VDDQ_N5 2 DQD1_<2> DQ5__DQ29 VDDQ_N5
11 DQC0_<11> DQ4__DQ28 VDDQ_N10 20 DQC1_<20> DQ4__DQ28 VDDQ_N10 28 DQD0_<28> E4 DQ4__DQ28 VDDQ_N10 N10 0 DQD1_<0> E4 DQ4__DQ28 VDDQ_N10 N10
15 DQC0_<15> B2 DQ3__DQ27 VDDQ_P1 P1 17 DQC1_<17> B2 DQ3__DQ27 VDDQ_P1 P1 B2 P1 B2 P1
B4 P3 B4 P3
29 DQD0_<29> DQ3__DQ27 VDDQ_P1 1 DQD1_<1> DQ3__DQ27 VDDQ_P1
14 DQC0_<14> DQ2__DQ26 VDDQ_P3 23 DQC1_<23> DQ2__DQ26 VDDQ_P3 30 DQD0_<30> B4 DQ2__DQ26 VDDQ_P3 P3 5 DQD1_<5> B4 DQ2__DQ26 VDDQ_P3 P3
00
13 DQC0_<13> A2 DQ1__DQ25 VDDQ_P12 P12 22 DQC1_<22> A2 DQ1__DQ25 VDDQ_P12 P12 A2 P12 A2 P12
A4 P14 A4 P14
24 DQD0_<24> DQ1__DQ25 VDDQ_P12 6 DQD1_<6> DQ1__DQ25 VDDQ_P12
8 DQC0_<8> DQ0__DQ24 VDDQ_P14 21 DQC1_<21> DQ0__DQ24 VDDQ_P14 26 DQD0_<26> A4 DQ0__DQ24 VDDQ_P14 P14 3 DQD1_<3> A4 DQ0__DQ24 VDDQ_P14 P14
VDDQ_T1 T1 VDDQ_T1 T1 T1 T1
T3 T3 VDDQ_T1 VDDQ_T1
VDDQ_T3 VDDQ_T3 VDDQ_T3 T3 VDDQ_T3 T3
T12 T12
07
VDDQ_T12 VDDQ_T12 VDDQ_T12 T12 VDDQ_T12 T12
VDDQ_T14 T14 VDDQ_T14 T14 T14 T14
MAC0_<8..0>
VDDQ_T14 VDDQ_T14
4 IN +MVDD MAC1_<8..0> +MVDD 4 MAD0_<8..0> +MVDD 4 MAD1_<8..0> +MVDD
8 MAC0_<8> J5 RFU_A12_NC
4 IN 8 MAC1_<8> J5 RFU_A12_NC IN J5
IN J5
K4 C5 K4 C5
8 MAD0_<8> RFU_A12_NC 8 MAD1_<8> RFU_A12_NC
74
7 MAC0_<7> A7_A8__A0_A10 VDD_C5 0 MAC1_<0> A7_A8__A0_A10 VDD_C5 7 MAD0_<7> K4 A7_A8__A0_A10 VDD_C5 C5 0 MAD1_<0> K4 A7_A8__A0_A10 VDD_C5 C5
K5 C10 K5 C10
M
6 MAC0_<6> A6_A11__A1_A9 VDD_C10 1 MAC1_<1> A6_A11__A1_A9 VDD_C10 6 MAD0_<6> K5 A6_A11__A1_A9 VDD_C10 C10 1 MAD1_<1> K5 A6_A11__A1_A9 VDD_C10 C10
5 MAC0_<5> K10 A5_BA1__A3_BA3 VDD_D11 D11 3 MAC1_<3> K10 A5_BA1__A3_BA3 VDD_D11 D11 K10 D11 K10 D11
K11 G1 K11 G1
5 MAD0_<5> A5_BA1__A3_BA3 VDD_D11 3 MAD1_<3> A5_BA1__A3_BA3 VDD_D11
65 SI　
4 MAC0_<4> A4_BA2__A2_BA0 VDD_G1 2 MAC1_<2> A4_BA2__A2_BA0 VDD_G1 4 MAD0_<4> K11 A4_BA2__A2_BA0 VDD_G1 G1 2 MAD1_<2> K11 A4_BA2__A2_BA0 VDD_G1 G1
3 MAC0_<3> H10 A3_BA3__A5_BA1 VDD_G4 G4 5 MAC1_<5> H10 A3_BA3__A5_BA1 VDD_G4 G4 H10 G4 H10 G4
H11 G11 H11 G11
3 MAD0_<3> A3_BA3__A5_BA1 VDD_G4 5 MAD1_<5> A3_BA3__A5_BA1 VDD_G4
2 MAC0_<2> A2_BA0__A4_BA2 VDD_G11 4 MAC1_<4> A2_BA0__A4_BA2 VDD_G11 2 MAD0_<2> H11 A2_BA0__A4_BA2 VDD_G11 G11 4 MAD1_<4> H11 A2_BA0__A4_BA2 VDD_G11 G11
1 MAC0_<1> H5 A1_A9__A6_A11 VDD_G14 G14 6 MAC1_<6> H5 A1_A9__A6_A11 VDD_G14 G14 H5 G14 H5 G14
H4 L1 H4 L1
1 MAD0_<1> A1_A9__A6_A11 VDD_G14 6 MAD1_<6> A1_A9__A6_A11 VDD_G14
0 MAC0_<0> A0_A10__A7_A8 VDD_L1 7 MAC1_<7> A0_A10__A7_A8 VDD_L1 0 MAD0_<0> H4 A0_A10__A7_A8 VDD_L1 L1 7 MAD1_<7> H4 A0_A10__A7_A8 VDD_L1 L1
VDD_L4 L4 VDD_L4 L4
　
VDD_L4 L4 VDD_L4 L4
L11 L11
C VDD_L11
VDD_L14 L14
VDD_L11
VDD_L14 L14 VDD_L11 L11
L14
VDD_L11 L11
L14
C
D4 P11 D4 P11 VDD_L14 VDD_L14
4 WCKC0_0 WCK01__WCK23 VDD_P11 4 WCKC1_1 WCK01__WCK23 VDD_P11
張 CON
IN D5 R5
IN D5 R5 4 IN WCKD0_1 D4 WCK01__WCK23 VDD_P11 P11 4 IN WCKD1_0 D4 WCK01__WCK23 VDD_P11 P11
4 IN WCKC0b_0 WCK01#__WCK23# VDD_R5 4 IN WCKC1b_1 WCK01#__WCK23# VDD_R5 4 WCKD0b_1 D5 WCK01#__WCK23# VDD_R5 R5 4 WCKD1b_0 D5 WCK01#__WCK23# VDD_R5 R5
VDD_R10 R10 VDD_R10 R10 IN R10
IN R10
P4 P4 VDD_R10 VDD_R10
4 IN WCKC0_1 WCK23__WCK01 4 IN WCKC1_0 WCK23__WCK01 4 WCKD0_0 P4 WCK23__WCK01 4 WCKD1_1 P4 WCK23__WCK01
4 IN WCKC0b_1 P5 WCK23#__WCK01# 4 IN WCKC1b_0 P5 WCK23#__WCK01# IN P5
IN P5
A1 A1 4 IN WCKD0b_0 WCK23#__WCK01# 4 IN WCKD1b_1 WCK23#__WCK01#
VSSQ_A1 VSSQ_A1 A1 A1
文
R2 A3 R2 A3 VSSQ_A1 VSSQ_A1
4 OUT EDCC0_3 EDC3__EDC0 VSSQ_A3 4 OUT EDCC1_0 EDC3__EDC0 VSSQ_A3 R2 A3 R2 A3
F
R13 A12 R13 A12 4 OUT EDCD0_1 EDC3__EDC0 VSSQ_A3 4 OUT EDCD1_2 EDC3__EDC0 VSSQ_A3
4 OUT EDCC0_2 EDC2__EDC1 VSSQ_A12 4 OUT EDCC1_1 EDC2__EDC1 VSSQ_A12 4 EDCD0_0 R13 EDC2__EDC1 VSSQ_A12 A12 4 EDCD1_3 R13 EDC2__EDC1 VSSQ_A12 A12
4 OUT EDCC0_0 C13 EDC1__EDC2 VSSQ_A14 A14 4 OUT EDCC1_3 C13 EDC1__EDC2 VSSQ_A14 A14 OUT C13 A14
OUT C13 A14
RM 　 ID
C2 C1 C2 C1 4 OUT EDCD0_2 EDC1__EDC2 VSSQ_A14 4 OUT EDCD1_1 EDC1__EDC2 VSSQ_A14
4 OUT EDCC0_1 EDC0__EDC3 VSSQ_C1 4 OUT EDCC1_2 EDC0__EDC3 VSSQ_C1 4 EDCD0_3 C2 EDC0__EDC3 VSSQ_C1 C1 4 EDCD1_0 C2 EDC0__EDC3 VSSQ_C1 C1
VSSQ_C3 C3 VSSQ_C3 C3 OUT C3
OUT C3
P2 C4 P2 C4 VSSQ_C3 VSSQ_C3
4 BI DDBIC0_3 DBI3#__DBI0# VSSQ_C4 4 BI DDBIC1_0 DBI3#__DBI0# VSSQ_C4 4 DDBID0_1 P2 DBI3#__DBI0# VSSQ_C4 C4 4 DDBID1_2 P2 DBI3#__DBI0# VSSQ_C4 C4
4 BI DDBIC0_2 P13 DBI2#__DBI1# VSSQ_C11 C11 4 BI DDBIC1_1 P13 DBI2#__DBI1# VSSQ_C11 C11 BI P13 C11
BI P13 C11
A( RD EN
D13 C12 D13 C12 4 BI DDBID0_0 DBI2#__DBI1# VSSQ_C11 4 BI DDBID1_3 DBI2#__DBI1# VSSQ_C11
4 BI DDBIC0_0 DBI1#__DBI2# VSSQ_C12 4 BI DDBIC1_3 DBI1#__DBI2# VSSQ_C12 4 DDBID0_2 D13 DBI1#__DBI2# VSSQ_C12 C12 4 DDBID1_1 D13 DBI1#__DBI2# VSSQ_C12 C12
4 BI DDBIC0_1 D2 DBI0#__DBI3# VSSQ_C14 C14 4 BI DDBIC1_2 D2 DBI0#__DBI3# VSSQ_C14 C14 BI D2 C14
BI D2 C14
E1 E1 4 BI DDBID0_3 DBI0#__DBI3# VSSQ_C14 4 BI DDBID1_0 DBI0#__DBI3# VSSQ_C14
VSSQ_E1 VSSQ_E1 VSSQ_E1 E1 VSSQ_E1 E1
VSSQ_E3 E3 VSSQ_E3 E3 E3 E3
VSSQ_E3 VSSQ_E3
吳 (C TI
VSSQ_E12 E12 VSSQ_E12 E12 E12 E12
G3 E14 G3 E14 VSSQ_E12 VSSQ_E12
4 IN RASC0b RAS#__CAS# VSSQ_E14 4 IN CASC1b RAS#__CAS# VSSQ_E14 4 RASD0b G3 RAS#__CAS# VSSQ_E14 E14 4 CASD1b G3 RAS#__CAS# VSSQ_E14 E14
4 IN CASC0b L3 CAS#__RAS# VSSQ_F5 F5 4 IN RASC1b L3 CAS#__RAS# VSSQ_F5 F5 IN L3 F5
IN L3 F5
F10 F10 4 IN CASD0b CAS#__RAS# VSSQ_F5 4 IN RASD1b CAS#__RAS# VSSQ_F5
VSSQ_F10 VSSQ_F10 VSSQ_F10 F10 VSSQ_F10 F10
積 )2 AL
VSSQ_H2 H2 VSSQ_H2 H2 H2 H2
J3 H13 J3 H13 VSSQ_H2 VSSQ_H2
4 IN CKEC0 CKE# VSSQ_H13 4 IN CKEC1 CKE# VSSQ_H13 J3 H13 +MVDD J3 H13
+MVDD J11 K2 +MVDD J11 K2 4 IN CKED0 CKE# VSSQ_H13 4 IN CKED1 CKE# VSSQ_H13
4 IN CLKC0b CK# VSSQ_K2 4 IN CLKC1b CK# VSSQ_K2 +MVDD J11 K2 J11 K2
J12 K13 J12 K13 4 IN CLKD0b CK# VSSQ_K2 4 IN CLKD1b CK# VSSQ_K2
4 IN CLKC0 CK VSSQ_K13 4 IN CLKC1 CK VSSQ_K13 4 CLKD0 J12 CK VSSQ_K13 K13 4 CLKD1 J12 CK VSSQ_K13 K13
R2400 M5 M5 IN IN
源 01
60.4R VSSQ_M5 R2500 60.4R VSSQ_M5 R2600 60.4R VSSQ_M5 M5 R2700 60.4R VSSQ_M5 M5
R2401 60.4R VSSQ_M10 M10 R2501 60.4R VSSQ_M10 M10 M10 R2701 M10
G12 N1 G12 N1
R2601 60.4R VSSQ_M10 60.4R VSSQ_M10
4 IN CSC0b_0 CS#__WE# VSSQ_N1 4 IN WEC1b CS#__WE# VSSQ_N1 4 CSD0b_0 G12 CS#__WE# VSSQ_N1 N1 4 WED1b G12 CS#__WE# VSSQ_N1 N1
4 IN WEC0b L12 WE#__CS# VSSQ_N3 N3 4 IN CSC1b_0 L12 WE#__CS# VSSQ_N3 N3 IN L12 N3
IN L12 N3
N12 N12 4 IN WED0b WE#__CS# VSSQ_N3 4 IN CSD1b_0 WE#__CS# VSSQ_N3
VSSQ_N12 VSSQ_N12
)
VSSQ_N12 N12 VSSQ_N12 N12
N14 N14
20
VSSQ_N14 VSSQ_N14 VSSQ_N14 N14 VSSQ_N14 N14
R2402 120R J13 ZQ VSSQ_R1 R1 R2502 120R J13 ZQ VSSQ_R1 R1 J13 R1 J13 R1
J10 R3 J10 R3
R2602 120R ZQ VSSQ_R1 R2702 120R ZQ VSSQ_R1
SEN VSSQ_R3 SEN VSSQ_R3 J10 SEN VSSQ_R3 R3 J10 SEN VSSQ_R3 R3
VSSQ_R4 R4 VSSQ_R4 R4 R4 R4
R11 R11 VSSQ_R4 VSSQ_R4
B VSSQ_R11 VSSQ_R11 B
6
VSSQ_R11 R11 VSSQ_R11 R11
5 2 DRAM_RST2 J2 RESET# VSSQ_R12 R12 5 2 DRAM_RST2 J2 RESET# VSSQ_R12 R12
IN J1 R14
IN J1 R14 5 2 IN DRAM_RST2 J2 RESET# VSSQ_R12 R12 5 2 IN DRAM_RST2 J2 RESET# VSSQ_R12 R12
MF VSSQ_R14 MF VSSQ_R14
05
+MVDD J1 MF VSSQ_R14 R14 J1 MF VSSQ_R14 R14
VSSQ_V1 V1 VSSQ_V1 V1 +MVDD
VSSQ_V1 V1 VSSQ_V1 V1
VSSQ_V3 V3 VSSQ_V3 V3 V3 V3
V12 V12 VSSQ_V3 VSSQ_V3
VSSQ_V12 VSSQ_V12 VSSQ_V12 V12 VSSQ_V12 V12
VSSQ_V14 V14 VSSQ_V14 V14 V14 V14
00
A5 A5 VSSQ_V14 VSSQ_V14
+MVDD R2405 2.37K Vpp_NC +MVDD R2505 2.37K Vpp_NC R2605 2.37K A5 Vpp_NC R2705 2.37K A5 Vpp_NC
R2406 5.49K V5 Vpp_NC1 R2506 V5 Vpp_NC1 +MVDD +MVDD
5.49K
R2606 5.49K V5 Vpp_NC1 R2706 5.49K V5 Vpp_NC1
C2401 1uF VSS_B5 B5 C2501 1uF VSS_B5 B5 B5 B5
A10 B10 A10 B10
C2601 1uF VSS_B5 C2701 1uF VSS_B5
VREFD1 VSS_B10 VREFD1 VSS_B10 A10 B10 A10 B10
1
V10 D10 V10 D10 VREFD1 VSS_B10 VREFD1 VSS_B10
+MVDD R2407 2.37K VREFD2 VSS_D10 +MVDD R2507 2.37K VREFD2 VSS_D10 R2607 V10 VREFD2 VSS_D10 D10 R2707 2.37K V10 VREFD2 VSS_D10 D10
G5 G5 +MVDD 2.37K
+MVDD
R2408 5.49K VSS_G5 R2508 5.49K VSS_G5 R2608 5.49K VSS_G5 G5 R2708 5.49K VSS_G5 G5
C2403 1uF VSS_G10 G10 C2503 1uF VSS_G10 G10 G10 G10
H1 H1
C2603 1uF VSS_G10 C2703 1uF VSS_G10
VSS_H1 VSS_H1 VSS_H1 H1 VSS_H1 H1
+MVDD R2409 2.37K VSS_H14 H14 +MVDD R2509 2.37K VSS_H14 H14 H14 H14
K1 K1 +MVDD
R2609 2.37K VSS_H14 +MVDD R2709 2.37K VSS_H14
R2410 5.49K VSS_K1 R2510 5.49K VSS_K1 R2610 5.49K VSS_K1 K1 R2710 5.49K VSS_K1 K1
C2405 1uF J14 VREFC VSS_K14 K14 C2505 1uF J14 VREFC VSS_K14 K14 J14 K14 J14 K14
L5 L5
C2605 1uF VREFC VSS_K14 C2705 1uF VREFC VSS_K14
VSS_L5 VSS_L5 VSS_L5 L5 VSS_L5 L5
VSS_L10 L10 VSS_L10 L10 L10 L10
P10 P10 VSS_L10 VSS_L10
VSS_P10 VSS_P10 VSS_P10 P10 VSS_P10 P10
4 ADBIC0 J4 ABI# VSS_T5 T5 4 ADBIC1 J4 ABI# VSS_T5 T5
IN T10
IN T10 4 IN ADBID0 J4 ABI# VSS_T5 T5 4 IN ADBID1 J4 ABI# VSS_T5 T5
VSS_T10 VSS_T10 VSS_T10 T10 VSS_T10 T10
+MVDD +MVDD +MVDD

+MVDD
C2510
C2511
C2512
C2513
C2514
C2515
C2516
C2517
C2518
C2519
C2610
C2611
C2612
C2613
C2614
C2615
C2616
C2617
C2618
C2619
C2410
C2411
C2412
C2413
C2414
C2415
C2416
C2417
C2418
C2419
C2710
C2711
C2712
C2713
C2714
C2715
C2716
C2717
C2718
C2719

0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
1 COMMERCE VALLEY
10uF
10uF
10uF
10uF
10uF
10uF
10uF
10uF
+MVDD +MVDD
+MVDD +MVDD
SHEET: MEMORY CH CD schematic and design, including, not limited to, any implied warranty
DATE: Thu Nov 03 14:06:56 2011 REV: 1.0
C2520
C2521
C2522
C2523
C2524
C2525
C2526
C2527
C2528
C2620
C2621
C2622
C2623
C2624
C2625
C2626
C2627
C2628
C2720
C2721
C2722
C2723
C2724
C2725
C2726
C2727
C2728
information included herein.

C2420
C2421
C2422
C2423
C2424
C2425
C2426
C2427
C2428

1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
10uF
10uF
10uF
TITLE
10uF
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(6) TAHITI Memory Channel E&F
U1 U1
7 BI DQE0_<31..0> BANK E DQE1_<31..0>
BI 7 7 BI DQF0_<31..0> BANK F DQF1_<31..0>
BI 7
Part 7 of 20 Part 8 of 20
0 DQE0_<0> AD13 DQE0_0 DQE1_0 AU13 DQE1_<0> 0 0 DQF0_<0> BD21 DQF0_0 DQF1_0 BM18 DQF1_<0> 0
1 DQE0_<1> AJ13 DQE0_1 DQE1_1 AW16 DQE1_<1> 1 1 DQF0_<1> BF18 DQF0_1 DQF1_1 BK20 DQF1_<1> 1
D 2 DQE0_<2> AF13 DQE0_2 DQE1_2 BB11 DQE1_<2> 2 2 DQF0_<2> BE20 DQF0_2 DQF1_2 BN21 DQF1_<2> 2 D
3 DQE0_<3> AJ12 DQE0_3 DQE1_3 AW14 DQE1_<3> 3 3 DQF0_<3> BF15 DQF0_3 DQF1_3 BM21 DQF1_<3> 3
4 DQE0_<4> AK13 DQE0_4 DQE1_4 BB13 DQE1_<4> 4 4 DQF0_<4> BC15 DQF0_4 DQF1_4 BN18 DQF1_<4> 4
5 DQE0_<5> AF12 DQE0_5 DQE1_5 AY13 DQE1_<5> 5 5 DQF0_<5> BD17 DQF0_5 DQF1_5 BN23 DQF1_<5> 5
6 DQE0_<6> AC13 DQE0_6 DQE1_6 BC12 DQE1_<6> 6 6 DQF0_<6> BE21 DQF0_6 DQF1_6 BK18 DQF1_<6> 6
7 DQE0_<7> AG11 DQE0_7 DQE1_7 AU15 DQE1_<7> 7 7 DQF0_<7> BG15 DQF0_7 DQF1_7 BK21 DQF1_<7> 7
8 DQE0_<8> AT11 DQE0_8 DQE1_8 BH10 DQE1_<8> 8 8 DQF0_<8> BF12 DQF0_8 DQF1_8 BJ30 DQF1_<8> 8
9 DQE0_<9> AU10 DQE0_9 DQE1_9 BJ8 DQE1_<9> 9 9 DQF0_<9> BK9 DQF0_9 DQF1_9 BJ27 DQF1_<9> 9
10 DQE0_<10> AP13 DQE0_10 DQE1_10 BJ7 DQE1_<10> 10 10 DQF0_<10> BB16 DQF0_10 DQF1_10 BH26 DQF1_<10> 10
11 DQE0_<11> AP12 DQE0_11 DQE1_11 BE10 DQE1_<11> 11 11 DQF0_<11> BK7 DQF0_11 DQF1_11 BF30 DQF1_<11> 11
12 DQE0_<12> AT13 DQE0_12 DQE1_12 BE8 DQE1_<12> 12 12 DQF0_<12> BB14 DQF0_12 DQF1_12 BG27 DQF1_<12> 12
13 DQE0_<13> AW8 DQE0_13 DQE1_13 BF9 DQE1_<13> 13 13 DQF0_<13> BE11 DQF0_13 DQF1_13 BE29 DQF1_<13> 13
14 DQE0_<14> AW7 DQE0_14 DQE1_14 BF7 DQE1_<14> 14 14 DQF0_<14> BC13 DQF0_14 DQF1_14 BG26 DQF1_<14> 14
15 DQE0_<15> AU12 DQE0_15 DQE1_15 BH9 DQE1_<15> 15 15 DQF0_<15> BL10 DQF0_15 DQF1_15 BG30 DQF1_<15> 15
16 DQE0_<16> AJ15 DQE0_16 DQE1_16 BK3 DQE1_<16> 16 16 DQF0_<16> BK12 DQF0_16 DQF1_16 BW26 DQF1_<16> 16
17 DQE0_<17> AP16 DQE0_17 DQE1_17 BL5 DQE1_<17> 17 17 DQF0_<17> BG20 DQF0_17 DQF1_17 BT29 DQF1_<17> 17
18 DQE0_<18> AK14 DQE0_18 DQE1_18 BN5 DQE1_<18> 18 18 DQF0_<18> BK14 DQF0_18 DQF1_18 BR25 DQF1_<18> 18
19 DQE0_<19> AN14 DQE0_19 DQE1_19 BP1 DQE1_<19> 19 19 DQF0_<19> BJ18 DQF0_19 DQF1_19 BW30 DQF1_<19> 19
AK16 BN4 BJ15 BR27
00
20 DQE0_<20> DQE0_20 DQE1_20 DQE1_<20> 20 20 DQF0_<20> DQF0_20 DQF1_20 DQF1_<20> 20
21 DQE0_<21> AN16 DQE0_21 DQE1_21 BM3 DQE1_<21> 21 21 DQF0_<21> BH17 DQF0_21 DQF1_21 BR29 DQF1_<21> 21
22 DQE0_<22> AJ16 DQE0_22 DQE1_22 BK1 DQE1_<22> 22 22 DQF0_<22> BH14 DQF0_22 DQF1_22 BU26 DQF1_<22> 22
23 DQE0_<23> AL13 DQE0_23 DQE1_23 BJ4 DQE1_<23> 23 23 DQF0_<23> BG18 DQF0_23 DQF1_23 BU28 DQF1_<23> 23
AW10 DQE0_24 DQE1_24 BN15 BE23 DQF0_24 DQF1_24 BN24
07
24 DQE0_<24> DQE1_<24> 24 24 DQF0_<24> DQF1_<24> 24
25 DQE0_<25> AY12 DQE0_25 DQE1_25 BL17 DQE1_<25> 25 25 DQF0_<25> BD29 DQF0_25 DQF1_25 BM27 DQF1_<25> 25
26 DQE0_<26> BB7 DQE0_26 DQE1_26 BN12 DQE1_<26> 26 26 DQF0_<26> BD26 DQF0_26 DQF1_26 BM24 DQF1_<26> 26
27 DQE0_<27> BB10 DQE0_27 DQE1_27 BL14 DQE1_<27> 27 27 DQF0_<27> BG24 DQF0_27 DQF1_27 BL29 DQF1_<27> 27
28 DQE0_<28> BB8 DQE0_28 DQE1_28 BN11 DQE1_<28> 28 28 DQF0_<28> BF27 DQF0_28 DQF1_28 BL26 DQF1_<28> 28
74
AW11 DQE0_29 DQE1_29 BN17 BH23 DQF0_29 DQF1_29 BK29
M
29 DQE0_<29> DQE1_<29> 29 29 DQF0_<29> DQF1_<29> 29
30 DQE0_<30> AY10 DQE0_30 DQE1_30 BL12 DQE1_<30> 30 30 DQF0_<30> BF24 DQF0_30 DQF1_30 BK26 DQF1_<30> 30
31 DQE0_<31> AW13 DQE0_31 DQE1_31 BK17 DQE1_<31> 31 31 DQF0_<31> BD27 DQF0_31 DQF1_31 BN27 DQF1_<31> 31
65 SI　
7 MAE0_<8..0> MAE1_<8..0> 7 7 MAF0_<8..0> MAF1_<8..0> 7
IN AR4 BC5
IN IN BU10 BT17
IN
0 MAE0_<0> MAE0_0 MAE1_0 MAE1_<0> 0 0 MAF0_<0> MAF0_0 MAF1_0 MAF1_<0> 0
1 MAE0_<1> AR5 MAE0_1 MAE1_1 BC4 MAE1_<1> 1 1 MAF0_<1> BT9 MAF0_1 MAF1_1 BU18 MAF1_<1> 1
2 MAE0_<2> AP3 MAE0_2 MAE1_2 BD1 MAE1_<2> 2 2 MAF0_<2> BW8 MAF0_2 MAF1_2 BR19 MAF1_<2> 2
3 MAE0_<3> AP1 MAE0_3 MAE1_3 BD3 MAE1_<3> 3 3 MAF0_<3> BR9 MAF0_3 MAF1_3 BW18 MAF1_<3> 3
　
4 MAE0_<4> AN5 MAE0_4 MAE1_4 BE4 MAE1_<4> 4 4 MAF0_<4> BT7 MAF0_4 MAF1_4 BU20 MAF1_<4> 4
C 5 MAE0_<5> AN4 MAE0_5 MAE1_5 BE5 MAE1_<5> 5 5 MAF0_<5> BU8 MAF0_5 MAF1_5 BT19 MAF1_<5> 5 C
6 MAE0_<6> AU5 MAE0_6 MAE1_6 BA4 MAE1_<6> 6 6 MAF0_<6> BT11 MAF0_6 MAF1_6 BU16 MAF1_<6> 6
張 CON
7 MAE0_<7> AT1 MAE0_7 MAE1_7 BB3 MAE1_<7> 7 7 MAF0_<7> BR11 MAF0_7 MAF1_7 BW16 MAF1_<7> 7
8 MAE0_<8> AT3 MAE0_8 MAE1_8 BB1 MAE1_<8> 8 8 MAF0_<8> BW10 MAF0_8 MAF1_8 BR17 MAF1_<8> 8
AL5 MAE0_9 MAE1_9 BG5 BR6 MAF0_9 MAF1_9 BU22
7 WCKE0_0 AN11 WCKE0_0 WCKE1_0 BC10 WCKE1_0 7 7 WCKF0_0 BL8 WCKF0_0 WCKF1_0 BL23 WCKF1_0 7
OUT OUT OUT OUT
文
7 WCKE0b_0 AN10 WCKE0B_0 WCKE1B_0 BC9 WCKE1b_0 7 7 WCKF0b_0 BM7 WCKF0B_0 WCKF1B_0 BK24 WCKF1b_0 7
OUT OUT OUT OUT
F
7 WCKE0_1 AT15 WCKE0_1 WCKE1_1 BN9 WCKE1_1 7 7 WCKF0_1 BG21 WCKF0_1 WCKF1_1 BU24 WCKF1_1 7
OUT OUT OUT OUT
RM 　 ID
7 WCKE0b_1 AT16 WCKE0B_1 WCKE1B_1 BN10 WCKE1b_1 7 7 WCKF0b_1 BH21 WCKF0B_1 WCKF1B_1 BW24 WCKF1b_1 7
OUT OUT OUT OUT
7 EDCE0_0 AG13 EDCE0_0 EDCE1_0 AY16 EDCE1_0 7 7 EDCF0_0 BE17 EDCF0_0 EDCF1_0 BN20 EDCF1_0 7
IN AU7 BF10
IN IN BE14 BH29
IN
7 IN EDCE0_1 EDCE0_1 EDCE1_1 EDCE1_1
IN 7 7 IN EDCF0_1 EDCF0_1 EDCF1_1 EDCF1_1
IN 7
A( RD EN
7 EDCE0_2 AL15 EDCE0_2 EDCE1_2 BL4 EDCE1_2 7 7 EDCF0_2 BG17 EDCF0_2 EDCF1_2 BT27 EDCF1_2 7
IN AY7 BN14
IN IN BD24 BN26
IN
7 IN EDCE0_3 EDCE0_3 EDCE1_3 EDCE1_3
IN 7 7 IN EDCF0_3 EDCF0_3 EDCF1_3 EDCF1_3
IN 7
7 DDBIE0_0 AG14 DDBIE0_0 DDBIE1_0 AY15 DDBIE1_0 7 7 DDBIF0_0 BD18 DDBIF0_0 DDBIF1_0 BL20 DDBIF1_0 7
BI BI BI BI
吳 (C TI
7 DDBIE0_1 AU9 DDBIE0_1 DDBIE1_1 BH7 DDBIE1_1 7 7 DDBIF0_1 BE13 DDBIF0_1 DDBIF1_1 BG29 DDBIF1_1 7
BI AL16 BM1
BI BI BK15 BW28
BI
7 BI DDBIE0_2 DDBIE0_2 DDBIE1_2 DDBIE1_2
BI 7 7 BI DDBIF0_2 DDBIF0_2 DDBIF1_2 DDBIF1_2
BI 7
7 DDBIE0_3 AY9 DDBIE0_3 DDBIE1_3 BM15 DDBIE1_3 7 7 DDBIF0_3 BE26 DDBIF0_3 DDBIF1_3 BK27 DDBIF1_3 7
BI BI BI BI
積 )2 AL
AL12 WCDRE0_0 WCDRE1_0 BC7 BM9 WCDRF0_0 WCDRF1_0 BK23
AN13 WCDRE0_1 WCDRE1_1 BE7 BL7 WCDRF0_1 WCDRF1_1 BJ24
AP15 WCDRE0_2 WCDRE1_2 BN8 BH20 WCDRF0_2 WCDRF1_2 BT25
AU16 WCDRE0_3 WCDRE1_3 BM11 BG23 WCDRF0_3 WCDRF1_3 BT23
源 01
7 ADBIE0 AV3 ADBIE0 ADBIE1 AY1 ADBIE1 7 7 ADBIF0 BW12 ADBIF0 ADBIF1 BR15 ADBIF1 7
OUT OUT OUT OUT
7 CSE0b_0 AK1 CSE0B_0 CSE1B_0 BH1 CSE1b_0 7 7 CSF0b_0 BR3 CSF0B_0 CSF1B_0 BW22 CSF1b_0 7
OUT AK3 BH3
OUT OUT BP5 BR23
OUT
CSE0B_1 CSE1B_1 CSF0B_1 CSF1B_1
B
7
7
7
OUT
OUT
OUT
CASE0b
RASE0b
WEE0b
AU4
AW5
AM1
CASE0B
RASE0B
WEE0B
CASE1B
RASE1B
WEE1B
BA5
AW4
BF3
CASE1b
RASE1b
WEE1b
OUT
OUT
OUT
7
7
7
) 20
7
7
7
OUT
OUT
OUT
CASF0b
RASF0b
WEF0b
BU12
BT13
BR7
CASF0B
RASF0B
WEF0B
CASF1B
RASF1B
WEF1B
BT15
BU14
BW20
CASF1b
RASF1b
WEF1b
OUT
OUT
OUT
7
7
7
B
6
AV1 AY3 +MVDD BR13 BW14 +MVDD
7 OUT CKEE0 CKEE0 CKEE1 CKEE1
OUT 7 7 OUT CKEF0 CKEF0 CKEF1 CKEF1
OUT 7
05
7 CLKE0 AM3 CLKE0 CLKE1 BG4 CLKE1 7 7 CLKF0 BW6 CLKF0 CLKF1 BT21 CLKF1 7
OUT AL4 BF1
OUT OUT BU5 BR21
OUT
7 OUT CLKE0b CLKE0B CLKE1B CLKE1b
OUT 7 7 OUT CLKF0b CLKF0B CLKF1B CLKF1b
OUT 7
R3641 R3651
40.2R 40.2R
00
MVREFDE AP18 MVREFD_E MVREFDF BB23 MVREFD_F
R3642 +MVDD R3652 +MVDD

C3642 100R C3652 100R
1
1uF 1uF
MVREFD/S =0.7* DNI MVREFD/S =0.7* DNI
R3643 R3653
40.2R 40.2R
MVREFSE AT18 MVREFS_E MVREFSF BB24
R3644 R3654
C3644 100R C3654 100R
1uF 1uF
DNI DNI
Tahiti Tahiti

SHEET: TAHITI_MEM EF schematic and design, including, not limited to, any implied warranty

TITLE
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(7) GDDR5 Memory Channel E&F

U2900 U3000 6 DQF1_<31..0> U3100
6 BI DQE0_<31..0> U2800 PATH=I424
6 BI DQE1_<31..0> PATH=I468
6 BI DQF0_<31..0> PATH=I269 BI PATH=I301
14 DQE0_<14> M2 DQ31__DQ7 VDDQ_B1 B1 4 DQE1_<4> M2 DQ31__DQ7 VDDQ_B1 B1 31 DQF0_<31> M2 DQ31__DQ7 VDDQ_B1 B1 3 DQF1_<3> M2 DQ31__DQ7 VDDQ_B1 B1
13 DQE0_<13> M4 DQ30__DQ6 VDDQ_B3 B3 6 DQE1_<6> M4 DQ30__DQ6 VDDQ_B3 B3 25 DQF0_<25> M4 DQ30__DQ6 VDDQ_B3 B3 7 DQF1_<7> M4 DQ30__DQ6 VDDQ_B3 B3
9 DQE0_<9> N2 DQ29__DQ5 VDDQ_B12 B12 5 DQE1_<5> N2 DQ29__DQ5 VDDQ_B12 B12 26 DQF0_<26> N2 DQ29__DQ5 VDDQ_B12 B12 2 DQF1_<2> N2 DQ29__DQ5 VDDQ_B12 B12
15 DQE0_<15> N4 DQ28__DQ4 VDDQ_B14 B14 2 DQE1_<2> N4 DQ28__DQ4 VDDQ_B14 B14 28 DQF0_<28> N4 DQ28__DQ4 VDDQ_B14 B14 5 DQF1_<5> N4 DQ28__DQ4 VDDQ_B14 B14
8 DQE0_<8> T2 DQ27__DQ3 VDDQ_D1 D1 3 DQE1_<3> T2 DQ27__DQ3 VDDQ_D1 D1 30 DQF0_<30> T2 DQ27__DQ3 VDDQ_D1 D1 6 DQF1_<6> T2 DQ27__DQ3 VDDQ_D1 D1
11 DQE0_<11> T4 DQ26__DQ2 VDDQ_D3 D3 1 DQE1_<1> T4 DQ26__DQ2 VDDQ_D3 D3 24 DQF0_<24> T4 DQ26__DQ2 VDDQ_D3 D3 1 DQF1_<1> T4 DQ26__DQ2 VDDQ_D3 D3
12 DQE0_<12> V2 DQ25__DQ1 VDDQ_D12 D12 0 DQE1_<0> V2 DQ25__DQ1 VDDQ_D12 D12 27 DQF0_<27> V2 DQ25__DQ1 VDDQ_D12 D12 4 DQF1_<4> V2 DQ25__DQ1 VDDQ_D12 D12
10 DQE0_<10> V4 DQ24__DQ0 VDDQ_D14 D14 7 DQE1_<7> V4 DQ24__DQ0 VDDQ_D14 D14 29 DQF0_<29> V4 DQ24__DQ0 VDDQ_D14 D14 0 DQF1_<0> V4 DQ24__DQ0 VDDQ_D14 D14
0 DQE0_<0> M13 DQ23__DQ15 VDDQ_E5 E5 10 DQE1_<10> M13 DQ23__DQ15 VDDQ_E5 E5 22 DQF0_<22> M13 DQ23__DQ15 VDDQ_E5 E5 15 DQF1_<15> M13 DQ23__DQ15 VDDQ_E5 E5
6 DQE0_<6> M11 DQ22__DQ14 VDDQ_E10 E10 13 DQE1_<13> M11 DQ22__DQ14 VDDQ_E10 E10 16 DQF0_<16> M11 DQ22__DQ14 VDDQ_E10 E10 9 DQF1_<9> M11 DQ22__DQ14 VDDQ_E10 E10
2 DQE0_<2> N13 DQ21__DQ13 VDDQ_F1 F1 9 DQE1_<9> N13 DQ21__DQ13 VDDQ_F1 F1 18 DQF0_<18> N13 DQ21__DQ13 VDDQ_F1 F1 8 DQF1_<8> N13 DQ21__DQ13 VDDQ_F1 F1
5 DQE0_<5> N11 DQ20__DQ12 VDDQ_F3 F3 14 DQE1_<14> N11 DQ20__DQ12 VDDQ_F3 F3 20 DQF0_<20> N11 DQ20__DQ12 VDDQ_F3 F3 12 DQF1_<12> N11 DQ20__DQ12 VDDQ_F3 F3
D 1 DQE0_<1> T13
T11
F14
15 DQE1_<15> T13
T11
F14
23 DQF0_<23> T13
T11
F14
11 DQF1_<11> T13
T11
F14
D
3 DQE0_<3> DQ18__DQ10 VDDQ_F14 11 DQE1_<11> DQ18__DQ10 VDDQ_F14 17 DQF0_<17> DQ18__DQ10 VDDQ_F14 10 DQF1_<10> DQ18__DQ10 VDDQ_F14
7 DQE0_<7> V13 DQ17__DQ9 VDDQ_G2 G2 8 DQE1_<8> V13 DQ17__DQ9 VDDQ_G2 G2 21 DQF0_<21> V13 DQ17__DQ9 VDDQ_G2 G2 13 DQF1_<13> V13 DQ17__DQ9 VDDQ_G2 G2
4 DQE0_<4> V11 DQ16__DQ8 VDDQ_G13 G13 12 DQE1_<12> V11 DQ16__DQ8 VDDQ_G13 G13 19 DQF0_<19> V11 DQ16__DQ8 VDDQ_G13 G13 14 DQF1_<14> V11 DQ16__DQ8 VDDQ_G13 G13
20 DQE0_<20> F13 DQ15__DQ23 VDDQ_H3 H3 25 DQE1_<25> F13 DQ15__DQ23 VDDQ_H3 H3 13 DQF0_<13> F13 DQ15__DQ23 VDDQ_H3 H3 19 DQF1_<19> F13 DQ15__DQ23 VDDQ_H3 H3
23 DQE0_<23> F11 DQ14__DQ22 VDDQ_H12 H12 29 DQE1_<29> F11 DQ14__DQ22 VDDQ_H12 H12 8 DQF0_<8> F11 DQ14__DQ22 VDDQ_H12 H12 21 DQF1_<21> F11 DQ14__DQ22 VDDQ_H12 H12
18 DQE0_<18> E13 DQ13__DQ21 VDDQ_K3 K3 31 DQE1_<31> E13 DQ13__DQ21 VDDQ_K3 K3 14 DQF0_<14> E13 DQ13__DQ21 VDDQ_K3 K3 17 DQF1_<17> E13 DQ13__DQ21 VDDQ_K3 K3
21 DQE0_<21> E11 DQ12__DQ20 VDDQ_K12 K12 24 DQE1_<24> E11 DQ12__DQ20 VDDQ_K12 K12 9 DQF0_<9> E11 DQ12__DQ20 VDDQ_K12 K12 23 DQF1_<23> E11 DQ12__DQ20 VDDQ_K12 K12
16 DQE0_<16> B13 DQ11__DQ19 VDDQ_L2 L2 26 DQE1_<26> B13 DQ11__DQ19 VDDQ_L2 L2 10 DQF0_<10> B13 DQ11__DQ19 VDDQ_L2 L2 20 DQF1_<20> B13 DQ11__DQ19 VDDQ_L2 L2
19 DQE0_<19> B11 DQ10__DQ18 VDDQ_L13 L13 28 DQE1_<28> B11 DQ10__DQ18 VDDQ_L13 L13 11 DQF0_<11> B11 DQ10__DQ18 VDDQ_L13 L13 22 DQF1_<22> B11 DQ10__DQ18 VDDQ_L13 L13
22 DQE0_<22> A13 DQ9__DQ17 VDDQ_M1 M1 27 DQE1_<27> A13 DQ9__DQ17 VDDQ_M1 M1 12 DQF0_<12> A13 DQ9__DQ17 VDDQ_M1 M1 18 DQF1_<18> A13 DQ9__DQ17 VDDQ_M1 M1
17 DQE0_<17> A11 DQ8__DQ16 VDDQ_M3 M3 30 DQE1_<30> A11 DQ8__DQ16 VDDQ_M3 M3 15 DQF0_<15> A11 DQ8__DQ16 VDDQ_M3 M3 16 DQF1_<16> A11 DQ8__DQ16 VDDQ_M3 M3
25 DQE0_<25> F2 DQ7__DQ31 VDDQ_M12 M12 23 DQE1_<23> F2 DQ7__DQ31 VDDQ_M12 M12 1 DQF0_<1> F2 DQ7__DQ31 VDDQ_M12 M12 28 DQF1_<28> F2 DQ7__DQ31 VDDQ_M12 M12
30 DQE0_<30> F4 DQ6__DQ30 VDDQ_M14 M14 16 DQE1_<16> F4 DQ6__DQ30 VDDQ_M14 M14 5 DQF0_<5> F4 DQ6__DQ30 VDDQ_M14 M14 30 DQF1_<30> F4 DQ6__DQ30 VDDQ_M14 M14
26 DQE0_<26> E2 DQ5__DQ29 VDDQ_N5 N5 17 DQE1_<17> E2 DQ5__DQ29 VDDQ_N5 N5 2 DQF0_<2> E2 DQ5__DQ29 VDDQ_N5 N5 26 DQF1_<26> E2 DQ5__DQ29 VDDQ_N5 N5
24 DQE0_<24> E4 DQ4__DQ28 VDDQ_N10 N10 22 DQE1_<22> E4 DQ4__DQ28 VDDQ_N10 N10 7 DQF0_<7> E4 DQ4__DQ28 VDDQ_N10 N10 24 DQF1_<24> E4 DQ4__DQ28 VDDQ_N10 N10
28 DQE0_<28> B2 DQ3__DQ27 VDDQ_P1 P1 19 DQE1_<19> B2 DQ3__DQ27 VDDQ_P1 P1 0 DQF0_<0> B2 DQ3__DQ27 VDDQ_P1 P1 31 DQF1_<31> B2 DQ3__DQ27 VDDQ_P1 P1
31 DQE0_<31> B4 DQ2__DQ26 VDDQ_P3 P3 18 DQE1_<18> B4 DQ2__DQ26 VDDQ_P3 P3 4 DQF0_<4> B4 DQ2__DQ26 VDDQ_P3 P3 27 DQF1_<27> B4 DQ2__DQ26 VDDQ_P3 P3
27 DQE0_<27> A2 DQ1__DQ25 VDDQ_P12 P12 20 DQE1_<20> A2 DQ1__DQ25 VDDQ_P12 P12 6 DQF0_<6> A2 DQ1__DQ25 VDDQ_P12 P12 25 DQF1_<25> A2 DQ1__DQ25 VDDQ_P12 P12
00
29 DQE0_<29> A4 DQ0__DQ24 VDDQ_P14 P14 21 DQE1_<21> A4 DQ0__DQ24 VDDQ_P14 P14 3 DQF0_<3> A4 DQ0__DQ24 VDDQ_P14 P14 29 DQF1_<29> A4 DQ0__DQ24 VDDQ_P14 P14
07
6 MAE0_<8..0> +MVDD 6 MAE1_<8..0> +MVDD +MVDD 6 MAF1_<8..0> +MVDD
IN J5
IN J5 J5
IN J5
8 MAE0_<8> RFU_A12_NC 8 MAE1_<8> RFU_A12_NC 6 IN MAF0_<8..0> 8 MAF0_<8> RFU_A12_NC 8 MAF1_<8> RFU_A12_NC
7 MAE0_<7> K4 A7_A8__A0_A10 VDD_C5 C5 0 MAE1_<0> K4 A7_A8__A0_A10 VDD_C5 C5 7 MAF0_<7> K4 A7_A8__A0_A10 VDD_C5 C5 0 MAF1_<0> K4 A7_A8__A0_A10 VDD_C5 C5
74
6 MAE0_<6> K5 A6_A11__A1_A9 VDD_C10 C10 1 MAE1_<1> K5 A6_A11__A1_A9 VDD_C10 C10 6 MAF0_<6> K5 A6_A11__A1_A9 VDD_C10 C10 1 MAF1_<1> K5 A6_A11__A1_A9 VDD_C10 C10
M
5 MAE0_<5> K10 A5_BA1__A3_BA3 VDD_D11 D11 3 MAE1_<3> K10 A5_BA1__A3_BA3 VDD_D11 D11 5 MAF0_<5> K10 A5_BA1__A3_BA3 VDD_D11 D11 3 MAF1_<3> K10 A5_BA1__A3_BA3 VDD_D11 D11
4 MAE0_<4> K11 A4_BA2__A2_BA0 VDD_G1 G1 2 MAE1_<2> K11 A4_BA2__A2_BA0 VDD_G1 G1 4 MAF0_<4> K11 A4_BA2__A2_BA0 VDD_G1 G1 2 MAF1_<2> K11 A4_BA2__A2_BA0 VDD_G1 G1
65 SI　
3 MAE0_<3> H10 A3_BA3__A5_BA1 VDD_G4 G4 5 MAE1_<5> H10 A3_BA3__A5_BA1 VDD_G4 G4 3 MAF0_<3> H10 A3_BA3__A5_BA1 VDD_G4 G4 5 MAF1_<5> H10 A3_BA3__A5_BA1 VDD_G4 G4
2 MAE0_<2> H11 A2_BA0__A4_BA2 VDD_G11 G11 4 MAE1_<4> H11 A2_BA0__A4_BA2 VDD_G11 G11 2 MAF0_<2> H11 A2_BA0__A4_BA2 VDD_G11 G11 4 MAF1_<4> H11 A2_BA0__A4_BA2 VDD_G11 G11
1 MAE0_<1> H5 A1_A9__A6_A11 VDD_G14 G14 6 MAE1_<6> H5 A1_A9__A6_A11 VDD_G14 G14 1 MAF0_<1> H5 A1_A9__A6_A11 VDD_G14 G14 6 MAF1_<6> H5 A1_A9__A6_A11 VDD_G14 G14
0 MAE0_<0> H4 A0_A10__A7_A8 VDD_L1 L1 7 MAE1_<7> H4 A0_A10__A7_A8 VDD_L1 L1 0 MAF0_<0> H4 A0_A10__A7_A8 VDD_L1 L1 7 MAF1_<7> H4 A0_A10__A7_A8 VDD_L1 L1
VDD_L4 L4 VDD_L4 L4 VDD_L4 L4 VDD_L4 L4
L11 L11 L11 L11
　
C D4
VDD_L14 L14
P11 D4
VDD_L14 L14
P11 D4
VDD_L14 L14
P11 D4
VDD_L14 L14
P11
C
6 IN WCKE0_1 WCK01__WCK23 VDD_P11 6 IN WCKE1_1 WCK01__WCK23 VDD_P11 6 IN WCKF0_0 WCK01__WCK23 VDD_P11 6 IN WCKF1_1 WCK01__WCK23 VDD_P11
張 CON
6 WCKE0b_1 D5 WCK01#__WCK23# VDD_R5 R5 6 WCKE1b_1 D5 WCK01#__WCK23# VDD_R5 R5 6 WCKF0b_0 D5 WCK01#__WCK23# VDD_R5 R5 6 WCKF1b_1 D5 WCK01#__WCK23# VDD_R5 R5
IN R10
IN R10
IN R10
IN R10
VDD_R10 VDD_R10 VDD_R10 VDD_R10
6 WCKE0_0 P4 WCK23__WCK01 6 WCKE1_0 P4 WCK23__WCK01 6 WCKF0_1 P4 WCK23__WCK01 6 WCKF1_0 P4 WCK23__WCK01
IN P5
IN P5
IN P5
IN P5
6 IN WCKE0b_0 WCK23#__WCK01# 6 IN WCKE1b_0 WCK23#__WCK01# 6 IN WCKF0b_1 WCK23#__WCK01# 6 IN WCKF1b_0 WCK23#__WCK01#
VSSQ_A1 A1 VSSQ_A1 A1 VSSQ_A1 A1 VSSQ_A1 A1
EDCE0_1 R2 EDC3__EDC0 VSSQ_A3 A3 EDCE1_0 R2 EDC3__EDC0 VSSQ_A3 A3 EDCF0_3 R2 EDC3__EDC0 VSSQ_A3 A3 EDCF1_0 R2 EDC3__EDC0 VSSQ_A3 A3
文
6 OUT 6 OUT 6 OUT 6 OUT
R13 A12 R13 A12 R13 A12 R13 A12
F
6 OUT EDCE0_0 EDC2__EDC1 VSSQ_A12 6 OUT EDCE1_1 EDC2__EDC1 VSSQ_A12 6 OUT EDCF0_2 EDC2__EDC1 VSSQ_A12 6 OUT EDCF1_1 EDC2__EDC1 VSSQ_A12
6 EDCE0_2 C13 EDC1__EDC2 VSSQ_A14 A14 6 EDCE1_3 C13 EDC1__EDC2 VSSQ_A14 A14 6 EDCF0_1 C13 EDC1__EDC2 VSSQ_A14 A14 6 EDCF1_2 C13 EDC1__EDC2 VSSQ_A14 A14
OUT C2 C1
OUT C2 C1
OUT C2 C1
OUT C2 C1
RM 　 ID
6 OUT EDCE0_3 EDC0__EDC3 VSSQ_C1 6 OUT EDCE1_2 EDC0__EDC3 VSSQ_C1 6 OUT EDCF0_0 EDC0__EDC3 VSSQ_C1 6 OUT EDCF1_3 EDC0__EDC3 VSSQ_C1
VSSQ_C3 C3 VSSQ_C3 C3 VSSQ_C3 C3 VSSQ_C3 C3
6 DDBIE0_1 P2 DBI3#__DBI0# VSSQ_C4 C4 6 DDBIE1_0 P2 DBI3#__DBI0# VSSQ_C4 C4 6 DDBIF0_3 P2 DBI3#__DBI0# VSSQ_C4 C4 6 DDBIF1_0 P2 DBI3#__DBI0# VSSQ_C4 C4
BI P13 C11
BI P13 C11
BI P13 C11
BI P13 C11
6 BI DDBIE0_0 DBI2#__DBI1# VSSQ_C11 6 BI DDBIE1_1 DBI2#__DBI1# VSSQ_C11 6 BI DDBIF0_2 DBI2#__DBI1# VSSQ_C11 6 BI DDBIF1_1 DBI2#__DBI1# VSSQ_C11
6 DDBIE0_2 D13 DBI1#__DBI2# VSSQ_C12 C12 6 DDBIE1_3 D13 DBI1#__DBI2# VSSQ_C12 C12 6 DDBIF0_1 D13 DBI1#__DBI2# VSSQ_C12 C12 6 DDBIF1_2 D13 DBI1#__DBI2# VSSQ_C12 C12
A( RD EN
BI D2 C14
BI D2 C14
BI D2 C14
BI D2 C14
6 BI DDBIE0_3 DBI0#__DBI3# VSSQ_C14 6 BI DDBIE1_2 DBI0#__DBI3# VSSQ_C14 6 BI DDBIF0_0 DBI0#__DBI3# VSSQ_C14 6 BI DDBIF1_3 DBI0#__DBI3# VSSQ_C14
吳 (C TI
6 RASE0b G3 RAS#__CAS# VSSQ_E14 E14 6 CASE1b G3 RAS#__CAS# VSSQ_E14 E14 6 RASF0b G3 RAS#__CAS# VSSQ_E14 E14 6 CASF1b G3 RAS#__CAS# VSSQ_E14 E14
IN L3 F5
IN L3 F5
IN L3 F5
IN L3 F5
6 IN CASE0b CAS#__RAS# VSSQ_F5 6 IN RASE1b CAS#__RAS# VSSQ_F5 6 IN CASF0b CAS#__RAS# VSSQ_F5 6 IN RASF1b CAS#__RAS# VSSQ_F5
VSSQ_F10 F10 VSSQ_F10 F10 VSSQ_F10 F10 VSSQ_F10 F10
VSSQ_H2 H2 VSSQ_H2 H2 VSSQ_H2 H2 VSSQ_H2 H2
積 )2 AL
6 CKEE0 J3 CKE# VSSQ_H13 H13 6 CKEE1 J3 CKE# VSSQ_H13 H13 6 CKEF0 J3 CKE# VSSQ_H13 H13 6 CKEF1 J3 CKE# VSSQ_H13 H13
IN J11 K2 +MVDD IN J11 K2 +MVDD IN J11 K2 +MVDD IN J11 K2
+MVDD 6 IN CLKE0b CK# VSSQ_K2 6 IN CLKE1b CK# VSSQ_K2 6 IN CLKF0b CK# VSSQ_K2 6 IN CLKF1b CK# VSSQ_K2
6 CLKE0 J12 CK VSSQ_K13 K13 6 CLKE1 J12 CK VSSQ_K13 K13 6 CLKF0 J12 CK VSSQ_K13 K13 6 CLKF1 J12 CK VSSQ_K13 K13
IN M5
IN M5
IN M5
IN M5
R2800 60.4R VSSQ_M5 R2900 60.4R VSSQ_M5 R3000 60.4R VSSQ_M5 R3100 60.4R VSSQ_M5
源 01
R2801 60.4R VSSQ_M10 M10 R2901 60.4R VSSQ_M10 M10 R3001 60.4R VSSQ_M10 M10 R3101 60.4R VSSQ_M10 M10
6 CSE0b_0 G12 CS#__WE# VSSQ_N1 N1 6 WEE1b G12 CS#__WE# VSSQ_N1 N1 6 CSF0b_0 G12 CS#__WE# VSSQ_N1 N1 6 WEF1b G12 CS#__WE# VSSQ_N1 N1
IN L12 N3
IN L12 N3
IN L12 N3
IN L12 N3
6 IN WEE0b WE#__CS# VSSQ_N3 6 IN CSE1b_0 WE#__CS# VSSQ_N3 6 IN WEF0b WE#__CS# VSSQ_N3 6 IN CSF1b_0 WE#__CS# VSSQ_N3
)
20
R2802
120R J13 ZQ VSSQ_R1 R1 R2902 120R J13 ZQ VSSQ_R1 R1 R3002 120R J13 ZQ VSSQ_R1 R1 R3102 120R J13 ZQ VSSQ_R1 R1
J10 SEN VSSQ_R3 R3 J10 SEN VSSQ_R3 R3 J10 SEN VSSQ_R3 R3 J10 SEN VSSQ_R3 R3
B B
6
7 2 DRAM_RST3 J2 RESET# VSSQ_R12 R12 7 2 DRAM_RST3 J2 RESET# VSSQ_R12 R12 7 2 DRAM_RST3 J2 RESET# VSSQ_R12 R12 7 2 DRAM_RST3 J2 RESET# VSSQ_R12 R12
IN J1 R14
IN J1 R14
IN J1 R14
IN J1 R14
MF VSSQ_R14 +MVDD MF VSSQ_R14 MF VSSQ_R14 +MVDD MF VSSQ_R14
V1 V1 V1 V1
05
VSSQ_V1 VSSQ_V1 VSSQ_V1 VSSQ_V1
A5 A5 A5 A5
00
+MVDD R2805 2.37K Vpp_NC +MVDD
R2905 2.37K Vpp_NC +MVDD R3005 2.37K Vpp_NC +MVDD R3105 2.37K Vpp_NC
R2806 5.49K V5 Vpp_NC1 R2906 5.49K V5 Vpp_NC1 R3006 5.49K V5 Vpp_NC1 R3106 5.49K V5 Vpp_NC1
C2801 1uF VSS_B5 B5 C2901 1uF VSS_B5 B5 C3001 1uF VSS_B5 B5 C3101 1uF VSS_B5 B5
A10 VREFD1 VSS_B10 B10 A10 VREFD1 VSS_B10 B10 A10 VREFD1 VSS_B10 B10 A10 VREFD1 VSS_B10 B10
V10 VREFD2 VSS_D10 D10 V10 VREFD2 VSS_D10 D10 V10 VREFD2 VSS_D10 D10 V10 VREFD2 VSS_D10 D10
1
2.37K R2907 2.37K +MVDD R3007 2.37K R3107 2.37K
+MVDD R2807 +MVDD +MVDD
R2808 5.49K VSS_G5 G5 R2908 5.49K VSS_G5 G5 R3008 5.49K VSS_G5 G5 R3108 5.49K VSS_G5 G5
C2803 1uF VSS_G10 G10 C2903 1uF VSS_G10 G10 C3003 1uF VSS_G10 G10 C3103 1uF VSS_G10 G10
VSS_H1 H1 VSS_H1 H1 VSS_H1 H1 VSS_H1 H1
+MVDD R2809 2.37K VSS_H14 H14 R2909 2.37K VSS_H14 H14 +MVDD R3009 2.37K VSS_H14 H14 +MVDD R3109 2.37K VSS_H14 H14
+MVDD
R2810 5.49K VSS_K1 K1 R2910 5.49K VSS_K1 K1 R3010 5.49K VSS_K1 K1 R3110 5.49K VSS_K1 K1
C2805 1uF J14 VREFC VSS_K14 K14 C2905 1uF J14 VREFC VSS_K14 K14 C3005 1uF J14 VREFC VSS_K14 K14 C3105 1uF J14 VREFC VSS_K14 K14
VSS_P10 P10 VSS_P10 P10 VSS_P10 P10 VSS_P10 P10
6 ADBIE0 J4 ABI# VSS_T5 T5 6 ADBIE1 J4 ABI# VSS_T5 T5 6 ADBIF0 J4 ABI# VSS_T5 T5 6 ADBIF1 J4 ABI# VSS_T5 T5
IN T10
IN T10
IN T10
IN T10
VSS_T10 VSS_T10 VSS_T10 VSS_T10
+MVDD +MVDD
+MVDD +MVDD
C2810
C2811
C2812
C2813
C2814
C2815
C2816
C2817
C2818
C2819
C2910
C2911
C2912
C2913
C2914
C2915
C2916
C2917
C2918
C2919
C3010
C3011
C3012
C3013
C3014
C3015
C3016
C3017
C3018
C3019
C3110
C3111
C3112
C3113
C3114
C3115
C3116
C3117
C3118
C3119

0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10uF
10uF
10uF
10uF
1 COMMERCE VALLEY
10uF
10uF
10uF
10uF
+MVDD +MVDD +MVDD +MVDD evaluation requires a Board Technology License Agreement with AMD.
SHEET: MEMORY CH EF schematic and design, including, not limited to, any implied warranty
C2820
C2821
C2822
C2823
C2824
C2825
C2826
C2827
C2828
C3029
C2920
C2921
C2922
C2923
C2924
C2925
C2926
C2927
C2928
C3020
C3021
C3022
C3023
C3024
C3025
C3026
C3027
C3028
C3120
C3121
C3122
C3123
C3124
C3125
C3126
C3127
C3128

1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF

10uF
10uF
10uF
10uF
10uF
TITLE
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(8) TAHITI GPIO/CF/CLKs
U1
+3.3V_BUS
GPIO
Part 9 of 20
BE40 VDDR3 GPIO_0_PWRCNTL_4 AP44 GPIO_0_PHASE_SHED# 19
BD39 BN45 GPIO_1
OUT
VDDR3 GPIO_1 OUT 19
C1 C2 C3 BE39 VDDR3 GPIO_2 BG37 GPIO_2 19
1uF 0.1uF 0.1uF BD40
OUT
10V VDDR3 Unprotected FLASH
+1.8V
AW46 GPIO_5_REG_HOT +3.3V_BUS +3.3V_BUS
GPIO_5_REG_HOT IN 14
BD37 AM43 GPIO_6_TACH U3
VDD_CT GPIO_6_TACH IN 13 BIOS1
BE36 VDD_CT GPIO_7 BG46 GPIO_7 TP10 3 WP VDD 8
C4 C5 C6 BE37 VDD_CT GPIO_8_ROMSO BJ50 GPIO_8 RP1 1 8 33R GPIO_8_R 2 SO HOLD 7
1uF 1uF 0.1uF BD36 BH50 GPIO_9 RP1 2 7 33R GPIO_9_R 5 BIOS
VDD_CT GPIO_9_ROMSI SI
GPIO_10_ROMSCK BH49 GPIO_10 RP1 3 6 33R GPIO_10_R 6 SCK C7
BG43 GPIO_11 R14 0R PR_FLASH_CE 1 4 0.1uF
CE GND
D +1.8V R15 3.24K 1% PS_0 BC43 PS_0
GPIO_11
GPIO_12 BF42 GPIO_12 +3.3V_BUS D
R16 5.62K 1% GPIO_13 BE42 GPIO_13 Pm25LD010C-SCE
C16 0.68uF 4V GPIO_14_HPD2 BH45 GPIO_14_VDDCI_VID0 18 Function Table
AU45 GPIO_15_VDDC_VID0
OUT +3.3V_BUS +3.3V_BUS +3.3V_BUS
GPIO_15_PWRCNTL_0 OUT 17
+1.8V R17 8.45K 1% PS_1 BC42 PS_1 GPIO_16_8P_DETECT AU44 L(S) B0 to A
R18 2K 1% GPIO_17_THERMAL_INT AP46 GPIO_17_THERMAL_INT 13 R23
C18 0.1uF BJ48 HPD3
IN 100K
GPIO_18_HPD3 IN 11 DNI H(S) B1 to A
AP45 GPIO_19_CTF Protected FLASH
GPIO_19_CTF OUT 13 C15
R19 4.53K 1% PS_2 BC41 AT45 GPIO_20_VDDC_VID1 0.1uF
GPIO_30_FLASH_WP +3.3V_BUS
+1.8V PS_2 GPIO_20_PWRCNTL_1 OUT 17 DNI R26 R27
R20 4.99K 1% BD42 GPIO_21_FLASH_SEL R24 DNI 3.32K U4 10K 10K U2
GPIO_21 DNI DNI BIOS2
C20 0.01uF 25V BF48 GPIO_22 RP1 4 5 33R 4 5 R25 DNI 10K 3 8
GPIO_22_ROMCSB A VCC WP VDD
2 SO HOLD 7
+1.8V R21 3.4K 1% PS_3 BC39 PS_3 GPIO_29 BL46 GPIO_29_VDDCI_VID1 18 FLASH_SEL_R 6 S B0 3 5 SI BIOS
R22 100K 1% BL40 GPIO_30_FLASH_WP
OUT 6
GPIO_30 SCK C12
C22 0.082uF 16V 2 1 SR_FLASH_CE 1 4 0.1uF
B1 CE
3
GND GND DNI
AT44
3
GPIO_28_FDO GPIO_28_FDO 13 19 Pm25LD010C-SCE
OUT NC7SB3157P6X
?
R28 5.1K PWRGOOD BJ49 BK49 HPD1 DNI
+1.8V PWRGOOD HPD1 IN 9 DNI
DNI
00
R29 1K SW1
BU50 +3.3V_BUS
M4
M3
M2
M1
GENERICA DNI
GENERICB BF43
TP1 BG42 BM45 GENERICC
07
CMON_VINP GENERICC R52 DNI 10K GPIO_14_VDDCI_VID0
GENERICD BH37 GENERICD MR52 10K
C14 GENERICE_HPD4 BL48 HPD4 10
0.1uF BH46 HPD5
IN MR53 10K
R53 DNI 10K GPIO_15_VDDC_VID0
GENERICF_HPD5 IN 10
BV31 GENERICG_HPD6 BK48 HPD6 9
74
NC IN
BJ46 R54 DNI 10K GPIO_20_VDDC_VID1
M
NC MR54 10K
BL39 NC CEC BG45 CEC 9
BK39
BI R55 DNI 10K GPIO_29_VDDCI_VID1
65 SI　
NC MR55 10K
AW45 NC
AW44 NC
AY45 +3.3V_BUS
NC
AY44 NC SCL AU46 SCL R30 0R REGLTR_SCL 17 19 PIN BASED STRAPS
BC38 AT46 SDA R31 0R REGLTR_SDA
OUT
NC SDA BI 17 19
　
R1 10K GPIO_0_PHASE_SHED#
C Tahiti R50 10K
+3.3V_BUS MR1 DNI 10K
GPIO(0) - TX_CFG_DRV_FULL_SWING (Transmitter Power Savings Enable)
0: 50% Tx output swing for mobile mode
C
Place all components on the bottom side. R51 10K 1: full Tx output swing (Default setting for Desktop)
張 CON
R2 10K GPIO_1 GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)
U1 MR2 DNI 10K 0: Tx de-emphasis disabled for mobile mode
+1.8V J1
DVP 1: Tx de-emphasis enabled (Default setting for Desktop)
Part 10 of 20 Lower Cable Card Edge
614NOPN128 GPIO(2) - BIF_GEN3_EN_A
文
BE33 VDDR4 DVPDATA_0 BL30 DVPDATA_0 10 1 R3 10K GPIO_2 0 : Driver Controlled Gen3
F
BD33 BG31 DVPDATA_1 11 2 MR3 DNI 10K
VDDR4 DVPDATA_1 1 : Strap Controlled Gen3
C8 C9 C10 C11 BE34 VDDR4 DVPDATA_2 BH31 DVPDATA_2 14 4
RM 　 ID
10uF 4.7uF 1uF 1uF BD34 BK31 DVPDATA_3 15 5
4V VDDR4 DVPDATA_3
DVPDATA_4 BL31 DVPDATA_4 18 6 R4 DNI 10K GPIO_9_R
BF33 19 8 MR4 DNI VGA DISABLE : 1 for disable (set to 0 for normal operation)
DVPDATA_5 DVPDATA_5 10K
DVPDATA_6 BG33 DVPDATA_6 22 9
+3.3V_BUS +3.3V_BUS
A( RD EN
DVPDATA_7 BH33 DVPDATA_7 23 12
DVPDATA_8 BF34 DVPDATA_8 26 13 R5 10K GPIO_13 GPIO(13,12,11) - CONFIG[2..0]
DVPDATA_9 BH34 DVPDATA_9 27 16 MR5 DNI 10K 100 - 512Kbit M25P05A (ST)
DVPDATA_10 BJ34 DVPDATA_10 30 17 R6 DNI 10K GPIO_12 CONFIG[2] 101 - 1Mbit M25P10A (ST)
R32 R33
吳 (C TI
BF36 DVPDATA_11 31 20 MR6 DNI 10K 101 - 2Mbit M25P20 (ST)
4.7K 4.7K DVPDATA_11
21 GPIO_11 101 - 4Mbit M25P40 (ST)
R7 10K CONFIG[1] 101 - 8Mbit M25P80 (ST)
13 DDC6CLK AN46 DDC6CLK DVPCLK BN30 DVOCLK 3 24 MR7 DNI 10K 100 - 512Kbit Pm25LV512 (Chingis)
OUT DDC6DATA AN45 BM30 DVPCNTL_2 7 25 101 - 1Mbit Pm25LV010 (Chingis)
13 BI DDC6DATA DVPCNTL_2 CONFIG[0]
積 )2 AL
DVPCNTL_1 BH36 DVPCNTL_1 35 28
SWAP_LOCK_A BF40 SWAPLOCKA DVPCNTL_0 BG36 DVPCNTL_0 34 29
TP2
TP3
SWAP_LOCK_B BG40 SWAPLOCKB GPIO_2 38 32
GENERICD 39 33 R8 10K VSYNC 11
GENLK_CLK BM48 36 MR8 DNI 10K
OUT
GENLK_CLK AUD[1:0] (AUD[1]= HSYNC , AUD[0]= VSYNC) )
源 01
TP4
GENLK_VSYNC BN48 GENLK_VSYNC J2 37 R9 10K HSYNC 11 00 - No audio function;
TP5
40 MR9 DNI 10K
OUT 01 - Audio for DisplayPort only;
614NOPN128 10 - Audio for DisplayPort and HDMI if dongle is
TP6
CLKREQB AN44 CLKREQB DVPDATA_12 BJ39 DVPDATA_12 10 1 detected;
DVPDATA_13 BJ40 DVPDATA_13 11 2 11 - Audio for both DisplayPort and HDMI.
)
DVPDATA_14 BK40 DVPDATA_14 14 4 HDMI must only be enabled on systems that are
20
+1.8V DVPDATA_15 BH42 DVPDATA_15 15 5 legally entitled. It is the responsibility of the system
BJ42 DVPDATA_16 18 6 designer to ensure that the system is entitled to
DVPDATA_16 support this feature.
R34 221R VREFG BR31 VREFG DVPDATA_17 BK42 DVPDATA_17 19 8
R35 110R DVPDATA_18 BK43 DVPDATA_18 22 9 R10 10K GPIO_8_R
B B
6
C19 0.1uF DVPDATA_19 BL43 DVPDATA_19 23 12 MR10 DNI 10K BIF_CLK_PM_EN
DVPDATA_20 BM43 DVPDATA_20 26 13 0 - Disable CLKREQ# power management capability
05
AK45 RSVD DVPDATA_21 BJ45 DVPDATA_21 27 16 +3.3V_BUS 1 - Enable CLKREQ# power management capability
AK46 RSVD DVPDATA_22 BK45 DVPDATA_22 30 17
BU55 RSVD DVPDATA_23 BL45 DVPDATA_23 31 20 RESERVED:
BR54 RSVD 21 STRAP_BIOS_ROM_EN
BLM15AG121SN1D
BLM15AG121SN1D
00
BN55 RSVD DVPCNTL_MVP_1 BG39 DVP_MVP_CNTL_1 3 24 CLKREQ# that requires open drain connection, and cannot be used as pinstrap
BN53 RSVD DVPCNTL_MVP_0 BH39 DVP_MVP_CNTL_0 7 25 Don't set high at reset
TP7 RSV_I2CDAT 35 28
Tahiti TP8 RSV_I2CCLK 34 29
1
GPIO_1 38 32
Please pay attention to the grounding GENERICC 39 33
strategies for these filter capacitors to 36
maintain a close loop for current. 37
2
40 Y1
27.000MHz_10PPM_30R
XOUT_OSC 1 3 XIN_OSC
2 4
LOCATION=U1 U5 +3.3V_BUS
R11 15K GPIO_28_FDO GPIO(28) - MLPS_DIS
C17 20pF 10 XTALOUT XTALIN 1 C21 20pF MR11 DNI 10K
B1 1
B2 1
+1.8V CLOCKS
Part 11 of 20 VDD_100M 4 VDD33_100M R12 10K GENLK_VSYNC GENLK_VSYNC - CEC_DIS
B3 1 2 BLM15AG121SN1D BR50 BU48 XO_IN2 5 8 R36 R37 MR12 DNI 10K
+DPLL_PVDD DPLL_PVDD XO_IN2 R38 0R CLK_100M 100M_OUT VDD_27M VDD33_27M 5.1K 5.1K
BR49 XTAL_VDDR DNI DNI
C23 C24 SS_SEL0 7 SS_SEL0 R13 10K GENLK_CLK GENLK_CLK - SMS_EN_HARD

C25
10uF 0.1uF
10V
0.1uF SS_SEL1 3 SS_SEL1 MR13 DNI 10K
BN50 DPLL_PVSS XO_IN BW48 XO_IN R39 0R CLK_27M 9 27M_OUT
+0.94V
GND_100M 6
B4 1 2 BM50 2 C13 C26 R40 R41
BLM15AG121SN1D +DPLL_VDDC DPLL_VDDC GND_27M 0.1uF 0.1uF 5.1K 5.1K
R42 GND_PAD 11
182R
C27 C28 DNI
0.1uF
1uF SL16010DCT
XTALIN BV49 XTALIN
+1.8V CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
IN 19 Divider for 1.8V signaling.
B5 1 2 BLM15AG121SN1D +SPll_PVDD BF45 SPLL_PVDD AMD - GRAPHICS C 2010 Advanced Micro Devices
19
XTALOUT BT49 XTALOUT
OUT R43
221R 1 COMMERCE VALLEY This AMD Board schematic and design is the exclusive property of AMD, and
A C29
10uF
C30
1uF
C31
0.1uF
TP9
DNI
MARKHAM, ONTARIO, L3T 7X6 is provided only to entities under a non-disclosure agreement with AMD A
BE44 for evaluation purposes. Further distribution or disclosure is strictly
+0.94V SPLL_PVSS
B6 1 2 BLM15AG121SN1D +SPLL_VDDC BD43 evaluation requires a Board Technology License Agreement with AMD.
SPLL_VDDC
SHEET: TAHITI GPIO CF CLK schematic and design, including, not limited to, any implied warranty
C32 C33 of merchantability or fitness for a particular purpose, and disclaims
1uF 0.1uF
route 50ohms single-ended/100ohms diff responsibility for any consequences resulting from use of the
+1.8V and keep short
B7 2 1 220R_2A +MPV18 G7 MPLL_PVDD CLKTESTA BD45 CLKTESTA C34 0.1uF CLKTESTA_C R44 51.1R
H7 MPLL_PVDD SHEET NUMBER: 8 OF 21 TITLE:
C35 C36 C37 C38 C39 C40 C41
G8 MPLL_PVDD CLKTESTB BE46 CLKTESTB C42 0.1uF CLKTESTB_C R45 51.1R
10uF
DNI
10uF
DNI
10uF 4.7uF
4V
4.7uF
4V
1uF 0.1uF
TITLE
Tahiti DOCUMENT NUMBER: 105-C38600-00
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(9) TAHITI HDMI DVI AB
U1
TMDP_AB J1700
Part 17 of 20 +3.3V_DP
R1700 150R DPAB_CALR BN43 DPAB_CALR TX2P_DPA0P BT43 ATX2P C1701 0.1uF ATX2P_C 1
ML_Lane_0p
20
D +1.8V
TX2M_DPA0N BR43 ATX2M C1702 0.1uF ATX2M_C 3
ML_Lane_0n
DP_PWR D
C1733 C1732
BN36 TX1P_DPA1P BU42 ATX1P C1703 0.1uF ATX1P_C 4 100uF 22uF
DP_VDDR ML_Lane_1p
BN34 DNI
DP_VDDR
C1718 C1719 C1720 C1721 C1722 C1723 BM33 DP_VDDR TX1M_DPA1N BV41 ATX1M C1704 0.1uF ATX1M_C 6
0.1uF 10uF 10uF 1uF 1uF 0.1uF ML_Lane_1n
BN33 DP_VDDR
BM34 DP_VDDR TX0P_DPA2P BT41 ATX0P C1705 0.1uF ATX0P_C 7
ML_Lane_2p
BM36 DP_VDDR
TX0M_DPA2N BR41 ATX0M C1706 0.1uF ATX0M_C 9
ML_Lane_2n
TXCAP_DPA3P BU40 ATXCP C1707 0.1uF ATXCP_C 10

ML_Lane_3p
TXCAM_DPA3N BV39 ATXCM C1708 0.1uF ATXCM_C 12

ML_Lane_3n
R1731 100K
DPA_AUXP 15
+0.94V AUX_CHp
R1733 100K
+3.3V_BUS
DPA_AUXN 17
AUX_CHn
BM40 DP_VDDC DDCCLK_AUX3P BK37 AUX3P C1730 0.1uF
BN37
00
DP_VDDC +12V_BUS +12V_BUS
BM42 BL37 AUX3N C1731 0.1uF +3.3V_BUS
C1724 C1725 C1726 C1727 C1728 C1729 DP_VDDC DDCDATA_AUX3N
10uF 10uF 1uF 1uF 0.1uF 0.1uF BN42 DP_VDDC
BM37
3
DP_VDDC
BN40 DP_VDDC 2 3 3 2 R1725 R1726 1 R1729 10K HPD_DPA 18
07
Q1704 Hot_Det
BN39 Q1709 Q1710 10K 10K
DP_VDDC MMBT3904
BM39 BSH111 BSH111 R1730 2
2
DP_VDDC 8 HPD6 10K
R1732
OUT GND
5
1 1
1 1
AUX3_BYPASS_EN 10K
GND
8
3
74
Q1711 Q1712 GND
C1709 1 1 DPA_DONGLE_DET DPA_DONGLE_DET 13 CONFIG_1 11
M
BSH111 BSH111 Q1708 GND
2 3 3 2 0.1uF 16
2N7002 GND
BW56 Q1707 R1723 R1727 14 CONFIG_2 19
2
DP_VSS 1M 5.1M CONFG_2
65 SI　
MMBT3904 GND
BW32 DP_VSS
BR44 DP_VSS DislpayPort
BR42 DP_VSS
BR40 DP_VSS
BR38 +5V_VESA
DP_VSS
　
BR36 DP_VSS HDMI
C BR34 DP_VSS TX5P_DPB0P BT47 BTX2P C1710 0.1uF BTX2P_C B1
TMDS Data 2+
C
BR32 DP_VSS R1710 499R +5V PWR B18
張 CON
BM53 DP_VSS TX5M_DPB0N BR47 BTX2M C1711 0.1uF BTX2M_C B3 TMDS Data 2-
BL55 DP_VSS R1711 499R C1700
BW50 DP_VSS TX4P_DPB1P BU46 BTX1P C1712 0.1uF BTX1P_C B4 TMDS Data 1+ 1uF
BW46 DP_VSS R1712 499R
BW44 DP_VSS TX4M_DPB1N BV45 BTX1M C1713 0.1uF BTX1M_C B6 TMDS Data 1-
文
F
BW40 DP_VSS TX3P_DPB2P BT45 BTX0P C1714 0.1uF BTX0P_C B7 TMDS Data 0+
RM 　 ID
BW36 DP_VSS TX3M_DPB2N BR45 BTX0M C1715 0.1uF BTX0M_C B9 TMDS Data 0-
BV47 DP_VSS TXCBP_DPB3P BU44 BTXCP C1716 0.1uF BTXCP_C B10 TMDS Clock+
BU57 DP_VSS R1716 499R
A( RD EN
BT59 DP_VSS TXCBM_DPB3N BV43 BTXCM C1717 0.1uF BTXCM_C B12 TMDS Clock-
BR53 DP_VSS R1717 499R
BR52 +5V_VESA
DP_VSS
BL53
3
DP_VSS
吳 (C TI
BR46 DP_VSS 11 9 DVI_EN 1
BN52 BN46 DDCCLK4
IN Q1701
DP_VSS DDCCLK_AUX4P 2N7002
BM59
2
DP_VSS R1718 R1719
BL58 BM46 DDCDATA4 2.2K 2.2K
DP_VSS DDCDATA_AUX4N
積 )2 AL
Tahiti R1720 33R HDMI_DDCCLK B15 DDC Clock
R1721 33R HDMI_DDCDATA B16 DDC Data GND B2
GND B5
源 01
+3.3V_BUS +3.3V_BUS B8
GND
GND B11
GND B17
3
1 R1722 10K HPD_HDMI B19 Hot Plug Detect
)
Q1702
R1709 MMBT3904 G1
20
27K CASE
R1724 B14 G2
2
8 HPD1 10K NC
OUT CASE
G3
CASE
8 CEC 2 3 CEC_Q B13 CEC G4
BI CASE
B Q1703 B
6
2N7002 DP+HDMI
1
05
11 9 DVI_EN
IN
ATX2P_C 5 D
U1700
Y4 6 ATX2P_C
00
1
ATX2M_C 4 C Y3 7 ATX2M_C
3 8 MJ1700 +5V_VESA
GND GND1
ATX1P_C 2 B Y2 9 ATX1P_C ATX2P_C 1 TMDS Data 2+
ATX1M_C 1 A Y1 10 ATX1M_C R1701 DNI 499R +5V Pwr 18
ATX2M_C 3 TMDS Data 2-
RCLAMP0524P R1702 DNI 499R
DNI ATX1P_C 4 TMDS Data 1+
R1703 DNI 499R
U1701 ATX1M_C 6 TMDS Data 1-
ATX0P_C 5 D Y4 6 ATX0P_C R1704 DNI 499R
ATX0M_C 4 C Y3 7 ATX0M_C ATX0P_C 7 TMDS Data 0+
3 GND GND1 8 R1705 DNI 499R
ATXCP_C 2 B Y2 9 ATXCP_C ATX0M_C 9 TMDS Data 0-
ATXCM_C 1 A Y1 10 ATXCM_C R1706 DNI 499R
ATXCP_C 10 TMDS Clock+
RCLAMP0524P R1707 DNI 499R
DNI ATXCM_C 12 TMDS Clock-
R1708 DNI 499R
U1702
BTX2P_C 5 6 BTX2P_C
3
D Y4
BTX2M_C 4 C Y3 7 BTX2M_C 11 9 DVI_EN 1
3 8
IN Q1700
GND GND1 2N7002
2 9 DNI CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2
BTX1P_C B Y2 BTX1P_C
BTX1M_C 1 A Y1 10 BTX1M_C Optional ESD protection dioes AMD - GRAPHICS C 2010 Advanced Micro Devices
HDMI_DDCCLK 15 DDC Clock

A RCLAMP0524P
DNI D1716 2 1 ESD8V0R1B-02LRH HDMI_DDCCLK MARKHAM, ONTARIO, L3T 7X6 is provided only to entities under a non-disclosure agreement with AMD A
DNI HDMI_DDCDATA 16 8 for evaluation purposes. Further distribution or disclosure is strictly
DDC Data D0 Shld
U1703 D1717 2 1 ESD8V0R1B-02LRH HDMI_DDCDATA D1 Shld 5 prohibited. Use of this schematic and design for any purpose other than
BTX0P_C 5 6 BTX0P_C DNI 2 evaluation requires a Board Technology License Agreement with AMD.
D Y4 D2 Shld
4 7 D1718 2 1 11 AMD makes no representations or warranties of any kind regarding this
BTX0M_C C Y3 BTX0M_C ESD8V0R1B-02LRH
DNI
DPA_AUXP Clk Shld SHEET: TAHITI HDMI DP AB schematic and design, including, not limited to, any implied warranty
3 GND GND1 8 GND (+5V) 17
BTXCP_C 2 9 BTXCP_C D1719 2 1 ESD8V0R1B-02LRH DPA_AUXN HPD_HDMI 19 of merchantability or fitness for a particular purpose, and disclaims
B Y2 Hot Plog Detect
1 10 DNI 20 responsibility for any consequences resulting from use of the
BTXCM_C A Y1 BTXCM_C CASE DATE: Wed Nov 02 15:28:39 2011 REV: 1.0 information included herein.
14 NC CASE 21
RCLAMP0524P CASE 22
DNI CEC_Q 13 CEC CASE 23 SHEET NUMBER: 9 OF 21 TITLE:
DNI
HDMI_LONG_TYPE TITLE
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(10) TAHITI mDP mDP CD
D U1 D
TMDP_CD J1800
Part 18 of 20 +3.3V_DP +3.3V_BUS
R1800 150R DPCD_CALR BJ37 BT35 DPC_C0P C1801 0.1uF DPC_0P 3
DPCD_CALR TX2P_DPC0P ML_Lane_0p
20 F1800 1 2 NANOSMDC150F-2
DP_PWR
TX2M_DPC0N BR35 DPC_C0N C1802 0.1uF DPC_0N 5 ML_Lane_0n
TX1P_DPC1P BU34 DPC_C1P C1803 0.1uF DPC_1P 9 ML_Lane_1p C1821 C1822

100uF 22uF
BV33 DPC_C1N C1804 0.1uF DPC_1N 11 DNI
TX1M_DPC1N ML_Lane_1n
TX0P_DPC2P BT33 DPC_C2P C1805 0.1uF DPC_2P 15 ML_Lane_2p
TX0M_DPC2N BR33 DPC_C2N C1806 0.1uF DPC_2N 17 ML_Lane_2n
TXCCP_DPC3P BU32 DPC_C3P C1807 0.1uF DPC_3P 10 ML_Lane_3p
TXCCM_DPC3N BT31 DPC_C3N C1808 0.1uF DPC_3N 12 ML_Lane_3n
00
AUX1P BM31 AUX1P C1809 0.1uF DPC_AUXP 16 AUX_CHp
R1801 100K
AUX1N BN31 AUX1N C1810 0.1uF DPC_AUXN 18 AUX_CHn
R1802 100K
07
+3.3V_BUS
DDC1CLK BK33 DDC1CLK 2 3
+12V_BUS +12V_BUS +3.3V_BUS
Q1800
DDC1DATA BL33 DDC1DATA 2N7002 2 3
3
Q1801
74
2N7002 1 R1805 10K HPD_DPC 2 Hot_Det PWR_RTN 19
M
R1803 R1804
Q1802
G1
1
10K 10K MMBT3904 G1
G2
2
HPD5 R1806 10K G2
65 SI　
8 OUT
AUX1_BYPASS_EN R1807 10K GND 1
7
3
GND
1 Q1804 1 DPC_DONGLE_DET 4 CONFIG_1 GND 8
Q1803 2N7002 GND 13
R1808 R1809 6 14
2
MMBT3904 1M 5.1M CONFIG_2 GND
　
C MINIDP_JAE_TYPE C
張 CON
J1801
TX5P_DPD0P BT39 DPD_D0P C1811 0.1uF DPD_0P 3 ML_Lane_0p

DP_PWR 20
TX5M_DPD0N BR39 DPD_D0N C1812 0.1uF DPD_0N 5 ML_Lane_0n
文 F
TX4P_DPD1P BU38 DPD_D1P C1813 0.1uF DPD_1P 9 ML_Lane_1p C1823 C1824
100uF 22uF
RM 　 ID
BV37 DPD_D1N C1814 0.1uF DPD_1N 11 DNI
TX4M_DPD1N ML_Lane_1n
TX3P_DPD2P BT37 DPD_D2P C1815 0.1uF DPD_2P 15 ML_Lane_2p
A( RD EN
TX3M_DPD2N BR37 DPD_D2N C1816 0.1uF DPD_2N 17 ML_Lane_2n
TXCDP_DPD3P BU36 DPD_D3P C1817 0.1uF DPD_3P 10 ML_Lane_3p
吳 (C TI
TXCDM_DPD3N BV35 DPD_D3N C1818 0.1uF DPD_3N 12 ML_Lane_3n
AUX2P BK34 AUX2P C1819 0.1uF DPD_AUXP 16 AUX_CHp

R1810 100K
積 )2 AL
AUX2N BL34 AUX2N C1820 0.1uF DPD_AUXN 18 AUX_CHn
R1811 100K +3.3V_BUS
BK36 DDC2CLK 2 3 +12V_BUS +12V_BUS
DDC2CLK
+3.3V_BUS
Q1805
DDC2DATA BL36 DDC2DATA 2N7002 2 3
源 01
1
Q1806
3
Tahiti 2N7002 R1812 R1813
Q1807 1 R1814 10K HPD_DPD 2 Hot_Det PWR_RTN 19
1 10K 10K MMBT3904 G1
G1
G2
2
8 HPD4 R1815 10K G2
OUT
)
AUX2_BYPASS_EN R1816 10K GND 1
20
7
3
GND
Q1808 1 Q1809 1 DPD_DONGLE_DET 4 CONFIG_1 GND 8
MMBT3904 2N7002 GND 13
R1818 6 14
2
R1817 1M 5.1M CONFIG_2 GND
B B
6
MINIDP_JAE_TYPE
05
OPTIONAL ESD PROTECTION
00
1
DIODES
REG1800 REG1801
DPC_0P 5 D Y4 6 DPC_0P DPD_0P 5 D Y4 6 DPD_0P
DPC_0N 4 C Y3 7 DPC_0N DPD_0N 4 C Y3 7 DPD_0N
3 GND GND1 8 3 GND GND1 8
DPC_1P 2 B Y2 9 DPC_1P DPD_1P 2 B Y2 9 DPD_1P
DPC_1N 1 A Y1 10 DPC_1N DPD_1N 1 A Y1 10 DPD_1N
RCLAMP0524P RCLAMP0524P
DNI DNI
REG1802 REG1803
DPC_2P 5 D Y4 6 DPC_2P DPD_2P 5 D Y4 6 DPD_2P
DPC_2N 4 C Y3 7 DPC_2N DPD_2N 4 C Y3 7 DPD_2N
3 GND GND1 8 3 GND GND1 8
DPC_3P 2 B Y2 9 DPC_3P DPD_3P 2 B Y2 9 DPD_3P
DPC_3N 1 A Y1 10 DPC_3N DPD_3N 1 A Y1 10 DPD_3N
RCLAMP0524P RCLAMP0524P
DNI DNI CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
D1800 2 1 ESD5V3U1U-02LRH DPC_AUXN AMD - GRAPHICS C 2010 Advanced Micro Devices

DNI
A D1801 2 1
DNI
ESD5V3U1U-02LRH DPC_AUXP
D1802 2 1 ESD5V3U1U-02LRH DPD_AUXN prohibited. Use of this schematic and design for any purpose other than
DNI
D1803 2 1 ESD5V3U1U-02LRH DPD_AUXP AMD makes no representations or warranties of any kind regarding this
DNI SHEET: TAHITI mDP mDP CD schematic and design, including, not limited to, any implied warranty
D1804 2 1 ESD5V3U1U-02LRH DPC_DONGLE_DET of merchantability or fitness for a particular purpose, and disclaims
DNI
D1805 2 1 ESD5V3U1U-02LRH DPD_DONGLE_DET DATE: Wed Nov 02 15:28:39 2011 REV: 1.0 information included herein.
DNI

TITLE
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LOCATION=U1
(11) TAHITI DVI EF DAC
TMDP_EF
Part 19 of 20
R1900 150R DPEF_CALR BN51 DPEF_CALR TX2P_DPE0P BV53 DPE_TX2P C1901 0.1uF
TX2M_DPE0N BW54 DPE_TX2N C1902 0.1uF
TX1P_DPE1P BT53 DPE_TX1P C1903 0.1uF
TX1M_DPE1N BU52 DPE_TX1N C1904 0.1uF
TX0P_DPE2P BW52 DPE_TX0P C1905 0.1uF
TX0M_DPE2N BV51 DPE_TX0N C1906 0.1uF
TXCEP_DPE3P BT51 DPE_TXCAP C1907 0.1uF

D D
TXCEM_DPE3N BR51 DPE_TXCAN C1908 0.1uF
DDCCLK_AUX5P BN49 DDCAUX5P +5V_VESA

TP1901
DDCDATA_AUX5N BM49 DDCAUX5N TP1902
EFTX2P +5V_VESA
Optional ESD protection dioes R1902 499R
EFTX2M
R1903 499R C1900
1uF
D1901 2 1 ESD5V3U1U-02LRH EFTX2P EFTX1P
DNI R1904 499R
D1902 2 1 ESD5V3U1U-02LRH EFTX2M EFTX1M
DNI R1905 499R
D1903 2 1 ESD5V3U1U-02LRH EFTX1P EFTX0P
DNI R1906
00
499R
D1904 2 1 ESD5V3U1U-02LRH EFTX1M EFTX0M
DNI R1907 499R
D1905 2 1 ESD5V3U1U-02LRH EFTX0P EFTXCP
DNI R1908 499R
07
D1906 2 1 ESD5V3U1U-02LRH EFTX0M EFTXCM SCREW1901
DNI R1909 499R
D1907 2 1 ESD5V3U1U-02LRH EFTXCP TX5P_DPF0P BL56 DPF_TX5P C1911 0.1uF EFTX5P
DNI R1910 499R
74
D1908 2 1 ESD5V3U1U-02LRH EFTXCM TX5M_DPF0N BM57 DPF_TX5N C1912 0.1uF EFTX5M
M
DNI R1911 499R
D1909 2 1 ESD5V3U1U-02LRH EFTX5P TX4P_DPF1P BM55 DPF_TX4P C1913 0.1uF EFTX4P
65 SI　
DNI R1912 499R SCREW1902
D1910 2 1 ESD5V3U1U-02LRH EFTX5M TX4M_DPF1N BN56 DPF_TX4N C1914 0.1uF EFTX4M
DNI R1913 499R
D1911 2 1 ESD5V3U1U-02LRH EFTX4P TX3P_DPF2P BN58 DPF_TX3P C1915 0.1uF EFTX3P
DNI R1914 499R
　
D1912 2 1 ESD5V3U1U-02LRH EFTX4M TX3M_DPF2N BP59 DPF_TX3N C1916 0.1uF EFTX3M
C DNI R1915 499R C
D1913 2 1 ESD5V3U1U-02LRH EFTX3P TXCFP_DPF3P BP55 +5V_VESA
張 CON
DNI
+12V_BUS R1916 100K C1909 0.1uF16V
D1914 2 1 ESD5V3U1U-02LRH EFTX3M BR57
3
TXCFM_DPF3N
DNI DVI_EN DVI_EN 1
11 9 9 OUT Q1901
11 2N7002
R1917 R1918
2
2.2K 2.2K
文 F
DDCCLK_AUX7P BM52 DDC7CLK R1919 33R DVIEF_DDCCLK
RM 　 ID
DDCDATA_AUX7N BL52 DDC7DATA R1920 33R DVIEF_DDCDATA
Tahiti
A( RD EN
吳 (C TI
LOCATION=U1
+3.3V_BUS HPD_DVIEF
+1.8V
VGA
Part 12 of 20
3
36NH 36NH
積 )2 AL
B1500 1 2 BLM15AG121SN1D +VDD12DI BF50 VDD1DI R BJ53 RED L1500 1 2 RED_L1 L1501 1 2 RED_L Q1902 1 R1921 10K HPD_DVIEF
MMBT3904
R1922 J1900
2
C1500 C1501 C1502 8 HPD3 10K
1uF 0.1uF 0.01uF OUT 25
R1500 R1501 C1503 C1504 CASE
BF49 VSS1DI 150R 150R 8pF 12pF
源 01
+1.8V
EFTX2M 1 TMDS_Data2-
EFTX2P 2 TMDS_Data2+
B1501 1 2 BLM15AG121SN1D +AVDD_DAC12 BL51 AVDD 3 TMDS_Data2/4_Shield
BM51 AVDD 36NH 36NH EFTX4M 4 TMDS_Data4-
)
G BJ52 GREEN L1502 1 2 GREEN_L1 L1503 1 2 GREEN_L EFTX4P 5 TMDS_Data4+
20
C1505 C1506 DVIEF_DDCCLK 6 DDC_Clock
1uF 0.1uF DVIEF_DDCDATA 7 DDC_Data
BL50 AVSSQ R1502 R1503 C1507 C1508 VSYNC_R 8 Analog_VSYNC
150R 150R 8pF 12pF EFTX1M 9 TMDS_Data1-
B B
6
R1504 499R RSET BL49 RSET 11 TMDS_Data1/3_Shield
05
36NH 36NH EFTX3P 13 TMDS_Data3+
B BK52 BLUE L1504 1 2 BLUE_L1 L1505 1 2 BLUE_L +5V_VESA 14 +5V_Power
15 GND_(for_+5V)
00
HPD_DVIEF 16 Hot_Plug_Detect
R1505 R1506 C1509 C1510 EFTX0M 17 TMDS_Data0-
150R 150R 8pF 12pF EFTX0P 18 TMDS_Data0+
19 TMDS_Data0/5_Shield
1
22 TMDS_Clock_Shield
HSYNC BK51 HSYNC 2 3 HSYNC_DAC1_B R1507 24R HSYNC_R EFTXCP 23 TMDS_Clock+
8 U1501 EFTXCM 24 TMDS_Clock-
IN 74VHCT125 C1511
12pF RED_L C1
1
Analog_Red
GREEN_L C2 Analog_Green
BLUE_L C3
4
Please pay attention to the grounding Analog_Blue

strategies for these filter capacitors to 8 HSYNC_R C4 Analog_HYNC
maintain a close loop for current. BJ51
IN VSYNC 5 6 VSYNC_DAC1_B R1508 24R VSYNC_R C5 27
VSYNC Analog_GND CASE#M3
U1501 C6 Analog_GND#C6 CASE#M4 28
Tahiti 74VHCT125 CASE#M5 29
C1512 26 CASE#M2 CASE#M6 30
12pF
9 8 DVI_CONNECTOR
U1501
74VHCT125
10
OPTIONAL ESD PROTECTION DIODES

13
D1500 2 1 ESD5V3U1U-02LRH RED_L CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
D1501 2 1
DNI
ESD5V3U1U-02LRH GREEN_L
12 11 AMD - GRAPHICS C 2010 Advanced Micro Devices
DNI
U1501
74VHCT125
A D1502 2 1 ESD5V3U1U-02LRH BLUE_L MARKHAM, ONTARIO, L3T 7X6 is provided only to entities under a non-disclosure agreement with AMD A
DNI for evaluation purposes. Further distribution or disclosure is strictly
D1503 2 1 ESD8V0R1B-02LRH DVIEF_DDCCLK prohibited. Use of this schematic and design for any purpose other than
DNI evaluation requires a Board Technology License Agreement with AMD.
D1504 2 1 +5V AMD makes no representations or warranties of any kind regarding this
ESD8V0R1B-02LRH DVIEF_DDCDATA SHEET: TAHITI DVI EF DAC schematic and design, including, not limited to, any implied warranty
DNI
C1513 0.1uF of merchantability or fitness for a particular purpose, and disclaims
D1505 2 1 ESD8V0R1B-02LRH HSYNC_R
DNI responsibility for any consequences resulting from use of the
DATE: Wed Nov 02 15:28:39 2011 REV: 1.0
14
D1506 2 1 ESD8V0R1B-02LRH vSYNC_R information included herein.

DNI
U1501
74VHCT125 TITLE
7
NOTES: NOTE
8 7 6 5 4 3 2 1
9 8 7 6 5 4 3 2 1
(12) TAHITI POWER
U1 U1
GND GND
Part 13 of 20 Part 14 of 20
AN37 VSS VSS U21 B7 VSS VSS AG15
AL34 VSS VSS U17 BA2 VSS VSS AG45
E AH17
AD32
VSS VSS BC36
BC29
BB15
BC14
VSS VSS AG51
AG9
E
VSS VSS VSS VSS
W43 VSS VSS BC27 BC8 VSS VSS AH55
W37 VSS VSS BC23 BD20 VSS VSS AJ2
U31 VSS VSS BC19 BE12 VSS VSS AK12
BB38 VSS VSS BC17 BE2 VSS VSS AK5
AW32 VSS VSS BB34 BF17 VSS VSS AL2
AU24 VSS VSS BA28 BF23 VSS VSS AM5
AN36 VSS VSS BB19 BF8 VSS VSS AN2
AL33 VSS VSS BB17 BH11 VSS VSS AP14
AG43 VSS VSS BA39 BH24 VSS VSS AP8
AD27 VSS VSS BA34 BH30 VSS VSS AT12
AB23 VSS VSS BA23 BH8 VSS VSS AT5
U26 VSS VSS BA21 BJ17 VSS VSS AU2
W19 VSS VSS AW43 BJ20 VSS VSS AW2
W17 VSS VSS AW38 BJ23 VSS VSS AY11
V42 VSS VSS AW28 BK5 VSS VSS AY8
W38 BA22 BL11 B13 +VDDC U1 +VDDC +MVDD U1 +VDDCI
VSS VSS VSS VSS
V23 VSS VSS AV42 BL2 VSS VSS B17 POWER POWER
U43 VSS VSS AV37 BL27 VSS VSS B21 Part 16 of 20 Part 15 of 20
U41 VSS VSS AV32 BM14 VSS VSS B25 AA19 VDDC VDDC BB29 AA15 VDDR1 VDDCI AA18
U38 VSS VSS AV29 BR16 VSS VSS B29 AJ28 VDDC VDDC AP36 AJ53 VDDR1 VDDCI AG42
U36 VSS VSS AV23 BV15 VSS VSS B33 AL24 VDDC VDDC W21 BC16 VDDR1 VDDCI AW18
C1200
C1201
C1202
C1203
C1204
C1205
C1206
C1207
C1208
C1209
C1270
C1271
C1272
C1273
C1274
C1400
C1402
C1403
C1404
C1300
C1301
C1302
C1303
C1304
C1305
C1306
C1307
C1308
C1309
U28 VSS VSS AU43 C3 VSS VSS B37 AT41 VDDC VDDC AA22 BH18 VDDR1 VDDCI V21
U23 VSS VSS AU39 E26 VSS VSS B47 AP21 VDDC VDDC AB29 J11 VDDR1 VDDCI W27
AU26 VSS VSS AU34 E49 VSS VSS B51 AT29 VDDC VDDC AB31 L9 VDDR1 VDDCI V33
AW33 VSS VSS AU19 H34 VSS VSS AF8 AU27 VDDC VDDC W39 M48 VDDR1 VDDCI W34
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
22uF
22uF
22uF
22uF
22uF
BB39 VSS VSS AU17 J20 VSS VSS AF52 BC34 VDDC VDDC AA21 R16 VDDR1 VDDCI W36
U32 VSS VSS AT38 K8 VSS VSS AF49 AP34 VDDC VDDC AA24 V17 VDDR1 VDDCI V41
W41 VSS VSS AT33 L58 VSS VSS AE58 AP39 VDDC VDDC AA26 AA51 VDDR1 VDDCI W42
AA17 VSS VSS AT26 M49 VSS VSS AD48 AB19 VDDC VDDC AA27 AB43 VDDR1 VDDCI AA42
AA23 VSS VSS AT21 P36 VSS VSS AD15 AB39 VDDC VDDC AA29 AC14 VDDR1 VDDCI AB18
AA32 VSS VSS AP38 R39 VSS VSS AC58 AC38 VDDC VDDC AA31 AC44 VDDR1 VDDCI AB42
AA37 VSS VSS AP33 U46 VSS VSS AC49 AF22 VDDC VDDC AA33 AD9 VDDR1 VDDCI AD19
C1275
C1276
C1277
C1278
C1279
AB17 VSS VSS AP28 W2 VSS VSS AC2 AF41 VDDC VDDC AA34 AD12 VDDR1 VDDCI V37
W31 VSS VSS AP23 AD51 VSS VSS AB55 AG33 VDDC VDDC AA38 AF14 VDDR1 VDDCI AD43
C1210
C1211
C1212
C1213
C1214
C1215
C1216
C1217
C1218
C1219
C1410
C1411
C1412
C1415
C1416
C1417
C1418
C1419
C1310
C1311
C1312
C1313
C1314
C1315
C1316
C1317
C1318
C1319
D AB36 VSS VSS AN31 AJ52 VSS VSS AA9 AN38 VDDC VDDC AA39 AF46 VDDR1 VDDCI AG19 D
00
AC17 VSS VSS AN28 AV5 VSS VSS AA49 AJ21 VDDC VDDC AP41 AJ14 VDDR1 VDDCI AF19
22uF
22uF
22uF
22uF
22uF
AC19 VSS VSS AN23 B41 VSS VSS AA2 AJ24 VDDC VDDC AB21 AJ46 VDDR1 VDDCI AF42
AC24 VSS VSS AN18 BE27 VSS VSS A56 AJ29 VDDC VDDC AB22 AK9 VDDR1 VDDCI AH18
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
AC33 VSS VSS AM42 BJ29 VSS VSS Y9 AJ31 VDDC VDDC AB26 AK47 VDDR1 VDDCI AH19
07
AC39 VSS VSS AM34 E52 VSS VSS Y55 AJ32 VDDC VDDC AB27 AL11 VDDR1 VDDCI AJ18
AC43 VSS VSS AM29 AD55 VSS VSS Y52 AH39 VDDC VDDC AB28 AN9 VDDR1 VDDCI AL18
AD21 VSS VSS AM24 AJ58 VSS VSS Y5 AJ37 VDDC VDDC AB32 AN15 VDDR1 VDDCI AN19
AD26 VSS VSS AM17 AW12 VSS VSS Y49 AJ39 VDDC VDDC AB33 AT9 VDDR1 VDDCI AM19
C1280
C1281
C1282
C1283
C1284
74
AD39 VSS VSS AL41 B43 VSS VSS Y44 AJ38 VDDC VDDC AB37 AU14 VDDR1 VDDCI AU18
M
AF23 VSS VSS AL26 BE9 VSS VSS Y14 AL22 VDDC VDDC AB38 AY14 VDDR1 VDDCI AP19
AF28 VSS VSS AL17 BJ5 VSS VSS V55 AL21 VDDC VDDC AC22 BB9 VDDR1 VDDCI AT19
65 SI　
AF32 VSS VSS AJ42 E8 VSS VSS V51 AL23 VDDC VDDC AP42 BC11 VDDR1 VDDCI AV18
22uF
22uF
22uF
22uF
22uF
C1220
C1221
C1222
C1223
C1224
C1225
C1226
C1227
C1228
C1229
C1420
C1421
C1422
C1423
C1424
C1425
C1426
C1427
C1428
C1429
C1320
C1321
C1322
C1323
C1324
AF38 VSS VSS AJ34 AA12 VSS VSS V5 AL28 VDDC VDDC AC23 BC22 VDDR1 VDDCI BA19
AF17 VSS VSS AJ27 AA46 VSS VSS V45 AL29 VDDC VDDC AC27 BD23 VDDR1 VDDCI BA18
AG24 VSS VSS AJ19 AA58 VSS VSS V18 AT31 VDDC VDDC AC28 BE16 VDDR1 VDDCI BA24
AG29 VSS VSS AH43 AB5 VSS VSS V15 AT32 VDDC VDDC AC29 BF13 VDDR1 VDDCI BA26
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
AG36 AH36 AC11 V12 AM22 AC31 BF14 BA27
　
VSS VSS VSS VSS VDDC VDDC VDDR1 VDDCI
AG41 VSS VSS AH29 AC46 VSS VSS U8 AM23 VDDC VDDC AC32 BF20 VDDR1 VDDCI BB21
AH26 VSS VSS AH24 AC52 VSS VSS U58 AT36 VDDC VDDC AC36 BF26 VDDR1 VDDCI BB22
C1285
C1286
C1287
C1288
C1289
張 CON
AH34 VSS VSS AG37 AC8 VSS VSS U52 AM27 VDDC VDDC AC37 BF29 VDDR1 VDDCI BC24
AJ36 VSS VSS AG31 AD45 VSS VSS U2 AT37 VDDC VDDC AD23 BG14 VDDR1 VDDCI BB26
AJ17 VSS VSS AG28 AD5 VSS VSS U16 AM28 VDDC VDDC AD24 BH12 VDDR1 VDDCI BB27
AJ26 VSS VSS AG23 AF11 VSS VSS U14 AT42 VDDC VDDC AD28 BJ10 VDDR1 VDDCI V22
22uF
22uF
22uF
22uF
22uF
AJ33 VSS VSS AF43 AF5 VSS VSS T55 AN21 VDDC VDDC AD29 BJ11 VDDR1 VDDCI W24
AJ41 VSS VSS AF37 AF55 VSS VSS T5 AN22 VDDC VDDC AD31 BJ14 VDDR1 VDDCI V28
文
C1230
C1231
C1232
C1233
C1234
C1235
C1236
C1237
C1238
C1239
C1430
C1431
C1432
C1433
C1434
C1435
C1436
C1437
C1438
C1439
C1325
C1326
C1327
C1328
C1329
C1330
C1331
C1332
W22 AF31 AG12 T17 AN26 AD34 BK10 V29
F
AL19 VSS VSS AF27 AG2 VSS VSS R9 AN27 VDDC VDDC AD36 BK11 VDDR1 VDDCI V31
AL27 AF21 AG48 R58 AU32 AL31 BL15 V32
RM 　 ID
AL42 VSS VSS AD38 AG58 VSS VSS R48 AU33 VDDC VDDC AD37 BL21 VDDR1 VDDCI U29
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
AM21 VSS VSS AD22 AH5 VSS VSS R44 AU37 VDDC VDDC AL32 BM8 VDDR1 VDDCI V38
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
C1290
C1291
C1292
C1293
C1294
AM26 VSS VSS AD17 AJ11 VSS VSS R30 AU38 VDDC VDDC AL39 BN29 VDDR1 VDDCI V39
AM31 VSS VSS AC41 AJ49 VSS VSS R27 BB37 VDDC VDDC AF24 H48 VDDR1 VDDCI W26
A( RD EN
AM36 VSS VSS AC34 AK15 VSS VSS R24 AP24 VDDC VDDC AL37 J18 VDDR1 VDDCI W28
AN17 VSS VSS AC26 AL14 VSS VSS R2 AP26 VDDC VDDC AF26 J24 VDDR1
22uF
22uF
22uF
22uF
22uF
AM18 VSS VSS AC21 AL8 VSS VSS R18 AP29 VDDC VDDC AF29 J30 VDDR1
C AN24 VSS VSS AC18 AN12 VSS VSS R12 AV33 VDDC VDDC AL38 J33 VDDR1 C
吳 (C TI
AN29 VSS VSS AB41 AP11 VSS VSS P8 AV34 VDDC VDDC AF33 J36 VDDR1
AN32 VSS VSS AB34 AP5 VSS VSS P55 AV38 VDDC VDDC AF34 M42 VDDR1
C1240
C1241
C1242
C1243
C1244
C1245
C1246
C1247
C1248
C1249
C1440
C1441
C1442
C1443
C1444
C1445
C1447
C1448
C1449
AP27 VSS VSS W29 AR2 VSS VSS P52 AV39 VDDC VDDC AF36 J45 VDDR1
AP32 VSS VSS AA43 AT14 VSS VSS P5 AT23 VDDC VDDC AF39 K10 VDDR1 VSS BH40
積 )2 AL
AP37 VSS VSS AA36 AU11 VSS VSS P34 AT24 VDDC VDDC AG21 K49 VDDR1 VSS BF39
AT17 VSS VSS AA28 AU8 VSS VSS P31 AT28 VDDC VDDC AM32 K50 VDDR1 VSS BK50
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
AT22 VSS VSS G58 AW9 VSS VSS P20 AW31 VDDC VDDC AG22 L11 VDDR1 VSS BL42
AT27 VSS VSS G53 AY5 VSS VSS P17 AW34 VDDC VDDC AM33 L14 VDDR1 VSS BK30
源 01
AT34 VSS VSS E48 B11 VSS VSS P14 AW36 VDDC VDDC AG26 L17 VDDR1 VSS BJ36
AT39 VSS VSS E46 B15 VSS VSS N58 AW39 VDDC VDDC AM37 L20 VDDR1 VSS BJ31
AP17 VSS VSS E44 B19 VSS VSS N2 AW41 VDDC VDDC AG27 L31 VDDR1 VSS BF31
AV19 VSS VSS E42 B23 VSS VSS M8 BA32 VDDC VDDC AM38 L43 VDDR1 VSS AY46
)
AU36 VSS VSS E40 B27 VSS VSS M55 BA36 VDDC VDDC AG32 L49 VDDR1 VSS AK55
20
AU41 VSS VSS E38 B31 VSS VSS M52 AU22 VDDC VDDC AM39 L50 VDDR1 VSS AK48
AV17 VSS VSS E36 B35 VSS VSS M45 AU23 VDDC VDDC AG34 M12 VDDR1 VSS BG34
C1451
C1452
C1453
C1454
C1455
C1456
C1457
C1458
C1459
C1250
C1251
C1252
C1253
C1254
C1255
C1256
C1257
C1258
C1259
C1450
AV24 VSS VSS E34 B39 VSS VSS J42 BA37 VDDC VDDC AG38 M24 VDDR1 VSS BE43
AV31 VSS VSS E32 B49 VSS VSS M39 BA41 VDDC VDDC AG39 N46 VDDR1 VSS BF37
6
AV36 VSS VSS E30 B53 VSS VSS M36 AU28 VDDC VDDC AH22 P11 VDDR1 VSS BU30
AV41 VSS VSS E24 B9 VSS VSS M33 AU29 VDDC VDDC AH23 P23 VDDR1 VSS BR30
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
AW17 E22 BB12 M30 BA42 AH27 P26 BK46
05
VSS VSS VSS VSS VDDC VDDC VDDR1 VSS
AW23 VSS VSS E20 BB5 VSS VSS M27 BB41 VDDC VDDC AN33 P29 VDDR1 VSS BJ43
AW29 VSS VSS E18 BC2 VSS VSS M21 BA31 VDDC VDDC AH28 P37 VDDR1 VSS BJ33
AW42 VSS VSS E16 BD15 VSS VSS M18 BB33 VDDC VDDC AN34 P40 VDDR1 VSS BH48
BA17 E14 BD5 M15 AU21 AH31 P46 BE30
00
VSS VSS VSS VSS VDDC VDDC VDDR1 VSS
AW19 VSS VSS E12 BE18 VSS VSS L51 BB42 VDDC VDDC AH32 P47 VDDR1 VSS AK57
BA33 VSS VSS E10 BE24 VSS VSS L48 AV21 VDDC VDDC AN39 P49 VDDR1 VSS AK51
BA38 VSS VSS D59 BF21 VSS VSS L46 AV22 VDDC VDDC AH33 R21 VDDR1 VSS BR48
BA43 VSS VSS D1 BF5 VSS VSS L40 BC33 VDDC VDDC AN41 R33 VDDR1 VSS AL46
1
C1260
C1261
C1262
C1263
C1264
C1265
C1266
C1267
C1268
C1269
C1460
C1461
C1462
C1463
C1464
C1465
C1466
C1467
BB18 VSS VSS C10 BG2 VSS VSS L37 AV26 VDDC VDDC AH37 R51 VDDR1 VSS BK53
BB28 VSS VSS BW4 BH15 VSS VSS L34 AV27 VDDC VDDC AM41 T15 VDDR1 VSS BK55
BB32 VSS VSS BV9 BH27 VSS VSS L29 AV28 VDDC VDDC AH38 T20 VDDR1 VSS AP43
BB36 VSS VSS BV7 BH5 VSS VSS L26 AP31 VDDC VDDC AH41 T43 VDDR1 VSS AN43
22uF
22uF
22uF
22uF
22uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
22uF
22uF
22uF
BC18 VSS VSS BV29 BJ12 VSS VSS L23 AW21 VDDC VDDC AH42 T45 VDDR1 VSS AN42
BC21 VSS VSS BV27 BJ2 VSS VSS L2 AW24 VDDC VDDC AJ22 U11 VDDR1
BC26 VSS VSS BV25 BJ21 VSS VSS K55 AW26 VDDC VDDC AJ23 U18 VDDR1
B BC28
BC32
VSS VSS AJ44
A4
BJ26
BK8
VSS VSS K52
K5
AW27
AW22
VDDC V9
V48
VDDR1 B
VSS VSS VSS VSS VDDC VDDR1
BC37 VSS VSS BM10 BL18 VSS VSS K3 BB31 VDDC FB_VDDC AU42 FB_VDDC OUT 17 19 Y11 VDDR1
U19 VSS VSS BM12 BL24 VSS VSS J9 BA29 VDDC FB_VSSC AV43 FB_VSSC OUT 17 19 Y16 VDDR1 FB_VDDCI BE31 FB_VDDCI OUT 18 19
U22 VSS VSS BM20 BL9 VSS VSS J58 Y46 VDDR1 FB_VSSCI BD31 FB_VSSCI OUT 18 19
U24 VSS VSS BM23 BM17 VSS VSS J51 Tahiti
U34 VSS VSS BM26 BR18 VSS VSS J49 Tahiti
U37 VSS VSS BM29 BV17 VSS VSS J39
U39 VSS VSS BM5 C57 VSS VSS J27
U42 VSS VSS BN2 E28 VSS VSS J2
V19 VSS VSS BN7 E50 VSS VSS J15
W32 VSS VSS BR10 H37 VSS VSS H8
AD41 VSS VSS BR12 J21 VSS VSS H55
V43 VSS VSS BR14 L12 VSS VSS H52
W18 VSS VSS BR20 M11 VSS VSS H50
W23 VSS VSS BR22 M5 VSS VSS H5
W33 VSS VSS BR24 P43 VSS VSS H46
AB24 VSS VSS BR26 R42 VSS VSS H43
AD33 VSS VSS BR28 U49 VSS VSS H40
AH21 VSS VSS BR8 W58 VSS VSS H31
AL36 VSS VSS BT1 AE2 VSS VSS H29
AP22 VSS VSS BU3 AJ8 VSS VSS H26
AU31 VSS VSS BV11 AW15 VSS VSS H23
AW37 VSS VSS BV13 B45 VSS VSS H17
BB43 VSS VSS BV19 BF11 VSS VSS H14
U33 VSS VSS BV21 BJ9 VSS VSS H12
AA41 VSS VSS BV23 G2 VSS VSS H10
Tahiti Tahiti

SHEET: TAHITI POWER schematic and design, including, not limited to, any implied warranty

TITLE
NOTES: NOTE
9 8 7 6 5 4 3 2 1
9 8 7 6 5 4 3 2 1
(13) TAHITI THERMAL MECH
E +3.3V_BUS E
USE Q203 2020002300G, R200, R249, D1719
AND C3609 FOR CHEAPER FAN CONTROLLER.
C200 C201 C202 REQUIRES BIG CHANGE IN FAN TABLE.

10uF 1uF 100pF
DNI DNI DNI
+3.3V_BUS TCRIT R200 DNI 0R CTF_GATE2
GPU_DMINUS 13 19 13 19
GPU_DPLUS
OUT U200
OUT 13 19 13 19 +12V_EXT_A +12V_EXT_B +12V_BUS
R201 1 10 DDC6CLK_R DNI DDC6CLK
2.61K TCRIT SMBCLK R202 100R
IN 8
U1 DNI
+1.8V 2 9 DDC6_DATA_R R203 DNI DDC6DATA
1
Thermal VDD SMBDAT 100R
BI 8
Part 20 of 20
B201 1 2 BLM15AG121SN1D +TSVDD BK59 TSVDD DPLUS AL44 GPU_DPLUS 3 D+ TACH 8 GPIO_6_TACH NB200 MB200 B200
C203 0.0022uF 50V 220R_2A 220R_2A 220R_2A
AL45 GPU_DMINUS 4 7 ThermINT DNI GPIO_17_THERMAL_INT DNI DNI
C204 C205 DMINUS D- ALERT R204 0R
OUT 8
1uF 0.1uF
2
R237 20K +3.3V_BUS
LM_PWM 5 PWN GND 6 FANOUT_P
BK57 TSVSS TMON_CAL BH43 TMON_CAL TP200
TP201 11 THMPAD MC200
10uF
Tahiti 16V R240
20K
2
LM96163CISD
DNI
1 R213
Q211 0R
DNI
AO3415L
R243
D +3.3V_BUS +3.3V_BUS +12V_BUS 20K
D
00
3
07
R206 R207 R208
5.1K 10K 10K
DNI J200
PWM_FAN 4
GPIO_6_TACH R209 1K 3
3
8
74
OUT FANOUT_P_Q 2
R205
M
0R PWM_b R210 1K 1 Q200 1
DNI
MMBT3904
3
R211
65 SI　
19 8 GPIO_28_FDO R212 10K PWM 1 3.83K
IN Q201 1X4 3A 2MM
2
MMBT3904
2
R247 DNI 20K 1 Q216 For 4-WIRE FAN ONLY
MMBT3904
3
DNI
2
　
CTF_OUT R246 20K 1 Q202
MMBT3904
2
1
This circuit provides a
張 CON
+12V_BUS minimum voltage for the fan,
PX_EN R252 DNI 20K independent of PWM input
3
3
14 13 1 PERST#_buf R214 10K PERST#_buf_R 1 Q203 R215
IN 0R 19 IN D200
MMBT3904 DNI BAT54S +12V_BUS
R217
2
DNI
文
5.1K
3
DNI
F
1 Q215
2
R216 R244 20K
2.61K MMBT3904
RM 　 ID
DNI
2
R218 FANOUT_P
+12V_BUS 1K
To maximize fan output DNI
during CTF trigger.
3
R219
R220 1 6.8K 20K 1
1
1K Q204 DNI R245
1
+
A( RD EN
MMBT3904 C206 + Q212
Critial Temperature Fault 10uF C212
2
R221 DNI 100uF MMBT3904
2.61K 10V
2
J201
2
DNI DNI
1
C CTF By-pass
C
吳 (C TI
R222 DNI 100K Pfb 1 1 Nfb R223 DNI 820R FANOUT_N 2
For one time CTF use R223 47k.
+3.3V_BUS +3.3V_BUS Q205 Q206 HDR_1X2
MMBT3906 MMBT3906
3
DNI DNI DNI
For resetable CTF use R223 2k. R224
積 )2 AL
C207 R225 1M R226
1uF 1M DNI
0R
DNI DNI DNI
R227
3
20K
2
4
1 Q214
2
源 01
Q207 TCRIT R228 DNI 0R VDDC_OE 2N7002 Vdiff 1
1 MMBT3906 OUT 14 15 17 Q208
2
DNI BCP68
R248 DNI Header is 2mm, and
3
3
C211 1M it does not follow
DNI 1 Q209 1uF
3
R229 R230 1K R231 2.54mm spacing as 4-pin
16V
)
20K MMBT3904 DNI 1K PWM Fan Specification
DNI
20
DNI
DNI
2
CTF_OUT
CTF_GATE2 Place close to its CTLR
3
1 Q210 R232
6
MMBT3904 20K DNI D201
TCRIT MR228 0R INPUT_RAILS_UP 1 14 15 16 1N4148W For 2-WIRE FAN ONLY
OUT 2 1 DNI FAN_EN
2
05
MR230 1K 1 MQ209
GPIO_19_CTF R233 4.7K R234 47K MMBT3904
8 IN
2
R235
100K
C209
0.01uF
00
1
+3.3V_BUS
1
D202 3 R238 DNI 2.2K CTF_OUT 19

BAT54S IN
+3.3V_BUS
C208
0.1uF
R239
B 1K B
2
14 13 1 PERST#_buf
IN
8
7
U201
2
R250 1 Q213 2 5
Vcc
PR
19 14 1 PX_EN 20K R253 D Q
IN MMBT3906 10K
DNI
3
1 3 R249 499K
C Q
CL
G
3
1 Q217 NC7SZ74K8X
MMBT3904
4
6
R241
33K
1
DNI
C210
22uF
2
+12V_BUS +3.3V_BUS
R255 R251
SK200 20K 20K
3
NA DNI
MT213 1 Q218
NA 2N7002
3
HS200
1 Q219
2
PERST#_buf R254 100K
MMBT3904
2
C213
1uF
16V
1
2
3
4
5
6
7
8
9
NA
SHEET: TAHITI THERMAL schematic and design, including, not limited to, any implied warranty
DATE: Thu Nov 03 14:35:49 2011 REV: 1.0 information included herein.

TITLE
NOTES: NOTE
9 8 7 6 5 4 3 2 1
9 8 7 6 5 4 3 2 1
(14) POWER MGMNT
+3.3V_BUS
E E
R1010
+3.3V_BUS 10K
+12V_BUS
R1003 INPUT_RAILS_UP 1 13 15 16
5.11K OUT +3.3V_BUS
3
1 +3.3V_BUS
R1004 Q1000
11.3K MMBT3904
3
C1005 R1050
1 0.1uF 10K
2
Q1001
MMBT3904
R1033
+12V_EXT_A +1.8V 10K VDDC_OE
DNI OUT 13 15 17
3
R1000 0R R1005
+12V_EXT_A_CON +12V_EXT_A 1K
1 Q1030
R1001 0R MMBT3904
J1000 R1006 R1031 DNI
11.3K 10K
3
+12V 1 1
L1000 20.47uH DNI
2
2 DNI
+12V 1 1
3 Q1002 Q1031
+12V C1000 MMBT3904 MMBT3904
47pF DNI
C1001
2
10uF R1007 R1032 C1020
1K 10K 0.1uF
DNI DNI
GND 4
GND 6
3
Sense 5 6P_SENSE_A R1002 DNI 0R SENSE_A_GND_PIN
8P_SENSE_A MR1002 0R BUS 12V and AUX A Power up Seq 19 13 1 PX_EN R1034 10K 1 Q1032
D 6P_HDER C1002 IN MMBT3904 D
00
47pF
DNI
DNI
2
R1035
10K
DNI
+12V_EXT_A_CON
07
3
MJ1000
74 M
+12V 1
13 1 PERST#_buf R1036 10K 1 Q1033 R1038
+12V 2 IN MMBT3904 0R
65 SI　
+12V 3 DNI
2
R1037
10K
DNI
　
GND
GND 7 +12V_BUS
GND 8
張 CON
SENSE_1 6
SENSE_2 4 +3.3V_BUS
R1023
10K
PCIX_POWER_8_POS C1003
3
47pF
文 F
R1024 1 Q1020
2.32K MMBT3904
3
RM 　 ID
1
2
Q1021 C1026
MMBT3904 0.1uF
+12V_EXT_B
A( RD EN
2
R1020 0R R1025
1K +3.3V_BUS +3.3V_BUS
+12V_EXT_B_CON +12V_EXT_B
R1021 0R
J1001 R1026
C C
吳 (C TI
11.3K
3
+12V 1 1
L1001 20.47uH
2 DNI
+12V 1 R1040 R1041
3 Q1022 10K 10K
+12V C1022 MMBT3904
47pF
積 )2 AL
MVDD_VID0 17
C1021 OUT
2
R1027 MVDD_VID1 17
10uF
1K OUT
GND 4 R1042 R1043
源 01
6 10K 10K
GND
DNI DNI
Sense 5 6P_SENSE_B R1022 0R SENSE_B_GND_PIN
)
8P_SENSE_B MR1022 DNI 0R
BUS 3.3V and 12V AUX B 6PIN/8PIN Power up Seq
20
6P_HDER C1023
47pF
MJ1001
1
+12V_EXT_B_CON
6 05
00
+12V
+12V 2
+12V 3
GND
GND
GND
SENSE_1
5
7
8
6
1 +3.3V_BUS
R1048
10K
B SENSE_2 4
VDDC_PWR_GOOD 1
R1047 DNI 2
0R
B
18 17 IN
PCIX_POWER_8_POS C1024 18 IN VDDCI_PWR_GOOD 1
R1049 2
0R MVDD_EN OUT 17
47pF
DNI DNI
+3.3V_BUS
R1046
10K
17 IN MVDD_VR_HOT R1045 DNI 0R

17 IN VDDC_VR_HOT 1
R1044 2
0R GPIO_5_REG_HOT OUT 8

SHEET: POWER MNGMNT schematic and design, including, not limited to, any implied warranty

TITLE
NOTES: NOTE
9 8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(15) BIF, 5V, 1.8V REG
D D
Regulators for +5V, and +5V_VESA
+12V_BUS
U400 +5V_VESA 150mA
00
MC78M05CDT
1 IN OUT 3 F400 1 2 NA
4 C401 C402
07
GND
TAB
C400 1uF 1uF
1uF
2
74 M
65 SI　
+12V_BUS
EN PIN: DNI
C350 0.0068uF R350 DNI 3.65K R351 200K 1V8_FB_TRACE
<0.4V, Disable;
>1.6V, Enable.
1.8V_FB R353 0R
R352
　
158K R401 R402 +5V +5V_VR
C 16 14 13 1 IN INPUT_RAILS_UP 360R
DNI
360R
DNI
C
張 CON
1
C351 U350 R400 0R R403 0R
2.2uF 10 EN/SYNC FB 1
NS350
1
Sense Point
9 2 +1.8V D400
GND GND ML350 2.2uH_3.25A BZT52C5V1
+3.3V_BUS
2
DNI DNI
2
文
8 SW2 SW1 3 1V8_PHASE 1 2
F
1 2
7 IN2 IN1 4 C355 C356 C357 C358 C359 C360 C361
RM 　 ID
L350 1.0uH_7.5A 0.1uF 22uF 22uF 22uF 22uF 22uF 22uF
THM
THM
6 5 OVERLAP
C352 C354 C353 POK BS
22uF 22uF 0.1uF
1
DNI
MP28115
R357 D350
A( RD EN
12
11
0R BAT54KFILM
2
C363
吳 (C TI
0.1uF
1V8_PHASE +12V_BUS
U401 +5V_VR
MC78M05CDT
DNI
積 )2 AL
1 IN OUT 3 R404 0R
R367 0R VDDC_OE 13 14 17
OUT 4 C404 C405
GND
TAB
C403 1uF 1uF
1uF
源 01
2
B ) 20 B
6 05
00
1

SHEET: BIF 1.8V 5V REG schematic and design, including, not limited to, any implied warranty

TITLE
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(16) 0.94V REG

+5V
R300 2.2R R301 0R
share pad
GND
D 0.935V_LGD D
R302 C300
22.1K 0.1uF
1%
0.935V_PHASE C301
0.1uF R325 1.65K
R326 0R R303 3.65K

Current Sensing
C302 +VCC
20
19
18
17
16
0.1uF 0.935V_CCSP
603 0.935V_CCSN
C303
0.1uF
PHASE
LG
VCC
DROOP
CSP
Differential trace from Inductor
R304
0R
+5V D300
BAT54KFILM
2 1 1 BOOT CSN 15 R305 1.65K
00
R327 0R
0.935V_HGD 2 UG EN/PSM 14 R306 10K INPUT_RAILS_UP 1 13 14 15

IN
07
C305 0.015uF
R307
3 13 10K
POK U300 VID1
R309 8.06K
74 4 RSET3
M VID0 12
65 SI　
+12V_BUS
C306 0.027uF R310 0R
R311 8.06K 5 MODE/RSET2 COMP 11 0.935V_REG_COMP R312 8.06K 2 1
　
C308 0.015uF
C NS300 C
REFIN/RSET1
C309 Sense Point
22 GND2 0.01uF
張 CON
25V
21
FBRTN
RSET0
GND1
RT
FB
C311
NA R313 10pF
20K 50V
10
1%
文
RM 　 ID F
17.4K
17.4K
17.4K
0.015uF
17.4K
0.015uF
0.015uF
0.015uF
0.935V_FB
+0.94V
A( RD EN
NS301
R318 1K R317 12R 1 2
C313
C314
C315
C316
0.935_FB_TRACE
R319
R320
R321
R322
Reserve for
R323
吳 (C TI
0R Loop Test Sense Point
積 )2 AL
For UP1509 (2480103300G), voltage with following resistors:
0.935V_CCSP
VID0: 1.2 * R322/R302
VID1: 1.2 * R321/R302
VID2: 1.2 * R320/R302
源 01
VID3: 1.2 * R319/R302
B
+12V_BUS
) 20 B
0.935V_HGD
C310
0.027uF
50V
C320
10uF
25V
6
C321
10uF
25V
05
00
1
1
FDMC8200
Q300
+0.94V
L301
2.2uH_8A
10
0.935V_PHASE 1 2
0.935V_LGD
1
+ C317
330uF
2
2V C318
R324 22uF
2
NS302
NS303
2.2R 4V
Sense Point
C319
1
0.0033uF
50V

Place Rs and Cs across QL
Route like AMD - GRAPHICS C 2010 Advanced Micro Devices
0.935V_CCSP
0.935V_CCSN
differential pair 1 COMMERCE VALLEY This AMD Board schematic and design is the exclusive property of AMD, and
SHEET: 0.94V REG schematic and design, including, not limited to, any implied warranty

TITLE
Ref: Released ver 1 of P00790
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L500
+12V_BUS +12V_EXT_B TEMPERATURE SENSE
1
1 2 Place near VDDC phase
0.47uH C648 C649 Route traces as differential pair
R583 0.01R 10uF 10uF
+12V_EXT_B 16V 16V
R584
2
0.01R
1
47K
C646 C647 1 2
10uF 10uF +VDDC Q520 +VDDC
6
1
1
+ 16V 16V NTC500
5
1
CB501 C591 C592 C593 C594 L510 L520
NS500
270uF 10uF 10uF 1uF 0.1uF 1 2 + CB502 C600 C601 C602 C603 2 4 1 2
16V 16V 16V 16V 16V 270uF 10uF 10uF 1uF 0.1uF 1
2
2
Q510 150nH 16V 16V 16V 16V 16V 150nH +12V_EXT_B +12V_BUS
6
2
C511 C512 C521 C522
5 0.1uF 0.01uF 0.1uF 0.01uF
2
16V 10V R589 13K
2 4 16V 10V 1K
3
R500
2
1 R514
1
NS510
NS511
NS520
NS521
C500 1000pF 1K
1
7
6
5
4
7
6
5
4
C604 C605 C606 C607 C608
C595 C596 C597 C598 C599 10uF 10uF 10uF 1uF 0.1uF 50V C518 0.1uF
10uF 10uF 10uF 1uF 0.1uF 16V 16V 16V 16V 16V
2
16V
D 16V 16V 16V 16V 16V R501 NS501 D
2
1
Route FB_VDDC traces
+12V_EXT_A 13K R581 1K 1 2
Q511 Q521 as differential pair
R510 0R C510 0.1uF 3 VDDC_ISENN1 R520 0R C520 0.1uF 3 VDDC_ISENN2
16V VDDC_ISENP1 16V VDDC_ISENP2 R502 1K R508 0R FB_VSSC 12 19
U510 U520 J500
IN
+12V_EXT_B 1 REGLTR_SCL C501 1000pF +3.3V_BUS R509 0R FB_VDDC
Route as Route as IN 12 19
1 10 1 10 2 50V
1
2
1
2
BOOT HI_GATE differential BOOT HI_GATE differential REGLTR_SDA
4 VCC SWITCH 9 pair 4 VCC SWITCH 9 pair R582 1K 1 2
VDDC_PWM1 3 6 VDDC_PWM2 3 6 header_1x2_2mm_smt R503 R564
PWM LO_GATE PWM LO_GATE C644 C645 +12V_EXT_B
C513 C514 10pF 10pF +12V_BUS 13K NS502
1uF 0.1uF C523 C524 50V 50V 75R 1%
16V 16V 2 8 R569 0R 1uF 0.1uF 2 8 R570 0R J501 13K +VDDC
HVCC MODE 16V 16V HVCC MODE R590
5 LVCC GND 7 5 LVCC GND 7 1 R504 1K C506 0.47uF
GND 11 GND 11 2 6.3V
C515 C516 C525 C526 C502 1000pF +3.3V_BUS
+5V_VR 4.7uF 0.1uF +5V_VR 4.7uF 0.1uF header_1x2_2mm_smt 50V
6.3V 16V 6.3V 16V 4.7uF
TEMPERATURE COMP
+12V_EXT_B C507 C5051000pF
CHL8510CRT CHL8510CRT
13 14 15
R505 6.3V 50V
+MVDD +VDDC
19
Route traces as differential pair

13K +3.3V_BUS C528
19
C503 0.01uF 0.1uF
Place near VDDC output inductor

00
R585 R586 16V
8
25V
14
14
18
14
14
14
14
0.01R 0.01R
8
+12V_EXT_A
+12V_EXT_A
R706 R519
BI
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
R587 0.01R 100R 100R Close to VDDC R506
07
Close to MVDD
R588 0.01R
1
1
Q540 Output Caps Output Caps 6.19K
C650 C651
+VDDC
CA504 + CB504 + C618 C619 C620 6 +VDDC
V_BOOT = 1.00V
10uF 10uF 100uF 150uF 10uF 10uF 1uF 5 R516
1
16V 16V L530 16V 16V 16V 16V 16V L540

+ + 1 2 2 4 1 2
2
2
CA503 CB503 C609 C610 C611 C612 1.24K
74
100uF 150uF 10uF 10uF 1uF 0.1uF 1 C504 0.01uF
M
150nH 150nH
NTC501
16V 16V 16V 16V 16V 16V Q530
GPIO_15_VDDC_VID0
GPIO_20_VDDC_VID1
R517
1.78K
6
2
C531 C532 C541 C542 25V C519

5 0.1uF 0.01uF 0.1uF 0.01uF 82pF
10K
65 SI　
VDDC_PWR_GOOD
16V 10V 16V 10V 50V
2 4
1
2
VDDC_VR_HOT
R507 R518
10K
REGLTR_SCL
REGLTR_SDA
1
10K
MVDD_VID1
MVDD_VID0
MVDD_VR_HOT
NS530
NS531
NS540
NS541
4.32K
1
7
6
5
4
7
6
5
4
C621 C622 C623 C624 C625 C626 1.24K
VDDC_OE
MVDD_EN
C613 C614 C615 C616 C617 0.1uF 10uF 10uF 10uF 1uF 0.1uF VMAX = 1.381V
10uF 10uF 10uF 1uF 0.1uF 16V 16V 16V 16V 16V 16V
3
Route traces as differential pair

16V 16V 16V 16V 16V
　
R712
R524
2
11 R525
R515
C Q531 Q541 7.5K C
2
R540 0.1% 301R 1%
TEMPERATURE SENSE
R700
NTC700
R530 0R C530 0.1uF 3 VDDC_ISENN3 C540 0.1uF 3 VDDC_ISENN4 C718
張 CON
47K
1K
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
10
16V VDDC_ISENP3 16V VDDC_ISENP4 0.1uF
1
0R 16V
U530 U540 C717
Place near MVDD phase

0.1uF
+12V_EXT_A NS700 16V
VAR_GATE
WARM_RESET-E1/TSEN2-E2
VMAX
VBOOT
SCL
SDA
SMB_ALERT-E1/VIDSEL1_L2-E2
ENABLE
VR_HOT/PROCHOT_IOUT_CRITICAL
VIDSEL0_L1
VIDSEL1_L1
VIDSEL0_L2
VINSEN_AUX_2
VINSEN_AUX_1
VINSEN
NC-E1/EN_L2-E2
VR_READY_L2
VR_READY_L1
V18A
TSEN
RRES
VRTN
VSEN
PSI-E1/VR_HOT_L2-E2
VCC
RCSM
RCSP
ISEN8
Route as Route as
1 10 1 10 1 2
1
2
1
2
BOOT HI_GATE differential BOOT HI_GATE differential R715
4 VCC SWITCH 9 pair 4 VCC SWITCH 9 pair
文
VDDC_PWM3 3 PWM LO_GATE 6 VDDC_PWM4 3 PWM LO_GATE 6 100K 1%
F
C533 C534 C543 C544
1uF 0.1uF 2 HVCC MODE 8 R571 0R 1uF 0.1uF 2 HVCC MODE 8 R572 0R R711
16V 16V 16V 16V 301R
RM 　 ID
5 LVCC GND 7 5 LVCC GND 7 57 GND
GND 11 GND 11
C535 C536 C545 C546 58 GND
MVDD_ISENN
MVDD_ISENP
CPU6208CRT
+5V_VR 4.7uF 0.1uF +5V_VR 4.7uF 0.1uF
6.3V 16V 6.3V 16V
A( RD EN
U500
CHL8510CRT CHL8510CRT 59 GND
60 GND
吳 (C TI
61 GND
62 GND
+12V_EXT_A +12V_EXT_A
積 )2 AL
Q550 +VDDC Q560 +VDDC
6 6
RCSM_L2
RCSP_L2
VSEN_L2
VRTN_L2
5 5
1
IRTN 8
IRTN 1
ISEN 1
IRTN 2
ISEN 2
IRTN 3
ISEN 3
IRTN 4
ISEN 4
IRTN 5
ISEN 5
IRTN 6
ISEN 6
IRTN 7
ISEN 7
L550 L560
PWM8
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
+ CC505 + C627 2 4 1 2 + + 2 4 1 2
VCC
CA505 C628 C629 C630 CA506 CB506 C636 C637 C638
100uF 150uF 10uF 10uF 1uF 0.1uF 1 150nH 100uF 150uF 10uF 10uF 1uF 1 150nH
源 01
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
2
2
C551 C552 C561 C562
0.1uF 0.01uF 0.1uF 0.01uF R713 301R
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
16V 16V 10V MVDD_ISENN
10V
3
3
2
2
1
VDDC_PWM6
VDDC_PWM5
VDDC_PWM4
VDDC_PWM3
VDDC_PWM2
VDDC_PWM1
)
NS550
NS551
NS560
NS561
MVDD_PWM
7
6
5
4
7
6
5
4
C631 C632 C633 C634 C635
20
10uF 10uF 10uF 1uF 0.1uF C639 C640 C641 C642 C643
16V 16V 16V 16V 16V 0.1uF 10uF 10uF 1uF 0.1uF
2
16V 16V 16V 16V 16V

1
1
Q551 Q561
B B
6
R550 C550 0.1uF 3 VDDC_ISENN5 R560 0R C560 0.1uF 3 VDDC_ISENN6
0R 16V VDDC_ISENP5 16V VDDC_ISENP6 NS701
05
U550 U560 R701 1 2
+12V_EXT_A +12V_EXT_A
Route as Route as R567 R568 0R
1 10 1 10 C720
1
2
1
2
BOOT HI_GATE differential BOOT HI_GATE differential 1000pF +MVDD
4 VCC SWITCH 9 pair 4 VCC SWITCH 9 pair 0R 0R 50V
00
VDDC_PWM5 3 PWM LO_GATE 6 VDDC_PWM6 3 PWM LO_GATE 6 R513 R512 R523 R522 R533 R532 R543 R542 NS702
301R 301R 301R 301R 301R 301R 301R 301R R702 1 2
C553 C554 C563 C564
1uF 0.1uF 2 HVCC MODE 8 R573 0R 1uF 0.1uF 2 HVCC MODE 8 R574 0R R553 R552 R563 R562 0R
16V 16V 16V 16V 301R 301R 301R 301R
5 LVCC GND 7 5 LVCC GND 7 C517 0.1uF C527 0.1uF C537 0.1uF C547 0.1uF
1
GND 11 GND 11 16V 16V 16V 16V +3.3V_BUS
C555 C556 C565 C566 C557 0.1uF C567 0.1uF
+5V_VR 4.7uF 0.1uF +5V_VR 4.7uF 0.1uF R575 R576 R577 R578 16V 16V
6.3V 16V 6.3V 16V R565
CHL8510CRT CHL8510CRT 100K 1% 100K 1% 100K 1% 100K 1% VDDC_PWM6
R579 R580
C508 C509 0R
R511 R521 R531 R541 100K 1% 100K 1% 0.1uF 1uF
+VDDC 301R 301R 301R 301R 16V 10V R566
VDDC_PWM5
Output Bulk Caps R551
301R
R561
301R
0R
1
1
+12V_EXT_A + CB507 + CB508 + CB509 + CB510 + CB511 + CB512 + CB513 + CB505
Q710 820uF 820uF 820uF 820uF 820uF 820uF 820uF 820uF R703
VDDC_ISENN1
VDDC_ISENP1
VDDC_ISENN2
VDDC_ISENP2
VDDC_ISENN3
VDDC_ISENP3
VDDC_ISENN4
VDDC_ISENP4
VDDC_ISENN5
VDDC_ISENP5
VDDC_ISENN6
VDDC_ISENP6
+MVDD 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
6
2
2
1.24K
5 TEMPERATURE COMP
NTC701
1
L700
+ + C721 C719
R704
2 4 1 2
1.78K
CA700 CB700 C722 C723 C724 82pF Place near MVDD output inductor
100uF 150uF 10uF 10uF 1uF 0.1uF 1 +VDDC 50V
1
16V 16V 16V 16V 16V 16V 150nH Route traces as differential pair
10K
+ + Output MLCC
2
1
C711 C712 CB701 CB702 R705
0.1uF 0.01uF 560uF 820uF
16V 10V 2.5V 2.5V
3
2
2
1.24K
C529
C538
C539
C548
C549
C558
C559
C568
C569
C570
1
NS710
NS711
7
6
5
4
C725 C726 C727 C728 C729

10uF 10uF 10uF 1uF 0.1uF
16V 16V 16V 16V 16V
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
4V
4V
4V
4V
4V
4V
4V
4V
4V
4V
2
C730 C731 C732 C733 C734 C735 C736

+VDDC
AMD - GRAPHICS
1
4V 4V 4V 4V 4V 4V 4V C 2010 Advanced Micro Devices

22uF
22uF
22uF
22uF
22uF
22uF
22uF
Q711
R710 C710 0.1uF 3 MVDD_ISENN 1 COMMERCE VALLEY This AMD Board schematic and design is the exclusive property of AMD, and
A 0R 16V MVDD_ISENP MARKHAM, ONTARIO, L3T 7X6 is provided only to entities under a non-disclosure agreement with AMD A
C571
C572
C573
C574
C575
C576
C577
C578
C579
U710 C580 for evaluation purposes. Further distribution or disclosure is strictly

+12V_EXT_A prohibited. Use of this schematic and design for any purpose other than
Route as evaluation requires a Board Technology License Agreement with AMD.
1 10
1
2
BOOT HI_GATE differential

22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
4V
4V
4V
4V
4V
4V
4V
4V
4V
4V
4 9 AMD makes no representations or warranties of any kind regarding this

VCC SWITCH pair +VDDC
SHEET: VDDC+MVDD schematic and design, including, not limited to, any implied warranty
MVDD_PWM 3 PWM LO_GATE 6 C737 C738 C739 C740 C741 C742 C743
C713 C714 4V 4V 4V 4V 4V 4V 4V
22uF
22uF
22uF
22uF
22uF
22uF
22uF
1uF 0.1uF 2 8 R714 responsibility for any consequences resulting from use of the
16V 16V HVCC MODE 0R DATE: Wed Nov 02 15:28:38 2011 REV: 1.0 information included herein.
5 LVCC GND 7
C581
C582
C583
C584
C585
C586
C587
C588
C589
C590
GND 11
+5V_VR
C715 C716 SHEET NUMBER: 17 OF 21 TITLE:
4.7uF 0.1uF
6.3V 16V
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
22uF
4V
4V
4V
4V
4V
4V
4V
4V
4V
4V
CHL8510CRT TITLE
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
+12V_BUS
ML900
1 2
L901 100nH
Q910 +VDDCI +VDDCI
1 2 VDDCI_FILTERED_SOURCE 6
BSF030NE2LQ
5
1
0.47uH_17.5A L900
+ CB900 + CB901 C905 C927 C906 C907 C908 2 4 1 2
100uF 100uF 10uF 10uF 10uF 1uF 0.1uF 1
1
16V 16V 16V 16V 16V 16V 16V 120nH
+ + + +
2
C909 C910 CB902 MCB902 CB903 MCB903 C911 C912 C913 C914 C915 C916 R931 Close to VDDCI
0.1uF 0.01uF 330uF 330uF 330uF 330uF 22uF 22uF 22uF 22uF 22uF 22uF 100R Output Caps
16V 10V 2.5V 2V 2.5V 2V 4V 4V 4V 4V 4V 4V
2
2
2
14 OUT VDDCI_PWR_GOOD OVERLAP OVERLAP
NS900
NS901
7
6
5
4
00
1
C917 0.1uF16V R900
0R VDDCI_ISENN
3
VID11 = 0.950V R901 6.2K R902 93.1K VDDCI_ISENP
07
Q911
BSB013NE2LXI Route as
VID10 = 0.900V C918 0.1uF16V R920 DNI 5.11K C900 differential
1uF
1
2
16V pair
R903 2K R904 88.7K
74
MR930 DNI 0R
1
M
19 VDDCI_DAC R930 DNI 0R AM113
IN
U900
MODE/VSET2
VSET3
PGD
HDR
BST
65 SI　
C919 0.1uF16V
CGND is Controller Ground. R919
VID01 = 0.875V R905 1.5K R906 80.6K Create a ground plane under the controller 0R
1
D900 and connect to GND through R9XX at VDDCI
BAT54KFILM regulator output.
　
C920 0.1uF16V 6 REFIN/VSET1 LX 20
C C
2
CGND
R907 221R R908 7.32K 7 19 +5V
VID00 = 0.85V VSET0 LDR
張 CON
19 OUT VDDCI_DAC_GND
8 TSET VDDP 18
C921 0.1uF16V
9 RSN VDDA 17 R918 20R C904
R909 200K R910 7.32K 1uF
16V
文
10 RSP CSP 16 C903
F
1uF
16V
C922 0.1uF16V
RM 　 ID
ON/SKIP
GND#22
GND#21
CGND
R921 0R
VID0
VID1
CSN
CGND R929 DNI 5.11K
VIN
R922 DNI 0R R915 0R R923 0R
A( RD EN
FB_VSSCI
22
21
11
12
13
14
15
19 12 IN R928 576R R913 7.87K VDDCI_ISENP
吳 (C TI
19 12 IN FB_VDDCI R916 0R C901
0.033uF
16V
積 )2 AL
VDDCI_ISENP R924 DNI 5.11K R914 576R VDDCI_ISENN
R927
+12V_BUS 4.02K
源 01
DNI
R925 5.11K
+5V
)
CGND R911 5.11K
B 20 C923
0.1uF
C924
0.1uF
R912
4.02K
B
6
16V 16V
DNI DNI
05
R926
4.02K CGND
DNI
GPIO_14_VDDCI_VID0
00
GPIO_29_VDDCI_VID1
CGND
8 IN
8 IN
VDDC_PWR_GOOD
IN
17 14
1

SHEET: VDDCI schematic and design, including, not limited to, any implied warranty

TITLE
NOTES: NOTE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(21) DEBUG CIRCUITS
LED GREEN "ON" shows PX_EN

D4002 +3.3V_BUS
+3.3V_BUS SML-010PTT86
+3.3V_BUS PEX_LED 1 2 PEX_LED_PWR R4001 499R
3
C4000 13 1 PX_EN R4021 10K PEX_LED_ON 1 Q4001
0.1uF IN
D 1
U4000
8
R4000
18.2K
14
1
J4001
MMBT3904
D
VCC VID0 1%
2
2
2 GND VID1 7
19 17 8 REGLTR_SCL 3 SCL VREF 6 VDDCI_DAC 18
IN REGLTR_SDA 4 5
OUT header_1x2_2mm_smt
19 17 8 BI SDA R1
18 VDDCI_DAC_GND
IN
UP6266
R4002 J4002
2480105100G 13 GPU_DMINUS 1
R4005
35.7K
1%
IN GPU_DPLUS 2
0R 13 IN
DNI header_1x2_2mm_smt
SWITCH CONNECTIONS TO PINSTRAPS
SW4001 GPIO(0) - TX_CFG_DRV_FULL_SWING (Transmitter Power Savings Enable)

J4004 8 GPIO_0_PHASE_SHED# 2 3 0: 50% Tx output swing for mobile mode
+3.3V_BUS IN
JTAG_SOCKET_8 NA 1: full Tx output swing (Default setting for Desktop)
00
1 JTAG_TDO 7 8 SW4000
IN 5 6
GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)
1 OUT JTAG_TDI
8 IN GPIO_1 2 3 0: Tx de-emphasis disabled for mobile mode
1 JTAG_TMS 3 4
IN JTAG_TCK 1 2 TESTEN NA 1: Tx de-emphasis enabled (Default setting for Desktop)
1 IN OUT 1 +3.3V_BUS
07
SW4000 GPIO(2) - BIF_GEN3_EN_A
8 IN GPIO_2 1 4 NR4000 2.2K 0 : Driver Controlled Gen3
J4000 NA 1 : Strap Controlled Gen3
1 GPUSMCLK 1
OUT 2
74
1 BI GPUSMDAT SW4001
M
13 8 GPIO_28_FDO 1 4 NR4001 2.2K
header_1x2_2mm_smt IN
NA
8 OUT XTALIN C4011 20pF
65 SI　 LED RED "ON" shows Fault

D4000
SML-010-L +3.3V_BUS
1
2
1 2
　
Y4000 LED LED_PWR R4003 499R
3
C R4022
1M
27.000MHz_10PPM_30R
C
19 13 CTF_OUT R4004 1K LED_ON 1 Q4000
3
4
IN
張 CON
MMBT3904
8 XTALOUT R4023 0R XTALOUT_R C4012 20pF
IN
2
文
RM 　 ID F CTF_OUT
OUT 13 19 PWM_b
OUT 13
2
A( RD EN
SW4002
SW4002
NA
NA
Bypass Switch
(not for production)
3
吳 (C TI
DNI For Production
積 )2 AL
源 01
+5V +3.3V_CLEAN
R4007 150R
) 20
1
R4008
10K
1%
B B
6
V=2.5V(1+Rt/Rb)+Iref.Rt 2 REG4000
LM431CCM/N1B
05
MR4009 DNI 0R
R4011
31.6K R4009
3
1% 0R
00
+3.3V_CLEAN
+5V REG4001 +3.3V_CLEAN
1
LM4132AMF-3.3/NOPB C4005
6
4 VIN NC 1 0.1uF
6
FB_VDDC_R FB_VDDC
GND
3 EN VREF 5 +3.3V_CLEAN 3 R4012 10K 0.1% 12 17

1 J4003
IN
2
3 R4013 1K 0.1% 1 R4015 10K 0.1% 2

3
2
C4006 C4007 C4008 D4001

4.7uF 4.7uF 0.1uF 1 4 FB_VSSC_R R4014 10K 0.1% SMTRFCONN FB_VSSC
SD
BAT54C 3 C4009 IN 12 17
100pF U4002
50V LMV118MFNOPB
4
SD
+3.3V_CLEAN
U4003
LMV118MFNOPB MR4020 DNI FB_VDDCI
1
5
0R 12 18
U4004 1 J4005
IN
5 4 VDDC_NON_DIFF R4020 2
2
VA VIN 0R
3
19 17 8 IN REGLTR_SCL 1 SCL ALERT 2 SMTRFCONN FB_VSSCI IN 12 18
R4016 1K 0.1%
19 17 8 REGLTR_SDA 8 SDA ADR0 3 ADR0 R4017 10K R4010 10K 0.1%
BI
7 GND ADR1 6 ADR1 R4019 10K R4030 R4031
33R 100R C4004 12pF 50V
ADC121C021CIMM
C4010
0.01uF 1 COMMERCE VALLEY This AMD Board schematic and design is the exclusive property of AMD, and
A ADDR0 ADDR1 I2C SLAVE ADDRESS 25V
FLOATING FLOATING 0X50 prohibited. Use of this schematic and design for any purpose other than
FLOATING GND 0X51
SHEET: DEBUG CIRCUITS AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
GND FLOATING 0X54 of merchantability or fitness for a particular purpose, and disclaims
GND GND 0X55

TITLE
NOTES: NOTE
8 7 6 5 4 3 2 1
9 8 7 6 5 4 3 2 1
E E
MEMORY CHANNEL A&B MEMORY CHANNEL C&D MEMORY CHANNEL E&F
External Connector
GDDR5 4pcs 64Mx32 GDDR5 4pcs 64Mx32 GDDR5 4pcs 64Mx32
+12V_EXT_A
External Connector
+12V_EXT_B
CH A/B/C/D/E/F
JTAG/I2C
Debug TMDPC mDisplayPort
AC Coupling Caps
D CrossFire
D
00
DVOCLK
CrossFire Connector
DVPCNTL_[0..2] DDC1 AUX1
DVPDATA[23:0]
POWER REGULATORS Interlink
07
DVP_MVP_CNTL[1:0]
HPD5
GPIO[2:1]
GENERICC, D
74 M
From EXT_A, EXT_B:
Regulator HOT GPIO5
65 SI　
+VDDC
TMDPD AC Coupling Caps mDisplayPort
From +12V_BUS:
　
GPIO DDC2 AUX2
Connector
+VDDCI, +MVDDC
+5V, +5V_VESA, +5V_HDMI
Straps
HPD4
張 CON
From +12V_BUS OR EXT_B:
+VDDQ
BIOS ROM
From +12V_BUS, 3.3V (0.95V):
PCIE_VDDC, DPLL_VDDC, SPLL_VDDC

DP_VDDC Speed control
Thermal
DDC6
文
RM 　 IDF
DDC4
HPD1
HDMI
Connector
A( RD EN
AC Coupling Caps and
& temperature GPIO17, GPIO6_TACH
TMDPA
Inductors
INTERRUPT
From +3.3V Direct: sense
C FAN D+/D- C
吳 (C TI
Temp. Sensing
VDDR3
FDO
Built-in PWM
積 )2 AL
From 3.3V (1.8V)
LVTMDPEF
PCIE_PVDD,VDD_CT, VDDR4, AC Coupling Caps
源 01
Dynamic Power Management
DPLL_PVDD, XTAL_VDDR, SPLL_PVDD
DVI-I
MPLL_PVDD, DP_VDDR, VDD1DI, AVDD
) 20
TSVDD POWER DELIVERY CRTDAC RGB Filters
Connector
DDC7
TAHITI
6 HPD3
05
+5V_VESA
00
100MHz
XO_IN2
27MHz
XO_IN Clock
1
XTALIN
Temperature Critical
CTF
PCI-Express
Power Sequencing
B Circuit
B
RH TAHITI GDDR5 3GB

+3.3V_BUS 64Mx32 mDP mDP HDMI
+12V_BUS
PCI-Express Bus DVI

SHEET: BLOCK DIAGRAM schematic and design, including, not limited to, any implied warranty
DATE: Fri Oct 28 12:01:04 2011 REV: 1.0 information included herein.

TITLE
NOTES: NOTE
9 8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AMD TITLE:
ENGINEER:
TITLE
NOTES:
DOCUMENT NUMBER: 105-C38600-00 DATE:

Thu Nov 03 14:05:25 2011
C 2010 Advanced Micro Devices

SHEET NUMBER:
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
21 OF 21
AMD - GRAPHICS
REV: 1.0
REVISION HISTORY XXX NOTE

for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the information included herein.
1 COMMERCE VALLEY
MARKHAM, ONTARIO, L3T 7X6
SCH PCB Date REVISION DESCRIPTON
Rev Rev
Base on -00A :
D 1 00B 11/08/31 1. Change the power deliver tree for support Pro ASIC D
2, Change the VDDC input bulk cpas due to height volidation the specs
Base on -00B :
2 00 11/11/01
1. Change the circuit for fan control in BACO mode
00
07
74 M
65 SI　
　
C C
張 CON
文
RM 　 ID F
A( RD EN
吳 (C TI
積 )2 AL
源 01
B ) 20 B
6 05
00
1
A A
8 7 6 5 4 3 2 1

R9 - 280X Shematic

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8 7 6 5 4 3 2 1

(1) PCI-E INTERFACE

x16 PCIe Tahiti

SHEET NUMBER: 1 OF 21 TITLE:

(2) TAHITI Memory Channel A&B

AC56 WCDRA0_0 WCDRA1_0 AC47 L52 WCDRB0_0 WCDRB1_0 T37

源 01 3 OUT CSB0b_0 A48

6 3 OUT DRAM_RST1 R3618 51R DRAM_RST1_R R3605 10R

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

SHEET NUMBER: 2 OF 21 TITLE:

GDDR5 GDDR5 GDDR5 GDDR5

+MVDD +MVDD +MVDD

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

DATE: Wed Nov 02 15:28:39 2011 REV: 1.0

information included herein.

SHEET NUMBER: 3 OF 21 TITLE:

(4) TAHITI Memory Channel C&D

MVREFDC V24 MVREFD_C MVREFDD AD18 MVREFD_D

MVREFSC V26 MVREFS_C MVREFSD AF18 MVREFS_D

C3624 R3624 R3634

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

SHEET NUMBER: 4 OF 21 TITLE:

+MVDD +MVDD +MVDD +MVDD

+MVDD +MVDD +MVDD

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

information included herein.

SHEET NUMBER: 5 OF 21 TITLE:

DOCUMENT NUMBER: 105-C38600-00

R3642 +MVDD R3652 +MVDD

MVREFSE AT18 MVREFS_E MVREFSF BB24

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

SHEET NUMBER: 6 OF 21 TITLE:

+MVDD +MVDD +MVDD +MVDD

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

responsibility for any consequences resulting from use of the

SHEET NUMBER: 7 OF 21 TITLE:

C23 C24 SS_SEL0 7 SS_SEL0 R13 10K GENLK_CLK GENLK_CLK - SMS_EN_HARD

(9) TAHITI HDMI DVI AB

TXCAP_DPA3P BU40 ATXCP C1707 0.1uF ATXCP_C 10

TXCAM_DPA3N BV39 ATXCM C1708 0.1uF ATXCM_C 12

HDMI_DDCCLK 15 DDC Clock

(10) TAHITI mDP mDP CD

TX1P_DPC1P BU34 DPC_C1P C1803 0.1uF DPC_1P 9 ML_Lane_1p C1821 C1822

TX0P_DPC2P BT33 DPC_C2P C1805 0.1uF DPC_2P 15 ML_Lane_2p

TX0M_DPC2N BR33 DPC_C2N C1806 0.1uF DPC_2N 17 ML_Lane_2n

TXCCP_DPC3P BU32 DPC_C3P C1807 0.1uF DPC_3P 10 ML_Lane_3p

TXCCM_DPC3N BT31 DPC_C3N C1808 0.1uF DPC_3N 12 ML_Lane_3n

TX5P_DPD0P BT39 DPD_D0P C1811 0.1uF DPD_0P 3 ML_Lane_0p

TX3P_DPD2P BT37 DPD_D2P C1815 0.1uF DPD_2P 15 ML_Lane_2p

TXCDP_DPD3P BU36 DPD_D3P C1817 0.1uF DPD_3P 10 ML_Lane_3p

AUX2P BK34 AUX2P C1819 0.1uF DPD_AUXP 16 AUX_CHp

D1800 2 1 ESD5V3U1U-02LRH DPC_AUXN AMD - GRAPHICS C 2010 Advanced Micro Devices

SHEET NUMBER: 10 OF 21 TITLE:

TX2M_DPE0N BW54 DPE_TX2N C1902 0.1uF

TX1P_DPE1P BT53 DPE_TX1P C1903 0.1uF

TX1M_DPE1N BU52 DPE_TX1N C1904 0.1uF

TX0P_DPE2P BW52 DPE_TX0P C1905 0.1uF

TX0M_DPE2N BV51 DPE_TX0N C1906 0.1uF

TXCEP_DPE3P BT51 DPE_TXCAP C1907 0.1uF

DDCCLK_AUX5P BN49 DDCAUX5P +5V_VESA

Please pay attention to the grounding Analog_Blue

OPTIONAL ESD PROTECTION DIODES

D1506 2 1 ESD8V0R1B-02LRH vSYNC_R information included herein.

65 SI　 LED RED "ON" shows Fault