9730721, 234 Pa Clock signal - Wikipedia
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Clock signal
In clectronies and especially synchronous digital cireuits, a clock signal (historically also known as logic
beat!) oscillates between a high and a low state and is used like a metronome to coordinate actions of
digital circuits.
A clock signal is produced by a clock generator. Although more complex arrangements are used, the most
common clock signal is in the form of a square wave with a 50% duty cycle, usually with a fixed, constant
frequency.
cuits using the clock signal for synchronization may become active at either the rising edge,
falling edge, or, in the case of double data rate, both in the rising and in the falling edges of the clock cycle.
Contents
Digital circu
Single-phase clock
Two-phase clock
4-phase clock
Clock multiplier
Dynamic frequency change
Other circuits
Distribution
See also
References
Further reading
Digital circuits
Most integrated circuits (ICs) of sufficient complexity use a clock signal in order to synchronize different
parts of the circuit, cycling at a rate slower than the worst-case internal propagation delays. In some cases,
more than one clock cycle is required to perform a predictable action. As ICs become more complex, the
problem of supplying accurate and synchronized clocks to all the circuits becomes increasingly difficult. The
preeminent example of such complex chips is the microprocessor, the central component of modern
computers, which relies on a clock from a crystal oscillator. The only exceptions are asynchronous circuits
such as asynchronous CPUs.
A clock signal might also be gated, that is, combined with a controlling signal that enables or disables the
clock signal for a certain part of a circuit. This technique is often used to save power by effectively shutting
down portions of a digital circuit when they are not in use, but comes at a cost of increased complexity in
timing analysis.
Single-phase clock
Most modern synchronous circuits use only a "single phase clock" — in other words, all clock signals are
(effectively) transmitted on 1 wire.
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Two-phase clock
In synchronous circuits, a "two-phase clock" refers to clock signals distributed on 2 wires, each with non-
overlapping pulses. Traditionally one wire is called "phase 1” or "1", the other wire carries the "phase 2" or
'p2" signal.lI[31[4II5] Because the two phases are guaranteed non-overlapping, gated latches rather than
edge-triggered flip-flops can be used to store state information so long as the inputs to latches on one phase
only depend on outputs from latches on the other phase. Since a gated latch uses only four gates versus six
gates for an edge-triggered flip-flop, a two phase clock can lead to a design with a smaller overall gate count
but usually at some penalty in design difficulty and performance.
MOS ICs typically used dual clock signals (a two-phase clock) in the 1970s. These were generated externally
for both the 6800 and 8080 microprocessors.!*! The next generation of microprocessors incorporated the
clock generation on chip. The 8080 uses a 2 MHz clock but the processing throughput is sit ir to the
1 MHz 6800. The 8080 requires more clock cycles to execute a processor instruction. The 6800 has a
minimum clock rate of 100 kHz and the 8080 has a minimum clock rate of 500 kHz. Higher speed versions
of both microprocessors were released by 1976.(7)
The 6501 requires an external 2-phase clock generator. The MOS Technology 6502 uses the same 2-phase
logic internally, but also includes a two-phase clock generator on-chip, so it only needs a single phase clock
input, simplifying system design.
4-phase clock
Some early integrated circuits use four-phase logic, requiring a four phase clock input consisting of four
separate, non-overlapping clock signals.(8I This was particularly common among early microprocessors
such as the National Semiconductor IMP-16, Texas Instruments TMS9goo, and the Western Digital WD16
chipset used in the DEC LSI-11.
Four phase clocks have only rarely been used in newer CMOS processors such as the DEC WRL MultiTitan
microprocessor.91_ and in Intrinsity's Fastiqg technology. Most modern microprocessors and
microcontrollers use a single-phase clock.
Many modern microcomputers use a "clock multiplier” which multiplies a lower frequency external clock to
the appropriate clock rate of the microprocessor. This allows the CPU to operate at a much higher
frequency than the rest of the computer, which affords performance gains in situations where the CPU does
not need to wait on an external factor (like memory or input/output).
Dynamic frequency change
The vast majority of digital devices do not require a clock at a fixed, constant frequency. As long as the
imum and maximum clock periods are respected, the time between clock edges can vary widely from
one edge to the next and back again. Such digital devices work just as well with a clock generator that
dynamically changes its frequency, such as spread-spectrum clock generation, dynamic frequency scaling,
ete. Devices that use static logic do not even have a maximum clock period (or in other words, minimum
clock frequency); such devices can be slowed and paused indefinitely, then resumed at full clock speed at
any later time.
Other circuits
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Some sensitive mixed-signal cireuits, such as precision analog-to-digital converters, use sine waves rather
than square waves as their clock signals, because square waves contain high-frequency harmonics that can
interfere with the analog circuitry and cause noise. Such sine wave clocks are often differential signals,
because this type of signal has twice the slew rate, and therefore half the timing uncertainty, of a single-
ended signal with the same voltage range. Differential signals radiate less strongly than a single line.
Alternatively, a single line shielded by power and ground lines can be used.
In CMOS circuits, gate capacitances are charged and discharged continually. A capacitor does not dissipate
energy, but energy is wasted in the driving transistors. In reversible computing, inductors can be used to
store this energy and reduce the energy loss, but they tend to be quite large. Alternatively, using a sine wave
clock, CMOS transmission gates and energy-saving techniques, the power requirements can be reduced.
Distribution
‘The most effective way to get the clock signal to every part of a chip that needs it, with the lowest skew, is a
metal grid. In a large microprocessor, the power used to drive the clock signal can be over 30% of the total
power used by the entire chip. The whole structure with the gates at the ends and all amplifiers in between
have to be loaded and unloaded every cycle.("°ll""] To save energy, clock gating temporarily shuts off part of
the tree.
The clock distribution network (or clock tree, when this network forms a tree) distributes the clock
signal(s) from a common point to all the elements that need it. Since this function is vital to the operation
of a synchronous system, much attention has been given to the characteristics of these clock signals and the
electrical networks used in their distribution. Clock signals are often regarded as simple control signals;
however, these signals have some very special characteristics and attributes.
Clock signals are typically loaded with the greatest fanout and operate at the highest speeds of any signal
within the synchronous system. Since the data signals are provided with a temporal reference by the clock
signals, the clock waveforms must be particularly clean and sharp. Furthermore, these clock signals are
particularly affected by technology scaling (see Moore's law), in that long global interconnect lines become
significantly more resistive as line dimensions are decreased. This increased line resistance is one of the
primary reasons for the increasing significance of clock distribution on synchronous performance. Finally,
the control of any differences and uncertainty in the arrival times of the clock signals can severely limit the
maximum performance of the entire system and create catastrophic race conditions in which an incorrect
data signal may latch within a register.
Most synchronous digital systems consist of cascaded banks of sequential registers with combinational
logic between each set of registers. The functional requirements of the digital system are satisfied by the
logic stages. Each logic stage introduces delay that affects timing performance, and the timing performance
of the digital design can be evaluated relative to the timing requirements by a timing analysis. Often special
consideration must be made to meet the timing requirements. For example, the global performance and
local timing requirements may be satisfied by the careful insertion of pipeline registers into equally spaced
time windows to satisfy critical worst-case timing constraints. The proper design of the clock distribution
network helps ensure that critical timing requirements are satisfied and that no race conditions exist (see
also clock skew).
The delay components that make up a general synchronous system are composed of the following three
individual subsystems: the memory storage elements, the logic elements, and the clocking circuitry and
distribution network.
Novel structures are currently under development to ameliorate these issues and provide effective
solutions. Important areas of research include resonant clocking techniques, on-chip optical interconnect,
and local synchronization methodologies.
htpson. wikipedia orghwikiClock_signal a89730721, 234 Pa Clock signal - Wikipedia
See also
Clock rate
Electronic design automation
Design flow (EDA)
Integrated circuit design
Self-clocking signal
Four-phase logic
Jitter
Bit-synchronous operation
Pulse-per-second signal
Clock domain crossing
References
1
FM1600B Microcircuit Computer Ferranti Digital Systems (https:/iwww sba.unipi i/sites/defaultfiles/201
5_05_29 08 44_13.pdf) (PDF). Bracknell, Berkshire, UK: Ferranti Limited, Digital Systems
Depariment. Ociober 1968 [September 1968]. List DSD 68/6. Archived (https://web.archive.org/web/20
200519075443/https://www.sba.unipi.itsites/defaultifiles/2015_05_29 08 44 13.pdf) (PDF) from the
original on 2020-05-19. Retrieved 2020-05-19,
‘Two-phase clock (http://www. princeton.edu/~wolfimodem-visi/Overheads/CHAPS-2/sid010.htm)
Archived (https://web.archive.org/web/20071109090150/http://www. princeton.edu/~wolfimodem-visi/Ov
etheads/CHAPS-2/sid010.htm) November 9, 2007, at the Wayback Machine
Two-phase non-overlapping clock generator (https://web archive org/web/20111226073122/http:/itams-
www.informatik.uni-hamburg.de/applets/hades/webdemos/12-gatedelay/40-Ipog/two-phase-clock-gen.h
tm), Tams-www.informatik.uni-hamburg.de, archived from the original (http://tams-www.informatik.uni-h
amburg.de/applets/hades/webdemos/12-gatedelay/40-tpegitwo-phase-clock-gen.html) on 2011-12-26,
retrieved 2012-01-08
Concepts in Digital Imaging - Two Phase CCD Clocking (http://micro.magnet.fsu.edu/primeridigitalimagi
ng/conceptsitwophase.html), Micro. magnet fsu.edu, retrieved 2012-01-08
Cell cgf104: Two phase non-overlapping clock generator (https://web.archive.orgiweb/2012020805434
8ihttp:/www.hpc.msstate.edu/mpl/distributions/scmos/scmos_doc/cells/cgf104.html), Hpc.msstate.edu,
archived from the original (http://www.hpc.msstate.edu/mp\/distributions/scmos/semos_docicells/cgf10
4.ntmi) on 2012-02-08, reirieved 2012-01-08
“How to drive a microprocessor” (https://commons.wikimedia.orgiwiki/File:Motorola_MC6870_ad_April_
1976 jpg). Electronics. New York: McGraw-Hill. 49 (8): 159. April 15, 1976. Motorola's Component
Products Department sold hybrid ICs that included a quartz oscillator. These IC produced the two-
phase non-overlapping waveforms the 6800 and 8080 required. Later Intel produced the 8224 clock
generator and Motorola produced the MC6875. The Intel 8085 and the Motorola 6802 include this
circuitry on the microprocessor chip.
“Intel's Higher Speed 8080 uP" (https://web.archive.orgiweb/20190123102914/http://bitsavers.org/pdtim
icrocomputerAssociates/Microcomputer_Digest_v02n03_Sep75.pdf) (PDF). Microcomputer Digest.
Cupertino CA: Microcomputer Associates. 2 (3): 7. September 1975. Archived from the original (http:/Aw
ww-bitsavers.org/pdt/microcomputerAssociates/Microcomputer_Digest_v02n03_Sep75.pdf) (PDF) on
2019-01-23. Retrieved 2011-01-24
Concepts in digital imaging - Four Phase CCD Clocking (hitp://micro.magnet.fsu.edu/primeridigitalimagi
ng/concepts/fourphase.htmi), Micro. magnet fsu.edu, retrieved 2012-01-08
Norman P. Jouppi and Jeffrey Y. F. Tang. "A 20-MIPS Sustained 32-bit CMOS Microprocessor with High
Ratio of Sustained to Peak Performance" (http://citeseerx.ist.psu.edu/viewdocidownload ?doi=10.1.1.85.
988&rep=rep' &type=pdt). 1989. CiteSeer*: 10.1.1.85.988 (http:/citeseerx ist psu edu/viewdoc/summar
y2doi=10.1.1.85.988) p. 10
htpson. wikipedia orghwikiClock_signal 469730721, 234 Pa Clock signal - Wikipedia
10, Anand Lal Shimpi (2008), Intel's Atom Architecture: The Journey Begins (http:/www.anandtech.com/sh
owdoc.aspx?i=3276&p=14)
11, Paul V. Bolotoff (2007), Alpha: The history in facts and comments (https://web.archive.org/web/2012021
8005309/http://alasir.com/articles/alpha_history/alpha_21264.html), archived from the original (hitp://ala
sir.com/arlicles/alpha_history/alpha_21264.htmi) on 2012-02-18, retrieved 2012-01-03, "power
consumed by the clock subsystem of EV6 was about 32% of the total core power. To compare, it was
about 25% for EV56, about 37% for EVS and about 40% for EV4."
Further reading
= Eby G. Friedman (Ed.), Clock Distribution Networks in VLSI Circuits and Systems, ISBN 0-7803-1058-
6, IEEE Press. 1995,
= Eby G. Friedman, "Clock Distribution Networks in Synchronous Digital Integrated Circuits" (https:
g/10.1109%2F5.929649), Proceedings of the IEEE, Vol. 89, No. 5, pp. 665-692, May 2001.
= "ISPD 2010 High Performance Clock Network Synthesis Contest" (http://archive.sigda.org/ispd/contest
s/10/ispd10cns.htm)), international Symposium on Physical Design, intel, IBM, 2010
= D.-J. Lee, “High-performance and Low-power Clock Network Synthesis in the Presence of Variation’ (ht
tp:/www.eecs.umich.edu/~imarkov/pubs/diss/DJdiss. pdt), Ph.D. dissertation, University of Michigan,
2011
= I. L. Markov, D.-J. Lee, "Algorithmic Tuning of Clock Trees and Derived Non-Tree Structures” (http://ww
w.eecs.umich.edu/~imarkov/pubs/confliccad11-tuto.pdf), in Proc. Int. Conf, Comp.-Aided Design
(ICCAD), 2011
= V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic, and N. M. Nedovie, Digital System Clocking: High-
Performance and Low-Power Aspects, ISBN 0-47 1-27447-X, IEEE Press/Wiley- Interscience, 2003.
= Mitch Dale, "The power of RTL Clock-gating” (https://web.archive.orgiweb/20131224102708/http://chipd
esignmag.com/display.php?articleld=915), Electronic Systems Design Engineering Incorporating Chip
Design, January 20, 2007.
joi.or
Adapted from Eby Friedman (http://www.ece.rochester.edu/users/friedman/)'s column in the ACM
SIGDA (http://www.sigda.org) e-newsletter (https: //web.archive.org/web/20070208034716/http://www.
sigda.org/newsletter/index.html) by Igor Markov (http://www.eecs.umich.edu/~imarkov/)
Original text is available at
https://web.archive.org/web/20100711135550/http://www.sigda.org/newsletter/2005/eNews_o51201.html
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