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    10 views16 pages

    Ad7579 7580

    Uploaded by

    Lorenzo L.

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
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    ANALOG DEVICES LC”M0s 10-Bit Sampling A/D Converters AD7579/AD7580 FEATURES 20ys Conversion ‘On-Chip Sample-Hold ‘50kHz Sampling Rate ‘25kH2 Full-Power Input Bandwidth Choice of Data Formats Single +5V Supply Low Power (50mW) ‘Skinny 24-Pin DIP and 28-Terminal Surface Mount Packages GENERAL DESCRIPTION ‘The AD7579 and AD7580 are 10-bit, successive approximation ADCs. They have differential unalog inputs that will accept ‘unipolar or bipolar input signals while operating from only a single +5V supply. Input ranges of 0 10 +2.5V, 0 to +SV and “£2.5V are possible with no external signal conditioning. Only an external 2.5V reference and clock and control signals are required to make them operate. ‘With conversion time of less than 20s and an on-chip sample-hold amplifier, the devices are ideally suited for digitizing ac signals. ‘The maximum sampling rate is SOkHz, giving an input bandwidth cof 25kHz, The parts are specified not only with traditional static specifications sch as linearity and offset but also with dynamic specifications (SNR, Harmonic Distortion, IMD). ‘The AD7579 and AD7580 are microprocessor-compatible with ‘standard microprocessor control inputs (CS, RD, WR, RDY, TNT) and data outputs capable of interfacing to high-speed data buses. There isa choice of data formats, with the AD7579 ‘offering an (8+2) read and the AD7S80 offering a 10-bit parallel word, Space saving and low power are also features of these devices. ‘They dissipate less than SOmW from a single +SV supply and are offered in a 0.3", 24-pin package and in plasticfceramic chip carrier for surface mounting. REV.A, Information furnished by Analog Devios is believed to be accurate and {tliale: However na responsibilty sumed by Analog Devices for its se, nor for any Infringements of patents or other ights of third parties ‘which may result from ite eo, No license le grantee by implesbon oF ny patent or patent rights of Analog Deviees ‘terwiee under FUNCTIONAL BLOCK DIAGRAMS PRODUCT HIGHLIGHTS 1. 20us conversion time with on-chip sample-hold makes the ‘AD7579 and AD7580 ideal for audio and higher bandwidth signals, e.g., modem applications. 2, Differential analog inputs can accept unipolar or bipolar input signals, but only a single, +5V power supply is needed. 3. Versatile and easy-to-use digital interface has fast bus access! relinquish times, allowing connection to most popular micro- processors. 0. Box 3106, Norwood, MA 02062-9106, US.A, Fax: 617/326-8703 Twx: 710/394-6577 ‘Cable: ANALOG NORWOODMASS One Technology Way. (Vo = +5V 5%, Vosy = +2.5¥, AGND = DEND = OV; AD7579/AD7580 —SPECIFICATIONS tsa testcaion ain reoe' wis ctems sd TA x Parameter Versions | Verio Veni Unite Condition Comments ‘STATICCHARACTERISTICN “Tes apeciesins pry ore Reseaion 0 w w Bits tre Analog iepat Reng SeeDiferetl Applications. Inurl Noatoesry “ 2 LsBmax ‘Nomisingeniesgurantcedoverthe Diferedal Line Error 208 208 1SBmer faltemperore range Full Scale Eon ss ss Sima ZeroCode ree? 22 = (smn Connected sin Figure 12 a 33 TsBeae (Coonetdsin Figure 14015, Powe: Supp Reston 03 20s TSB mex AIVVon SV ‘DYNAMICCHARACTERISTICN™ Conversion Tine 169 169 6 pein fea =2:SMt ty Is is ss fem SecPuncioaal Dei, Sampling Rate 0 0 so Keizma Clock Range 025 25025 2028 iri Max Signi Noje Ratio s s ss arin See Termicalagy.T,=25C. 3s o se aor Toul Harmonic Distortion an os os Bre Ty-280. 68 a6 6 aon Intermadaatin Distortion <6 oe o Bye ‘Thisicharcezed toboth SMPTE, and CCITTstandarls, Fy =29. Sloe Rae we we 1 Vigan SecTevmlocegy ANALOG INPUT RANGES Figure 12 AD?S79/AD7S60 connexes atin Figur 12 Span Vere Vane Vers Vina Cmimet-Made Range Owen — | OVan | 0am | Via CMR os 0s os TSB Figures AD7S7AD S80 conned ann Figure 4 Span are Were Ware Vax Common Made Range dwinn — | Om — | Ow Vom | Yeon CMR 03 os as TSB Fare 5 ADISIWAD7S60eonnectedsia Figure 1S Span Nur Weer esr Vmax Common Mode Range “Verte | ~Ve Varese | Via 2Von-Vie) | @Vo0~Vies) | @Vo0~Vass) con os os as LsEv NTTENUATORINPUTRESISTANGE | 515 si 35 Hiiminkiimax | Tk pc Reiss mews bam Vint )A, Vind BorVind Vin 8 ‘COMPARATORINPUTRESISTANGE | 10 my © amin "ADISIIAD TSS connectedein Fie? REFERENCE INPUT ‘Vaan (For Specie Performance) a2 425 a28 v 8 Jean ts 1 1s Aman Tosicerors GRD, WR, HBEN, "ipa Input Low Voge 08 os os Vinee ‘Yn pat High Voge 2 2 24 vain Tryrloput Caren we : Pn “ Amos TT 210 210 10 name Co Tapa Capaciance* io 10 0 ine Toaicourruts ‘Db0%0DBI(DB9) Yor sOutput Low Vatage os os o4 Vinee Von, Op High alge “0 40 40 Vela Flog Sut Leakage Current a a S10 Ame Fling Site Output to i o pees py, INT You,Outpt Law Vatage au os os Vmax Tange" 160 FOWER REQUIREMENT Von as Rj +s v + Stee Specified Pesormance Ino 0 wo wo Amar Typaly AWB Vop™ 13 Pores Dinipaon 0 so so Wm TE vonat ve ‘Senpras ic emarcooran earpstenane apres sempre ‘hosing may epee ne oe han eid Ne maybe arma pousetae Vue 165, Siena nibecn cane ite REV. A AD7579/AD7580 TIMING SPECIFICATIONS’ Limitat | Limieat Timicat 3c Tray Tas Tyiy Tae Parameter? | (AllGrades)| (,K,A,BGrades)| (SGrade) ‘Units | Test Conditions/Comments 4 ° 0 ° nsmin | GSto WR SerupTime ® 0 so 0 nsmin | WRPulse Width 8 ° ° ° nsmin | CStoWR Hold Time 4 100 100 120 max | WRtoINT Propagation Delay & ° ° ° nnsmin | CStoRD Setup Time % te ta te namin | RD Pulse Width y ° ° ° asmin | CStoRD Hold Time % 20 2 30 tsmin | HBEN RD Setup Time & 10 10 10 smin | HBEN1oRD Hold Time tte 0 1s 130 rsmin | RDY Access Time tu 100 100 120 nsmax | RDtoINT Propagation Delay te 10 Bs 130 rosmax | Data Acces Time After RD B 10 10 10 namin | Data Hold Time, RDY Hold Time “6 0 %0 asmax estos ae ample eed at $25 cae cmp. Al pat cot ga speed wih es (10 to PL 59) dined a age elt 1.6 2. Chests amd tuyte mesard hte on out of Pie an 3 ined athe ine rege oan ctr ota oc ba 3. tps dle tine gid fr the ta ine to change SV when dd wih the dru of Fg {RT Aco RY ue opersn output and ned tel pllp reas or operon. Speco tect change witout nse. ser + om oan + = a. a ‘1000 t 100pF ka oh? ny i we 2, High-2 0 Vow b. High-Zt0 Vox “are nnoeromas pa eeeon Figure 2. Load Circuits for Access Time Tests (t2) Figure 1. AD7579/AD7680 Start Cycle Timing t i” 2. Vow to HighZ b. Vox to Highz Figure 4, Loed Circuits for Output Float Delay (tr) — -£ View Looe He 490 RY AE 20 EXTERAL PAUP RESTORE a. High-Z to Vow Bb. Vos to HighZ Figure 5. Load Circuit for INT Propagation Delays Figure 2. AD7579/AD7580 Read Cycle Timing REV. A AD7579/AD7580 ABSOLUTE MAXIMUM RATINGS* Vpp to AGND -0.3V 10 +7 Vpp to DGND +0.3V 10 +7V AGND to DGND. =0.3V, Vop, 03Y, Vpn +0.3V 039, Vip +030 -03V, Vpp +0.3V Digital Input Voltage to DGND Digital Output Voltage to DGND CLK Input Voltage to DGND VarrtAGND .. =03V, Von Vint +A, Ving + B00 AGND (Figure 12) -0.3V, Vp +0.3V Ving~ YA, Ving — Bt AGND (Figure 12). . -0.3V, Vpp +030 Vix(-+)A to AGND (Figure 14) Vin(~ JA to AGND (Figure 14) Vint+)AtoAGND (Figure 15). . -0.6V, 2Vpp +0.6V -0.6V, 2Vpp +0.6V —Vrrr -0.6V, 2Vpp - Vaux +0.6V CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect- fed; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam shouldbe discharged to the destination socket before devices are removed. ‘TERMINOLOGY LEAST SIGNIFICANT BIT (LSB) ‘An ADC with 10-bit resolution can resolve one part in 24° (1/1024 of full scale). For the AD7S79/AD7580 operating in the unipolar range with 2.5V span, one LSB is 2.44mV. ZERO CODE ERROR ‘This is a measure of the difference between the ideal (0.5LSB) and the actual differential analog input level required to produce the first positive LSB code transition (00 . . . 00 10 00. . . 01). FULL-SCALE ERROR “The ideal difference between the fist transition voltage and last \ransition voltage for an ADC is (F.S.~2LSB). AD7579/AD7580 Full-Scale Error is defined as the deviation between this ideal difference and the measured difference. (COMMON-MODE RANGE ‘The voltage at both inputs to the AD7S79/AD7580 can be raised above or lowered below analog ground potential, providing ‘Vix(+) is equal to oF more positive than Vix(—). Figures 12, 14, and 15 show circuits for various Analog Input Ranges. The Common-Mode Range represents the voltage extremes which ‘can be applied tothe circuits of Figure 12, 14 or 15, For example, ‘when the AD7579/AD7580 is connected as in Figure 15, the (Common-Mode Range is -2.5V to +7.5V. SLEW RATE ‘Slew Rate is the maximum allowable rate of change of input signal such thatthe digital sample values are not in error. The Slew Rate performance of AD7579/AD7580 allows sampling of fan input full-scale (2.5V pk-pk) sine wave up to 20kHz. Ving—)At0 AGND (Figure 15) =Varr -0.6V, 2Vnp ~Vaee +0.6V ‘Operating Temperature Range ‘Commercial (J, K Versions) = Oto +70°C Industrial (A, B Versions) =25°C to +85°C 35°C to +128 1 65°C w + 150°C Extended (S Version) Storage Temperature Range Lead Temperature (soldering, 10sec) +300°C Power Dissipation (Any Package) to +75°C 450mW Derates Above +75°C by 6mWrc ‘sires above thot fisted under “Able Mats Ratings” may ous permanent mag te deie. Tissues ting oly nl functional operatinaf the dere ‘thescor any other cnions above these dicted i the operations etons ofthis ‘pecistion no mpd, Exposure to asl museum rating conitons forex tended perindsmay afer device. SNe SIGNAL-TO-NOISE RATIO Signal-o-Noise Ratio (SNR) is measured signal to noise at the ‘output of the ADC. The signal is the rms magnitude of the fundamental, Noise is the rms sum of all nonfundamental signals up to half the sampling frequency. SNR is dependent on the ‘number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical SNR for a sine-wave input is given by: SNR =(6.02N+1.7) 4B, where N is the number of bits in the ADC. Thus for an ideal 10-bit ADC, SNR = 6248. INTERMODULATION DISTORTION ‘With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products, of order (m-+n), at sum and difference frequencies of mfanfb, where m,n = 0,1,2,3,—. Intermodulation terms are those for which m oF a is not equal to zero, HARMONIC DISTORTION ‘Harmonie distortion is the ratio of the square root of the sum-of- ‘the-squares of the rms values of the harmonics to the rms value of the fundamental. For the AD7S79/AD7580, Harmonic Dis- log VF VES VE VE TVA) By vi here V; is the rms amplitude of the fundamental and V2, Vs, Vay Vsy Vo are the rms amplitudes of the individual harmonics. REV.A AD7579/AD7580 cneenocane ——— Tenpernre Models? ‘Range INL ‘Model?-? ‘Range INL ADBDN | oees7eC —]sise Teor ADIs [eee TE | =i _P RI Aree |e rece smas|nc Moet | ecutwe § (evame | ADT | eee (ius | Pann Abner [ecosme |Ztse: | han Aor | eeeawe _ |ziduse| Pass Foc |e eden ADT | eae eee | stese | oe Rprmnny |crcorere suse ae spree | Tas tase | Zunean | Got Apne | ace tabe |Zuaen | Gas poet lewen im ||susee| oe Abiewee | Taxcuriasc| sic [Got eee Dawinimtentip NOE mares et wine 0200 te steer eg hp com D4 ET can pecan as oO (Gwen pene re aa : rose Cn pe ye Pas ee ae ee aaa 9D = Caumic DIP; E = Laadess Ceramic Chip Carver, N = Plastic DIP; “Germic DIP, E~ Leadless Ceramic Chip Carr; N ~ Piastc DIP; = Plastic Leaded Chip Carer; Q= Cerdip. For otineinfrmation se Pestic Leaded Chip Case; Q.~ Cerdp. For outie informations Fag Inrnatin son Piet PIN CONFIGURATIONS pie tect =] =o Saf eR fine nal len =e 19 08 ool sje Sonaeit “_ ve-rocamacr 3 eaee al os Bibasi a /AD7580 Es — : 7 24 086 whl Fe]oen wr ss one ono [i or Fini so-nocomact i REV.A -5- AD7579/AD7580 PIN FUNCTION DESCRIPTION (DIP PACKAGE) Moemonic PiaNumber Description Maemonic PiaNumber Description ADISTS ADTSB0 [ADIS7S AD1S40 VaR Analog input in DOND 242 Disial Gand VEER 2 2 Anulog Input Pi. BEEN 13 High Byte Emble Input. Used. Vea 3 3 Alog Input i. tm ADIS for 2 Bye Reading VIB 4 Analog Input Pin. The four See Tab Il, 1V. Either the thabg lope pins connect igh Byc or the Low Byte the on-chip np aerator mr be vad fe (Ce Roe junamy be, | RDY 4B Open Drain Output. Tiss Configured win Tablet for screed during Read Gsle Cerour apa roge, ‘When accessed iti low daring Ver S'S) Vane dnp. Thi is nominally Conversion and high impedance Wav. trhencoovenion complet AGND 6 6 —_Alog Ground ppops7 1822 ——ThyeeState Data Outputs on cS 7 7 Chip Select Input. AD7579. The data format is WR 8 8 ‘Write Input. Used with CS to right justified. Munctavenion SoeTabies” — DBODB? - —1423._—‘ThreeStie Dats Outputs on iu, “ ADIS80. HH 9 «9——_Read input Used with Sto 1G. 23 = tema connection. This pin ead ate Sc Tab I. is comesed irra om the INT 10 10——_Open Druin, Ouput, ih IAD. should be le inpedane ding conversion pen an ot ed ab fede Gost ow when conversion is through pin in doublesied conplee. prue cacut bord UK Chock ur, Yoo 2424 Psitive Power Supply. Thi *SSV nonna a ani Taorapa [Commonose | | RI | HEN] recon iinet [zon [wat] Yack [Wa Spun | ane Eee | fae Fee — Few PVs) [8a [Va P¥a [2s [av oie a i ec Figwets | Vit) | AGND | Vini-) | AGND | sv Jove +10V. tele elas Se Converscnen LotR roms [vmce) [var [vmco [ver [ov [rasveszse 2 |! [2 [t | Rameamcomcensns, a Tobie. Analog Inout Ranges Table. AD7579 Truth Table hfe beens some | 927 lone {ons | pee jpx4pm2{ oni} ose 2 LE LE [Seer tarreena tow [sr [ose] ps ose [ons [naz nn [0 0 [ur |i | suarConversion os t of WR wicH |£0t+}o Jo [o jo Jo ps | DBs. $Y fo [esensesttaan = ‘Reta fran Table i. AD7S80 Truth Table Table IV. AD7579 Output Dota Format CIRCUIT INFORMATION ANALOG INPUT CIRCUITRY ‘The AD7S79 isa 10-bit ADC with an (8+2) output bus structure designed for 8-bit microprocessor systems. The AD7580 is a 10- bit ADC with @ 10-bit parallel output bus structure. The ADC circuitry is identical in both parts. Block diagrams are shown on the first page of this data sheet. Figure 6 shows the input circuitry to the ADC comparator. ‘This comparator has differential inputs which are accessed through, the attenuator networks made up of resistors R. The attenuators ‘can be used to scale and offset analog input voltages, and this is done in Figures 14 and 15 to alter the basic ADC input range. ‘The analog inputs to the comparator are differential with the provisos that V+ is always greater than or equal to V~, Vis ‘greater than or equal to AGND and that V+ is less than or ‘equal to Vpp. These conditions must be satisfied when using the ADC in any of the voltage ranges. TL Figure 6. AD7579/AD7580 Input Circuit REV. A AD7579/AD7580 Figure 7 shows an ac equivalent input circuit for the AD7579/ ‘AD7580 when used in the 2.5V Unipolar Mode of Figure 12. ‘The ADC comparstor is a sampled data comparator and the input circuitry for this is represented by Sa, Req and Ca, Req is ‘a combination ofthe switch-on resistance and the input impedance ‘of the comparator. When conversion stats, Vin(+) is sampled for at least (2tcix + twa + 200ns) before the comparator goes into the hold mode. This means that the analog input has a minimum of 1-1ns (fox = 2-SMHz, twa = 100ns) to settle before the comparator makes a decision. By using the typical values in Figure 7 for R, Req and Ca, the input time constant is S0ns. Setting to + /4LSB in a 10-bit system takes 8.3 time constants or 4152s in this case. This means that Ving -+) has plenty of time to settle before the ADC comparison cycle begins. cis important to remember that any source resistance or source capacitance appearing at the input will also increase the serdling time and this should be kept to a minimum in all cases, ate Figure 7. AD7579/AD7580 Equivalent input Circuit During ‘Sampling With a 2.5MHz clock, the AD7579/AD7580 has a maximum conversion time of 18.5ys. If lus is allowed for reading the data ‘outputs, the maximum sampling rate for the device is SOkHz. ‘This means that the maximum analog input frequency is 25kHz according to the Nyquist theory. The ADC input impedance in the Unipolar Configuration of Figure 12 is 10M0.. A medium ‘bandwidth op amp will drive this at 25kHz. When the input attenuators are used for signal conditioning, the input impedance is 10K0., The drive requirements on the amplifier will now be ‘greater but any errors resulting will be gain errors only. Suitable ‘op amps for driving the AD7S79/AD7580 in any of the input configurations are the AD711, AD OP-27, ADS44. These will deliver specified device performance over the input bandwidth. REFERENCE INPUT ‘The AD7579/AD7580 Var input is connected to the on-chip DAC. The input impedance of this is code dependent and the ‘greatest variation occurs when the DAC resistors are at their lower limit. In this case, the impedance changes from 1.75K02 t0 5.25K01 as the DAC is switched. To ensure that the error during ‘conversion is les than 1/2LSB, the Reference output impedance should be less then 10. References which satisfy this are the ‘ADS80 (shown in Figure 8) and the AD1403 from Analog Devices. Ifa timmable reference such as the ADS#4 is used, it is possible to trim out the ADG full-scale error by adjusting the reference output. REV. A a INTERNAL SAMPLE-AND-HOLD ‘When an ADC without sample-and-hold is used to digitize ac signals, the analog input must not change by more than 1/2LSB

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